1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_ 28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_ 29 30 #include "../globals-vixl.h" 31 32 namespace vixl { 33 namespace aarch64 { 34 35 const unsigned kNumberOfRegisters = 32; 36 const unsigned kNumberOfVRegisters = 32; 37 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters; 38 // Callee saved registers are x21-x30(lr). 39 const int kNumberOfCalleeSavedRegisters = 10; 40 const int kFirstCalleeSavedRegisterIndex = 21; 41 // Callee saved FP registers are d8-d15. 42 const int kNumberOfCalleeSavedFPRegisters = 8; 43 const int kFirstCalleeSavedFPRegisterIndex = 8; 44 45 // clang-format off 46 #define AARCH64_REGISTER_CODE_LIST(R) \ 47 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 48 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 49 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 50 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 51 52 #define INSTRUCTION_FIELDS_LIST(V_) \ 53 /* Register fields */ \ 54 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \ 55 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \ 56 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \ 57 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \ 58 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \ 59 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \ 60 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \ 61 \ 62 /* Common bits */ \ 63 V_(SixtyFourBits, 31, 31, ExtractBits) \ 64 V_(FlagsUpdate, 29, 29, ExtractBits) \ 65 \ 66 /* PC relative addressing */ \ 67 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \ 68 V_(ImmPCRelLo, 30, 29, ExtractBits) \ 69 \ 70 /* Add/subtract/logical shift register */ \ 71 V_(ShiftDP, 23, 22, ExtractBits) \ 72 V_(ImmDPShift, 15, 10, ExtractBits) \ 73 \ 74 /* Add/subtract immediate */ \ 75 V_(ImmAddSub, 21, 10, ExtractBits) \ 76 V_(ShiftAddSub, 23, 22, ExtractBits) \ 77 \ 78 /* Add/substract extend */ \ 79 V_(ImmExtendShift, 12, 10, ExtractBits) \ 80 V_(ExtendMode, 15, 13, ExtractBits) \ 81 \ 82 /* Move wide */ \ 83 V_(ImmMoveWide, 20, 5, ExtractBits) \ 84 V_(ShiftMoveWide, 22, 21, ExtractBits) \ 85 \ 86 /* Logical immediate, bitfield and extract */ \ 87 V_(BitN, 22, 22, ExtractBits) \ 88 V_(ImmRotate, 21, 16, ExtractBits) \ 89 V_(ImmSetBits, 15, 10, ExtractBits) \ 90 V_(ImmR, 21, 16, ExtractBits) \ 91 V_(ImmS, 15, 10, ExtractBits) \ 92 \ 93 /* Test and branch immediate */ \ 94 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \ 95 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \ 96 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \ 97 \ 98 /* Conditionals */ \ 99 V_(Condition, 15, 12, ExtractBits) \ 100 V_(ConditionBranch, 3, 0, ExtractBits) \ 101 V_(Nzcv, 3, 0, ExtractBits) \ 102 V_(ImmCondCmp, 20, 16, ExtractBits) \ 103 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \ 104 \ 105 /* Floating point */ \ 106 V_(FPType, 23, 22, ExtractBits) \ 107 V_(ImmFP, 20, 13, ExtractBits) \ 108 V_(FPScale, 15, 10, ExtractBits) \ 109 \ 110 /* Load Store */ \ 111 V_(ImmLS, 20, 12, ExtractSignedBits) \ 112 V_(ImmLSUnsigned, 21, 10, ExtractBits) \ 113 V_(ImmLSPair, 21, 15, ExtractSignedBits) \ 114 V_(ImmShiftLS, 12, 12, ExtractBits) \ 115 V_(LSOpc, 23, 22, ExtractBits) \ 116 V_(LSVector, 26, 26, ExtractBits) \ 117 V_(LSSize, 31, 30, ExtractBits) \ 118 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \ 119 V_(PrefetchHint, 4, 3, ExtractBits) \ 120 V_(PrefetchTarget, 2, 1, ExtractBits) \ 121 V_(PrefetchStream, 0, 0, ExtractBits) \ 122 \ 123 /* Other immediates */ \ 124 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \ 125 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \ 126 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \ 127 V_(ImmException, 20, 5, ExtractBits) \ 128 V_(ImmHint, 11, 5, ExtractBits) \ 129 V_(ImmBarrierDomain, 11, 10, ExtractBits) \ 130 V_(ImmBarrierType, 9, 8, ExtractBits) \ 131 \ 132 /* System (MRS, MSR, SYS) */ \ 133 V_(ImmSystemRegister, 20, 5, ExtractBits) \ 134 V_(SysO0, 19, 19, ExtractBits) \ 135 V_(SysOp, 18, 5, ExtractBits) \ 136 V_(SysOp0, 20, 19, ExtractBits) \ 137 V_(SysOp1, 18, 16, ExtractBits) \ 138 V_(SysOp2, 7, 5, ExtractBits) \ 139 V_(CRn, 15, 12, ExtractBits) \ 140 V_(CRm, 11, 8, ExtractBits) \ 141 \ 142 /* Load-/store-exclusive */ \ 143 V_(LdStXLoad, 22, 22, ExtractBits) \ 144 V_(LdStXNotExclusive, 23, 23, ExtractBits) \ 145 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \ 146 V_(LdStXSizeLog2, 31, 30, ExtractBits) \ 147 V_(LdStXPair, 21, 21, ExtractBits) \ 148 \ 149 /* NEON generic fields */ \ 150 V_(NEONQ, 30, 30, ExtractBits) \ 151 V_(NEONSize, 23, 22, ExtractBits) \ 152 V_(NEONLSSize, 11, 10, ExtractBits) \ 153 V_(NEONS, 12, 12, ExtractBits) \ 154 V_(NEONL, 21, 21, ExtractBits) \ 155 V_(NEONM, 20, 20, ExtractBits) \ 156 V_(NEONH, 11, 11, ExtractBits) \ 157 V_(ImmNEONExt, 14, 11, ExtractBits) \ 158 V_(ImmNEON5, 20, 16, ExtractBits) \ 159 V_(ImmNEON4, 14, 11, ExtractBits) \ 160 \ 161 /* NEON Modified Immediate fields */ \ 162 V_(ImmNEONabc, 18, 16, ExtractBits) \ 163 V_(ImmNEONdefgh, 9, 5, ExtractBits) \ 164 V_(NEONModImmOp, 29, 29, ExtractBits) \ 165 V_(NEONCmode, 15, 12, ExtractBits) \ 166 \ 167 /* NEON Shift Immediate fields */ \ 168 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \ 169 V_(ImmNEONImmh, 22, 19, ExtractBits) \ 170 V_(ImmNEONImmb, 18, 16, ExtractBits) 171 // clang-format on 172 173 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 174 /* NZCV */ \ 175 V_(Flags, 31, 28, ExtractBits) \ 176 V_(N, 31, 31, ExtractBits) \ 177 V_(Z, 30, 30, ExtractBits) \ 178 V_(C, 29, 29, ExtractBits) \ 179 V_(V, 28, 28, ExtractBits) \ 180 M_(NZCV, Flags_mask) \ 181 /* FPCR */ \ 182 V_(AHP, 26, 26, ExtractBits) \ 183 V_(DN, 25, 25, ExtractBits) \ 184 V_(FZ, 24, 24, ExtractBits) \ 185 V_(RMode, 23, 22, ExtractBits) \ 186 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 187 188 // Fields offsets. 189 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 190 const int Name##_offset = LowBit; \ 191 const int Name##_width = HighBit - LowBit + 1; \ 192 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 193 #define NOTHING(A, B) 194 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 195 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 196 #undef NOTHING 197 #undef DECLARE_FIELDS_BITS 198 199 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 200 // from ImmPCRelLo and ImmPCRelHi. 201 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 202 203 // Disable `clang-format` for the `enum`s below. We care about the manual 204 // formatting that `clang-format` would destroy. 205 // clang-format off 206 207 // Condition codes. 208 enum Condition { 209 eq = 0, // Z set Equal. 210 ne = 1, // Z clear Not equal. 211 cs = 2, // C set Carry set. 212 cc = 3, // C clear Carry clear. 213 mi = 4, // N set Negative. 214 pl = 5, // N clear Positive or zero. 215 vs = 6, // V set Overflow. 216 vc = 7, // V clear No overflow. 217 hi = 8, // C set, Z clear Unsigned higher. 218 ls = 9, // C clear or Z set Unsigned lower or same. 219 ge = 10, // N == V Greater or equal. 220 lt = 11, // N != V Less than. 221 gt = 12, // Z clear, N == V Greater than. 222 le = 13, // Z set or N != V Less then or equal 223 al = 14, // Always. 224 nv = 15, // Behaves as always/al. 225 226 // Aliases. 227 hs = cs, // C set Unsigned higher or same. 228 lo = cc // C clear Unsigned lower. 229 }; 230 231 inline Condition InvertCondition(Condition cond) { 232 // Conditions al and nv behave identically, as "always true". They can't be 233 // inverted, because there is no "always false" condition. 234 VIXL_ASSERT((cond != al) && (cond != nv)); 235 return static_cast<Condition>(cond ^ 1); 236 } 237 238 enum FPTrapFlags { 239 EnableTrap = 1, 240 DisableTrap = 0 241 }; 242 243 enum FlagsUpdate { 244 SetFlags = 1, 245 LeaveFlags = 0 246 }; 247 248 enum StatusFlags { 249 NoFlag = 0, 250 251 // Derive the flag combinations from the system register bit descriptions. 252 NFlag = N_mask, 253 ZFlag = Z_mask, 254 CFlag = C_mask, 255 VFlag = V_mask, 256 NZFlag = NFlag | ZFlag, 257 NCFlag = NFlag | CFlag, 258 NVFlag = NFlag | VFlag, 259 ZCFlag = ZFlag | CFlag, 260 ZVFlag = ZFlag | VFlag, 261 CVFlag = CFlag | VFlag, 262 NZCFlag = NFlag | ZFlag | CFlag, 263 NZVFlag = NFlag | ZFlag | VFlag, 264 NCVFlag = NFlag | CFlag | VFlag, 265 ZCVFlag = ZFlag | CFlag | VFlag, 266 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 267 268 // Floating-point comparison results. 269 FPEqualFlag = ZCFlag, 270 FPLessThanFlag = NFlag, 271 FPGreaterThanFlag = CFlag, 272 FPUnorderedFlag = CVFlag 273 }; 274 275 enum Shift { 276 NO_SHIFT = -1, 277 LSL = 0x0, 278 LSR = 0x1, 279 ASR = 0x2, 280 ROR = 0x3, 281 MSL = 0x4 282 }; 283 284 enum Extend { 285 NO_EXTEND = -1, 286 UXTB = 0, 287 UXTH = 1, 288 UXTW = 2, 289 UXTX = 3, 290 SXTB = 4, 291 SXTH = 5, 292 SXTW = 6, 293 SXTX = 7 294 }; 295 296 enum SystemHint { 297 NOP = 0, 298 YIELD = 1, 299 WFE = 2, 300 WFI = 3, 301 SEV = 4, 302 SEVL = 5 303 }; 304 305 enum BarrierDomain { 306 OuterShareable = 0, 307 NonShareable = 1, 308 InnerShareable = 2, 309 FullSystem = 3 310 }; 311 312 enum BarrierType { 313 BarrierOther = 0, 314 BarrierReads = 1, 315 BarrierWrites = 2, 316 BarrierAll = 3 317 }; 318 319 enum PrefetchOperation { 320 PLDL1KEEP = 0x00, 321 PLDL1STRM = 0x01, 322 PLDL2KEEP = 0x02, 323 PLDL2STRM = 0x03, 324 PLDL3KEEP = 0x04, 325 PLDL3STRM = 0x05, 326 327 PLIL1KEEP = 0x08, 328 PLIL1STRM = 0x09, 329 PLIL2KEEP = 0x0a, 330 PLIL2STRM = 0x0b, 331 PLIL3KEEP = 0x0c, 332 PLIL3STRM = 0x0d, 333 334 PSTL1KEEP = 0x10, 335 PSTL1STRM = 0x11, 336 PSTL2KEEP = 0x12, 337 PSTL2STRM = 0x13, 338 PSTL3KEEP = 0x14, 339 PSTL3STRM = 0x15 340 }; 341 342 template<int op0, int op1, int crn, int crm, int op2> 343 class SystemRegisterEncoder { 344 public: 345 static const uint32_t value = 346 ((op0 << SysO0_offset) | 347 (op1 << SysOp1_offset) | 348 (crn << CRn_offset) | 349 (crm << CRm_offset) | 350 (op2 << SysOp2_offset)) >> ImmSystemRegister_offset; 351 }; 352 353 // System/special register names. 354 // This information is not encoded as one field but as the concatenation of 355 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). 356 enum SystemRegister { 357 NZCV = SystemRegisterEncoder<3, 3, 4, 2, 0>::value, 358 FPCR = SystemRegisterEncoder<3, 3, 4, 4, 0>::value 359 }; 360 361 enum InstructionCacheOp { 362 IVAU = ((0x3 << SysOp1_offset) | 363 (0x7 << CRn_offset) | 364 (0x5 << CRm_offset) | 365 (0x1 << SysOp2_offset)) >> SysOp_offset 366 }; 367 368 enum DataCacheOp { 369 CVAC = ((0x3 << SysOp1_offset) | 370 (0x7 << CRn_offset) | 371 (0xa << CRm_offset) | 372 (0x1 << SysOp2_offset)) >> SysOp_offset, 373 CVAU = ((0x3 << SysOp1_offset) | 374 (0x7 << CRn_offset) | 375 (0xb << CRm_offset) | 376 (0x1 << SysOp2_offset)) >> SysOp_offset, 377 CIVAC = ((0x3 << SysOp1_offset) | 378 (0x7 << CRn_offset) | 379 (0xe << CRm_offset) | 380 (0x1 << SysOp2_offset)) >> SysOp_offset, 381 ZVA = ((0x3 << SysOp1_offset) | 382 (0x7 << CRn_offset) | 383 (0x4 << CRm_offset) | 384 (0x1 << SysOp2_offset)) >> SysOp_offset 385 }; 386 387 // Instruction enumerations. 388 // 389 // These are the masks that define a class of instructions, and the list of 390 // instructions within each class. Each enumeration has a Fixed, FMask and 391 // Mask value. 392 // 393 // Fixed: The fixed bits in this instruction class. 394 // FMask: The mask used to extract the fixed bits in the class. 395 // Mask: The mask used to identify the instructions within a class. 396 // 397 // The enumerations can be used like this: 398 // 399 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 400 // switch(instr->Mask(PCRelAddressingMask)) { 401 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 402 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 403 // default: printf("Unknown instruction\n"); 404 // } 405 406 407 // Generic fields. 408 enum GenericInstrField { 409 SixtyFourBits = 0x80000000, 410 ThirtyTwoBits = 0x00000000, 411 FP32 = 0x00000000, 412 FP64 = 0x00400000 413 }; 414 415 enum NEONFormatField { 416 NEONFormatFieldMask = 0x40C00000, 417 NEON_Q = 0x40000000, 418 NEON_8B = 0x00000000, 419 NEON_16B = NEON_8B | NEON_Q, 420 NEON_4H = 0x00400000, 421 NEON_8H = NEON_4H | NEON_Q, 422 NEON_2S = 0x00800000, 423 NEON_4S = NEON_2S | NEON_Q, 424 NEON_1D = 0x00C00000, 425 NEON_2D = 0x00C00000 | NEON_Q 426 }; 427 428 enum NEONFPFormatField { 429 NEONFPFormatFieldMask = 0x40400000, 430 NEON_FP_2S = FP32, 431 NEON_FP_4S = FP32 | NEON_Q, 432 NEON_FP_2D = FP64 | NEON_Q 433 }; 434 435 enum NEONLSFormatField { 436 NEONLSFormatFieldMask = 0x40000C00, 437 LS_NEON_8B = 0x00000000, 438 LS_NEON_16B = LS_NEON_8B | NEON_Q, 439 LS_NEON_4H = 0x00000400, 440 LS_NEON_8H = LS_NEON_4H | NEON_Q, 441 LS_NEON_2S = 0x00000800, 442 LS_NEON_4S = LS_NEON_2S | NEON_Q, 443 LS_NEON_1D = 0x00000C00, 444 LS_NEON_2D = LS_NEON_1D | NEON_Q 445 }; 446 447 enum NEONScalarFormatField { 448 NEONScalarFormatFieldMask = 0x00C00000, 449 NEONScalar = 0x10000000, 450 NEON_B = 0x00000000, 451 NEON_H = 0x00400000, 452 NEON_S = 0x00800000, 453 NEON_D = 0x00C00000 454 }; 455 456 // PC relative addressing. 457 enum PCRelAddressingOp { 458 PCRelAddressingFixed = 0x10000000, 459 PCRelAddressingFMask = 0x1F000000, 460 PCRelAddressingMask = 0x9F000000, 461 ADR = PCRelAddressingFixed | 0x00000000, 462 ADRP = PCRelAddressingFixed | 0x80000000 463 }; 464 465 // Add/sub (immediate, shifted and extended.) 466 const int kSFOffset = 31; 467 enum AddSubOp { 468 AddSubOpMask = 0x60000000, 469 AddSubSetFlagsBit = 0x20000000, 470 ADD = 0x00000000, 471 ADDS = ADD | AddSubSetFlagsBit, 472 SUB = 0x40000000, 473 SUBS = SUB | AddSubSetFlagsBit 474 }; 475 476 #define ADD_SUB_OP_LIST(V) \ 477 V(ADD), \ 478 V(ADDS), \ 479 V(SUB), \ 480 V(SUBS) 481 482 enum AddSubImmediateOp { 483 AddSubImmediateFixed = 0x11000000, 484 AddSubImmediateFMask = 0x1F000000, 485 AddSubImmediateMask = 0xFF000000, 486 #define ADD_SUB_IMMEDIATE(A) \ 487 A##_w_imm = AddSubImmediateFixed | A, \ 488 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 489 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 490 #undef ADD_SUB_IMMEDIATE 491 }; 492 493 enum AddSubShiftedOp { 494 AddSubShiftedFixed = 0x0B000000, 495 AddSubShiftedFMask = 0x1F200000, 496 AddSubShiftedMask = 0xFF200000, 497 #define ADD_SUB_SHIFTED(A) \ 498 A##_w_shift = AddSubShiftedFixed | A, \ 499 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 500 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 501 #undef ADD_SUB_SHIFTED 502 }; 503 504 enum AddSubExtendedOp { 505 AddSubExtendedFixed = 0x0B200000, 506 AddSubExtendedFMask = 0x1F200000, 507 AddSubExtendedMask = 0xFFE00000, 508 #define ADD_SUB_EXTENDED(A) \ 509 A##_w_ext = AddSubExtendedFixed | A, \ 510 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 511 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 512 #undef ADD_SUB_EXTENDED 513 }; 514 515 // Add/sub with carry. 516 enum AddSubWithCarryOp { 517 AddSubWithCarryFixed = 0x1A000000, 518 AddSubWithCarryFMask = 0x1FE00000, 519 AddSubWithCarryMask = 0xFFE0FC00, 520 ADC_w = AddSubWithCarryFixed | ADD, 521 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 522 ADC = ADC_w, 523 ADCS_w = AddSubWithCarryFixed | ADDS, 524 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 525 SBC_w = AddSubWithCarryFixed | SUB, 526 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 527 SBC = SBC_w, 528 SBCS_w = AddSubWithCarryFixed | SUBS, 529 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 530 }; 531 532 533 // Logical (immediate and shifted register). 534 enum LogicalOp { 535 LogicalOpMask = 0x60200000, 536 NOT = 0x00200000, 537 AND = 0x00000000, 538 BIC = AND | NOT, 539 ORR = 0x20000000, 540 ORN = ORR | NOT, 541 EOR = 0x40000000, 542 EON = EOR | NOT, 543 ANDS = 0x60000000, 544 BICS = ANDS | NOT 545 }; 546 547 // Logical immediate. 548 enum LogicalImmediateOp { 549 LogicalImmediateFixed = 0x12000000, 550 LogicalImmediateFMask = 0x1F800000, 551 LogicalImmediateMask = 0xFF800000, 552 AND_w_imm = LogicalImmediateFixed | AND, 553 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 554 ORR_w_imm = LogicalImmediateFixed | ORR, 555 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 556 EOR_w_imm = LogicalImmediateFixed | EOR, 557 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 558 ANDS_w_imm = LogicalImmediateFixed | ANDS, 559 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 560 }; 561 562 // Logical shifted register. 563 enum LogicalShiftedOp { 564 LogicalShiftedFixed = 0x0A000000, 565 LogicalShiftedFMask = 0x1F000000, 566 LogicalShiftedMask = 0xFF200000, 567 AND_w = LogicalShiftedFixed | AND, 568 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 569 AND_shift = AND_w, 570 BIC_w = LogicalShiftedFixed | BIC, 571 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 572 BIC_shift = BIC_w, 573 ORR_w = LogicalShiftedFixed | ORR, 574 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 575 ORR_shift = ORR_w, 576 ORN_w = LogicalShiftedFixed | ORN, 577 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 578 ORN_shift = ORN_w, 579 EOR_w = LogicalShiftedFixed | EOR, 580 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 581 EOR_shift = EOR_w, 582 EON_w = LogicalShiftedFixed | EON, 583 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 584 EON_shift = EON_w, 585 ANDS_w = LogicalShiftedFixed | ANDS, 586 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 587 ANDS_shift = ANDS_w, 588 BICS_w = LogicalShiftedFixed | BICS, 589 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 590 BICS_shift = BICS_w 591 }; 592 593 // Move wide immediate. 594 enum MoveWideImmediateOp { 595 MoveWideImmediateFixed = 0x12800000, 596 MoveWideImmediateFMask = 0x1F800000, 597 MoveWideImmediateMask = 0xFF800000, 598 MOVN = 0x00000000, 599 MOVZ = 0x40000000, 600 MOVK = 0x60000000, 601 MOVN_w = MoveWideImmediateFixed | MOVN, 602 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 603 MOVZ_w = MoveWideImmediateFixed | MOVZ, 604 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 605 MOVK_w = MoveWideImmediateFixed | MOVK, 606 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 607 }; 608 609 // Bitfield. 610 const int kBitfieldNOffset = 22; 611 enum BitfieldOp { 612 BitfieldFixed = 0x13000000, 613 BitfieldFMask = 0x1F800000, 614 BitfieldMask = 0xFF800000, 615 SBFM_w = BitfieldFixed | 0x00000000, 616 SBFM_x = BitfieldFixed | 0x80000000, 617 SBFM = SBFM_w, 618 BFM_w = BitfieldFixed | 0x20000000, 619 BFM_x = BitfieldFixed | 0xA0000000, 620 BFM = BFM_w, 621 UBFM_w = BitfieldFixed | 0x40000000, 622 UBFM_x = BitfieldFixed | 0xC0000000, 623 UBFM = UBFM_w 624 // Bitfield N field. 625 }; 626 627 // Extract. 628 enum ExtractOp { 629 ExtractFixed = 0x13800000, 630 ExtractFMask = 0x1F800000, 631 ExtractMask = 0xFFA00000, 632 EXTR_w = ExtractFixed | 0x00000000, 633 EXTR_x = ExtractFixed | 0x80000000, 634 EXTR = EXTR_w 635 }; 636 637 // Unconditional branch. 638 enum UnconditionalBranchOp { 639 UnconditionalBranchFixed = 0x14000000, 640 UnconditionalBranchFMask = 0x7C000000, 641 UnconditionalBranchMask = 0xFC000000, 642 B = UnconditionalBranchFixed | 0x00000000, 643 BL = UnconditionalBranchFixed | 0x80000000 644 }; 645 646 // Unconditional branch to register. 647 enum UnconditionalBranchToRegisterOp { 648 UnconditionalBranchToRegisterFixed = 0xD6000000, 649 UnconditionalBranchToRegisterFMask = 0xFE000000, 650 UnconditionalBranchToRegisterMask = 0xFFFFFC1F, 651 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 652 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 653 RET = UnconditionalBranchToRegisterFixed | 0x005F0000 654 }; 655 656 // Compare and branch. 657 enum CompareBranchOp { 658 CompareBranchFixed = 0x34000000, 659 CompareBranchFMask = 0x7E000000, 660 CompareBranchMask = 0xFF000000, 661 CBZ_w = CompareBranchFixed | 0x00000000, 662 CBZ_x = CompareBranchFixed | 0x80000000, 663 CBZ = CBZ_w, 664 CBNZ_w = CompareBranchFixed | 0x01000000, 665 CBNZ_x = CompareBranchFixed | 0x81000000, 666 CBNZ = CBNZ_w 667 }; 668 669 // Test and branch. 670 enum TestBranchOp { 671 TestBranchFixed = 0x36000000, 672 TestBranchFMask = 0x7E000000, 673 TestBranchMask = 0x7F000000, 674 TBZ = TestBranchFixed | 0x00000000, 675 TBNZ = TestBranchFixed | 0x01000000 676 }; 677 678 // Conditional branch. 679 enum ConditionalBranchOp { 680 ConditionalBranchFixed = 0x54000000, 681 ConditionalBranchFMask = 0xFE000000, 682 ConditionalBranchMask = 0xFF000010, 683 B_cond = ConditionalBranchFixed | 0x00000000 684 }; 685 686 // System. 687 // System instruction encoding is complicated because some instructions use op 688 // and CR fields to encode parameters. To handle this cleanly, the system 689 // instructions are split into more than one enum. 690 691 enum SystemOp { 692 SystemFixed = 0xD5000000, 693 SystemFMask = 0xFFC00000 694 }; 695 696 enum SystemSysRegOp { 697 SystemSysRegFixed = 0xD5100000, 698 SystemSysRegFMask = 0xFFD00000, 699 SystemSysRegMask = 0xFFF00000, 700 MRS = SystemSysRegFixed | 0x00200000, 701 MSR = SystemSysRegFixed | 0x00000000 702 }; 703 704 enum SystemHintOp { 705 SystemHintFixed = 0xD503201F, 706 SystemHintFMask = 0xFFFFF01F, 707 SystemHintMask = 0xFFFFF01F, 708 HINT = SystemHintFixed | 0x00000000 709 }; 710 711 enum SystemSysOp { 712 SystemSysFixed = 0xD5080000, 713 SystemSysFMask = 0xFFF80000, 714 SystemSysMask = 0xFFF80000, 715 SYS = SystemSysFixed | 0x00000000 716 }; 717 718 // Exception. 719 enum ExceptionOp { 720 ExceptionFixed = 0xD4000000, 721 ExceptionFMask = 0xFF000000, 722 ExceptionMask = 0xFFE0001F, 723 HLT = ExceptionFixed | 0x00400000, 724 BRK = ExceptionFixed | 0x00200000, 725 SVC = ExceptionFixed | 0x00000001, 726 HVC = ExceptionFixed | 0x00000002, 727 SMC = ExceptionFixed | 0x00000003, 728 DCPS1 = ExceptionFixed | 0x00A00001, 729 DCPS2 = ExceptionFixed | 0x00A00002, 730 DCPS3 = ExceptionFixed | 0x00A00003 731 }; 732 733 enum MemBarrierOp { 734 MemBarrierFixed = 0xD503309F, 735 MemBarrierFMask = 0xFFFFF09F, 736 MemBarrierMask = 0xFFFFF0FF, 737 DSB = MemBarrierFixed | 0x00000000, 738 DMB = MemBarrierFixed | 0x00000020, 739 ISB = MemBarrierFixed | 0x00000040 740 }; 741 742 enum SystemExclusiveMonitorOp { 743 SystemExclusiveMonitorFixed = 0xD503305F, 744 SystemExclusiveMonitorFMask = 0xFFFFF0FF, 745 SystemExclusiveMonitorMask = 0xFFFFF0FF, 746 CLREX = SystemExclusiveMonitorFixed 747 }; 748 749 // Any load or store. 750 enum LoadStoreAnyOp { 751 LoadStoreAnyFMask = 0x0a000000, 752 LoadStoreAnyFixed = 0x08000000 753 }; 754 755 // Any load pair or store pair. 756 enum LoadStorePairAnyOp { 757 LoadStorePairAnyFMask = 0x3a000000, 758 LoadStorePairAnyFixed = 0x28000000 759 }; 760 761 #define LOAD_STORE_PAIR_OP_LIST(V) \ 762 V(STP, w, 0x00000000), \ 763 V(LDP, w, 0x00400000), \ 764 V(LDPSW, x, 0x40400000), \ 765 V(STP, x, 0x80000000), \ 766 V(LDP, x, 0x80400000), \ 767 V(STP, s, 0x04000000), \ 768 V(LDP, s, 0x04400000), \ 769 V(STP, d, 0x44000000), \ 770 V(LDP, d, 0x44400000), \ 771 V(STP, q, 0x84000000), \ 772 V(LDP, q, 0x84400000) 773 774 // Load/store pair (post, pre and offset.) 775 enum LoadStorePairOp { 776 LoadStorePairMask = 0xC4400000, 777 LoadStorePairLBit = 1 << 22, 778 #define LOAD_STORE_PAIR(A, B, C) \ 779 A##_##B = C 780 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 781 #undef LOAD_STORE_PAIR 782 }; 783 784 enum LoadStorePairPostIndexOp { 785 LoadStorePairPostIndexFixed = 0x28800000, 786 LoadStorePairPostIndexFMask = 0x3B800000, 787 LoadStorePairPostIndexMask = 0xFFC00000, 788 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 789 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 790 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 791 #undef LOAD_STORE_PAIR_POST_INDEX 792 }; 793 794 enum LoadStorePairPreIndexOp { 795 LoadStorePairPreIndexFixed = 0x29800000, 796 LoadStorePairPreIndexFMask = 0x3B800000, 797 LoadStorePairPreIndexMask = 0xFFC00000, 798 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 799 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 800 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 801 #undef LOAD_STORE_PAIR_PRE_INDEX 802 }; 803 804 enum LoadStorePairOffsetOp { 805 LoadStorePairOffsetFixed = 0x29000000, 806 LoadStorePairOffsetFMask = 0x3B800000, 807 LoadStorePairOffsetMask = 0xFFC00000, 808 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 809 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 810 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 811 #undef LOAD_STORE_PAIR_OFFSET 812 }; 813 814 enum LoadStorePairNonTemporalOp { 815 LoadStorePairNonTemporalFixed = 0x28000000, 816 LoadStorePairNonTemporalFMask = 0x3B800000, 817 LoadStorePairNonTemporalMask = 0xFFC00000, 818 LoadStorePairNonTemporalLBit = 1 << 22, 819 STNP_w = LoadStorePairNonTemporalFixed | STP_w, 820 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 821 STNP_x = LoadStorePairNonTemporalFixed | STP_x, 822 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 823 STNP_s = LoadStorePairNonTemporalFixed | STP_s, 824 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 825 STNP_d = LoadStorePairNonTemporalFixed | STP_d, 826 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d, 827 STNP_q = LoadStorePairNonTemporalFixed | STP_q, 828 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q 829 }; 830 831 // Load literal. 832 enum LoadLiteralOp { 833 LoadLiteralFixed = 0x18000000, 834 LoadLiteralFMask = 0x3B000000, 835 LoadLiteralMask = 0xFF000000, 836 LDR_w_lit = LoadLiteralFixed | 0x00000000, 837 LDR_x_lit = LoadLiteralFixed | 0x40000000, 838 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 839 PRFM_lit = LoadLiteralFixed | 0xC0000000, 840 LDR_s_lit = LoadLiteralFixed | 0x04000000, 841 LDR_d_lit = LoadLiteralFixed | 0x44000000, 842 LDR_q_lit = LoadLiteralFixed | 0x84000000 843 }; 844 845 #define LOAD_STORE_OP_LIST(V) \ 846 V(ST, RB, w, 0x00000000), \ 847 V(ST, RH, w, 0x40000000), \ 848 V(ST, R, w, 0x80000000), \ 849 V(ST, R, x, 0xC0000000), \ 850 V(LD, RB, w, 0x00400000), \ 851 V(LD, RH, w, 0x40400000), \ 852 V(LD, R, w, 0x80400000), \ 853 V(LD, R, x, 0xC0400000), \ 854 V(LD, RSB, x, 0x00800000), \ 855 V(LD, RSH, x, 0x40800000), \ 856 V(LD, RSW, x, 0x80800000), \ 857 V(LD, RSB, w, 0x00C00000), \ 858 V(LD, RSH, w, 0x40C00000), \ 859 V(ST, R, b, 0x04000000), \ 860 V(ST, R, h, 0x44000000), \ 861 V(ST, R, s, 0x84000000), \ 862 V(ST, R, d, 0xC4000000), \ 863 V(ST, R, q, 0x04800000), \ 864 V(LD, R, b, 0x04400000), \ 865 V(LD, R, h, 0x44400000), \ 866 V(LD, R, s, 0x84400000), \ 867 V(LD, R, d, 0xC4400000), \ 868 V(LD, R, q, 0x04C00000) 869 870 // Load/store (post, pre, offset and unsigned.) 871 enum LoadStoreOp { 872 LoadStoreMask = 0xC4C00000, 873 LoadStoreVMask = 0x04000000, 874 #define LOAD_STORE(A, B, C, D) \ 875 A##B##_##C = D 876 LOAD_STORE_OP_LIST(LOAD_STORE), 877 #undef LOAD_STORE 878 PRFM = 0xC0800000 879 }; 880 881 // Load/store unscaled offset. 882 enum LoadStoreUnscaledOffsetOp { 883 LoadStoreUnscaledOffsetFixed = 0x38000000, 884 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 885 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 886 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, 887 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 888 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 889 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 890 #undef LOAD_STORE_UNSCALED 891 }; 892 893 // Load/store post index. 894 enum LoadStorePostIndex { 895 LoadStorePostIndexFixed = 0x38000400, 896 LoadStorePostIndexFMask = 0x3B200C00, 897 LoadStorePostIndexMask = 0xFFE00C00, 898 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 899 A##B##_##C##_post = LoadStorePostIndexFixed | D 900 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 901 #undef LOAD_STORE_POST_INDEX 902 }; 903 904 // Load/store pre index. 905 enum LoadStorePreIndex { 906 LoadStorePreIndexFixed = 0x38000C00, 907 LoadStorePreIndexFMask = 0x3B200C00, 908 LoadStorePreIndexMask = 0xFFE00C00, 909 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 910 A##B##_##C##_pre = LoadStorePreIndexFixed | D 911 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 912 #undef LOAD_STORE_PRE_INDEX 913 }; 914 915 // Load/store unsigned offset. 916 enum LoadStoreUnsignedOffset { 917 LoadStoreUnsignedOffsetFixed = 0x39000000, 918 LoadStoreUnsignedOffsetFMask = 0x3B000000, 919 LoadStoreUnsignedOffsetMask = 0xFFC00000, 920 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 921 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 922 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 923 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 924 #undef LOAD_STORE_UNSIGNED_OFFSET 925 }; 926 927 // Load/store register offset. 928 enum LoadStoreRegisterOffset { 929 LoadStoreRegisterOffsetFixed = 0x38200800, 930 LoadStoreRegisterOffsetFMask = 0x3B200C00, 931 LoadStoreRegisterOffsetMask = 0xFFE00C00, 932 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 933 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 934 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 935 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 936 #undef LOAD_STORE_REGISTER_OFFSET 937 }; 938 939 enum LoadStoreExclusive { 940 LoadStoreExclusiveFixed = 0x08000000, 941 LoadStoreExclusiveFMask = 0x3F000000, 942 LoadStoreExclusiveMask = 0xFFE08000, 943 STXRB_w = LoadStoreExclusiveFixed | 0x00000000, 944 STXRH_w = LoadStoreExclusiveFixed | 0x40000000, 945 STXR_w = LoadStoreExclusiveFixed | 0x80000000, 946 STXR_x = LoadStoreExclusiveFixed | 0xC0000000, 947 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, 948 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, 949 LDXR_w = LoadStoreExclusiveFixed | 0x80400000, 950 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, 951 STXP_w = LoadStoreExclusiveFixed | 0x80200000, 952 STXP_x = LoadStoreExclusiveFixed | 0xC0200000, 953 LDXP_w = LoadStoreExclusiveFixed | 0x80600000, 954 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, 955 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, 956 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, 957 STLXR_w = LoadStoreExclusiveFixed | 0x80008000, 958 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, 959 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, 960 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, 961 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, 962 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, 963 STLXP_w = LoadStoreExclusiveFixed | 0x80208000, 964 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, 965 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, 966 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, 967 STLRB_w = LoadStoreExclusiveFixed | 0x00808000, 968 STLRH_w = LoadStoreExclusiveFixed | 0x40808000, 969 STLR_w = LoadStoreExclusiveFixed | 0x80808000, 970 STLR_x = LoadStoreExclusiveFixed | 0xC0808000, 971 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, 972 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, 973 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, 974 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000 975 }; 976 977 // Conditional compare. 978 enum ConditionalCompareOp { 979 ConditionalCompareMask = 0x60000000, 980 CCMN = 0x20000000, 981 CCMP = 0x60000000 982 }; 983 984 // Conditional compare register. 985 enum ConditionalCompareRegisterOp { 986 ConditionalCompareRegisterFixed = 0x1A400000, 987 ConditionalCompareRegisterFMask = 0x1FE00800, 988 ConditionalCompareRegisterMask = 0xFFE00C10, 989 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 990 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 991 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 992 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 993 }; 994 995 // Conditional compare immediate. 996 enum ConditionalCompareImmediateOp { 997 ConditionalCompareImmediateFixed = 0x1A400800, 998 ConditionalCompareImmediateFMask = 0x1FE00800, 999 ConditionalCompareImmediateMask = 0xFFE00C10, 1000 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 1001 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 1002 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 1003 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 1004 }; 1005 1006 // Conditional select. 1007 enum ConditionalSelectOp { 1008 ConditionalSelectFixed = 0x1A800000, 1009 ConditionalSelectFMask = 0x1FE00000, 1010 ConditionalSelectMask = 0xFFE00C00, 1011 CSEL_w = ConditionalSelectFixed | 0x00000000, 1012 CSEL_x = ConditionalSelectFixed | 0x80000000, 1013 CSEL = CSEL_w, 1014 CSINC_w = ConditionalSelectFixed | 0x00000400, 1015 CSINC_x = ConditionalSelectFixed | 0x80000400, 1016 CSINC = CSINC_w, 1017 CSINV_w = ConditionalSelectFixed | 0x40000000, 1018 CSINV_x = ConditionalSelectFixed | 0xC0000000, 1019 CSINV = CSINV_w, 1020 CSNEG_w = ConditionalSelectFixed | 0x40000400, 1021 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 1022 CSNEG = CSNEG_w 1023 }; 1024 1025 // Data processing 1 source. 1026 enum DataProcessing1SourceOp { 1027 DataProcessing1SourceFixed = 0x5AC00000, 1028 DataProcessing1SourceFMask = 0x5FE00000, 1029 DataProcessing1SourceMask = 0xFFFFFC00, 1030 RBIT = DataProcessing1SourceFixed | 0x00000000, 1031 RBIT_w = RBIT, 1032 RBIT_x = RBIT | SixtyFourBits, 1033 REV16 = DataProcessing1SourceFixed | 0x00000400, 1034 REV16_w = REV16, 1035 REV16_x = REV16 | SixtyFourBits, 1036 REV = DataProcessing1SourceFixed | 0x00000800, 1037 REV_w = REV, 1038 REV32_x = REV | SixtyFourBits, 1039 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 1040 CLZ = DataProcessing1SourceFixed | 0x00001000, 1041 CLZ_w = CLZ, 1042 CLZ_x = CLZ | SixtyFourBits, 1043 CLS = DataProcessing1SourceFixed | 0x00001400, 1044 CLS_w = CLS, 1045 CLS_x = CLS | SixtyFourBits 1046 }; 1047 1048 // Data processing 2 source. 1049 enum DataProcessing2SourceOp { 1050 DataProcessing2SourceFixed = 0x1AC00000, 1051 DataProcessing2SourceFMask = 0x5FE00000, 1052 DataProcessing2SourceMask = 0xFFE0FC00, 1053 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 1054 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 1055 UDIV = UDIV_w, 1056 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 1057 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 1058 SDIV = SDIV_w, 1059 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 1060 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 1061 LSLV = LSLV_w, 1062 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 1063 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 1064 LSRV = LSRV_w, 1065 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 1066 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 1067 ASRV = ASRV_w, 1068 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 1069 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 1070 RORV = RORV_w, 1071 CRC32B = DataProcessing2SourceFixed | 0x00004000, 1072 CRC32H = DataProcessing2SourceFixed | 0x00004400, 1073 CRC32W = DataProcessing2SourceFixed | 0x00004800, 1074 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 1075 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 1076 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 1077 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 1078 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 1079 }; 1080 1081 // Data processing 3 source. 1082 enum DataProcessing3SourceOp { 1083 DataProcessing3SourceFixed = 0x1B000000, 1084 DataProcessing3SourceFMask = 0x1F000000, 1085 DataProcessing3SourceMask = 0xFFE08000, 1086 MADD_w = DataProcessing3SourceFixed | 0x00000000, 1087 MADD_x = DataProcessing3SourceFixed | 0x80000000, 1088 MADD = MADD_w, 1089 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 1090 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 1091 MSUB = MSUB_w, 1092 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 1093 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 1094 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 1095 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 1096 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 1097 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 1098 }; 1099 1100 // Floating point compare. 1101 enum FPCompareOp { 1102 FPCompareFixed = 0x1E202000, 1103 FPCompareFMask = 0x5F203C00, 1104 FPCompareMask = 0xFFE0FC1F, 1105 FCMP_s = FPCompareFixed | 0x00000000, 1106 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 1107 FCMP = FCMP_s, 1108 FCMP_s_zero = FPCompareFixed | 0x00000008, 1109 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 1110 FCMP_zero = FCMP_s_zero, 1111 FCMPE_s = FPCompareFixed | 0x00000010, 1112 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 1113 FCMPE = FCMPE_s, 1114 FCMPE_s_zero = FPCompareFixed | 0x00000018, 1115 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, 1116 FCMPE_zero = FCMPE_s_zero 1117 }; 1118 1119 // Floating point conditional compare. 1120 enum FPConditionalCompareOp { 1121 FPConditionalCompareFixed = 0x1E200400, 1122 FPConditionalCompareFMask = 0x5F200C00, 1123 FPConditionalCompareMask = 0xFFE00C10, 1124 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1125 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1126 FCCMP = FCCMP_s, 1127 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1128 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1129 FCCMPE = FCCMPE_s 1130 }; 1131 1132 // Floating point conditional select. 1133 enum FPConditionalSelectOp { 1134 FPConditionalSelectFixed = 0x1E200C00, 1135 FPConditionalSelectFMask = 0x5F200C00, 1136 FPConditionalSelectMask = 0xFFE00C00, 1137 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1138 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1139 FCSEL = FCSEL_s 1140 }; 1141 1142 // Floating point immediate. 1143 enum FPImmediateOp { 1144 FPImmediateFixed = 0x1E201000, 1145 FPImmediateFMask = 0x5F201C00, 1146 FPImmediateMask = 0xFFE01C00, 1147 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1148 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1149 }; 1150 1151 // Floating point data processing 1 source. 1152 enum FPDataProcessing1SourceOp { 1153 FPDataProcessing1SourceFixed = 0x1E204000, 1154 FPDataProcessing1SourceFMask = 0x5F207C00, 1155 FPDataProcessing1SourceMask = 0xFFFFFC00, 1156 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1157 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1158 FMOV = FMOV_s, 1159 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1160 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1161 FABS = FABS_s, 1162 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1163 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1164 FNEG = FNEG_s, 1165 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1166 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1167 FSQRT = FSQRT_s, 1168 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1169 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1170 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000, 1171 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, 1172 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, 1173 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, 1174 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1175 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1176 FRINTN = FRINTN_s, 1177 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1178 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1179 FRINTP = FRINTP_s, 1180 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1181 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1182 FRINTM = FRINTM_s, 1183 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1184 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1185 FRINTZ = FRINTZ_s, 1186 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1187 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1188 FRINTA = FRINTA_s, 1189 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1190 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1191 FRINTX = FRINTX_s, 1192 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1193 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1194 FRINTI = FRINTI_s 1195 }; 1196 1197 // Floating point data processing 2 source. 1198 enum FPDataProcessing2SourceOp { 1199 FPDataProcessing2SourceFixed = 0x1E200800, 1200 FPDataProcessing2SourceFMask = 0x5F200C00, 1201 FPDataProcessing2SourceMask = 0xFFE0FC00, 1202 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1203 FMUL_s = FMUL, 1204 FMUL_d = FMUL | FP64, 1205 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1206 FDIV_s = FDIV, 1207 FDIV_d = FDIV | FP64, 1208 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1209 FADD_s = FADD, 1210 FADD_d = FADD | FP64, 1211 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1212 FSUB_s = FSUB, 1213 FSUB_d = FSUB | FP64, 1214 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1215 FMAX_s = FMAX, 1216 FMAX_d = FMAX | FP64, 1217 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1218 FMIN_s = FMIN, 1219 FMIN_d = FMIN | FP64, 1220 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1221 FMAXNM_s = FMAXNM, 1222 FMAXNM_d = FMAXNM | FP64, 1223 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1224 FMINNM_s = FMINNM, 1225 FMINNM_d = FMINNM | FP64, 1226 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1227 FNMUL_s = FNMUL, 1228 FNMUL_d = FNMUL | FP64 1229 }; 1230 1231 // Floating point data processing 3 source. 1232 enum FPDataProcessing3SourceOp { 1233 FPDataProcessing3SourceFixed = 0x1F000000, 1234 FPDataProcessing3SourceFMask = 0x5F000000, 1235 FPDataProcessing3SourceMask = 0xFFE08000, 1236 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1237 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1238 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1239 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1240 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1241 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1242 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1243 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1244 }; 1245 1246 // Conversion between floating point and integer. 1247 enum FPIntegerConvertOp { 1248 FPIntegerConvertFixed = 0x1E200000, 1249 FPIntegerConvertFMask = 0x5F20FC00, 1250 FPIntegerConvertMask = 0xFFFFFC00, 1251 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1252 FCVTNS_ws = FCVTNS, 1253 FCVTNS_xs = FCVTNS | SixtyFourBits, 1254 FCVTNS_wd = FCVTNS | FP64, 1255 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1256 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1257 FCVTNU_ws = FCVTNU, 1258 FCVTNU_xs = FCVTNU | SixtyFourBits, 1259 FCVTNU_wd = FCVTNU | FP64, 1260 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1261 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1262 FCVTPS_ws = FCVTPS, 1263 FCVTPS_xs = FCVTPS | SixtyFourBits, 1264 FCVTPS_wd = FCVTPS | FP64, 1265 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1266 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1267 FCVTPU_ws = FCVTPU, 1268 FCVTPU_xs = FCVTPU | SixtyFourBits, 1269 FCVTPU_wd = FCVTPU | FP64, 1270 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1271 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1272 FCVTMS_ws = FCVTMS, 1273 FCVTMS_xs = FCVTMS | SixtyFourBits, 1274 FCVTMS_wd = FCVTMS | FP64, 1275 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1276 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1277 FCVTMU_ws = FCVTMU, 1278 FCVTMU_xs = FCVTMU | SixtyFourBits, 1279 FCVTMU_wd = FCVTMU | FP64, 1280 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1281 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1282 FCVTZS_ws = FCVTZS, 1283 FCVTZS_xs = FCVTZS | SixtyFourBits, 1284 FCVTZS_wd = FCVTZS | FP64, 1285 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1286 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1287 FCVTZU_ws = FCVTZU, 1288 FCVTZU_xs = FCVTZU | SixtyFourBits, 1289 FCVTZU_wd = FCVTZU | FP64, 1290 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1291 SCVTF = FPIntegerConvertFixed | 0x00020000, 1292 SCVTF_sw = SCVTF, 1293 SCVTF_sx = SCVTF | SixtyFourBits, 1294 SCVTF_dw = SCVTF | FP64, 1295 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1296 UCVTF = FPIntegerConvertFixed | 0x00030000, 1297 UCVTF_sw = UCVTF, 1298 UCVTF_sx = UCVTF | SixtyFourBits, 1299 UCVTF_dw = UCVTF | FP64, 1300 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1301 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1302 FCVTAS_ws = FCVTAS, 1303 FCVTAS_xs = FCVTAS | SixtyFourBits, 1304 FCVTAS_wd = FCVTAS | FP64, 1305 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1306 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1307 FCVTAU_ws = FCVTAU, 1308 FCVTAU_xs = FCVTAU | SixtyFourBits, 1309 FCVTAU_wd = FCVTAU | FP64, 1310 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1311 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1312 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1313 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1314 FMOV_dx = FMOV_sw | SixtyFourBits | FP64, 1315 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, 1316 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000 1317 }; 1318 1319 // Conversion between fixed point and floating point. 1320 enum FPFixedPointConvertOp { 1321 FPFixedPointConvertFixed = 0x1E000000, 1322 FPFixedPointConvertFMask = 0x5F200000, 1323 FPFixedPointConvertMask = 0xFFFF0000, 1324 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1325 FCVTZS_ws_fixed = FCVTZS_fixed, 1326 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1327 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1328 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1329 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1330 FCVTZU_ws_fixed = FCVTZU_fixed, 1331 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1332 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1333 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1334 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1335 SCVTF_sw_fixed = SCVTF_fixed, 1336 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1337 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1338 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1339 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1340 UCVTF_sw_fixed = UCVTF_fixed, 1341 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1342 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1343 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1344 }; 1345 1346 // Crypto - two register SHA. 1347 enum Crypto2RegSHAOp { 1348 Crypto2RegSHAFixed = 0x5E280800, 1349 Crypto2RegSHAFMask = 0xFF3E0C00 1350 }; 1351 1352 // Crypto - three register SHA. 1353 enum Crypto3RegSHAOp { 1354 Crypto3RegSHAFixed = 0x5E000000, 1355 Crypto3RegSHAFMask = 0xFF208C00 1356 }; 1357 1358 // Crypto - AES. 1359 enum CryptoAESOp { 1360 CryptoAESFixed = 0x4E280800, 1361 CryptoAESFMask = 0xFF3E0C00 1362 }; 1363 1364 // NEON instructions with two register operands. 1365 enum NEON2RegMiscOp { 1366 NEON2RegMiscFixed = 0x0E200800, 1367 NEON2RegMiscFMask = 0x9F3E0C00, 1368 NEON2RegMiscMask = 0xBF3FFC00, 1369 NEON2RegMiscUBit = 0x20000000, 1370 NEON_REV64 = NEON2RegMiscFixed | 0x00000000, 1371 NEON_REV32 = NEON2RegMiscFixed | 0x20000000, 1372 NEON_REV16 = NEON2RegMiscFixed | 0x00001000, 1373 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, 1374 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, 1375 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, 1376 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, 1377 NEON_CLS = NEON2RegMiscFixed | 0x00004000, 1378 NEON_CLZ = NEON2RegMiscFixed | 0x20004000, 1379 NEON_CNT = NEON2RegMiscFixed | 0x00005000, 1380 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, 1381 NEON_SADALP = NEON2RegMiscFixed | 0x00006000, 1382 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, 1383 NEON_SQABS = NEON2RegMiscFixed | 0x00007000, 1384 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, 1385 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, 1386 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, 1387 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, 1388 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, 1389 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, 1390 NEON_ABS = NEON2RegMiscFixed | 0x0000B000, 1391 NEON_NEG = NEON2RegMiscFixed | 0x2000B000, 1392 NEON_XTN = NEON2RegMiscFixed | 0x00012000, 1393 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, 1394 NEON_SHLL = NEON2RegMiscFixed | 0x20013000, 1395 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, 1396 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, 1397 1398 NEON2RegMiscOpcode = 0x0001F000, 1399 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, 1400 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, 1401 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, 1402 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode, 1403 1404 // These instructions use only one bit of the size field. The other bit is 1405 // used to distinguish between instructions. 1406 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, 1407 NEON_FABS = NEON2RegMiscFixed | 0x0080F000, 1408 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, 1409 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, 1410 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, 1411 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, 1412 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, 1413 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, 1414 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, 1415 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, 1416 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, 1417 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, 1418 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, 1419 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, 1420 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, 1421 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, 1422 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, 1423 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, 1424 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, 1425 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, 1426 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, 1427 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, 1428 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, 1429 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, 1430 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, 1431 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, 1432 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, 1433 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, 1434 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, 1435 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, 1436 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, 1437 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, 1438 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, 1439 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, 1440 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, 1441 1442 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, 1443 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode 1444 }; 1445 1446 // NEON instructions with three same-type operands. 1447 enum NEON3SameOp { 1448 NEON3SameFixed = 0x0E200400, 1449 NEON3SameFMask = 0x9F200400, 1450 NEON3SameMask = 0xBF20FC00, 1451 NEON3SameUBit = 0x20000000, 1452 NEON_ADD = NEON3SameFixed | 0x00008000, 1453 NEON_ADDP = NEON3SameFixed | 0x0000B800, 1454 NEON_SHADD = NEON3SameFixed | 0x00000000, 1455 NEON_SHSUB = NEON3SameFixed | 0x00002000, 1456 NEON_SRHADD = NEON3SameFixed | 0x00001000, 1457 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, 1458 NEON_CMGE = NEON3SameFixed | 0x00003800, 1459 NEON_CMGT = NEON3SameFixed | 0x00003000, 1460 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, 1461 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, 1462 NEON_CMTST = NEON3SameFixed | 0x00008800, 1463 NEON_MLA = NEON3SameFixed | 0x00009000, 1464 NEON_MLS = NEON3SameFixed | 0x20009000, 1465 NEON_MUL = NEON3SameFixed | 0x00009800, 1466 NEON_PMUL = NEON3SameFixed | 0x20009800, 1467 NEON_SRSHL = NEON3SameFixed | 0x00005000, 1468 NEON_SQSHL = NEON3SameFixed | 0x00004800, 1469 NEON_SQRSHL = NEON3SameFixed | 0x00005800, 1470 NEON_SSHL = NEON3SameFixed | 0x00004000, 1471 NEON_SMAX = NEON3SameFixed | 0x00006000, 1472 NEON_SMAXP = NEON3SameFixed | 0x0000A000, 1473 NEON_SMIN = NEON3SameFixed | 0x00006800, 1474 NEON_SMINP = NEON3SameFixed | 0x0000A800, 1475 NEON_SABD = NEON3SameFixed | 0x00007000, 1476 NEON_SABA = NEON3SameFixed | 0x00007800, 1477 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, 1478 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, 1479 NEON_SQADD = NEON3SameFixed | 0x00000800, 1480 NEON_SQSUB = NEON3SameFixed | 0x00002800, 1481 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, 1482 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, 1483 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, 1484 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, 1485 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX, 1486 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP, 1487 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN, 1488 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP, 1489 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL, 1490 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD, 1491 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL, 1492 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, 1493 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, 1494 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, 1495 NEON_SQDMULH = NEON3SameFixed | 0x0000B000, 1496 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, 1497 1498 // NEON floating point instructions with three same-type operands. 1499 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, 1500 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, 1501 NEON3SameFPMask = NEON3SameMask | 0x00800000, 1502 NEON_FADD = NEON3SameFixed | 0x0000D000, 1503 NEON_FSUB = NEON3SameFixed | 0x0080D000, 1504 NEON_FMUL = NEON3SameFixed | 0x2000D800, 1505 NEON_FDIV = NEON3SameFixed | 0x2000F800, 1506 NEON_FMAX = NEON3SameFixed | 0x0000F000, 1507 NEON_FMAXNM = NEON3SameFixed | 0x0000C000, 1508 NEON_FMAXP = NEON3SameFixed | 0x2000F000, 1509 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, 1510 NEON_FMIN = NEON3SameFixed | 0x0080F000, 1511 NEON_FMINNM = NEON3SameFixed | 0x0080C000, 1512 NEON_FMINP = NEON3SameFixed | 0x2080F000, 1513 NEON_FMINNMP = NEON3SameFixed | 0x2080C000, 1514 NEON_FMLA = NEON3SameFixed | 0x0000C800, 1515 NEON_FMLS = NEON3SameFixed | 0x0080C800, 1516 NEON_FMULX = NEON3SameFixed | 0x0000D800, 1517 NEON_FRECPS = NEON3SameFixed | 0x0000F800, 1518 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, 1519 NEON_FABD = NEON3SameFixed | 0x2080D000, 1520 NEON_FADDP = NEON3SameFixed | 0x2000D000, 1521 NEON_FCMEQ = NEON3SameFixed | 0x0000E000, 1522 NEON_FCMGE = NEON3SameFixed | 0x2000E000, 1523 NEON_FCMGT = NEON3SameFixed | 0x2080E000, 1524 NEON_FACGE = NEON3SameFixed | 0x2000E800, 1525 NEON_FACGT = NEON3SameFixed | 0x2080E800, 1526 1527 // NEON logical instructions with three same-type operands. 1528 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, 1529 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, 1530 NEON3SameLogicalMask = 0xBFE0FC00, 1531 NEON3SameLogicalFormatMask = NEON_Q, 1532 NEON_AND = NEON3SameLogicalFixed | 0x00000000, 1533 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, 1534 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, 1535 NEON_EOR = NEON3SameLogicalFixed | 0x20000000, 1536 NEON_BIC = NEON3SameLogicalFixed | 0x00400000, 1537 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, 1538 NEON_BIT = NEON3SameLogicalFixed | 0x20800000, 1539 NEON_BSL = NEON3SameLogicalFixed | 0x20400000 1540 }; 1541 1542 // NEON instructions with three different-type operands. 1543 enum NEON3DifferentOp { 1544 NEON3DifferentFixed = 0x0E200000, 1545 NEON3DifferentFMask = 0x9F200C00, 1546 NEON3DifferentMask = 0xFF20FC00, 1547 NEON_ADDHN = NEON3DifferentFixed | 0x00004000, 1548 NEON_ADDHN2 = NEON_ADDHN | NEON_Q, 1549 NEON_PMULL = NEON3DifferentFixed | 0x0000E000, 1550 NEON_PMULL2 = NEON_PMULL | NEON_Q, 1551 NEON_RADDHN = NEON3DifferentFixed | 0x20004000, 1552 NEON_RADDHN2 = NEON_RADDHN | NEON_Q, 1553 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, 1554 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, 1555 NEON_SABAL = NEON3DifferentFixed | 0x00005000, 1556 NEON_SABAL2 = NEON_SABAL | NEON_Q, 1557 NEON_SABDL = NEON3DifferentFixed | 0x00007000, 1558 NEON_SABDL2 = NEON_SABDL | NEON_Q, 1559 NEON_SADDL = NEON3DifferentFixed | 0x00000000, 1560 NEON_SADDL2 = NEON_SADDL | NEON_Q, 1561 NEON_SADDW = NEON3DifferentFixed | 0x00001000, 1562 NEON_SADDW2 = NEON_SADDW | NEON_Q, 1563 NEON_SMLAL = NEON3DifferentFixed | 0x00008000, 1564 NEON_SMLAL2 = NEON_SMLAL | NEON_Q, 1565 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, 1566 NEON_SMLSL2 = NEON_SMLSL | NEON_Q, 1567 NEON_SMULL = NEON3DifferentFixed | 0x0000C000, 1568 NEON_SMULL2 = NEON_SMULL | NEON_Q, 1569 NEON_SSUBL = NEON3DifferentFixed | 0x00002000, 1570 NEON_SSUBL2 = NEON_SSUBL | NEON_Q, 1571 NEON_SSUBW = NEON3DifferentFixed | 0x00003000, 1572 NEON_SSUBW2 = NEON_SSUBW | NEON_Q, 1573 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, 1574 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, 1575 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, 1576 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, 1577 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, 1578 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, 1579 NEON_SUBHN = NEON3DifferentFixed | 0x00006000, 1580 NEON_SUBHN2 = NEON_SUBHN | NEON_Q, 1581 NEON_UABAL = NEON_SABAL | NEON3SameUBit, 1582 NEON_UABAL2 = NEON_UABAL | NEON_Q, 1583 NEON_UABDL = NEON_SABDL | NEON3SameUBit, 1584 NEON_UABDL2 = NEON_UABDL | NEON_Q, 1585 NEON_UADDL = NEON_SADDL | NEON3SameUBit, 1586 NEON_UADDL2 = NEON_UADDL | NEON_Q, 1587 NEON_UADDW = NEON_SADDW | NEON3SameUBit, 1588 NEON_UADDW2 = NEON_UADDW | NEON_Q, 1589 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit, 1590 NEON_UMLAL2 = NEON_UMLAL | NEON_Q, 1591 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit, 1592 NEON_UMLSL2 = NEON_UMLSL | NEON_Q, 1593 NEON_UMULL = NEON_SMULL | NEON3SameUBit, 1594 NEON_UMULL2 = NEON_UMULL | NEON_Q, 1595 NEON_USUBL = NEON_SSUBL | NEON3SameUBit, 1596 NEON_USUBL2 = NEON_USUBL | NEON_Q, 1597 NEON_USUBW = NEON_SSUBW | NEON3SameUBit, 1598 NEON_USUBW2 = NEON_USUBW | NEON_Q 1599 }; 1600 1601 // NEON instructions operating across vectors. 1602 enum NEONAcrossLanesOp { 1603 NEONAcrossLanesFixed = 0x0E300800, 1604 NEONAcrossLanesFMask = 0x9F3E0C00, 1605 NEONAcrossLanesMask = 0xBF3FFC00, 1606 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, 1607 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, 1608 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, 1609 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, 1610 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, 1611 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, 1612 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, 1613 1614 // NEON floating point across instructions. 1615 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000, 1616 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000, 1617 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000, 1618 1619 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, 1620 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, 1621 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, 1622 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 1623 }; 1624 1625 // NEON instructions with indexed element operand. 1626 enum NEONByIndexedElementOp { 1627 NEONByIndexedElementFixed = 0x0F000000, 1628 NEONByIndexedElementFMask = 0x9F000400, 1629 NEONByIndexedElementMask = 0xBF00F400, 1630 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, 1631 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, 1632 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, 1633 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, 1634 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, 1635 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, 1636 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, 1637 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, 1638 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, 1639 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, 1640 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, 1641 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, 1642 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, 1643 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, 1644 1645 // Floating point instructions. 1646 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, 1647 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, 1648 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, 1649 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, 1650 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, 1651 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000 1652 }; 1653 1654 // NEON register copy. 1655 enum NEONCopyOp { 1656 NEONCopyFixed = 0x0E000400, 1657 NEONCopyFMask = 0x9FE08400, 1658 NEONCopyMask = 0x3FE08400, 1659 NEONCopyInsElementMask = NEONCopyMask | 0x40000000, 1660 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, 1661 NEONCopyDupElementMask = NEONCopyMask | 0x20007800, 1662 NEONCopyDupGeneralMask = NEONCopyDupElementMask, 1663 NEONCopyUmovMask = NEONCopyMask | 0x20007800, 1664 NEONCopySmovMask = NEONCopyMask | 0x20007800, 1665 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, 1666 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, 1667 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, 1668 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, 1669 NEON_SMOV = NEONCopyFixed | 0x00002800, 1670 NEON_UMOV = NEONCopyFixed | 0x00003800 1671 }; 1672 1673 // NEON extract. 1674 enum NEONExtractOp { 1675 NEONExtractFixed = 0x2E000000, 1676 NEONExtractFMask = 0xBF208400, 1677 NEONExtractMask = 0xBFE08400, 1678 NEON_EXT = NEONExtractFixed | 0x00000000 1679 }; 1680 1681 enum NEONLoadStoreMultiOp { 1682 NEONLoadStoreMultiL = 0x00400000, 1683 NEONLoadStoreMulti1_1v = 0x00007000, 1684 NEONLoadStoreMulti1_2v = 0x0000A000, 1685 NEONLoadStoreMulti1_3v = 0x00006000, 1686 NEONLoadStoreMulti1_4v = 0x00002000, 1687 NEONLoadStoreMulti2 = 0x00008000, 1688 NEONLoadStoreMulti3 = 0x00004000, 1689 NEONLoadStoreMulti4 = 0x00000000 1690 }; 1691 1692 // NEON load/store multiple structures. 1693 enum NEONLoadStoreMultiStructOp { 1694 NEONLoadStoreMultiStructFixed = 0x0C000000, 1695 NEONLoadStoreMultiStructFMask = 0xBFBF0000, 1696 NEONLoadStoreMultiStructMask = 0xBFFFF000, 1697 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, 1698 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | 1699 NEONLoadStoreMultiL, 1700 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v, 1701 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v, 1702 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v, 1703 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v, 1704 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2, 1705 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3, 1706 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4, 1707 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v, 1708 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v, 1709 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v, 1710 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v, 1711 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2, 1712 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3, 1713 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 1714 }; 1715 1716 // NEON load/store multiple structures with post-index addressing. 1717 enum NEONLoadStoreMultiStructPostIndexOp { 1718 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, 1719 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, 1720 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, 1721 NEONLoadStoreMultiStructPostIndex = 0x00800000, 1722 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, 1723 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, 1724 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, 1725 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex, 1726 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex, 1727 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex, 1728 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex, 1729 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex, 1730 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex, 1731 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex, 1732 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex, 1733 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex, 1734 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex, 1735 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex 1736 }; 1737 1738 enum NEONLoadStoreSingleOp { 1739 NEONLoadStoreSingle1 = 0x00000000, 1740 NEONLoadStoreSingle2 = 0x00200000, 1741 NEONLoadStoreSingle3 = 0x00002000, 1742 NEONLoadStoreSingle4 = 0x00202000, 1743 NEONLoadStoreSingleL = 0x00400000, 1744 NEONLoadStoreSingle_b = 0x00000000, 1745 NEONLoadStoreSingle_h = 0x00004000, 1746 NEONLoadStoreSingle_s = 0x00008000, 1747 NEONLoadStoreSingle_d = 0x00008400, 1748 NEONLoadStoreSingleAllLanes = 0x0000C000, 1749 NEONLoadStoreSingleLenMask = 0x00202000 1750 }; 1751 1752 // NEON load/store single structure. 1753 enum NEONLoadStoreSingleStructOp { 1754 NEONLoadStoreSingleStructFixed = 0x0D000000, 1755 NEONLoadStoreSingleStructFMask = 0xBF9F0000, 1756 NEONLoadStoreSingleStructMask = 0xBFFFE000, 1757 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, 1758 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | 1759 NEONLoadStoreSingleL, 1760 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | 1761 NEONLoadStoreSingleStructLoad, 1762 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | 1763 NEONLoadStoreSingleStructLoad, 1764 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | 1765 NEONLoadStoreSingleStructLoad, 1766 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | 1767 NEONLoadStoreSingleStructLoad, 1768 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | 1769 NEONLoadStoreSingleStructFixed, 1770 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | 1771 NEONLoadStoreSingleStructFixed, 1772 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | 1773 NEONLoadStoreSingleStructFixed, 1774 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | 1775 NEONLoadStoreSingleStructFixed, 1776 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b, 1777 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h, 1778 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s, 1779 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d, 1780 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes, 1781 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b, 1782 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h, 1783 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s, 1784 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d, 1785 1786 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b, 1787 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h, 1788 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s, 1789 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d, 1790 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes, 1791 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b, 1792 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h, 1793 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s, 1794 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d, 1795 1796 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b, 1797 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h, 1798 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s, 1799 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d, 1800 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes, 1801 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b, 1802 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h, 1803 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s, 1804 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d, 1805 1806 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b, 1807 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h, 1808 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s, 1809 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d, 1810 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes, 1811 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b, 1812 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h, 1813 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s, 1814 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d 1815 }; 1816 1817 // NEON load/store single structure with post-index addressing. 1818 enum NEONLoadStoreSingleStructPostIndexOp { 1819 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, 1820 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, 1821 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, 1822 NEONLoadStoreSingleStructPostIndex = 0x00800000, 1823 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, 1824 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, 1825 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, 1826 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex, 1827 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex, 1828 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex, 1829 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex, 1830 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex, 1831 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex, 1832 1833 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex, 1834 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex, 1835 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex, 1836 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex, 1837 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex, 1838 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex, 1839 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex, 1840 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex, 1841 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex, 1842 1843 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex, 1844 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex, 1845 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex, 1846 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex, 1847 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex, 1848 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex, 1849 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex, 1850 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex, 1851 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex, 1852 1853 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex, 1854 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex, 1855 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex, 1856 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex, 1857 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex, 1858 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex, 1859 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex, 1860 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex, 1861 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex 1862 }; 1863 1864 // NEON modified immediate. 1865 enum NEONModifiedImmediateOp { 1866 NEONModifiedImmediateFixed = 0x0F000400, 1867 NEONModifiedImmediateFMask = 0x9FF80400, 1868 NEONModifiedImmediateOpBit = 0x20000000, 1869 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, 1870 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, 1871 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, 1872 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 1873 }; 1874 1875 // NEON shift immediate. 1876 enum NEONShiftImmediateOp { 1877 NEONShiftImmediateFixed = 0x0F000400, 1878 NEONShiftImmediateFMask = 0x9F800400, 1879 NEONShiftImmediateMask = 0xBF80FC00, 1880 NEONShiftImmediateUBit = 0x20000000, 1881 NEON_SHL = NEONShiftImmediateFixed | 0x00005000, 1882 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, 1883 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, 1884 NEON_SLI = NEONShiftImmediateFixed | 0x20005000, 1885 NEON_SRI = NEONShiftImmediateFixed | 0x20004000, 1886 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, 1887 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, 1888 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, 1889 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, 1890 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, 1891 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, 1892 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, 1893 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, 1894 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, 1895 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, 1896 NEON_USHR = NEONShiftImmediateFixed | 0x20000000, 1897 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, 1898 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, 1899 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, 1900 NEON_USRA = NEONShiftImmediateFixed | 0x20001000, 1901 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, 1902 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, 1903 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, 1904 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, 1905 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, 1906 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, 1907 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, 1908 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 1909 }; 1910 1911 // NEON table. 1912 enum NEONTableOp { 1913 NEONTableFixed = 0x0E000000, 1914 NEONTableFMask = 0xBF208C00, 1915 NEONTableExt = 0x00001000, 1916 NEONTableMask = 0xBF20FC00, 1917 NEON_TBL_1v = NEONTableFixed | 0x00000000, 1918 NEON_TBL_2v = NEONTableFixed | 0x00002000, 1919 NEON_TBL_3v = NEONTableFixed | 0x00004000, 1920 NEON_TBL_4v = NEONTableFixed | 0x00006000, 1921 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, 1922 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, 1923 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, 1924 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt 1925 }; 1926 1927 // NEON perm. 1928 enum NEONPermOp { 1929 NEONPermFixed = 0x0E000800, 1930 NEONPermFMask = 0xBF208C00, 1931 NEONPermMask = 0x3F20FC00, 1932 NEON_UZP1 = NEONPermFixed | 0x00001000, 1933 NEON_TRN1 = NEONPermFixed | 0x00002000, 1934 NEON_ZIP1 = NEONPermFixed | 0x00003000, 1935 NEON_UZP2 = NEONPermFixed | 0x00005000, 1936 NEON_TRN2 = NEONPermFixed | 0x00006000, 1937 NEON_ZIP2 = NEONPermFixed | 0x00007000 1938 }; 1939 1940 // NEON scalar instructions with two register operands. 1941 enum NEONScalar2RegMiscOp { 1942 NEONScalar2RegMiscFixed = 0x5E200800, 1943 NEONScalar2RegMiscFMask = 0xDF3E0C00, 1944 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, 1945 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, 1946 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, 1947 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero, 1948 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero, 1949 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero, 1950 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS, 1951 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS, 1952 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG, 1953 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG, 1954 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN, 1955 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN, 1956 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN, 1957 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD, 1958 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD, 1959 1960 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, 1961 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, 1962 1963 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, 1964 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, 1965 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, 1966 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, 1967 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF, 1968 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero, 1969 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero, 1970 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, 1971 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, 1972 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, 1973 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, 1974 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, 1975 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, 1976 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, 1977 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU, 1978 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS, 1979 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU, 1980 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS, 1981 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU, 1982 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS, 1983 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU, 1984 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN 1985 }; 1986 1987 // NEON scalar instructions with three same-type operands. 1988 enum NEONScalar3SameOp { 1989 NEONScalar3SameFixed = 0x5E200400, 1990 NEONScalar3SameFMask = 0xDF200400, 1991 NEONScalar3SameMask = 0xFF20FC00, 1992 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, 1993 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, 1994 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, 1995 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT, 1996 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI, 1997 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS, 1998 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST, 1999 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB, 2000 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD, 2001 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD, 2002 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB, 2003 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB, 2004 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL, 2005 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL, 2006 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL, 2007 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL, 2008 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL, 2009 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL, 2010 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL, 2011 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL, 2012 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH, 2013 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, 2014 2015 // NEON floating point scalar instructions with three same-type operands. 2016 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, 2017 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, 2018 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, 2019 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, 2020 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, 2021 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, 2022 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE, 2023 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT, 2024 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX, 2025 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS, 2026 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS, 2027 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD 2028 }; 2029 2030 // NEON scalar instructions with three different-type operands. 2031 enum NEONScalar3DiffOp { 2032 NEONScalar3DiffFixed = 0x5E200000, 2033 NEONScalar3DiffFMask = 0xDF200C00, 2034 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, 2035 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, 2036 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, 2037 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL 2038 }; 2039 2040 // NEON scalar instructions with indexed element operand. 2041 enum NEONScalarByIndexedElementOp { 2042 NEONScalarByIndexedElementFixed = 0x5F000000, 2043 NEONScalarByIndexedElementFMask = 0xDF000400, 2044 NEONScalarByIndexedElementMask = 0xFF00F400, 2045 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, 2046 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, 2047 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, 2048 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement, 2049 NEON_SQRDMULH_byelement_scalar 2050 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement, 2051 2052 // Floating point instructions. 2053 NEONScalarByIndexedElementFPFixed 2054 = NEONScalarByIndexedElementFixed | 0x00800000, 2055 NEONScalarByIndexedElementFPMask 2056 = NEONScalarByIndexedElementMask | 0x00800000, 2057 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, 2058 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, 2059 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, 2060 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement 2061 }; 2062 2063 // NEON scalar register copy. 2064 enum NEONScalarCopyOp { 2065 NEONScalarCopyFixed = 0x5E000400, 2066 NEONScalarCopyFMask = 0xDFE08400, 2067 NEONScalarCopyMask = 0xFFE0FC00, 2068 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT 2069 }; 2070 2071 // NEON scalar pairwise instructions. 2072 enum NEONScalarPairwiseOp { 2073 NEONScalarPairwiseFixed = 0x5E300800, 2074 NEONScalarPairwiseFMask = 0xDF3E0C00, 2075 NEONScalarPairwiseMask = 0xFFB1F800, 2076 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, 2077 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, 2078 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, 2079 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, 2080 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, 2081 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 2082 }; 2083 2084 // NEON scalar shift immediate. 2085 enum NEONScalarShiftImmediateOp { 2086 NEONScalarShiftImmediateFixed = 0x5F000400, 2087 NEONScalarShiftImmediateFMask = 0xDF800400, 2088 NEONScalarShiftImmediateMask = 0xFF80FC00, 2089 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, 2090 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, 2091 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, 2092 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR, 2093 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR, 2094 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR, 2095 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR, 2096 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA, 2097 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA, 2098 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA, 2099 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA, 2100 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN, 2101 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN, 2102 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN, 2103 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN, 2104 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN, 2105 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN, 2106 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU, 2107 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm, 2108 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm, 2109 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm, 2110 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm, 2111 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm, 2112 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm 2113 }; 2114 2115 // Unimplemented and unallocated instructions. These are defined to make fixed 2116 // bit assertion easier. 2117 enum UnimplementedOp { 2118 UnimplementedFixed = 0x00000000, 2119 UnimplementedFMask = 0x00000000 2120 }; 2121 2122 enum UnallocatedOp { 2123 UnallocatedFixed = 0x00000000, 2124 UnallocatedFMask = 0x00000000 2125 }; 2126 2127 // Re-enable `clang-format` after the `enum`s. 2128 // clang-format on 2129 2130 } // namespace aarch64 2131 } // namespace vixl 2132 2133 #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_ 2134
