1 //===-- ARMExpandPseudoInsts.cpp - Expand pseudo instructions -----*- C++ -*-=// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains a pass that expands pseudo instructions into target 11 // instructions to allow proper scheduling, if-conversion, and other late 12 // optimizations. This pass should be run after register allocation but before 13 // the post-regalloc scheduling pass. 14 // 15 //===----------------------------------------------------------------------===// 16 17 #define DEBUG_TYPE "arm-pseudo" 18 #include "ARM.h" 19 #include "ARMAddressingModes.h" 20 #include "ARMBaseInstrInfo.h" 21 #include "ARMBaseRegisterInfo.h" 22 #include "ARMMachineFunctionInfo.h" 23 #include "ARMRegisterInfo.h" 24 #include "llvm/CodeGen/MachineFrameInfo.h" 25 #include "llvm/CodeGen/MachineFunctionPass.h" 26 #include "llvm/CodeGen/MachineInstrBuilder.h" 27 #include "llvm/Target/TargetFrameLowering.h" 28 #include "llvm/Target/TargetRegisterInfo.h" 29 #include "llvm/Support/raw_ostream.h" // FIXME: for debug only. remove! 30 using namespace llvm; 31 32 namespace { 33 class ARMExpandPseudo : public MachineFunctionPass { 34 public: 35 static char ID; 36 ARMExpandPseudo() : MachineFunctionPass(ID) {} 37 38 const ARMBaseInstrInfo *TII; 39 const TargetRegisterInfo *TRI; 40 const ARMSubtarget *STI; 41 ARMFunctionInfo *AFI; 42 43 virtual bool runOnMachineFunction(MachineFunction &Fn); 44 45 virtual const char *getPassName() const { 46 return "ARM pseudo instruction expansion pass"; 47 } 48 49 private: 50 void TransferImpOps(MachineInstr &OldMI, 51 MachineInstrBuilder &UseMI, MachineInstrBuilder &DefMI); 52 bool ExpandMI(MachineBasicBlock &MBB, 53 MachineBasicBlock::iterator MBBI); 54 bool ExpandMBB(MachineBasicBlock &MBB); 55 void ExpandVLD(MachineBasicBlock::iterator &MBBI); 56 void ExpandVST(MachineBasicBlock::iterator &MBBI); 57 void ExpandLaneOp(MachineBasicBlock::iterator &MBBI); 58 void ExpandVTBL(MachineBasicBlock::iterator &MBBI, 59 unsigned Opc, bool IsExt, unsigned NumRegs); 60 void ExpandMOV32BitImm(MachineBasicBlock &MBB, 61 MachineBasicBlock::iterator &MBBI); 62 }; 63 char ARMExpandPseudo::ID = 0; 64 } 65 66 /// TransferImpOps - Transfer implicit operands on the pseudo instruction to 67 /// the instructions created from the expansion. 68 void ARMExpandPseudo::TransferImpOps(MachineInstr &OldMI, 69 MachineInstrBuilder &UseMI, 70 MachineInstrBuilder &DefMI) { 71 const MCInstrDesc &Desc = OldMI.getDesc(); 72 for (unsigned i = Desc.getNumOperands(), e = OldMI.getNumOperands(); 73 i != e; ++i) { 74 const MachineOperand &MO = OldMI.getOperand(i); 75 assert(MO.isReg() && MO.getReg()); 76 if (MO.isUse()) 77 UseMI.addOperand(MO); 78 else 79 DefMI.addOperand(MO); 80 } 81 } 82 83 namespace { 84 // Constants for register spacing in NEON load/store instructions. 85 // For quad-register load-lane and store-lane pseudo instructors, the 86 // spacing is initially assumed to be EvenDblSpc, and that is changed to 87 // OddDblSpc depending on the lane number operand. 88 enum NEONRegSpacing { 89 SingleSpc, 90 EvenDblSpc, 91 OddDblSpc 92 }; 93 94 // Entries for NEON load/store information table. The table is sorted by 95 // PseudoOpc for fast binary-search lookups. 96 struct NEONLdStTableEntry { 97 unsigned PseudoOpc; 98 unsigned RealOpc; 99 bool IsLoad; 100 bool HasWriteBack; 101 NEONRegSpacing RegSpacing; 102 unsigned char NumRegs; // D registers loaded or stored 103 unsigned char RegElts; // elements per D register; used for lane ops 104 105 // Comparison methods for binary search of the table. 106 bool operator<(const NEONLdStTableEntry &TE) const { 107 return PseudoOpc < TE.PseudoOpc; 108 } 109 friend bool operator<(const NEONLdStTableEntry &TE, unsigned PseudoOpc) { 110 return TE.PseudoOpc < PseudoOpc; 111 } 112 friend bool LLVM_ATTRIBUTE_UNUSED operator<(unsigned PseudoOpc, 113 const NEONLdStTableEntry &TE) { 114 return PseudoOpc < TE.PseudoOpc; 115 } 116 }; 117 } 118 119 static const NEONLdStTableEntry NEONLdStTable[] = { 120 { ARM::VLD1DUPq16Pseudo, ARM::VLD1DUPq16, true, false, SingleSpc, 2, 4}, 121 { ARM::VLD1DUPq16Pseudo_UPD, ARM::VLD1DUPq16_UPD, true, true, SingleSpc, 2, 4}, 122 { ARM::VLD1DUPq32Pseudo, ARM::VLD1DUPq32, true, false, SingleSpc, 2, 2}, 123 { ARM::VLD1DUPq32Pseudo_UPD, ARM::VLD1DUPq32_UPD, true, true, SingleSpc, 2, 2}, 124 { ARM::VLD1DUPq8Pseudo, ARM::VLD1DUPq8, true, false, SingleSpc, 2, 8}, 125 { ARM::VLD1DUPq8Pseudo_UPD, ARM::VLD1DUPq8_UPD, true, true, SingleSpc, 2, 8}, 126 127 { ARM::VLD1LNq16Pseudo, ARM::VLD1LNd16, true, false, EvenDblSpc, 1, 4 }, 128 { ARM::VLD1LNq16Pseudo_UPD, ARM::VLD1LNd16_UPD, true, true, EvenDblSpc, 1, 4 }, 129 { ARM::VLD1LNq32Pseudo, ARM::VLD1LNd32, true, false, EvenDblSpc, 1, 2 }, 130 { ARM::VLD1LNq32Pseudo_UPD, ARM::VLD1LNd32_UPD, true, true, EvenDblSpc, 1, 2 }, 131 { ARM::VLD1LNq8Pseudo, ARM::VLD1LNd8, true, false, EvenDblSpc, 1, 8 }, 132 { ARM::VLD1LNq8Pseudo_UPD, ARM::VLD1LNd8_UPD, true, true, EvenDblSpc, 1, 8 }, 133 134 { ARM::VLD1d64QPseudo, ARM::VLD1d64Q, true, false, SingleSpc, 4, 1 }, 135 { ARM::VLD1d64QPseudo_UPD, ARM::VLD1d64Q_UPD, true, true, SingleSpc, 4, 1 }, 136 { ARM::VLD1d64TPseudo, ARM::VLD1d64T, true, false, SingleSpc, 3, 1 }, 137 { ARM::VLD1d64TPseudo_UPD, ARM::VLD1d64T_UPD, true, true, SingleSpc, 3, 1 }, 138 139 { ARM::VLD1q16Pseudo, ARM::VLD1q16, true, false, SingleSpc, 2, 4 }, 140 { ARM::VLD1q16Pseudo_UPD, ARM::VLD1q16_UPD, true, true, SingleSpc, 2, 4 }, 141 { ARM::VLD1q32Pseudo, ARM::VLD1q32, true, false, SingleSpc, 2, 2 }, 142 { ARM::VLD1q32Pseudo_UPD, ARM::VLD1q32_UPD, true, true, SingleSpc, 2, 2 }, 143 { ARM::VLD1q64Pseudo, ARM::VLD1q64, true, false, SingleSpc, 2, 1 }, 144 { ARM::VLD1q64Pseudo_UPD, ARM::VLD1q64_UPD, true, true, SingleSpc, 2, 1 }, 145 { ARM::VLD1q8Pseudo, ARM::VLD1q8, true, false, SingleSpc, 2, 8 }, 146 { ARM::VLD1q8Pseudo_UPD, ARM::VLD1q8_UPD, true, true, SingleSpc, 2, 8 }, 147 148 { ARM::VLD2DUPd16Pseudo, ARM::VLD2DUPd16, true, false, SingleSpc, 2, 4}, 149 { ARM::VLD2DUPd16Pseudo_UPD, ARM::VLD2DUPd16_UPD, true, true, SingleSpc, 2, 4}, 150 { ARM::VLD2DUPd32Pseudo, ARM::VLD2DUPd32, true, false, SingleSpc, 2, 2}, 151 { ARM::VLD2DUPd32Pseudo_UPD, ARM::VLD2DUPd32_UPD, true, true, SingleSpc, 2, 2}, 152 { ARM::VLD2DUPd8Pseudo, ARM::VLD2DUPd8, true, false, SingleSpc, 2, 8}, 153 { ARM::VLD2DUPd8Pseudo_UPD, ARM::VLD2DUPd8_UPD, true, true, SingleSpc, 2, 8}, 154 155 { ARM::VLD2LNd16Pseudo, ARM::VLD2LNd16, true, false, SingleSpc, 2, 4 }, 156 { ARM::VLD2LNd16Pseudo_UPD, ARM::VLD2LNd16_UPD, true, true, SingleSpc, 2, 4 }, 157 { ARM::VLD2LNd32Pseudo, ARM::VLD2LNd32, true, false, SingleSpc, 2, 2 }, 158 { ARM::VLD2LNd32Pseudo_UPD, ARM::VLD2LNd32_UPD, true, true, SingleSpc, 2, 2 }, 159 { ARM::VLD2LNd8Pseudo, ARM::VLD2LNd8, true, false, SingleSpc, 2, 8 }, 160 { ARM::VLD2LNd8Pseudo_UPD, ARM::VLD2LNd8_UPD, true, true, SingleSpc, 2, 8 }, 161 { ARM::VLD2LNq16Pseudo, ARM::VLD2LNq16, true, false, EvenDblSpc, 2, 4 }, 162 { ARM::VLD2LNq16Pseudo_UPD, ARM::VLD2LNq16_UPD, true, true, EvenDblSpc, 2, 4 }, 163 { ARM::VLD2LNq32Pseudo, ARM::VLD2LNq32, true, false, EvenDblSpc, 2, 2 }, 164 { ARM::VLD2LNq32Pseudo_UPD, ARM::VLD2LNq32_UPD, true, true, EvenDblSpc, 2, 2 }, 165 166 { ARM::VLD2d16Pseudo, ARM::VLD2d16, true, false, SingleSpc, 2, 4 }, 167 { ARM::VLD2d16Pseudo_UPD, ARM::VLD2d16_UPD, true, true, SingleSpc, 2, 4 }, 168 { ARM::VLD2d32Pseudo, ARM::VLD2d32, true, false, SingleSpc, 2, 2 }, 169 { ARM::VLD2d32Pseudo_UPD, ARM::VLD2d32_UPD, true, true, SingleSpc, 2, 2 }, 170 { ARM::VLD2d8Pseudo, ARM::VLD2d8, true, false, SingleSpc, 2, 8 }, 171 { ARM::VLD2d8Pseudo_UPD, ARM::VLD2d8_UPD, true, true, SingleSpc, 2, 8 }, 172 173 { ARM::VLD2q16Pseudo, ARM::VLD2q16, true, false, SingleSpc, 4, 4 }, 174 { ARM::VLD2q16Pseudo_UPD, ARM::VLD2q16_UPD, true, true, SingleSpc, 4, 4 }, 175 { ARM::VLD2q32Pseudo, ARM::VLD2q32, true, false, SingleSpc, 4, 2 }, 176 { ARM::VLD2q32Pseudo_UPD, ARM::VLD2q32_UPD, true, true, SingleSpc, 4, 2 }, 177 { ARM::VLD2q8Pseudo, ARM::VLD2q8, true, false, SingleSpc, 4, 8 }, 178 { ARM::VLD2q8Pseudo_UPD, ARM::VLD2q8_UPD, true, true, SingleSpc, 4, 8 }, 179 180 { ARM::VLD3DUPd16Pseudo, ARM::VLD3DUPd16, true, false, SingleSpc, 3, 4}, 181 { ARM::VLD3DUPd16Pseudo_UPD, ARM::VLD3DUPd16_UPD, true, true, SingleSpc, 3, 4}, 182 { ARM::VLD3DUPd32Pseudo, ARM::VLD3DUPd32, true, false, SingleSpc, 3, 2}, 183 { ARM::VLD3DUPd32Pseudo_UPD, ARM::VLD3DUPd32_UPD, true, true, SingleSpc, 3, 2}, 184 { ARM::VLD3DUPd8Pseudo, ARM::VLD3DUPd8, true, false, SingleSpc, 3, 8}, 185 { ARM::VLD3DUPd8Pseudo_UPD, ARM::VLD3DUPd8_UPD, true, true, SingleSpc, 3, 8}, 186 187 { ARM::VLD3LNd16Pseudo, ARM::VLD3LNd16, true, false, SingleSpc, 3, 4 }, 188 { ARM::VLD3LNd16Pseudo_UPD, ARM::VLD3LNd16_UPD, true, true, SingleSpc, 3, 4 }, 189 { ARM::VLD3LNd32Pseudo, ARM::VLD3LNd32, true, false, SingleSpc, 3, 2 }, 190 { ARM::VLD3LNd32Pseudo_UPD, ARM::VLD3LNd32_UPD, true, true, SingleSpc, 3, 2 }, 191 { ARM::VLD3LNd8Pseudo, ARM::VLD3LNd8, true, false, SingleSpc, 3, 8 }, 192 { ARM::VLD3LNd8Pseudo_UPD, ARM::VLD3LNd8_UPD, true, true, SingleSpc, 3, 8 }, 193 { ARM::VLD3LNq16Pseudo, ARM::VLD3LNq16, true, false, EvenDblSpc, 3, 4 }, 194 { ARM::VLD3LNq16Pseudo_UPD, ARM::VLD3LNq16_UPD, true, true, EvenDblSpc, 3, 4 }, 195 { ARM::VLD3LNq32Pseudo, ARM::VLD3LNq32, true, false, EvenDblSpc, 3, 2 }, 196 { ARM::VLD3LNq32Pseudo_UPD, ARM::VLD3LNq32_UPD, true, true, EvenDblSpc, 3, 2 }, 197 198 { ARM::VLD3d16Pseudo, ARM::VLD3d16, true, false, SingleSpc, 3, 4 }, 199 { ARM::VLD3d16Pseudo_UPD, ARM::VLD3d16_UPD, true, true, SingleSpc, 3, 4 }, 200 { ARM::VLD3d32Pseudo, ARM::VLD3d32, true, false, SingleSpc, 3, 2 }, 201 { ARM::VLD3d32Pseudo_UPD, ARM::VLD3d32_UPD, true, true, SingleSpc, 3, 2 }, 202 { ARM::VLD3d8Pseudo, ARM::VLD3d8, true, false, SingleSpc, 3, 8 }, 203 { ARM::VLD3d8Pseudo_UPD, ARM::VLD3d8_UPD, true, true, SingleSpc, 3, 8 }, 204 205 { ARM::VLD3q16Pseudo_UPD, ARM::VLD3q16_UPD, true, true, EvenDblSpc, 3, 4 }, 206 { ARM::VLD3q16oddPseudo, ARM::VLD3q16, true, false, OddDblSpc, 3, 4 }, 207 { ARM::VLD3q16oddPseudo_UPD, ARM::VLD3q16_UPD, true, true, OddDblSpc, 3, 4 }, 208 { ARM::VLD3q32Pseudo_UPD, ARM::VLD3q32_UPD, true, true, EvenDblSpc, 3, 2 }, 209 { ARM::VLD3q32oddPseudo, ARM::VLD3q32, true, false, OddDblSpc, 3, 2 }, 210 { ARM::VLD3q32oddPseudo_UPD, ARM::VLD3q32_UPD, true, true, OddDblSpc, 3, 2 }, 211 { ARM::VLD3q8Pseudo_UPD, ARM::VLD3q8_UPD, true, true, EvenDblSpc, 3, 8 }, 212 { ARM::VLD3q8oddPseudo, ARM::VLD3q8, true, false, OddDblSpc, 3, 8 }, 213 { ARM::VLD3q8oddPseudo_UPD, ARM::VLD3q8_UPD, true, true, OddDblSpc, 3, 8 }, 214 215 { ARM::VLD4DUPd16Pseudo, ARM::VLD4DUPd16, true, false, SingleSpc, 4, 4}, 216 { ARM::VLD4DUPd16Pseudo_UPD, ARM::VLD4DUPd16_UPD, true, true, SingleSpc, 4, 4}, 217 { ARM::VLD4DUPd32Pseudo, ARM::VLD4DUPd32, true, false, SingleSpc, 4, 2}, 218 { ARM::VLD4DUPd32Pseudo_UPD, ARM::VLD4DUPd32_UPD, true, true, SingleSpc, 4, 2}, 219 { ARM::VLD4DUPd8Pseudo, ARM::VLD4DUPd8, true, false, SingleSpc, 4, 8}, 220 { ARM::VLD4DUPd8Pseudo_UPD, ARM::VLD4DUPd8_UPD, true, true, SingleSpc, 4, 8}, 221 222 { ARM::VLD4LNd16Pseudo, ARM::VLD4LNd16, true, false, SingleSpc, 4, 4 }, 223 { ARM::VLD4LNd16Pseudo_UPD, ARM::VLD4LNd16_UPD, true, true, SingleSpc, 4, 4 }, 224 { ARM::VLD4LNd32Pseudo, ARM::VLD4LNd32, true, false, SingleSpc, 4, 2 }, 225 { ARM::VLD4LNd32Pseudo_UPD, ARM::VLD4LNd32_UPD, true, true, SingleSpc, 4, 2 }, 226 { ARM::VLD4LNd8Pseudo, ARM::VLD4LNd8, true, false, SingleSpc, 4, 8 }, 227 { ARM::VLD4LNd8Pseudo_UPD, ARM::VLD4LNd8_UPD, true, true, SingleSpc, 4, 8 }, 228 { ARM::VLD4LNq16Pseudo, ARM::VLD4LNq16, true, false, EvenDblSpc, 4, 4 }, 229 { ARM::VLD4LNq16Pseudo_UPD, ARM::VLD4LNq16_UPD, true, true, EvenDblSpc, 4, 4 }, 230 { ARM::VLD4LNq32Pseudo, ARM::VLD4LNq32, true, false, EvenDblSpc, 4, 2 }, 231 { ARM::VLD4LNq32Pseudo_UPD, ARM::VLD4LNq32_UPD, true, true, EvenDblSpc, 4, 2 }, 232 233 { ARM::VLD4d16Pseudo, ARM::VLD4d16, true, false, SingleSpc, 4, 4 }, 234 { ARM::VLD4d16Pseudo_UPD, ARM::VLD4d16_UPD, true, true, SingleSpc, 4, 4 }, 235 { ARM::VLD4d32Pseudo, ARM::VLD4d32, true, false, SingleSpc, 4, 2 }, 236 { ARM::VLD4d32Pseudo_UPD, ARM::VLD4d32_UPD, true, true, SingleSpc, 4, 2 }, 237 { ARM::VLD4d8Pseudo, ARM::VLD4d8, true, false, SingleSpc, 4, 8 }, 238 { ARM::VLD4d8Pseudo_UPD, ARM::VLD4d8_UPD, true, true, SingleSpc, 4, 8 }, 239 240 { ARM::VLD4q16Pseudo_UPD, ARM::VLD4q16_UPD, true, true, EvenDblSpc, 4, 4 }, 241 { ARM::VLD4q16oddPseudo, ARM::VLD4q16, true, false, OddDblSpc, 4, 4 }, 242 { ARM::VLD4q16oddPseudo_UPD, ARM::VLD4q16_UPD, true, true, OddDblSpc, 4, 4 }, 243 { ARM::VLD4q32Pseudo_UPD, ARM::VLD4q32_UPD, true, true, EvenDblSpc, 4, 2 }, 244 { ARM::VLD4q32oddPseudo, ARM::VLD4q32, true, false, OddDblSpc, 4, 2 }, 245 { ARM::VLD4q32oddPseudo_UPD, ARM::VLD4q32_UPD, true, true, OddDblSpc, 4, 2 }, 246 { ARM::VLD4q8Pseudo_UPD, ARM::VLD4q8_UPD, true, true, EvenDblSpc, 4, 8 }, 247 { ARM::VLD4q8oddPseudo, ARM::VLD4q8, true, false, OddDblSpc, 4, 8 }, 248 { ARM::VLD4q8oddPseudo_UPD, ARM::VLD4q8_UPD, true, true, OddDblSpc, 4, 8 }, 249 250 { ARM::VST1LNq16Pseudo, ARM::VST1LNd16, false, false, EvenDblSpc, 1, 4 }, 251 { ARM::VST1LNq16Pseudo_UPD, ARM::VST1LNd16_UPD,false, true, EvenDblSpc, 1, 4 }, 252 { ARM::VST1LNq32Pseudo, ARM::VST1LNd32, false, false, EvenDblSpc, 1, 2 }, 253 { ARM::VST1LNq32Pseudo_UPD, ARM::VST1LNd32_UPD,false, true, EvenDblSpc, 1, 2 }, 254 { ARM::VST1LNq8Pseudo, ARM::VST1LNd8, false, false, EvenDblSpc, 1, 8 }, 255 { ARM::VST1LNq8Pseudo_UPD, ARM::VST1LNd8_UPD, false, true, EvenDblSpc, 1, 8 }, 256 257 { ARM::VST1d64QPseudo, ARM::VST1d64Q, false, false, SingleSpc, 4, 1 }, 258 { ARM::VST1d64QPseudo_UPD, ARM::VST1d64Q_UPD, false, true, SingleSpc, 4, 1 }, 259 { ARM::VST1d64TPseudo, ARM::VST1d64T, false, false, SingleSpc, 3, 1 }, 260 { ARM::VST1d64TPseudo_UPD, ARM::VST1d64T_UPD, false, true, SingleSpc, 3, 1 }, 261 262 { ARM::VST1q16Pseudo, ARM::VST1q16, false, false, SingleSpc, 2, 4 }, 263 { ARM::VST1q16Pseudo_UPD, ARM::VST1q16_UPD, false, true, SingleSpc, 2, 4 }, 264 { ARM::VST1q32Pseudo, ARM::VST1q32, false, false, SingleSpc, 2, 2 }, 265 { ARM::VST1q32Pseudo_UPD, ARM::VST1q32_UPD, false, true, SingleSpc, 2, 2 }, 266 { ARM::VST1q64Pseudo, ARM::VST1q64, false, false, SingleSpc, 2, 1 }, 267 { ARM::VST1q64Pseudo_UPD, ARM::VST1q64_UPD, false, true, SingleSpc, 2, 1 }, 268 { ARM::VST1q8Pseudo, ARM::VST1q8, false, false, SingleSpc, 2, 8 }, 269 { ARM::VST1q8Pseudo_UPD, ARM::VST1q8_UPD, false, true, SingleSpc, 2, 8 }, 270 271 { ARM::VST2LNd16Pseudo, ARM::VST2LNd16, false, false, SingleSpc, 2, 4 }, 272 { ARM::VST2LNd16Pseudo_UPD, ARM::VST2LNd16_UPD, false, true, SingleSpc, 2, 4 }, 273 { ARM::VST2LNd32Pseudo, ARM::VST2LNd32, false, false, SingleSpc, 2, 2 }, 274 { ARM::VST2LNd32Pseudo_UPD, ARM::VST2LNd32_UPD, false, true, SingleSpc, 2, 2 }, 275 { ARM::VST2LNd8Pseudo, ARM::VST2LNd8, false, false, SingleSpc, 2, 8 }, 276 { ARM::VST2LNd8Pseudo_UPD, ARM::VST2LNd8_UPD, false, true, SingleSpc, 2, 8 }, 277 { ARM::VST2LNq16Pseudo, ARM::VST2LNq16, false, false, EvenDblSpc, 2, 4}, 278 { ARM::VST2LNq16Pseudo_UPD, ARM::VST2LNq16_UPD, false, true, EvenDblSpc, 2, 4}, 279 { ARM::VST2LNq32Pseudo, ARM::VST2LNq32, false, false, EvenDblSpc, 2, 2}, 280 { ARM::VST2LNq32Pseudo_UPD, ARM::VST2LNq32_UPD, false, true, EvenDblSpc, 2, 2}, 281 282 { ARM::VST2d16Pseudo, ARM::VST2d16, false, false, SingleSpc, 2, 4 }, 283 { ARM::VST2d16Pseudo_UPD, ARM::VST2d16_UPD, false, true, SingleSpc, 2, 4 }, 284 { ARM::VST2d32Pseudo, ARM::VST2d32, false, false, SingleSpc, 2, 2 }, 285 { ARM::VST2d32Pseudo_UPD, ARM::VST2d32_UPD, false, true, SingleSpc, 2, 2 }, 286 { ARM::VST2d8Pseudo, ARM::VST2d8, false, false, SingleSpc, 2, 8 }, 287 { ARM::VST2d8Pseudo_UPD, ARM::VST2d8_UPD, false, true, SingleSpc, 2, 8 }, 288 289 { ARM::VST2q16Pseudo, ARM::VST2q16, false, false, SingleSpc, 4, 4 }, 290 { ARM::VST2q16Pseudo_UPD, ARM::VST2q16_UPD, false, true, SingleSpc, 4, 4 }, 291 { ARM::VST2q32Pseudo, ARM::VST2q32, false, false, SingleSpc, 4, 2 }, 292 { ARM::VST2q32Pseudo_UPD, ARM::VST2q32_UPD, false, true, SingleSpc, 4, 2 }, 293 { ARM::VST2q8Pseudo, ARM::VST2q8, false, false, SingleSpc, 4, 8 }, 294 { ARM::VST2q8Pseudo_UPD, ARM::VST2q8_UPD, false, true, SingleSpc, 4, 8 }, 295 296 { ARM::VST3LNd16Pseudo, ARM::VST3LNd16, false, false, SingleSpc, 3, 4 }, 297 { ARM::VST3LNd16Pseudo_UPD, ARM::VST3LNd16_UPD, false, true, SingleSpc, 3, 4 }, 298 { ARM::VST3LNd32Pseudo, ARM::VST3LNd32, false, false, SingleSpc, 3, 2 }, 299 { ARM::VST3LNd32Pseudo_UPD, ARM::VST3LNd32_UPD, false, true, SingleSpc, 3, 2 }, 300 { ARM::VST3LNd8Pseudo, ARM::VST3LNd8, false, false, SingleSpc, 3, 8 }, 301 { ARM::VST3LNd8Pseudo_UPD, ARM::VST3LNd8_UPD, false, true, SingleSpc, 3, 8 }, 302 { ARM::VST3LNq16Pseudo, ARM::VST3LNq16, false, false, EvenDblSpc, 3, 4}, 303 { ARM::VST3LNq16Pseudo_UPD, ARM::VST3LNq16_UPD, false, true, EvenDblSpc, 3, 4}, 304 { ARM::VST3LNq32Pseudo, ARM::VST3LNq32, false, false, EvenDblSpc, 3, 2}, 305 { ARM::VST3LNq32Pseudo_UPD, ARM::VST3LNq32_UPD, false, true, EvenDblSpc, 3, 2}, 306 307 { ARM::VST3d16Pseudo, ARM::VST3d16, false, false, SingleSpc, 3, 4 }, 308 { ARM::VST3d16Pseudo_UPD, ARM::VST3d16_UPD, false, true, SingleSpc, 3, 4 }, 309 { ARM::VST3d32Pseudo, ARM::VST3d32, false, false, SingleSpc, 3, 2 }, 310 { ARM::VST3d32Pseudo_UPD, ARM::VST3d32_UPD, false, true, SingleSpc, 3, 2 }, 311 { ARM::VST3d8Pseudo, ARM::VST3d8, false, false, SingleSpc, 3, 8 }, 312 { ARM::VST3d8Pseudo_UPD, ARM::VST3d8_UPD, false, true, SingleSpc, 3, 8 }, 313 314 { ARM::VST3q16Pseudo_UPD, ARM::VST3q16_UPD, false, true, EvenDblSpc, 3, 4 }, 315 { ARM::VST3q16oddPseudo, ARM::VST3q16, false, false, OddDblSpc, 3, 4 }, 316 { ARM::VST3q16oddPseudo_UPD, ARM::VST3q16_UPD, false, true, OddDblSpc, 3, 4 }, 317 { ARM::VST3q32Pseudo_UPD, ARM::VST3q32_UPD, false, true, EvenDblSpc, 3, 2 }, 318 { ARM::VST3q32oddPseudo, ARM::VST3q32, false, false, OddDblSpc, 3, 2 }, 319 { ARM::VST3q32oddPseudo_UPD, ARM::VST3q32_UPD, false, true, OddDblSpc, 3, 2 }, 320 { ARM::VST3q8Pseudo_UPD, ARM::VST3q8_UPD, false, true, EvenDblSpc, 3, 8 }, 321 { ARM::VST3q8oddPseudo, ARM::VST3q8, false, false, OddDblSpc, 3, 8 }, 322 { ARM::VST3q8oddPseudo_UPD, ARM::VST3q8_UPD, false, true, OddDblSpc, 3, 8 }, 323 324 { ARM::VST4LNd16Pseudo, ARM::VST4LNd16, false, false, SingleSpc, 4, 4 }, 325 { ARM::VST4LNd16Pseudo_UPD, ARM::VST4LNd16_UPD, false, true, SingleSpc, 4, 4 }, 326 { ARM::VST4LNd32Pseudo, ARM::VST4LNd32, false, false, SingleSpc, 4, 2 }, 327 { ARM::VST4LNd32Pseudo_UPD, ARM::VST4LNd32_UPD, false, true, SingleSpc, 4, 2 }, 328 { ARM::VST4LNd8Pseudo, ARM::VST4LNd8, false, false, SingleSpc, 4, 8 }, 329 { ARM::VST4LNd8Pseudo_UPD, ARM::VST4LNd8_UPD, false, true, SingleSpc, 4, 8 }, 330 { ARM::VST4LNq16Pseudo, ARM::VST4LNq16, false, false, EvenDblSpc, 4, 4}, 331 { ARM::VST4LNq16Pseudo_UPD, ARM::VST4LNq16_UPD, false, true, EvenDblSpc, 4, 4}, 332 { ARM::VST4LNq32Pseudo, ARM::VST4LNq32, false, false, EvenDblSpc, 4, 2}, 333 { ARM::VST4LNq32Pseudo_UPD, ARM::VST4LNq32_UPD, false, true, EvenDblSpc, 4, 2}, 334 335 { ARM::VST4d16Pseudo, ARM::VST4d16, false, false, SingleSpc, 4, 4 }, 336 { ARM::VST4d16Pseudo_UPD, ARM::VST4d16_UPD, false, true, SingleSpc, 4, 4 }, 337 { ARM::VST4d32Pseudo, ARM::VST4d32, false, false, SingleSpc, 4, 2 }, 338 { ARM::VST4d32Pseudo_UPD, ARM::VST4d32_UPD, false, true, SingleSpc, 4, 2 }, 339 { ARM::VST4d8Pseudo, ARM::VST4d8, false, false, SingleSpc, 4, 8 }, 340 { ARM::VST4d8Pseudo_UPD, ARM::VST4d8_UPD, false, true, SingleSpc, 4, 8 }, 341 342 { ARM::VST4q16Pseudo_UPD, ARM::VST4q16_UPD, false, true, EvenDblSpc, 4, 4 }, 343 { ARM::VST4q16oddPseudo, ARM::VST4q16, false, false, OddDblSpc, 4, 4 }, 344 { ARM::VST4q16oddPseudo_UPD, ARM::VST4q16_UPD, false, true, OddDblSpc, 4, 4 }, 345 { ARM::VST4q32Pseudo_UPD, ARM::VST4q32_UPD, false, true, EvenDblSpc, 4, 2 }, 346 { ARM::VST4q32oddPseudo, ARM::VST4q32, false, false, OddDblSpc, 4, 2 }, 347 { ARM::VST4q32oddPseudo_UPD, ARM::VST4q32_UPD, false, true, OddDblSpc, 4, 2 }, 348 { ARM::VST4q8Pseudo_UPD, ARM::VST4q8_UPD, false, true, EvenDblSpc, 4, 8 }, 349 { ARM::VST4q8oddPseudo, ARM::VST4q8, false, false, OddDblSpc, 4, 8 }, 350 { ARM::VST4q8oddPseudo_UPD, ARM::VST4q8_UPD, false, true, OddDblSpc, 4, 8 } 351 }; 352 353 /// LookupNEONLdSt - Search the NEONLdStTable for information about a NEON 354 /// load or store pseudo instruction. 355 static const NEONLdStTableEntry *LookupNEONLdSt(unsigned Opcode) { 356 unsigned NumEntries = array_lengthof(NEONLdStTable); 357 358 #ifndef NDEBUG 359 // Make sure the table is sorted. 360 static bool TableChecked = false; 361 if (!TableChecked) { 362 for (unsigned i = 0; i != NumEntries-1; ++i) 363 assert(NEONLdStTable[i] < NEONLdStTable[i+1] && 364 "NEONLdStTable is not sorted!"); 365 TableChecked = true; 366 } 367 #endif 368 369 const NEONLdStTableEntry *I = 370 std::lower_bound(NEONLdStTable, NEONLdStTable + NumEntries, Opcode); 371 if (I != NEONLdStTable + NumEntries && I->PseudoOpc == Opcode) 372 return I; 373 return NULL; 374 } 375 376 /// GetDSubRegs - Get 4 D subregisters of a Q, QQ, or QQQQ register, 377 /// corresponding to the specified register spacing. Not all of the results 378 /// are necessarily valid, e.g., a Q register only has 2 D subregisters. 379 static void GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, 380 const TargetRegisterInfo *TRI, unsigned &D0, 381 unsigned &D1, unsigned &D2, unsigned &D3) { 382 if (RegSpc == SingleSpc) { 383 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 384 D1 = TRI->getSubReg(Reg, ARM::dsub_1); 385 D2 = TRI->getSubReg(Reg, ARM::dsub_2); 386 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 387 } else if (RegSpc == EvenDblSpc) { 388 D0 = TRI->getSubReg(Reg, ARM::dsub_0); 389 D1 = TRI->getSubReg(Reg, ARM::dsub_2); 390 D2 = TRI->getSubReg(Reg, ARM::dsub_4); 391 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 392 } else { 393 assert(RegSpc == OddDblSpc && "unknown register spacing"); 394 D0 = TRI->getSubReg(Reg, ARM::dsub_1); 395 D1 = TRI->getSubReg(Reg, ARM::dsub_3); 396 D2 = TRI->getSubReg(Reg, ARM::dsub_5); 397 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 398 } 399 } 400 401 /// ExpandVLD - Translate VLD pseudo instructions with Q, QQ or QQQQ register 402 /// operands to real VLD instructions with D register operands. 403 void ARMExpandPseudo::ExpandVLD(MachineBasicBlock::iterator &MBBI) { 404 MachineInstr &MI = *MBBI; 405 MachineBasicBlock &MBB = *MI.getParent(); 406 407 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 408 assert(TableEntry && TableEntry->IsLoad && "NEONLdStTable lookup failed"); 409 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 410 unsigned NumRegs = TableEntry->NumRegs; 411 412 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 413 TII->get(TableEntry->RealOpc)); 414 unsigned OpIdx = 0; 415 416 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 417 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 418 unsigned D0, D1, D2, D3; 419 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 420 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 421 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 422 if (NumRegs > 2) 423 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 424 if (NumRegs > 3) 425 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 426 427 if (TableEntry->HasWriteBack) 428 MIB.addOperand(MI.getOperand(OpIdx++)); 429 430 // Copy the addrmode6 operands. 431 MIB.addOperand(MI.getOperand(OpIdx++)); 432 MIB.addOperand(MI.getOperand(OpIdx++)); 433 // Copy the am6offset operand. 434 if (TableEntry->HasWriteBack) 435 MIB.addOperand(MI.getOperand(OpIdx++)); 436 437 // For an instruction writing double-spaced subregs, the pseudo instruction 438 // has an extra operand that is a use of the super-register. Record the 439 // operand index and skip over it. 440 unsigned SrcOpIdx = 0; 441 if (RegSpc == EvenDblSpc || RegSpc == OddDblSpc) 442 SrcOpIdx = OpIdx++; 443 444 // Copy the predicate operands. 445 MIB.addOperand(MI.getOperand(OpIdx++)); 446 MIB.addOperand(MI.getOperand(OpIdx++)); 447 448 // Copy the super-register source operand used for double-spaced subregs over 449 // to the new instruction as an implicit operand. 450 if (SrcOpIdx != 0) { 451 MachineOperand MO = MI.getOperand(SrcOpIdx); 452 MO.setImplicit(true); 453 MIB.addOperand(MO); 454 } 455 // Add an implicit def for the super-register. 456 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 457 TransferImpOps(MI, MIB, MIB); 458 459 // Transfer memoperands. 460 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 461 462 MI.eraseFromParent(); 463 } 464 465 /// ExpandVST - Translate VST pseudo instructions with Q, QQ or QQQQ register 466 /// operands to real VST instructions with D register operands. 467 void ARMExpandPseudo::ExpandVST(MachineBasicBlock::iterator &MBBI) { 468 MachineInstr &MI = *MBBI; 469 MachineBasicBlock &MBB = *MI.getParent(); 470 471 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 472 assert(TableEntry && !TableEntry->IsLoad && "NEONLdStTable lookup failed"); 473 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 474 unsigned NumRegs = TableEntry->NumRegs; 475 476 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 477 TII->get(TableEntry->RealOpc)); 478 unsigned OpIdx = 0; 479 if (TableEntry->HasWriteBack) 480 MIB.addOperand(MI.getOperand(OpIdx++)); 481 482 // Copy the addrmode6 operands. 483 MIB.addOperand(MI.getOperand(OpIdx++)); 484 MIB.addOperand(MI.getOperand(OpIdx++)); 485 // Copy the am6offset operand. 486 if (TableEntry->HasWriteBack) 487 MIB.addOperand(MI.getOperand(OpIdx++)); 488 489 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 490 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 491 unsigned D0, D1, D2, D3; 492 GetDSubRegs(SrcReg, RegSpc, TRI, D0, D1, D2, D3); 493 MIB.addReg(D0).addReg(D1); 494 if (NumRegs > 2) 495 MIB.addReg(D2); 496 if (NumRegs > 3) 497 MIB.addReg(D3); 498 499 // Copy the predicate operands. 500 MIB.addOperand(MI.getOperand(OpIdx++)); 501 MIB.addOperand(MI.getOperand(OpIdx++)); 502 503 if (SrcIsKill) // Add an implicit kill for the super-reg. 504 MIB->addRegisterKilled(SrcReg, TRI, true); 505 TransferImpOps(MI, MIB, MIB); 506 507 // Transfer memoperands. 508 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 509 510 MI.eraseFromParent(); 511 } 512 513 /// ExpandLaneOp - Translate VLD*LN and VST*LN instructions with Q, QQ or QQQQ 514 /// register operands to real instructions with D register operands. 515 void ARMExpandPseudo::ExpandLaneOp(MachineBasicBlock::iterator &MBBI) { 516 MachineInstr &MI = *MBBI; 517 MachineBasicBlock &MBB = *MI.getParent(); 518 519 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); 520 assert(TableEntry && "NEONLdStTable lookup failed"); 521 NEONRegSpacing RegSpc = TableEntry->RegSpacing; 522 unsigned NumRegs = TableEntry->NumRegs; 523 unsigned RegElts = TableEntry->RegElts; 524 525 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), 526 TII->get(TableEntry->RealOpc)); 527 unsigned OpIdx = 0; 528 // The lane operand is always the 3rd from last operand, before the 2 529 // predicate operands. 530 unsigned Lane = MI.getOperand(MI.getDesc().getNumOperands() - 3).getImm(); 531 532 // Adjust the lane and spacing as needed for Q registers. 533 assert(RegSpc != OddDblSpc && "unexpected register spacing for VLD/VST-lane"); 534 if (RegSpc == EvenDblSpc && Lane >= RegElts) { 535 RegSpc = OddDblSpc; 536 Lane -= RegElts; 537 } 538 assert(Lane < RegElts && "out of range lane for VLD/VST-lane"); 539 540 unsigned D0 = 0, D1 = 0, D2 = 0, D3 = 0; 541 unsigned DstReg = 0; 542 bool DstIsDead = false; 543 if (TableEntry->IsLoad) { 544 DstIsDead = MI.getOperand(OpIdx).isDead(); 545 DstReg = MI.getOperand(OpIdx++).getReg(); 546 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 547 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)); 548 if (NumRegs > 1) 549 MIB.addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 550 if (NumRegs > 2) 551 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead)); 552 if (NumRegs > 3) 553 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 554 } 555 556 if (TableEntry->HasWriteBack) 557 MIB.addOperand(MI.getOperand(OpIdx++)); 558 559 // Copy the addrmode6 operands. 560 MIB.addOperand(MI.getOperand(OpIdx++)); 561 MIB.addOperand(MI.getOperand(OpIdx++)); 562 // Copy the am6offset operand. 563 if (TableEntry->HasWriteBack) 564 MIB.addOperand(MI.getOperand(OpIdx++)); 565 566 // Grab the super-register source. 567 MachineOperand MO = MI.getOperand(OpIdx++); 568 if (!TableEntry->IsLoad) 569 GetDSubRegs(MO.getReg(), RegSpc, TRI, D0, D1, D2, D3); 570 571 // Add the subregs as sources of the new instruction. 572 unsigned SrcFlags = (getUndefRegState(MO.isUndef()) | 573 getKillRegState(MO.isKill())); 574 MIB.addReg(D0, SrcFlags); 575 if (NumRegs > 1) 576 MIB.addReg(D1, SrcFlags); 577 if (NumRegs > 2) 578 MIB.addReg(D2, SrcFlags); 579 if (NumRegs > 3) 580 MIB.addReg(D3, SrcFlags); 581 582 // Add the lane number operand. 583 MIB.addImm(Lane); 584 OpIdx += 1; 585 586 // Copy the predicate operands. 587 MIB.addOperand(MI.getOperand(OpIdx++)); 588 MIB.addOperand(MI.getOperand(OpIdx++)); 589 590 // Copy the super-register source to be an implicit source. 591 MO.setImplicit(true); 592 MIB.addOperand(MO); 593 if (TableEntry->IsLoad) 594 // Add an implicit def for the super-register. 595 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 596 TransferImpOps(MI, MIB, MIB); 597 MI.eraseFromParent(); 598 } 599 600 /// ExpandVTBL - Translate VTBL and VTBX pseudo instructions with Q or QQ 601 /// register operands to real instructions with D register operands. 602 void ARMExpandPseudo::ExpandVTBL(MachineBasicBlock::iterator &MBBI, 603 unsigned Opc, bool IsExt, unsigned NumRegs) { 604 MachineInstr &MI = *MBBI; 605 MachineBasicBlock &MBB = *MI.getParent(); 606 607 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc)); 608 unsigned OpIdx = 0; 609 610 // Transfer the destination register operand. 611 MIB.addOperand(MI.getOperand(OpIdx++)); 612 if (IsExt) 613 MIB.addOperand(MI.getOperand(OpIdx++)); 614 615 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 616 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 617 unsigned D0, D1, D2, D3; 618 GetDSubRegs(SrcReg, SingleSpc, TRI, D0, D1, D2, D3); 619 MIB.addReg(D0).addReg(D1); 620 if (NumRegs > 2) 621 MIB.addReg(D2); 622 if (NumRegs > 3) 623 MIB.addReg(D3); 624 625 // Copy the other source register operand. 626 MIB.addOperand(MI.getOperand(OpIdx++)); 627 628 // Copy the predicate operands. 629 MIB.addOperand(MI.getOperand(OpIdx++)); 630 MIB.addOperand(MI.getOperand(OpIdx++)); 631 632 if (SrcIsKill) // Add an implicit kill for the super-reg. 633 MIB->addRegisterKilled(SrcReg, TRI, true); 634 TransferImpOps(MI, MIB, MIB); 635 MI.eraseFromParent(); 636 } 637 638 void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB, 639 MachineBasicBlock::iterator &MBBI) { 640 MachineInstr &MI = *MBBI; 641 unsigned Opcode = MI.getOpcode(); 642 unsigned PredReg = 0; 643 ARMCC::CondCodes Pred = llvm::getInstrPredicate(&MI, PredReg); 644 unsigned DstReg = MI.getOperand(0).getReg(); 645 bool DstIsDead = MI.getOperand(0).isDead(); 646 bool isCC = Opcode == ARM::MOVCCi32imm || Opcode == ARM::t2MOVCCi32imm; 647 const MachineOperand &MO = MI.getOperand(isCC ? 2 : 1); 648 MachineInstrBuilder LO16, HI16; 649 650 if (!STI->hasV6T2Ops() && 651 (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) { 652 // Expand into a movi + orr. 653 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); 654 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri)) 655 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 656 .addReg(DstReg); 657 658 assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!"); 659 unsigned ImmVal = (unsigned)MO.getImm(); 660 unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal); 661 unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal); 662 LO16 = LO16.addImm(SOImmValV1); 663 HI16 = HI16.addImm(SOImmValV2); 664 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 665 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 666 LO16.addImm(Pred).addReg(PredReg).addReg(0); 667 HI16.addImm(Pred).addReg(PredReg).addReg(0); 668 TransferImpOps(MI, LO16, HI16); 669 MI.eraseFromParent(); 670 return; 671 } 672 673 unsigned LO16Opc = 0; 674 unsigned HI16Opc = 0; 675 if (Opcode == ARM::t2MOVi32imm || Opcode == ARM::t2MOVCCi32imm) { 676 LO16Opc = ARM::t2MOVi16; 677 HI16Opc = ARM::t2MOVTi16; 678 } else { 679 LO16Opc = ARM::MOVi16; 680 HI16Opc = ARM::MOVTi16; 681 } 682 683 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(LO16Opc), DstReg); 684 HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(HI16Opc)) 685 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 686 .addReg(DstReg); 687 688 if (MO.isImm()) { 689 unsigned Imm = MO.getImm(); 690 unsigned Lo16 = Imm & 0xffff; 691 unsigned Hi16 = (Imm >> 16) & 0xffff; 692 LO16 = LO16.addImm(Lo16); 693 HI16 = HI16.addImm(Hi16); 694 } else { 695 const GlobalValue *GV = MO.getGlobal(); 696 unsigned TF = MO.getTargetFlags(); 697 LO16 = LO16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_LO16); 698 HI16 = HI16.addGlobalAddress(GV, MO.getOffset(), TF | ARMII::MO_HI16); 699 } 700 701 LO16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 702 HI16->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 703 LO16.addImm(Pred).addReg(PredReg); 704 HI16.addImm(Pred).addReg(PredReg); 705 706 TransferImpOps(MI, LO16, HI16); 707 MI.eraseFromParent(); 708 } 709 710 bool ARMExpandPseudo::ExpandMI(MachineBasicBlock &MBB, 711 MachineBasicBlock::iterator MBBI) { 712 MachineInstr &MI = *MBBI; 713 unsigned Opcode = MI.getOpcode(); 714 switch (Opcode) { 715 default: 716 return false; 717 case ARM::VMOVScc: 718 case ARM::VMOVDcc: { 719 unsigned newOpc = Opcode == ARM::VMOVScc ? ARM::VMOVS : ARM::VMOVD; 720 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(newOpc), 721 MI.getOperand(1).getReg()) 722 .addReg(MI.getOperand(2).getReg(), 723 getKillRegState(MI.getOperand(2).isKill())) 724 .addImm(MI.getOperand(3).getImm()) // 'pred' 725 .addReg(MI.getOperand(4).getReg()); 726 727 MI.eraseFromParent(); 728 return true; 729 } 730 case ARM::t2MOVCCr: 731 case ARM::MOVCCr: { 732 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVr : ARM::MOVr; 733 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 734 MI.getOperand(1).getReg()) 735 .addReg(MI.getOperand(2).getReg(), 736 getKillRegState(MI.getOperand(2).isKill())) 737 .addImm(MI.getOperand(3).getImm()) // 'pred' 738 .addReg(MI.getOperand(4).getReg()) 739 .addReg(0); // 's' bit 740 741 MI.eraseFromParent(); 742 return true; 743 } 744 case ARM::MOVCCs: { 745 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 746 (MI.getOperand(1).getReg())) 747 .addReg(MI.getOperand(2).getReg(), 748 getKillRegState(MI.getOperand(2).isKill())) 749 .addReg(MI.getOperand(3).getReg(), 750 getKillRegState(MI.getOperand(3).isKill())) 751 .addImm(MI.getOperand(4).getImm()) 752 .addImm(MI.getOperand(5).getImm()) // 'pred' 753 .addReg(MI.getOperand(6).getReg()) 754 .addReg(0); // 's' bit 755 756 MI.eraseFromParent(); 757 return true; 758 } 759 case ARM::MOVCCi16: { 760 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi16), 761 MI.getOperand(1).getReg()) 762 .addImm(MI.getOperand(2).getImm()) 763 .addImm(MI.getOperand(3).getImm()) // 'pred' 764 .addReg(MI.getOperand(4).getReg()); 765 766 MI.eraseFromParent(); 767 return true; 768 } 769 case ARM::t2MOVCCi: 770 case ARM::MOVCCi: { 771 unsigned Opc = AFI->isThumbFunction() ? ARM::t2MOVi : ARM::MOVi; 772 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(Opc), 773 MI.getOperand(1).getReg()) 774 .addImm(MI.getOperand(2).getImm()) 775 .addImm(MI.getOperand(3).getImm()) // 'pred' 776 .addReg(MI.getOperand(4).getReg()) 777 .addReg(0); // 's' bit 778 779 MI.eraseFromParent(); 780 return true; 781 } 782 case ARM::MVNCCi: { 783 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MVNi), 784 MI.getOperand(1).getReg()) 785 .addImm(MI.getOperand(2).getImm()) 786 .addImm(MI.getOperand(3).getImm()) // 'pred' 787 .addReg(MI.getOperand(4).getReg()) 788 .addReg(0); // 's' bit 789 790 MI.eraseFromParent(); 791 return true; 792 } 793 case ARM::Int_eh_sjlj_dispatchsetup: { 794 MachineFunction &MF = *MI.getParent()->getParent(); 795 const ARMBaseInstrInfo *AII = 796 static_cast<const ARMBaseInstrInfo*>(TII); 797 const ARMBaseRegisterInfo &RI = AII->getRegisterInfo(); 798 // For functions using a base pointer, we rematerialize it (via the frame 799 // pointer) here since eh.sjlj.setjmp and eh.sjlj.longjmp don't do it 800 // for us. Otherwise, expand to nothing. 801 if (RI.hasBasePointer(MF)) { 802 int32_t NumBytes = AFI->getFramePtrSpillOffset(); 803 unsigned FramePtr = RI.getFrameRegister(MF); 804 assert(MF.getTarget().getFrameLowering()->hasFP(MF) && 805 "base pointer without frame pointer?"); 806 807 if (AFI->isThumb2Function()) { 808 llvm::emitT2RegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 809 FramePtr, -NumBytes, ARMCC::AL, 0, *TII); 810 } else if (AFI->isThumbFunction()) { 811 llvm::emitThumbRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 812 FramePtr, -NumBytes, *TII, RI); 813 } else { 814 llvm::emitARMRegPlusImmediate(MBB, MBBI, MI.getDebugLoc(), ARM::R6, 815 FramePtr, -NumBytes, ARMCC::AL, 0, 816 *TII); 817 } 818 // If there's dynamic realignment, adjust for it. 819 if (RI.needsStackRealignment(MF)) { 820 MachineFrameInfo *MFI = MF.getFrameInfo(); 821 unsigned MaxAlign = MFI->getMaxAlignment(); 822 assert (!AFI->isThumb1OnlyFunction()); 823 // Emit bic r6, r6, MaxAlign 824 unsigned bicOpc = AFI->isThumbFunction() ? 825 ARM::t2BICri : ARM::BICri; 826 AddDefaultCC(AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 827 TII->get(bicOpc), ARM::R6) 828 .addReg(ARM::R6, RegState::Kill) 829 .addImm(MaxAlign-1))); 830 } 831 832 } 833 MI.eraseFromParent(); 834 return true; 835 } 836 837 case ARM::MOVsrl_flag: 838 case ARM::MOVsra_flag: { 839 // These are just fancy MOVs insructions. 840 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 841 MI.getOperand(0).getReg()) 842 .addOperand(MI.getOperand(1)) 843 .addReg(0) 844 .addImm(ARM_AM::getSORegOpc((Opcode == ARM::MOVsrl_flag ? 845 ARM_AM::lsr : ARM_AM::asr), 846 1))) 847 .addReg(ARM::CPSR, RegState::Define); 848 MI.eraseFromParent(); 849 return true; 850 } 851 case ARM::RRX: { 852 // This encodes as "MOVs Rd, Rm, rrx 853 MachineInstrBuilder MIB = 854 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVs), 855 MI.getOperand(0).getReg()) 856 .addOperand(MI.getOperand(1)) 857 .addOperand(MI.getOperand(1)) 858 .addImm(ARM_AM::getSORegOpc(ARM_AM::rrx, 0))) 859 .addReg(0); 860 TransferImpOps(MI, MIB, MIB); 861 MI.eraseFromParent(); 862 return true; 863 } 864 case ARM::tTPsoft: 865 case ARM::TPsoft: { 866 MachineInstrBuilder MIB = 867 BuildMI(MBB, MBBI, MI.getDebugLoc(), 868 TII->get(Opcode == ARM::tTPsoft ? ARM::tBL : ARM::BL)) 869 .addExternalSymbol("__aeabi_read_tp", 0); 870 871 MIB->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 872 TransferImpOps(MI, MIB, MIB); 873 MI.eraseFromParent(); 874 return true; 875 } 876 case ARM::tLDRpci_pic: 877 case ARM::t2LDRpci_pic: { 878 unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) 879 ? ARM::tLDRpci : ARM::t2LDRpci; 880 unsigned DstReg = MI.getOperand(0).getReg(); 881 bool DstIsDead = MI.getOperand(0).isDead(); 882 MachineInstrBuilder MIB1 = 883 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 884 TII->get(NewLdOpc), DstReg) 885 .addOperand(MI.getOperand(1))); 886 MIB1->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 887 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 888 TII->get(ARM::tPICADD)) 889 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 890 .addReg(DstReg) 891 .addOperand(MI.getOperand(2)); 892 TransferImpOps(MI, MIB1, MIB2); 893 MI.eraseFromParent(); 894 return true; 895 } 896 897 case ARM::MOV_ga_dyn: 898 case ARM::MOV_ga_pcrel: 899 case ARM::MOV_ga_pcrel_ldr: 900 case ARM::t2MOV_ga_dyn: 901 case ARM::t2MOV_ga_pcrel: { 902 // Expand into movw + movw. Also "add pc" / ldr [pc] in PIC mode. 903 unsigned LabelId = AFI->createPICLabelUId(); 904 unsigned DstReg = MI.getOperand(0).getReg(); 905 bool DstIsDead = MI.getOperand(0).isDead(); 906 const MachineOperand &MO1 = MI.getOperand(1); 907 const GlobalValue *GV = MO1.getGlobal(); 908 unsigned TF = MO1.getTargetFlags(); 909 bool isARM = (Opcode != ARM::t2MOV_ga_pcrel && Opcode!=ARM::t2MOV_ga_dyn); 910 bool isPIC = (Opcode != ARM::MOV_ga_dyn && Opcode != ARM::t2MOV_ga_dyn); 911 unsigned LO16Opc = isARM ? ARM::MOVi16_ga_pcrel : ARM::t2MOVi16_ga_pcrel; 912 unsigned HI16Opc = isARM ? ARM::MOVTi16_ga_pcrel :ARM::t2MOVTi16_ga_pcrel; 913 unsigned LO16TF = isPIC 914 ? ARMII::MO_LO16_NONLAZY_PIC : ARMII::MO_LO16_NONLAZY; 915 unsigned HI16TF = isPIC 916 ? ARMII::MO_HI16_NONLAZY_PIC : ARMII::MO_HI16_NONLAZY; 917 unsigned PICAddOpc = isARM 918 ? (Opcode == ARM::MOV_ga_pcrel_ldr ? ARM::PICLDR : ARM::PICADD) 919 : ARM::tPICADD; 920 MachineInstrBuilder MIB1 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 921 TII->get(LO16Opc), DstReg) 922 .addGlobalAddress(GV, MO1.getOffset(), TF | LO16TF) 923 .addImm(LabelId); 924 MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 925 TII->get(HI16Opc), DstReg) 926 .addReg(DstReg) 927 .addGlobalAddress(GV, MO1.getOffset(), TF | HI16TF) 928 .addImm(LabelId); 929 if (!isPIC) { 930 TransferImpOps(MI, MIB1, MIB2); 931 MI.eraseFromParent(); 932 return true; 933 } 934 935 MachineInstrBuilder MIB3 = BuildMI(MBB, MBBI, MI.getDebugLoc(), 936 TII->get(PICAddOpc)) 937 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) 938 .addReg(DstReg).addImm(LabelId); 939 if (isARM) { 940 AddDefaultPred(MIB3); 941 if (Opcode == ARM::MOV_ga_pcrel_ldr) 942 MIB2->setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); 943 } 944 TransferImpOps(MI, MIB1, MIB3); 945 MI.eraseFromParent(); 946 return true; 947 } 948 949 case ARM::MOVi32imm: 950 case ARM::MOVCCi32imm: 951 case ARM::t2MOVi32imm: 952 case ARM::t2MOVCCi32imm: 953 ExpandMOV32BitImm(MBB, MBBI); 954 return true; 955 956 case ARM::VMOVQQ: { 957 unsigned DstReg = MI.getOperand(0).getReg(); 958 bool DstIsDead = MI.getOperand(0).isDead(); 959 unsigned EvenDst = TRI->getSubReg(DstReg, ARM::qsub_0); 960 unsigned OddDst = TRI->getSubReg(DstReg, ARM::qsub_1); 961 unsigned SrcReg = MI.getOperand(1).getReg(); 962 bool SrcIsKill = MI.getOperand(1).isKill(); 963 unsigned EvenSrc = TRI->getSubReg(SrcReg, ARM::qsub_0); 964 unsigned OddSrc = TRI->getSubReg(SrcReg, ARM::qsub_1); 965 MachineInstrBuilder Even = 966 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 967 TII->get(ARM::VORRq)) 968 .addReg(EvenDst, 969 RegState::Define | getDeadRegState(DstIsDead)) 970 .addReg(EvenSrc, getKillRegState(SrcIsKill)) 971 .addReg(EvenSrc, getKillRegState(SrcIsKill))); 972 MachineInstrBuilder Odd = 973 AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), 974 TII->get(ARM::VORRq)) 975 .addReg(OddDst, 976 RegState::Define | getDeadRegState(DstIsDead)) 977 .addReg(OddSrc, getKillRegState(SrcIsKill)) 978 .addReg(OddSrc, getKillRegState(SrcIsKill))); 979 TransferImpOps(MI, Even, Odd); 980 MI.eraseFromParent(); 981 return true; 982 } 983 984 case ARM::VLDMQIA: { 985 unsigned NewOpc = ARM::VLDMDIA; 986 MachineInstrBuilder MIB = 987 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 988 unsigned OpIdx = 0; 989 990 // Grab the Q register destination. 991 bool DstIsDead = MI.getOperand(OpIdx).isDead(); 992 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); 993 994 // Copy the source register. 995 MIB.addOperand(MI.getOperand(OpIdx++)); 996 997 // Copy the predicate operands. 998 MIB.addOperand(MI.getOperand(OpIdx++)); 999 MIB.addOperand(MI.getOperand(OpIdx++)); 1000 1001 // Add the destination operands (D subregs). 1002 unsigned D0 = TRI->getSubReg(DstReg, ARM::dsub_0); 1003 unsigned D1 = TRI->getSubReg(DstReg, ARM::dsub_1); 1004 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead)) 1005 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead)); 1006 1007 // Add an implicit def for the super-register. 1008 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); 1009 TransferImpOps(MI, MIB, MIB); 1010 MI.eraseFromParent(); 1011 return true; 1012 } 1013 1014 case ARM::VSTMQIA: { 1015 unsigned NewOpc = ARM::VSTMDIA; 1016 MachineInstrBuilder MIB = 1017 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1018 unsigned OpIdx = 0; 1019 1020 // Grab the Q register source. 1021 bool SrcIsKill = MI.getOperand(OpIdx).isKill(); 1022 unsigned SrcReg = MI.getOperand(OpIdx++).getReg(); 1023 1024 // Copy the destination register. 1025 MIB.addOperand(MI.getOperand(OpIdx++)); 1026 1027 // Copy the predicate operands. 1028 MIB.addOperand(MI.getOperand(OpIdx++)); 1029 MIB.addOperand(MI.getOperand(OpIdx++)); 1030 1031 // Add the source operands (D subregs). 1032 unsigned D0 = TRI->getSubReg(SrcReg, ARM::dsub_0); 1033 unsigned D1 = TRI->getSubReg(SrcReg, ARM::dsub_1); 1034 MIB.addReg(D0).addReg(D1); 1035 1036 if (SrcIsKill) // Add an implicit kill for the Q register. 1037 MIB->addRegisterKilled(SrcReg, TRI, true); 1038 1039 TransferImpOps(MI, MIB, MIB); 1040 MI.eraseFromParent(); 1041 return true; 1042 } 1043 case ARM::VDUPfqf: 1044 case ARM::VDUPfdf:{ 1045 unsigned NewOpc = Opcode == ARM::VDUPfqf ? ARM::VDUPLN32q : 1046 ARM::VDUPLN32d; 1047 MachineInstrBuilder MIB = 1048 BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewOpc)); 1049 unsigned OpIdx = 0; 1050 unsigned SrcReg = MI.getOperand(1).getReg(); 1051 unsigned Lane = getARMRegisterNumbering(SrcReg) & 1; 1052 unsigned DReg = TRI->getMatchingSuperReg(SrcReg, 1053 Lane & 1 ? ARM::ssub_1 : ARM::ssub_0, 1054 &ARM::DPR_VFP2RegClass); 1055 // The lane is [0,1] for the containing DReg superregister. 1056 // Copy the dst/src register operands. 1057 MIB.addOperand(MI.getOperand(OpIdx++)); 1058 MIB.addReg(DReg); 1059 ++OpIdx; 1060 // Add the lane select operand. 1061 MIB.addImm(Lane); 1062 // Add the predicate operands. 1063 MIB.addOperand(MI.getOperand(OpIdx++)); 1064 MIB.addOperand(MI.getOperand(OpIdx++)); 1065 1066 TransferImpOps(MI, MIB, MIB); 1067 MI.eraseFromParent(); 1068 return true; 1069 } 1070 1071 case ARM::VLD1q8Pseudo: 1072 case ARM::VLD1q16Pseudo: 1073 case ARM::VLD1q32Pseudo: 1074 case ARM::VLD1q64Pseudo: 1075 case ARM::VLD1q8Pseudo_UPD: 1076 case ARM::VLD1q16Pseudo_UPD: 1077 case ARM::VLD1q32Pseudo_UPD: 1078 case ARM::VLD1q64Pseudo_UPD: 1079 case ARM::VLD2d8Pseudo: 1080 case ARM::VLD2d16Pseudo: 1081 case ARM::VLD2d32Pseudo: 1082 case ARM::VLD2q8Pseudo: 1083 case ARM::VLD2q16Pseudo: 1084 case ARM::VLD2q32Pseudo: 1085 case ARM::VLD2d8Pseudo_UPD: 1086 case ARM::VLD2d16Pseudo_UPD: 1087 case ARM::VLD2d32Pseudo_UPD: 1088 case ARM::VLD2q8Pseudo_UPD: 1089 case ARM::VLD2q16Pseudo_UPD: 1090 case ARM::VLD2q32Pseudo_UPD: 1091 case ARM::VLD3d8Pseudo: 1092 case ARM::VLD3d16Pseudo: 1093 case ARM::VLD3d32Pseudo: 1094 case ARM::VLD1d64TPseudo: 1095 case ARM::VLD3d8Pseudo_UPD: 1096 case ARM::VLD3d16Pseudo_UPD: 1097 case ARM::VLD3d32Pseudo_UPD: 1098 case ARM::VLD1d64TPseudo_UPD: 1099 case ARM::VLD3q8Pseudo_UPD: 1100 case ARM::VLD3q16Pseudo_UPD: 1101 case ARM::VLD3q32Pseudo_UPD: 1102 case ARM::VLD3q8oddPseudo: 1103 case ARM::VLD3q16oddPseudo: 1104 case ARM::VLD3q32oddPseudo: 1105 case ARM::VLD3q8oddPseudo_UPD: 1106 case ARM::VLD3q16oddPseudo_UPD: 1107 case ARM::VLD3q32oddPseudo_UPD: 1108 case ARM::VLD4d8Pseudo: 1109 case ARM::VLD4d16Pseudo: 1110 case ARM::VLD4d32Pseudo: 1111 case ARM::VLD1d64QPseudo: 1112 case ARM::VLD4d8Pseudo_UPD: 1113 case ARM::VLD4d16Pseudo_UPD: 1114 case ARM::VLD4d32Pseudo_UPD: 1115 case ARM::VLD1d64QPseudo_UPD: 1116 case ARM::VLD4q8Pseudo_UPD: 1117 case ARM::VLD4q16Pseudo_UPD: 1118 case ARM::VLD4q32Pseudo_UPD: 1119 case ARM::VLD4q8oddPseudo: 1120 case ARM::VLD4q16oddPseudo: 1121 case ARM::VLD4q32oddPseudo: 1122 case ARM::VLD4q8oddPseudo_UPD: 1123 case ARM::VLD4q16oddPseudo_UPD: 1124 case ARM::VLD4q32oddPseudo_UPD: 1125 case ARM::VLD1DUPq8Pseudo: 1126 case ARM::VLD1DUPq16Pseudo: 1127 case ARM::VLD1DUPq32Pseudo: 1128 case ARM::VLD1DUPq8Pseudo_UPD: 1129 case ARM::VLD1DUPq16Pseudo_UPD: 1130 case ARM::VLD1DUPq32Pseudo_UPD: 1131 case ARM::VLD2DUPd8Pseudo: 1132 case ARM::VLD2DUPd16Pseudo: 1133 case ARM::VLD2DUPd32Pseudo: 1134 case ARM::VLD2DUPd8Pseudo_UPD: 1135 case ARM::VLD2DUPd16Pseudo_UPD: 1136 case ARM::VLD2DUPd32Pseudo_UPD: 1137 case ARM::VLD3DUPd8Pseudo: 1138 case ARM::VLD3DUPd16Pseudo: 1139 case ARM::VLD3DUPd32Pseudo: 1140 case ARM::VLD3DUPd8Pseudo_UPD: 1141 case ARM::VLD3DUPd16Pseudo_UPD: 1142 case ARM::VLD3DUPd32Pseudo_UPD: 1143 case ARM::VLD4DUPd8Pseudo: 1144 case ARM::VLD4DUPd16Pseudo: 1145 case ARM::VLD4DUPd32Pseudo: 1146 case ARM::VLD4DUPd8Pseudo_UPD: 1147 case ARM::VLD4DUPd16Pseudo_UPD: 1148 case ARM::VLD4DUPd32Pseudo_UPD: 1149 ExpandVLD(MBBI); 1150 return true; 1151 1152 case ARM::VST1q8Pseudo: 1153 case ARM::VST1q16Pseudo: 1154 case ARM::VST1q32Pseudo: 1155 case ARM::VST1q64Pseudo: 1156 case ARM::VST1q8Pseudo_UPD: 1157 case ARM::VST1q16Pseudo_UPD: 1158 case ARM::VST1q32Pseudo_UPD: 1159 case ARM::VST1q64Pseudo_UPD: 1160 case ARM::VST2d8Pseudo: 1161 case ARM::VST2d16Pseudo: 1162 case ARM::VST2d32Pseudo: 1163 case ARM::VST2q8Pseudo: 1164 case ARM::VST2q16Pseudo: 1165 case ARM::VST2q32Pseudo: 1166 case ARM::VST2d8Pseudo_UPD: 1167 case ARM::VST2d16Pseudo_UPD: 1168 case ARM::VST2d32Pseudo_UPD: 1169 case ARM::VST2q8Pseudo_UPD: 1170 case ARM::VST2q16Pseudo_UPD: 1171 case ARM::VST2q32Pseudo_UPD: 1172 case ARM::VST3d8Pseudo: 1173 case ARM::VST3d16Pseudo: 1174 case ARM::VST3d32Pseudo: 1175 case ARM::VST1d64TPseudo: 1176 case ARM::VST3d8Pseudo_UPD: 1177 case ARM::VST3d16Pseudo_UPD: 1178 case ARM::VST3d32Pseudo_UPD: 1179 case ARM::VST1d64TPseudo_UPD: 1180 case ARM::VST3q8Pseudo_UPD: 1181 case ARM::VST3q16Pseudo_UPD: 1182 case ARM::VST3q32Pseudo_UPD: 1183 case ARM::VST3q8oddPseudo: 1184 case ARM::VST3q16oddPseudo: 1185 case ARM::VST3q32oddPseudo: 1186 case ARM::VST3q8oddPseudo_UPD: 1187 case ARM::VST3q16oddPseudo_UPD: 1188 case ARM::VST3q32oddPseudo_UPD: 1189 case ARM::VST4d8Pseudo: 1190 case ARM::VST4d16Pseudo: 1191 case ARM::VST4d32Pseudo: 1192 case ARM::VST1d64QPseudo: 1193 case ARM::VST4d8Pseudo_UPD: 1194 case ARM::VST4d16Pseudo_UPD: 1195 case ARM::VST4d32Pseudo_UPD: 1196 case ARM::VST1d64QPseudo_UPD: 1197 case ARM::VST4q8Pseudo_UPD: 1198 case ARM::VST4q16Pseudo_UPD: 1199 case ARM::VST4q32Pseudo_UPD: 1200 case ARM::VST4q8oddPseudo: 1201 case ARM::VST4q16oddPseudo: 1202 case ARM::VST4q32oddPseudo: 1203 case ARM::VST4q8oddPseudo_UPD: 1204 case ARM::VST4q16oddPseudo_UPD: 1205 case ARM::VST4q32oddPseudo_UPD: 1206 ExpandVST(MBBI); 1207 return true; 1208 1209 case ARM::VLD1LNq8Pseudo: 1210 case ARM::VLD1LNq16Pseudo: 1211 case ARM::VLD1LNq32Pseudo: 1212 case ARM::VLD1LNq8Pseudo_UPD: 1213 case ARM::VLD1LNq16Pseudo_UPD: 1214 case ARM::VLD1LNq32Pseudo_UPD: 1215 case ARM::VLD2LNd8Pseudo: 1216 case ARM::VLD2LNd16Pseudo: 1217 case ARM::VLD2LNd32Pseudo: 1218 case ARM::VLD2LNq16Pseudo: 1219 case ARM::VLD2LNq32Pseudo: 1220 case ARM::VLD2LNd8Pseudo_UPD: 1221 case ARM::VLD2LNd16Pseudo_UPD: 1222 case ARM::VLD2LNd32Pseudo_UPD: 1223 case ARM::VLD2LNq16Pseudo_UPD: 1224 case ARM::VLD2LNq32Pseudo_UPD: 1225 case ARM::VLD3LNd8Pseudo: 1226 case ARM::VLD3LNd16Pseudo: 1227 case ARM::VLD3LNd32Pseudo: 1228 case ARM::VLD3LNq16Pseudo: 1229 case ARM::VLD3LNq32Pseudo: 1230 case ARM::VLD3LNd8Pseudo_UPD: 1231 case ARM::VLD3LNd16Pseudo_UPD: 1232 case ARM::VLD3LNd32Pseudo_UPD: 1233 case ARM::VLD3LNq16Pseudo_UPD: 1234 case ARM::VLD3LNq32Pseudo_UPD: 1235 case ARM::VLD4LNd8Pseudo: 1236 case ARM::VLD4LNd16Pseudo: 1237 case ARM::VLD4LNd32Pseudo: 1238 case ARM::VLD4LNq16Pseudo: 1239 case ARM::VLD4LNq32Pseudo: 1240 case ARM::VLD4LNd8Pseudo_UPD: 1241 case ARM::VLD4LNd16Pseudo_UPD: 1242 case ARM::VLD4LNd32Pseudo_UPD: 1243 case ARM::VLD4LNq16Pseudo_UPD: 1244 case ARM::VLD4LNq32Pseudo_UPD: 1245 case ARM::VST1LNq8Pseudo: 1246 case ARM::VST1LNq16Pseudo: 1247 case ARM::VST1LNq32Pseudo: 1248 case ARM::VST1LNq8Pseudo_UPD: 1249 case ARM::VST1LNq16Pseudo_UPD: 1250 case ARM::VST1LNq32Pseudo_UPD: 1251 case ARM::VST2LNd8Pseudo: 1252 case ARM::VST2LNd16Pseudo: 1253 case ARM::VST2LNd32Pseudo: 1254 case ARM::VST2LNq16Pseudo: 1255 case ARM::VST2LNq32Pseudo: 1256 case ARM::VST2LNd8Pseudo_UPD: 1257 case ARM::VST2LNd16Pseudo_UPD: 1258 case ARM::VST2LNd32Pseudo_UPD: 1259 case ARM::VST2LNq16Pseudo_UPD: 1260 case ARM::VST2LNq32Pseudo_UPD: 1261 case ARM::VST3LNd8Pseudo: 1262 case ARM::VST3LNd16Pseudo: 1263 case ARM::VST3LNd32Pseudo: 1264 case ARM::VST3LNq16Pseudo: 1265 case ARM::VST3LNq32Pseudo: 1266 case ARM::VST3LNd8Pseudo_UPD: 1267 case ARM::VST3LNd16Pseudo_UPD: 1268 case ARM::VST3LNd32Pseudo_UPD: 1269 case ARM::VST3LNq16Pseudo_UPD: 1270 case ARM::VST3LNq32Pseudo_UPD: 1271 case ARM::VST4LNd8Pseudo: 1272 case ARM::VST4LNd16Pseudo: 1273 case ARM::VST4LNd32Pseudo: 1274 case ARM::VST4LNq16Pseudo: 1275 case ARM::VST4LNq32Pseudo: 1276 case ARM::VST4LNd8Pseudo_UPD: 1277 case ARM::VST4LNd16Pseudo_UPD: 1278 case ARM::VST4LNd32Pseudo_UPD: 1279 case ARM::VST4LNq16Pseudo_UPD: 1280 case ARM::VST4LNq32Pseudo_UPD: 1281 ExpandLaneOp(MBBI); 1282 return true; 1283 1284 case ARM::VTBL2Pseudo: ExpandVTBL(MBBI, ARM::VTBL2, false, 2); return true; 1285 case ARM::VTBL3Pseudo: ExpandVTBL(MBBI, ARM::VTBL3, false, 3); return true; 1286 case ARM::VTBL4Pseudo: ExpandVTBL(MBBI, ARM::VTBL4, false, 4); return true; 1287 case ARM::VTBX2Pseudo: ExpandVTBL(MBBI, ARM::VTBX2, true, 2); return true; 1288 case ARM::VTBX3Pseudo: ExpandVTBL(MBBI, ARM::VTBX3, true, 3); return true; 1289 case ARM::VTBX4Pseudo: ExpandVTBL(MBBI, ARM::VTBX4, true, 4); return true; 1290 } 1291 1292 return false; 1293 } 1294 1295 bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { 1296 bool Modified = false; 1297 1298 MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end(); 1299 while (MBBI != E) { 1300 MachineBasicBlock::iterator NMBBI = llvm::next(MBBI); 1301 Modified |= ExpandMI(MBB, MBBI); 1302 MBBI = NMBBI; 1303 } 1304 1305 return Modified; 1306 } 1307 1308 bool ARMExpandPseudo::runOnMachineFunction(MachineFunction &MF) { 1309 const TargetMachine &TM = MF.getTarget(); 1310 TII = static_cast<const ARMBaseInstrInfo*>(TM.getInstrInfo()); 1311 TRI = TM.getRegisterInfo(); 1312 STI = &TM.getSubtarget<ARMSubtarget>(); 1313 AFI = MF.getInfo<ARMFunctionInfo>(); 1314 1315 bool Modified = false; 1316 for (MachineFunction::iterator MFI = MF.begin(), E = MF.end(); MFI != E; 1317 ++MFI) 1318 Modified |= ExpandMBB(*MFI); 1319 return Modified; 1320 } 1321 1322 /// createARMExpandPseudoPass - returns an instance of the pseudo instruction 1323 /// expansion pass. 1324 FunctionPass *llvm::createARMExpandPseudoPass() { 1325 return new ARMExpandPseudo(); 1326 } 1327
