1 //===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that Mips uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "mips-lower" 16 #include "MipsISelLowering.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "MipsTargetObjectFile.h" 20 #include "MipsSubtarget.h" 21 #include "llvm/DerivedTypes.h" 22 #include "llvm/Function.h" 23 #include "llvm/GlobalVariable.h" 24 #include "llvm/Intrinsics.h" 25 #include "llvm/CallingConv.h" 26 #include "InstPrinter/MipsInstPrinter.h" 27 #include "llvm/CodeGen/CallingConvLower.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineFunction.h" 30 #include "llvm/CodeGen/MachineInstrBuilder.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/SelectionDAGISel.h" 33 #include "llvm/CodeGen/ValueTypes.h" 34 #include "llvm/Support/Debug.h" 35 #include "llvm/Support/ErrorHandling.h" 36 using namespace llvm; 37 38 // If I is a shifted mask, set the size (Size) and the first bit of the 39 // mask (Pos), and return true. 40 // For example, if I is 0x003ff800, (Pos, Size) = (11, 11). 41 static bool IsShiftedMask(uint64_t I, uint64_t &Pos, uint64_t &Size) { 42 if (!isUInt<32>(I) || !isShiftedMask_32(I)) 43 return false; 44 45 Size = CountPopulation_32(I); 46 Pos = CountTrailingZeros_32(I); 47 return true; 48 } 49 50 const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const { 51 switch (Opcode) { 52 case MipsISD::JmpLink: return "MipsISD::JmpLink"; 53 case MipsISD::Hi: return "MipsISD::Hi"; 54 case MipsISD::Lo: return "MipsISD::Lo"; 55 case MipsISD::GPRel: return "MipsISD::GPRel"; 56 case MipsISD::TlsGd: return "MipsISD::TlsGd"; 57 case MipsISD::TprelHi: return "MipsISD::TprelHi"; 58 case MipsISD::TprelLo: return "MipsISD::TprelLo"; 59 case MipsISD::ThreadPointer: return "MipsISD::ThreadPointer"; 60 case MipsISD::Ret: return "MipsISD::Ret"; 61 case MipsISD::FPBrcond: return "MipsISD::FPBrcond"; 62 case MipsISD::FPCmp: return "MipsISD::FPCmp"; 63 case MipsISD::CMovFP_T: return "MipsISD::CMovFP_T"; 64 case MipsISD::CMovFP_F: return "MipsISD::CMovFP_F"; 65 case MipsISD::FPRound: return "MipsISD::FPRound"; 66 case MipsISD::MAdd: return "MipsISD::MAdd"; 67 case MipsISD::MAddu: return "MipsISD::MAddu"; 68 case MipsISD::MSub: return "MipsISD::MSub"; 69 case MipsISD::MSubu: return "MipsISD::MSubu"; 70 case MipsISD::DivRem: return "MipsISD::DivRem"; 71 case MipsISD::DivRemU: return "MipsISD::DivRemU"; 72 case MipsISD::BuildPairF64: return "MipsISD::BuildPairF64"; 73 case MipsISD::ExtractElementF64: return "MipsISD::ExtractElementF64"; 74 case MipsISD::WrapperPIC: return "MipsISD::WrapperPIC"; 75 case MipsISD::DynAlloc: return "MipsISD::DynAlloc"; 76 case MipsISD::Sync: return "MipsISD::Sync"; 77 case MipsISD::Ext: return "MipsISD::Ext"; 78 case MipsISD::Ins: return "MipsISD::Ins"; 79 default: return NULL; 80 } 81 } 82 83 MipsTargetLowering:: 84 MipsTargetLowering(MipsTargetMachine &TM) 85 : TargetLowering(TM, new MipsTargetObjectFile()), 86 Subtarget(&TM.getSubtarget<MipsSubtarget>()), 87 HasMips64(Subtarget->hasMips64()), IsN64(Subtarget->isABI_N64()) { 88 89 // Mips does not have i1 type, so use i32 for 90 // setcc operations results (slt, sgt, ...). 91 setBooleanContents(ZeroOrOneBooleanContent); 92 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? 93 94 // Set up the register classes 95 addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass); 96 addRegisterClass(MVT::f32, Mips::FGR32RegisterClass); 97 98 if (HasMips64) 99 addRegisterClass(MVT::i64, Mips::CPU64RegsRegisterClass); 100 101 // When dealing with single precision only, use libcalls 102 if (!Subtarget->isSingleFloat()) { 103 if (HasMips64) 104 addRegisterClass(MVT::f64, Mips::FGR64RegisterClass); 105 else 106 addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass); 107 } 108 109 // Load extented operations for i1 types must be promoted 110 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); 111 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); 112 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 113 114 // MIPS doesn't have extending float->double load/store 115 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand); 116 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 117 118 // Used by legalize types to correctly generate the setcc result. 119 // Without this, every float setcc comes with a AND/OR with the result, 120 // we don't want this, since the fpcmp result goes to a flag register, 121 // which is used implicitly by brcond and select operations. 122 AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32); 123 124 // Mips Custom Operations 125 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom); 126 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); 127 setOperationAction(ISD::BlockAddress, MVT::i32, Custom); 128 setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom); 129 setOperationAction(ISD::JumpTable, MVT::i32, Custom); 130 setOperationAction(ISD::ConstantPool, MVT::i32, Custom); 131 setOperationAction(ISD::SELECT, MVT::f32, Custom); 132 setOperationAction(ISD::SELECT, MVT::f64, Custom); 133 setOperationAction(ISD::SELECT, MVT::i32, Custom); 134 setOperationAction(ISD::BRCOND, MVT::Other, Custom); 135 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom); 136 setOperationAction(ISD::VASTART, MVT::Other, Custom); 137 138 setOperationAction(ISD::SDIV, MVT::i32, Expand); 139 setOperationAction(ISD::SREM, MVT::i32, Expand); 140 setOperationAction(ISD::UDIV, MVT::i32, Expand); 141 setOperationAction(ISD::UREM, MVT::i32, Expand); 142 setOperationAction(ISD::SDIV, MVT::i64, Expand); 143 setOperationAction(ISD::SREM, MVT::i64, Expand); 144 setOperationAction(ISD::UDIV, MVT::i64, Expand); 145 setOperationAction(ISD::UREM, MVT::i64, Expand); 146 147 // Operations not directly supported by Mips. 148 setOperationAction(ISD::BR_JT, MVT::Other, Expand); 149 setOperationAction(ISD::BR_CC, MVT::Other, Expand); 150 setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); 151 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); 152 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); 153 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); 154 setOperationAction(ISD::CTPOP, MVT::i32, Expand); 155 setOperationAction(ISD::CTTZ, MVT::i32, Expand); 156 setOperationAction(ISD::ROTL, MVT::i32, Expand); 157 setOperationAction(ISD::ROTL, MVT::i64, Expand); 158 159 if (!Subtarget->hasMips32r2()) 160 setOperationAction(ISD::ROTR, MVT::i32, Expand); 161 162 if (!Subtarget->hasMips64r2()) 163 setOperationAction(ISD::ROTR, MVT::i64, Expand); 164 165 setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand); 166 setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand); 167 setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand); 168 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 169 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 170 setOperationAction(ISD::FSIN, MVT::f32, Expand); 171 setOperationAction(ISD::FSIN, MVT::f64, Expand); 172 setOperationAction(ISD::FCOS, MVT::f32, Expand); 173 setOperationAction(ISD::FCOS, MVT::f64, Expand); 174 setOperationAction(ISD::FPOWI, MVT::f32, Expand); 175 setOperationAction(ISD::FPOW, MVT::f32, Expand); 176 setOperationAction(ISD::FPOW, MVT::f64, Expand); 177 setOperationAction(ISD::FLOG, MVT::f32, Expand); 178 setOperationAction(ISD::FLOG2, MVT::f32, Expand); 179 setOperationAction(ISD::FLOG10, MVT::f32, Expand); 180 setOperationAction(ISD::FEXP, MVT::f32, Expand); 181 setOperationAction(ISD::FMA, MVT::f32, Expand); 182 setOperationAction(ISD::FMA, MVT::f64, Expand); 183 184 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 185 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 186 187 setOperationAction(ISD::VAARG, MVT::Other, Expand); 188 setOperationAction(ISD::VACOPY, MVT::Other, Expand); 189 setOperationAction(ISD::VAEND, MVT::Other, Expand); 190 191 // Use the default for now 192 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 193 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 194 195 setOperationAction(ISD::MEMBARRIER, MVT::Other, Custom); 196 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 197 198 setOperationAction(ISD::ATOMIC_LOAD, MVT::i32, Expand); 199 setOperationAction(ISD::ATOMIC_STORE, MVT::i32, Expand); 200 201 setInsertFencesForAtomic(true); 202 203 if (Subtarget->isSingleFloat()) 204 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand); 205 206 if (!Subtarget->hasSEInReg()) { 207 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); 208 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); 209 } 210 211 if (!Subtarget->hasBitCount()) 212 setOperationAction(ISD::CTLZ, MVT::i32, Expand); 213 214 if (!Subtarget->hasSwap()) 215 setOperationAction(ISD::BSWAP, MVT::i32, Expand); 216 217 setTargetDAGCombine(ISD::ADDE); 218 setTargetDAGCombine(ISD::SUBE); 219 setTargetDAGCombine(ISD::SDIVREM); 220 setTargetDAGCombine(ISD::UDIVREM); 221 setTargetDAGCombine(ISD::SETCC); 222 setTargetDAGCombine(ISD::AND); 223 setTargetDAGCombine(ISD::OR); 224 225 setMinFunctionAlignment(2); 226 227 setStackPointerRegisterToSaveRestore(Mips::SP); 228 computeRegisterProperties(); 229 230 setExceptionPointerRegister(Mips::A0); 231 setExceptionSelectorRegister(Mips::A1); 232 } 233 234 bool MipsTargetLowering::allowsUnalignedMemoryAccesses(EVT VT) const { 235 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 236 return SVT == MVT::i64 || SVT == MVT::i32 || SVT == MVT::i16; 237 } 238 239 EVT MipsTargetLowering::getSetCCResultType(EVT VT) const { 240 return MVT::i32; 241 } 242 243 // SelectMadd - 244 // Transforms a subgraph in CurDAG if the following pattern is found: 245 // (addc multLo, Lo0), (adde multHi, Hi0), 246 // where, 247 // multHi/Lo: product of multiplication 248 // Lo0: initial value of Lo register 249 // Hi0: initial value of Hi register 250 // Return true if pattern matching was successful. 251 static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { 252 // ADDENode's second operand must be a flag output of an ADDC node in order 253 // for the matching to be successful. 254 SDNode* ADDCNode = ADDENode->getOperand(2).getNode(); 255 256 if (ADDCNode->getOpcode() != ISD::ADDC) 257 return false; 258 259 SDValue MultHi = ADDENode->getOperand(0); 260 SDValue MultLo = ADDCNode->getOperand(0); 261 SDNode* MultNode = MultHi.getNode(); 262 unsigned MultOpc = MultHi.getOpcode(); 263 264 // MultHi and MultLo must be generated by the same node, 265 if (MultLo.getNode() != MultNode) 266 return false; 267 268 // and it must be a multiplication. 269 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 270 return false; 271 272 // MultLo amd MultHi must be the first and second output of MultNode 273 // respectively. 274 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 275 return false; 276 277 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 278 // of the values of MultNode, in which case MultNode will be removed in later 279 // phases. 280 // If there exist users other than ADDENode or ADDCNode, this function returns 281 // here, which will result in MultNode being mapped to a single MULT 282 // instruction node rather than a pair of MULT and MADD instructions being 283 // produced. 284 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 285 return false; 286 287 SDValue Chain = CurDAG->getEntryNode(); 288 DebugLoc dl = ADDENode->getDebugLoc(); 289 290 // create MipsMAdd(u) node 291 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 292 293 SDValue MAdd = CurDAG->getNode(MultOpc, dl, 294 MVT::Glue, 295 MultNode->getOperand(0),// Factor 0 296 MultNode->getOperand(1),// Factor 1 297 ADDCNode->getOperand(1),// Lo0 298 ADDENode->getOperand(1));// Hi0 299 300 // create CopyFromReg nodes 301 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 302 MAdd); 303 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 304 Mips::HI, MVT::i32, 305 CopyFromLo.getValue(2)); 306 307 // replace uses of adde and addc here 308 if (!SDValue(ADDCNode, 0).use_empty()) 309 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo); 310 311 if (!SDValue(ADDENode, 0).use_empty()) 312 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi); 313 314 return true; 315 } 316 317 // SelectMsub - 318 // Transforms a subgraph in CurDAG if the following pattern is found: 319 // (addc Lo0, multLo), (sube Hi0, multHi), 320 // where, 321 // multHi/Lo: product of multiplication 322 // Lo0: initial value of Lo register 323 // Hi0: initial value of Hi register 324 // Return true if pattern matching was successful. 325 static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { 326 // SUBENode's second operand must be a flag output of an SUBC node in order 327 // for the matching to be successful. 328 SDNode* SUBCNode = SUBENode->getOperand(2).getNode(); 329 330 if (SUBCNode->getOpcode() != ISD::SUBC) 331 return false; 332 333 SDValue MultHi = SUBENode->getOperand(1); 334 SDValue MultLo = SUBCNode->getOperand(1); 335 SDNode* MultNode = MultHi.getNode(); 336 unsigned MultOpc = MultHi.getOpcode(); 337 338 // MultHi and MultLo must be generated by the same node, 339 if (MultLo.getNode() != MultNode) 340 return false; 341 342 // and it must be a multiplication. 343 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 344 return false; 345 346 // MultLo amd MultHi must be the first and second output of MultNode 347 // respectively. 348 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 349 return false; 350 351 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 352 // of the values of MultNode, in which case MultNode will be removed in later 353 // phases. 354 // If there exist users other than SUBENode or SUBCNode, this function returns 355 // here, which will result in MultNode being mapped to a single MULT 356 // instruction node rather than a pair of MULT and MSUB instructions being 357 // produced. 358 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 359 return false; 360 361 SDValue Chain = CurDAG->getEntryNode(); 362 DebugLoc dl = SUBENode->getDebugLoc(); 363 364 // create MipsSub(u) node 365 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 366 367 SDValue MSub = CurDAG->getNode(MultOpc, dl, 368 MVT::Glue, 369 MultNode->getOperand(0),// Factor 0 370 MultNode->getOperand(1),// Factor 1 371 SUBCNode->getOperand(0),// Lo0 372 SUBENode->getOperand(0));// Hi0 373 374 // create CopyFromReg nodes 375 SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32, 376 MSub); 377 SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl, 378 Mips::HI, MVT::i32, 379 CopyFromLo.getValue(2)); 380 381 // replace uses of sube and subc here 382 if (!SDValue(SUBCNode, 0).use_empty()) 383 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo); 384 385 if (!SDValue(SUBENode, 0).use_empty()) 386 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi); 387 388 return true; 389 } 390 391 static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG, 392 TargetLowering::DAGCombinerInfo &DCI, 393 const MipsSubtarget* Subtarget) { 394 if (DCI.isBeforeLegalize()) 395 return SDValue(); 396 397 if (Subtarget->hasMips32() && SelectMadd(N, &DAG)) 398 return SDValue(N, 0); 399 400 return SDValue(); 401 } 402 403 static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG, 404 TargetLowering::DAGCombinerInfo &DCI, 405 const MipsSubtarget* Subtarget) { 406 if (DCI.isBeforeLegalize()) 407 return SDValue(); 408 409 if (Subtarget->hasMips32() && SelectMsub(N, &DAG)) 410 return SDValue(N, 0); 411 412 return SDValue(); 413 } 414 415 static SDValue PerformDivRemCombine(SDNode *N, SelectionDAG& DAG, 416 TargetLowering::DAGCombinerInfo &DCI, 417 const MipsSubtarget* Subtarget) { 418 if (DCI.isBeforeLegalizeOps()) 419 return SDValue(); 420 421 EVT Ty = N->getValueType(0); 422 unsigned LO = (Ty == MVT::i32) ? Mips::LO : Mips::LO64; 423 unsigned HI = (Ty == MVT::i32) ? Mips::HI : Mips::HI64; 424 unsigned opc = N->getOpcode() == ISD::SDIVREM ? MipsISD::DivRem : 425 MipsISD::DivRemU; 426 DebugLoc dl = N->getDebugLoc(); 427 428 SDValue DivRem = DAG.getNode(opc, dl, MVT::Glue, 429 N->getOperand(0), N->getOperand(1)); 430 SDValue InChain = DAG.getEntryNode(); 431 SDValue InGlue = DivRem; 432 433 // insert MFLO 434 if (N->hasAnyUseOfValue(0)) { 435 SDValue CopyFromLo = DAG.getCopyFromReg(InChain, dl, LO, Ty, 436 InGlue); 437 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), CopyFromLo); 438 InChain = CopyFromLo.getValue(1); 439 InGlue = CopyFromLo.getValue(2); 440 } 441 442 // insert MFHI 443 if (N->hasAnyUseOfValue(1)) { 444 SDValue CopyFromHi = DAG.getCopyFromReg(InChain, dl, 445 HI, Ty, InGlue); 446 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 1), CopyFromHi); 447 } 448 449 return SDValue(); 450 } 451 452 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { 453 switch (CC) { 454 default: llvm_unreachable("Unknown fp condition code!"); 455 case ISD::SETEQ: 456 case ISD::SETOEQ: return Mips::FCOND_OEQ; 457 case ISD::SETUNE: return Mips::FCOND_UNE; 458 case ISD::SETLT: 459 case ISD::SETOLT: return Mips::FCOND_OLT; 460 case ISD::SETGT: 461 case ISD::SETOGT: return Mips::FCOND_OGT; 462 case ISD::SETLE: 463 case ISD::SETOLE: return Mips::FCOND_OLE; 464 case ISD::SETGE: 465 case ISD::SETOGE: return Mips::FCOND_OGE; 466 case ISD::SETULT: return Mips::FCOND_ULT; 467 case ISD::SETULE: return Mips::FCOND_ULE; 468 case ISD::SETUGT: return Mips::FCOND_UGT; 469 case ISD::SETUGE: return Mips::FCOND_UGE; 470 case ISD::SETUO: return Mips::FCOND_UN; 471 case ISD::SETO: return Mips::FCOND_OR; 472 case ISD::SETNE: 473 case ISD::SETONE: return Mips::FCOND_ONE; 474 case ISD::SETUEQ: return Mips::FCOND_UEQ; 475 } 476 } 477 478 479 // Returns true if condition code has to be inverted. 480 static bool InvertFPCondCode(Mips::CondCode CC) { 481 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 482 return false; 483 484 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 485 return true; 486 487 assert(false && "Illegal Condition Code"); 488 return false; 489 } 490 491 // Creates and returns an FPCmp node from a setcc node. 492 // Returns Op if setcc is not a floating point comparison. 493 static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { 494 // must be a SETCC node 495 if (Op.getOpcode() != ISD::SETCC) 496 return Op; 497 498 SDValue LHS = Op.getOperand(0); 499 500 if (!LHS.getValueType().isFloatingPoint()) 501 return Op; 502 503 SDValue RHS = Op.getOperand(1); 504 DebugLoc dl = Op.getDebugLoc(); 505 506 // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of 507 // node if necessary. 508 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 509 510 return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, 511 DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32)); 512 } 513 514 // Creates and returns a CMovFPT/F node. 515 static SDValue CreateCMovFP(SelectionDAG& DAG, SDValue Cond, SDValue True, 516 SDValue False, DebugLoc DL) { 517 bool invert = InvertFPCondCode((Mips::CondCode) 518 cast<ConstantSDNode>(Cond.getOperand(2)) 519 ->getSExtValue()); 520 521 return DAG.getNode((invert ? MipsISD::CMovFP_F : MipsISD::CMovFP_T), DL, 522 True.getValueType(), True, False, Cond); 523 } 524 525 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG& DAG, 526 TargetLowering::DAGCombinerInfo &DCI, 527 const MipsSubtarget* Subtarget) { 528 if (DCI.isBeforeLegalizeOps()) 529 return SDValue(); 530 531 SDValue Cond = CreateFPCmp(DAG, SDValue(N, 0)); 532 533 if (Cond.getOpcode() != MipsISD::FPCmp) 534 return SDValue(); 535 536 SDValue True = DAG.getConstant(1, MVT::i32); 537 SDValue False = DAG.getConstant(0, MVT::i32); 538 539 return CreateCMovFP(DAG, Cond, True, False, N->getDebugLoc()); 540 } 541 542 static SDValue PerformANDCombine(SDNode *N, SelectionDAG& DAG, 543 TargetLowering::DAGCombinerInfo &DCI, 544 const MipsSubtarget* Subtarget) { 545 // Pattern match EXT. 546 // $dst = and ((sra or srl) $src , pos), (2**size - 1) 547 // => ext $dst, $src, size, pos 548 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 549 return SDValue(); 550 551 SDValue ShiftRight = N->getOperand(0), Mask = N->getOperand(1); 552 553 // Op's first operand must be a shift right. 554 if (ShiftRight.getOpcode() != ISD::SRA && ShiftRight.getOpcode() != ISD::SRL) 555 return SDValue(); 556 557 // The second operand of the shift must be an immediate. 558 uint64_t Pos; 559 ConstantSDNode *CN; 560 if (!(CN = dyn_cast<ConstantSDNode>(ShiftRight.getOperand(1)))) 561 return SDValue(); 562 563 Pos = CN->getZExtValue(); 564 565 uint64_t SMPos, SMSize; 566 // Op's second operand must be a shifted mask. 567 if (!(CN = dyn_cast<ConstantSDNode>(Mask)) || 568 !IsShiftedMask(CN->getZExtValue(), SMPos, SMSize)) 569 return SDValue(); 570 571 // Return if the shifted mask does not start at bit 0 or the sum of its size 572 // and Pos exceeds the word's size. 573 if (SMPos != 0 || Pos + SMSize > 32) 574 return SDValue(); 575 576 return DAG.getNode(MipsISD::Ext, N->getDebugLoc(), MVT::i32, 577 ShiftRight.getOperand(0), 578 DAG.getConstant(Pos, MVT::i32), 579 DAG.getConstant(SMSize, MVT::i32)); 580 } 581 582 static SDValue PerformORCombine(SDNode *N, SelectionDAG& DAG, 583 TargetLowering::DAGCombinerInfo &DCI, 584 const MipsSubtarget* Subtarget) { 585 // Pattern match INS. 586 // $dst = or (and $src1 , mask0), (and (shl $src, pos), mask1), 587 // where mask1 = (2**size - 1) << pos, mask0 = ~mask1 588 // => ins $dst, $src, size, pos, $src1 589 if (DCI.isBeforeLegalizeOps() || !Subtarget->hasMips32r2()) 590 return SDValue(); 591 592 SDValue And0 = N->getOperand(0), And1 = N->getOperand(1); 593 uint64_t SMPos0, SMSize0, SMPos1, SMSize1; 594 ConstantSDNode *CN; 595 596 // See if Op's first operand matches (and $src1 , mask0). 597 if (And0.getOpcode() != ISD::AND) 598 return SDValue(); 599 600 if (!(CN = dyn_cast<ConstantSDNode>(And0.getOperand(1))) || 601 !IsShiftedMask(~CN->getSExtValue(), SMPos0, SMSize0)) 602 return SDValue(); 603 604 // See if Op's second operand matches (and (shl $src, pos), mask1). 605 if (And1.getOpcode() != ISD::AND) 606 return SDValue(); 607 608 if (!(CN = dyn_cast<ConstantSDNode>(And1.getOperand(1))) || 609 !IsShiftedMask(CN->getZExtValue(), SMPos1, SMSize1)) 610 return SDValue(); 611 612 // The shift masks must have the same position and size. 613 if (SMPos0 != SMPos1 || SMSize0 != SMSize1) 614 return SDValue(); 615 616 SDValue Shl = And1.getOperand(0); 617 if (Shl.getOpcode() != ISD::SHL) 618 return SDValue(); 619 620 if (!(CN = dyn_cast<ConstantSDNode>(Shl.getOperand(1)))) 621 return SDValue(); 622 623 unsigned Shamt = CN->getZExtValue(); 624 625 // Return if the shift amount and the first bit position of mask are not the 626 // same. 627 if (Shamt != SMPos0) 628 return SDValue(); 629 630 return DAG.getNode(MipsISD::Ins, N->getDebugLoc(), MVT::i32, 631 Shl.getOperand(0), 632 DAG.getConstant(SMPos0, MVT::i32), 633 DAG.getConstant(SMSize0, MVT::i32), 634 And0.getOperand(0)); 635 } 636 637 SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) 638 const { 639 SelectionDAG &DAG = DCI.DAG; 640 unsigned opc = N->getOpcode(); 641 642 switch (opc) { 643 default: break; 644 case ISD::ADDE: 645 return PerformADDECombine(N, DAG, DCI, Subtarget); 646 case ISD::SUBE: 647 return PerformSUBECombine(N, DAG, DCI, Subtarget); 648 case ISD::SDIVREM: 649 case ISD::UDIVREM: 650 return PerformDivRemCombine(N, DAG, DCI, Subtarget); 651 case ISD::SETCC: 652 return PerformSETCCCombine(N, DAG, DCI, Subtarget); 653 case ISD::AND: 654 return PerformANDCombine(N, DAG, DCI, Subtarget); 655 case ISD::OR: 656 return PerformORCombine(N, DAG, DCI, Subtarget); 657 } 658 659 return SDValue(); 660 } 661 662 SDValue MipsTargetLowering:: 663 LowerOperation(SDValue Op, SelectionDAG &DAG) const 664 { 665 switch (Op.getOpcode()) 666 { 667 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 668 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 669 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 670 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 671 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 672 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 673 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 674 case ISD::SELECT: return LowerSELECT(Op, DAG); 675 case ISD::VASTART: return LowerVASTART(Op, DAG); 676 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 677 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 678 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op, DAG); 679 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op, DAG); 680 } 681 return SDValue(); 682 } 683 684 //===----------------------------------------------------------------------===// 685 // Lower helper functions 686 //===----------------------------------------------------------------------===// 687 688 // AddLiveIn - This helper function adds the specified physical register to the 689 // MachineFunction as a live in value. It also creates a corresponding 690 // virtual register for it. 691 static unsigned 692 AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC) 693 { 694 assert(RC->contains(PReg) && "Not the correct regclass!"); 695 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); 696 MF.getRegInfo().addLiveIn(PReg, VReg); 697 return VReg; 698 } 699 700 // Get fp branch code (not opcode) from condition code. 701 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { 702 if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT) 703 return Mips::BRANCH_T; 704 705 if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT) 706 return Mips::BRANCH_F; 707 708 return Mips::BRANCH_INVALID; 709 } 710 711 /* 712 static MachineBasicBlock* ExpandCondMov(MachineInstr *MI, MachineBasicBlock *BB, 713 DebugLoc dl, 714 const MipsSubtarget* Subtarget, 715 const TargetInstrInfo *TII, 716 bool isFPCmp, unsigned Opc) { 717 // There is no need to expand CMov instructions if target has 718 // conditional moves. 719 if (Subtarget->hasCondMov()) 720 return BB; 721 722 // To "insert" a SELECT_CC instruction, we actually have to insert the 723 // diamond control-flow pattern. The incoming instruction knows the 724 // destination vreg to set, the condition code register to branch on, the 725 // true/false values to select between, and a branch opcode to use. 726 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 727 MachineFunction::iterator It = BB; 728 ++It; 729 730 // thisMBB: 731 // ... 732 // TrueVal = ... 733 // setcc r1, r2, r3 734 // bNE r1, r0, copy1MBB 735 // fallthrough --> copy0MBB 736 MachineBasicBlock *thisMBB = BB; 737 MachineFunction *F = BB->getParent(); 738 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 739 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 740 F->insert(It, copy0MBB); 741 F->insert(It, sinkMBB); 742 743 // Transfer the remainder of BB and its successor edges to sinkMBB. 744 sinkMBB->splice(sinkMBB->begin(), BB, 745 llvm::next(MachineBasicBlock::iterator(MI)), 746 BB->end()); 747 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 748 749 // Next, add the true and fallthrough blocks as its successors. 750 BB->addSuccessor(copy0MBB); 751 BB->addSuccessor(sinkMBB); 752 753 // Emit the right instruction according to the type of the operands compared 754 if (isFPCmp) 755 BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB); 756 else 757 BuildMI(BB, dl, TII->get(Opc)).addReg(MI->getOperand(2).getReg()) 758 .addReg(Mips::ZERO).addMBB(sinkMBB); 759 760 // copy0MBB: 761 // %FalseValue = ... 762 // # fallthrough to sinkMBB 763 BB = copy0MBB; 764 765 // Update machine-CFG edges 766 BB->addSuccessor(sinkMBB); 767 768 // sinkMBB: 769 // %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ] 770 // ... 771 BB = sinkMBB; 772 773 if (isFPCmp) 774 BuildMI(*BB, BB->begin(), dl, 775 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 776 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB) 777 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 778 else 779 BuildMI(*BB, BB->begin(), dl, 780 TII->get(Mips::PHI), MI->getOperand(0).getReg()) 781 .addReg(MI->getOperand(3).getReg()).addMBB(thisMBB) 782 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB); 783 784 MI->eraseFromParent(); // The pseudo instruction is gone now. 785 return BB; 786 } 787 */ 788 MachineBasicBlock * 789 MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 790 MachineBasicBlock *BB) const { 791 switch (MI->getOpcode()) { 792 default: 793 assert(false && "Unexpected instr type to insert"); 794 return NULL; 795 case Mips::ATOMIC_LOAD_ADD_I8: 796 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::ADDu); 797 case Mips::ATOMIC_LOAD_ADD_I16: 798 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::ADDu); 799 case Mips::ATOMIC_LOAD_ADD_I32: 800 return EmitAtomicBinary(MI, BB, 4, Mips::ADDu); 801 802 case Mips::ATOMIC_LOAD_AND_I8: 803 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::AND); 804 case Mips::ATOMIC_LOAD_AND_I16: 805 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::AND); 806 case Mips::ATOMIC_LOAD_AND_I32: 807 return EmitAtomicBinary(MI, BB, 4, Mips::AND); 808 809 case Mips::ATOMIC_LOAD_OR_I8: 810 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::OR); 811 case Mips::ATOMIC_LOAD_OR_I16: 812 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::OR); 813 case Mips::ATOMIC_LOAD_OR_I32: 814 return EmitAtomicBinary(MI, BB, 4, Mips::OR); 815 816 case Mips::ATOMIC_LOAD_XOR_I8: 817 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::XOR); 818 case Mips::ATOMIC_LOAD_XOR_I16: 819 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::XOR); 820 case Mips::ATOMIC_LOAD_XOR_I32: 821 return EmitAtomicBinary(MI, BB, 4, Mips::XOR); 822 823 case Mips::ATOMIC_LOAD_NAND_I8: 824 return EmitAtomicBinaryPartword(MI, BB, 1, 0, true); 825 case Mips::ATOMIC_LOAD_NAND_I16: 826 return EmitAtomicBinaryPartword(MI, BB, 2, 0, true); 827 case Mips::ATOMIC_LOAD_NAND_I32: 828 return EmitAtomicBinary(MI, BB, 4, 0, true); 829 830 case Mips::ATOMIC_LOAD_SUB_I8: 831 return EmitAtomicBinaryPartword(MI, BB, 1, Mips::SUBu); 832 case Mips::ATOMIC_LOAD_SUB_I16: 833 return EmitAtomicBinaryPartword(MI, BB, 2, Mips::SUBu); 834 case Mips::ATOMIC_LOAD_SUB_I32: 835 return EmitAtomicBinary(MI, BB, 4, Mips::SUBu); 836 837 case Mips::ATOMIC_SWAP_I8: 838 return EmitAtomicBinaryPartword(MI, BB, 1, 0); 839 case Mips::ATOMIC_SWAP_I16: 840 return EmitAtomicBinaryPartword(MI, BB, 2, 0); 841 case Mips::ATOMIC_SWAP_I32: 842 return EmitAtomicBinary(MI, BB, 4, 0); 843 844 case Mips::ATOMIC_CMP_SWAP_I8: 845 return EmitAtomicCmpSwapPartword(MI, BB, 1); 846 case Mips::ATOMIC_CMP_SWAP_I16: 847 return EmitAtomicCmpSwapPartword(MI, BB, 2); 848 case Mips::ATOMIC_CMP_SWAP_I32: 849 return EmitAtomicCmpSwap(MI, BB, 4); 850 } 851 } 852 853 // This function also handles Mips::ATOMIC_SWAP_I32 (when BinOpcode == 0), and 854 // Mips::ATOMIC_LOAD_NAND_I32 (when Nand == true) 855 MachineBasicBlock * 856 MipsTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB, 857 unsigned Size, unsigned BinOpcode, 858 bool Nand) const { 859 assert(Size == 4 && "Unsupported size for EmitAtomicBinary."); 860 861 MachineFunction *MF = BB->getParent(); 862 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 863 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 864 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 865 DebugLoc dl = MI->getDebugLoc(); 866 867 unsigned OldVal = MI->getOperand(0).getReg(); 868 unsigned Ptr = MI->getOperand(1).getReg(); 869 unsigned Incr = MI->getOperand(2).getReg(); 870 871 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 872 unsigned AndRes = RegInfo.createVirtualRegister(RC); 873 unsigned Success = RegInfo.createVirtualRegister(RC); 874 875 // insert new blocks after the current block 876 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 877 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 878 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 879 MachineFunction::iterator It = BB; 880 ++It; 881 MF->insert(It, loopMBB); 882 MF->insert(It, exitMBB); 883 884 // Transfer the remainder of BB and its successor edges to exitMBB. 885 exitMBB->splice(exitMBB->begin(), BB, 886 llvm::next(MachineBasicBlock::iterator(MI)), 887 BB->end()); 888 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 889 890 // thisMBB: 891 // ... 892 // fallthrough --> loopMBB 893 BB->addSuccessor(loopMBB); 894 loopMBB->addSuccessor(loopMBB); 895 loopMBB->addSuccessor(exitMBB); 896 897 // loopMBB: 898 // ll oldval, 0(ptr) 899 // <binop> storeval, oldval, incr 900 // sc success, storeval, 0(ptr) 901 // beq success, $0, loopMBB 902 BB = loopMBB; 903 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(Ptr).addImm(0); 904 if (Nand) { 905 // and andres, oldval, incr 906 // nor storeval, $0, andres 907 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr); 908 BuildMI(BB, dl, TII->get(Mips::NOR), StoreVal) 909 .addReg(Mips::ZERO).addReg(AndRes); 910 } else if (BinOpcode) { 911 // <binop> storeval, oldval, incr 912 BuildMI(BB, dl, TII->get(BinOpcode), StoreVal).addReg(OldVal).addReg(Incr); 913 } else { 914 StoreVal = Incr; 915 } 916 BuildMI(BB, dl, TII->get(Mips::SC), Success) 917 .addReg(StoreVal).addReg(Ptr).addImm(0); 918 BuildMI(BB, dl, TII->get(Mips::BEQ)) 919 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 920 921 MI->eraseFromParent(); // The instruction is gone now. 922 923 return exitMBB; 924 } 925 926 MachineBasicBlock * 927 MipsTargetLowering::EmitAtomicBinaryPartword(MachineInstr *MI, 928 MachineBasicBlock *BB, 929 unsigned Size, unsigned BinOpcode, 930 bool Nand) const { 931 assert((Size == 1 || Size == 2) && 932 "Unsupported size for EmitAtomicBinaryPartial."); 933 934 MachineFunction *MF = BB->getParent(); 935 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 936 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 937 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 938 DebugLoc dl = MI->getDebugLoc(); 939 940 unsigned Dest = MI->getOperand(0).getReg(); 941 unsigned Ptr = MI->getOperand(1).getReg(); 942 unsigned Incr = MI->getOperand(2).getReg(); 943 944 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 945 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 946 unsigned Mask = RegInfo.createVirtualRegister(RC); 947 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 948 unsigned NewVal = RegInfo.createVirtualRegister(RC); 949 unsigned OldVal = RegInfo.createVirtualRegister(RC); 950 unsigned Incr2 = RegInfo.createVirtualRegister(RC); 951 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 952 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 953 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 954 unsigned AndRes = RegInfo.createVirtualRegister(RC); 955 unsigned BinOpRes = RegInfo.createVirtualRegister(RC); 956 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 957 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 958 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 959 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 960 unsigned SllRes = RegInfo.createVirtualRegister(RC); 961 unsigned Success = RegInfo.createVirtualRegister(RC); 962 963 // insert new blocks after the current block 964 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 965 MachineBasicBlock *loopMBB = MF->CreateMachineBasicBlock(LLVM_BB); 966 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 967 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 968 MachineFunction::iterator It = BB; 969 ++It; 970 MF->insert(It, loopMBB); 971 MF->insert(It, sinkMBB); 972 MF->insert(It, exitMBB); 973 974 // Transfer the remainder of BB and its successor edges to exitMBB. 975 exitMBB->splice(exitMBB->begin(), BB, 976 llvm::next(MachineBasicBlock::iterator(MI)), 977 BB->end()); 978 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 979 980 BB->addSuccessor(loopMBB); 981 loopMBB->addSuccessor(loopMBB); 982 loopMBB->addSuccessor(sinkMBB); 983 sinkMBB->addSuccessor(exitMBB); 984 985 // thisMBB: 986 // addiu masklsb2,$0,-4 # 0xfffffffc 987 // and alignedaddr,ptr,masklsb2 988 // andi ptrlsb2,ptr,3 989 // sll shiftamt,ptrlsb2,3 990 // ori maskupper,$0,255 # 0xff 991 // sll mask,maskupper,shiftamt 992 // nor mask2,$0,mask 993 // sll incr2,incr,shiftamt 994 995 int64_t MaskImm = (Size == 1) ? 255 : 65535; 996 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 997 .addReg(Mips::ZERO).addImm(-4); 998 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 999 .addReg(Ptr).addReg(MaskLSB2); 1000 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1001 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1002 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1003 .addReg(Mips::ZERO).addImm(MaskImm); 1004 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1005 .addReg(ShiftAmt).addReg(MaskUpper); 1006 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1007 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); 1008 1009 1010 // atomic.load.binop 1011 // loopMBB: 1012 // ll oldval,0(alignedaddr) 1013 // binop binopres,oldval,incr2 1014 // and newval,binopres,mask 1015 // and maskedoldval0,oldval,mask2 1016 // or storeval,maskedoldval0,newval 1017 // sc success,storeval,0(alignedaddr) 1018 // beq success,$0,loopMBB 1019 1020 // atomic.swap 1021 // loopMBB: 1022 // ll oldval,0(alignedaddr) 1023 // and newval,incr2,mask 1024 // and maskedoldval0,oldval,mask2 1025 // or storeval,maskedoldval0,newval 1026 // sc success,storeval,0(alignedaddr) 1027 // beq success,$0,loopMBB 1028 1029 BB = loopMBB; 1030 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1031 if (Nand) { 1032 // and andres, oldval, incr2 1033 // nor binopres, $0, andres 1034 // and newval, binopres, mask 1035 BuildMI(BB, dl, TII->get(Mips::AND), AndRes).addReg(OldVal).addReg(Incr2); 1036 BuildMI(BB, dl, TII->get(Mips::NOR), BinOpRes) 1037 .addReg(Mips::ZERO).addReg(AndRes); 1038 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1039 } else if (BinOpcode) { 1040 // <binop> binopres, oldval, incr2 1041 // and newval, binopres, mask 1042 BuildMI(BB, dl, TII->get(BinOpcode), BinOpRes).addReg(OldVal).addReg(Incr2); 1043 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(BinOpRes).addReg(Mask); 1044 } else {// atomic.swap 1045 // and newval, incr2, mask 1046 BuildMI(BB, dl, TII->get(Mips::AND), NewVal).addReg(Incr2).addReg(Mask); 1047 } 1048 1049 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1050 .addReg(OldVal).addReg(Mask2); 1051 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1052 .addReg(MaskedOldVal0).addReg(NewVal); 1053 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1054 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1055 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1056 .addReg(Success).addReg(Mips::ZERO).addMBB(loopMBB); 1057 1058 // sinkMBB: 1059 // and maskedoldval1,oldval,mask 1060 // srl srlres,maskedoldval1,shiftamt 1061 // sll sllres,srlres,24 1062 // sra dest,sllres,24 1063 BB = sinkMBB; 1064 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1065 1066 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1067 .addReg(OldVal).addReg(Mask); 1068 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1069 .addReg(ShiftAmt).addReg(MaskedOldVal1); 1070 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1071 .addReg(SrlRes).addImm(ShiftImm); 1072 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1073 .addReg(SllRes).addImm(ShiftImm); 1074 1075 MI->eraseFromParent(); // The instruction is gone now. 1076 1077 return exitMBB; 1078 } 1079 1080 MachineBasicBlock * 1081 MipsTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI, 1082 MachineBasicBlock *BB, 1083 unsigned Size) const { 1084 assert(Size == 4 && "Unsupported size for EmitAtomicCmpSwap."); 1085 1086 MachineFunction *MF = BB->getParent(); 1087 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1088 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1089 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1090 DebugLoc dl = MI->getDebugLoc(); 1091 1092 unsigned Dest = MI->getOperand(0).getReg(); 1093 unsigned Ptr = MI->getOperand(1).getReg(); 1094 unsigned OldVal = MI->getOperand(2).getReg(); 1095 unsigned NewVal = MI->getOperand(3).getReg(); 1096 1097 unsigned Success = RegInfo.createVirtualRegister(RC); 1098 1099 // insert new blocks after the current block 1100 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1101 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1102 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1103 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1104 MachineFunction::iterator It = BB; 1105 ++It; 1106 MF->insert(It, loop1MBB); 1107 MF->insert(It, loop2MBB); 1108 MF->insert(It, exitMBB); 1109 1110 // Transfer the remainder of BB and its successor edges to exitMBB. 1111 exitMBB->splice(exitMBB->begin(), BB, 1112 llvm::next(MachineBasicBlock::iterator(MI)), 1113 BB->end()); 1114 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1115 1116 // thisMBB: 1117 // ... 1118 // fallthrough --> loop1MBB 1119 BB->addSuccessor(loop1MBB); 1120 loop1MBB->addSuccessor(exitMBB); 1121 loop1MBB->addSuccessor(loop2MBB); 1122 loop2MBB->addSuccessor(loop1MBB); 1123 loop2MBB->addSuccessor(exitMBB); 1124 1125 // loop1MBB: 1126 // ll dest, 0(ptr) 1127 // bne dest, oldval, exitMBB 1128 BB = loop1MBB; 1129 BuildMI(BB, dl, TII->get(Mips::LL), Dest).addReg(Ptr).addImm(0); 1130 BuildMI(BB, dl, TII->get(Mips::BNE)) 1131 .addReg(Dest).addReg(OldVal).addMBB(exitMBB); 1132 1133 // loop2MBB: 1134 // sc success, newval, 0(ptr) 1135 // beq success, $0, loop1MBB 1136 BB = loop2MBB; 1137 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1138 .addReg(NewVal).addReg(Ptr).addImm(0); 1139 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1140 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1141 1142 MI->eraseFromParent(); // The instruction is gone now. 1143 1144 return exitMBB; 1145 } 1146 1147 MachineBasicBlock * 1148 MipsTargetLowering::EmitAtomicCmpSwapPartword(MachineInstr *MI, 1149 MachineBasicBlock *BB, 1150 unsigned Size) const { 1151 assert((Size == 1 || Size == 2) && 1152 "Unsupported size for EmitAtomicCmpSwapPartial."); 1153 1154 MachineFunction *MF = BB->getParent(); 1155 MachineRegisterInfo &RegInfo = MF->getRegInfo(); 1156 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); 1157 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 1158 DebugLoc dl = MI->getDebugLoc(); 1159 1160 unsigned Dest = MI->getOperand(0).getReg(); 1161 unsigned Ptr = MI->getOperand(1).getReg(); 1162 unsigned CmpVal = MI->getOperand(2).getReg(); 1163 unsigned NewVal = MI->getOperand(3).getReg(); 1164 1165 unsigned AlignedAddr = RegInfo.createVirtualRegister(RC); 1166 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); 1167 unsigned Mask = RegInfo.createVirtualRegister(RC); 1168 unsigned Mask2 = RegInfo.createVirtualRegister(RC); 1169 unsigned ShiftedCmpVal = RegInfo.createVirtualRegister(RC); 1170 unsigned OldVal = RegInfo.createVirtualRegister(RC); 1171 unsigned MaskedOldVal0 = RegInfo.createVirtualRegister(RC); 1172 unsigned ShiftedNewVal = RegInfo.createVirtualRegister(RC); 1173 unsigned MaskLSB2 = RegInfo.createVirtualRegister(RC); 1174 unsigned PtrLSB2 = RegInfo.createVirtualRegister(RC); 1175 unsigned MaskUpper = RegInfo.createVirtualRegister(RC); 1176 unsigned MaskedCmpVal = RegInfo.createVirtualRegister(RC); 1177 unsigned MaskedNewVal = RegInfo.createVirtualRegister(RC); 1178 unsigned MaskedOldVal1 = RegInfo.createVirtualRegister(RC); 1179 unsigned StoreVal = RegInfo.createVirtualRegister(RC); 1180 unsigned SrlRes = RegInfo.createVirtualRegister(RC); 1181 unsigned SllRes = RegInfo.createVirtualRegister(RC); 1182 unsigned Success = RegInfo.createVirtualRegister(RC); 1183 1184 // insert new blocks after the current block 1185 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 1186 MachineBasicBlock *loop1MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1187 MachineBasicBlock *loop2MBB = MF->CreateMachineBasicBlock(LLVM_BB); 1188 MachineBasicBlock *sinkMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1189 MachineBasicBlock *exitMBB = MF->CreateMachineBasicBlock(LLVM_BB); 1190 MachineFunction::iterator It = BB; 1191 ++It; 1192 MF->insert(It, loop1MBB); 1193 MF->insert(It, loop2MBB); 1194 MF->insert(It, sinkMBB); 1195 MF->insert(It, exitMBB); 1196 1197 // Transfer the remainder of BB and its successor edges to exitMBB. 1198 exitMBB->splice(exitMBB->begin(), BB, 1199 llvm::next(MachineBasicBlock::iterator(MI)), 1200 BB->end()); 1201 exitMBB->transferSuccessorsAndUpdatePHIs(BB); 1202 1203 BB->addSuccessor(loop1MBB); 1204 loop1MBB->addSuccessor(sinkMBB); 1205 loop1MBB->addSuccessor(loop2MBB); 1206 loop2MBB->addSuccessor(loop1MBB); 1207 loop2MBB->addSuccessor(sinkMBB); 1208 sinkMBB->addSuccessor(exitMBB); 1209 1210 // FIXME: computation of newval2 can be moved to loop2MBB. 1211 // thisMBB: 1212 // addiu masklsb2,$0,-4 # 0xfffffffc 1213 // and alignedaddr,ptr,masklsb2 1214 // andi ptrlsb2,ptr,3 1215 // sll shiftamt,ptrlsb2,3 1216 // ori maskupper,$0,255 # 0xff 1217 // sll mask,maskupper,shiftamt 1218 // nor mask2,$0,mask 1219 // andi maskedcmpval,cmpval,255 1220 // sll shiftedcmpval,maskedcmpval,shiftamt 1221 // andi maskednewval,newval,255 1222 // sll shiftednewval,maskednewval,shiftamt 1223 int64_t MaskImm = (Size == 1) ? 255 : 65535; 1224 BuildMI(BB, dl, TII->get(Mips::ADDiu), MaskLSB2) 1225 .addReg(Mips::ZERO).addImm(-4); 1226 BuildMI(BB, dl, TII->get(Mips::AND), AlignedAddr) 1227 .addReg(Ptr).addReg(MaskLSB2); 1228 BuildMI(BB, dl, TII->get(Mips::ANDi), PtrLSB2).addReg(Ptr).addImm(3); 1229 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); 1230 BuildMI(BB, dl, TII->get(Mips::ORi), MaskUpper) 1231 .addReg(Mips::ZERO).addImm(MaskImm); 1232 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) 1233 .addReg(ShiftAmt).addReg(MaskUpper); 1234 BuildMI(BB, dl, TII->get(Mips::NOR), Mask2).addReg(Mips::ZERO).addReg(Mask); 1235 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedCmpVal) 1236 .addReg(CmpVal).addImm(MaskImm); 1237 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) 1238 .addReg(ShiftAmt).addReg(MaskedCmpVal); 1239 BuildMI(BB, dl, TII->get(Mips::ANDi), MaskedNewVal) 1240 .addReg(NewVal).addImm(MaskImm); 1241 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) 1242 .addReg(ShiftAmt).addReg(MaskedNewVal); 1243 1244 // loop1MBB: 1245 // ll oldval,0(alginedaddr) 1246 // and maskedoldval0,oldval,mask 1247 // bne maskedoldval0,shiftedcmpval,sinkMBB 1248 BB = loop1MBB; 1249 BuildMI(BB, dl, TII->get(Mips::LL), OldVal).addReg(AlignedAddr).addImm(0); 1250 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal0) 1251 .addReg(OldVal).addReg(Mask); 1252 BuildMI(BB, dl, TII->get(Mips::BNE)) 1253 .addReg(MaskedOldVal0).addReg(ShiftedCmpVal).addMBB(sinkMBB); 1254 1255 // loop2MBB: 1256 // and maskedoldval1,oldval,mask2 1257 // or storeval,maskedoldval1,shiftednewval 1258 // sc success,storeval,0(alignedaddr) 1259 // beq success,$0,loop1MBB 1260 BB = loop2MBB; 1261 BuildMI(BB, dl, TII->get(Mips::AND), MaskedOldVal1) 1262 .addReg(OldVal).addReg(Mask2); 1263 BuildMI(BB, dl, TII->get(Mips::OR), StoreVal) 1264 .addReg(MaskedOldVal1).addReg(ShiftedNewVal); 1265 BuildMI(BB, dl, TII->get(Mips::SC), Success) 1266 .addReg(StoreVal).addReg(AlignedAddr).addImm(0); 1267 BuildMI(BB, dl, TII->get(Mips::BEQ)) 1268 .addReg(Success).addReg(Mips::ZERO).addMBB(loop1MBB); 1269 1270 // sinkMBB: 1271 // srl srlres,maskedoldval0,shiftamt 1272 // sll sllres,srlres,24 1273 // sra dest,sllres,24 1274 BB = sinkMBB; 1275 int64_t ShiftImm = (Size == 1) ? 24 : 16; 1276 1277 BuildMI(BB, dl, TII->get(Mips::SRLV), SrlRes) 1278 .addReg(ShiftAmt).addReg(MaskedOldVal0); 1279 BuildMI(BB, dl, TII->get(Mips::SLL), SllRes) 1280 .addReg(SrlRes).addImm(ShiftImm); 1281 BuildMI(BB, dl, TII->get(Mips::SRA), Dest) 1282 .addReg(SllRes).addImm(ShiftImm); 1283 1284 MI->eraseFromParent(); // The instruction is gone now. 1285 1286 return exitMBB; 1287 } 1288 1289 //===----------------------------------------------------------------------===// 1290 // Misc Lower Operation implementation 1291 //===----------------------------------------------------------------------===// 1292 SDValue MipsTargetLowering:: 1293 LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const 1294 { 1295 MachineFunction &MF = DAG.getMachineFunction(); 1296 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1297 1298 assert(getTargetMachine().getFrameLowering()->getStackAlignment() >= 1299 cast<ConstantSDNode>(Op.getOperand(2).getNode())->getZExtValue() && 1300 "Cannot lower if the alignment of the allocated space is larger than \ 1301 that of the stack."); 1302 1303 SDValue Chain = Op.getOperand(0); 1304 SDValue Size = Op.getOperand(1); 1305 DebugLoc dl = Op.getDebugLoc(); 1306 1307 // Get a reference from Mips stack pointer 1308 SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32); 1309 1310 // Subtract the dynamic size from the actual stack size to 1311 // obtain the new stack size. 1312 SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size); 1313 1314 // The Sub result contains the new stack start address, so it 1315 // must be placed in the stack pointer register. 1316 Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub, 1317 SDValue()); 1318 1319 // This node always has two return values: a new stack pointer 1320 // value and a chain 1321 SDVTList VTLs = DAG.getVTList(MVT::i32, MVT::Other); 1322 SDValue Ptr = DAG.getFrameIndex(MipsFI->getDynAllocFI(), getPointerTy()); 1323 SDValue Ops[] = { Chain, Ptr, Chain.getValue(1) }; 1324 1325 return DAG.getNode(MipsISD::DynAlloc, dl, VTLs, Ops, 3); 1326 } 1327 1328 SDValue MipsTargetLowering:: 1329 LowerBRCOND(SDValue Op, SelectionDAG &DAG) const 1330 { 1331 // The first operand is the chain, the second is the condition, the third is 1332 // the block to branch to if the condition is true. 1333 SDValue Chain = Op.getOperand(0); 1334 SDValue Dest = Op.getOperand(2); 1335 DebugLoc dl = Op.getDebugLoc(); 1336 1337 SDValue CondRes = CreateFPCmp(DAG, Op.getOperand(1)); 1338 1339 // Return if flag is not set by a floating point comparison. 1340 if (CondRes.getOpcode() != MipsISD::FPCmp) 1341 return Op; 1342 1343 SDValue CCNode = CondRes.getOperand(2); 1344 Mips::CondCode CC = 1345 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); 1346 SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32); 1347 1348 return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode, 1349 Dest, CondRes); 1350 } 1351 1352 SDValue MipsTargetLowering:: 1353 LowerSELECT(SDValue Op, SelectionDAG &DAG) const 1354 { 1355 SDValue Cond = CreateFPCmp(DAG, Op.getOperand(0)); 1356 1357 // Return if flag is not set by a floating point comparison. 1358 if (Cond.getOpcode() != MipsISD::FPCmp) 1359 return Op; 1360 1361 return CreateCMovFP(DAG, Cond, Op.getOperand(1), Op.getOperand(2), 1362 Op.getDebugLoc()); 1363 } 1364 1365 SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op, 1366 SelectionDAG &DAG) const { 1367 // FIXME there isn't actually debug info here 1368 DebugLoc dl = Op.getDebugLoc(); 1369 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 1370 1371 if (getTargetMachine().getRelocationModel() != Reloc::PIC_ && !IsN64) { 1372 SDVTList VTs = DAG.getVTList(MVT::i32); 1373 1374 MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering(); 1375 1376 // %gp_rel relocation 1377 if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) { 1378 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1379 MipsII::MO_GPREL); 1380 SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1); 1381 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1382 return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode); 1383 } 1384 // %hi/%lo relocation 1385 SDValue GAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1386 MipsII::MO_ABS_HI); 1387 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1388 MipsII::MO_ABS_LO); 1389 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GAHi, 1); 1390 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GALo); 1391 return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1392 } 1393 1394 EVT ValTy = Op.getValueType(); 1395 bool HasGotOfst = (GV->hasInternalLinkage() || 1396 (GV->hasLocalLinkage() && !isa<Function>(GV))); 1397 unsigned GotFlag = IsN64 ? 1398 (HasGotOfst ? MipsII::MO_GOT_PAGE : MipsII::MO_GOT_DISP) : 1399 MipsII::MO_GOT; 1400 SDValue GA = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, GotFlag); 1401 GA = DAG.getNode(MipsISD::WrapperPIC, dl, ValTy, GA); 1402 SDValue ResNode = DAG.getLoad(ValTy, dl, 1403 DAG.getEntryNode(), GA, MachinePointerInfo(), 1404 false, false, 0); 1405 // On functions and global targets not internal linked only 1406 // a load from got/GP is necessary for PIC to work. 1407 if (!HasGotOfst) 1408 return ResNode; 1409 SDValue GALo = DAG.getTargetGlobalAddress(GV, dl, ValTy, 0, 1410 IsN64 ? MipsII::MO_GOT_OFST : 1411 MipsII::MO_ABS_LO); 1412 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, ValTy, GALo); 1413 return DAG.getNode(ISD::ADD, dl, ValTy, ResNode, Lo); 1414 } 1415 1416 SDValue MipsTargetLowering::LowerBlockAddress(SDValue Op, 1417 SelectionDAG &DAG) const { 1418 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 1419 // FIXME there isn't actually debug info here 1420 DebugLoc dl = Op.getDebugLoc(); 1421 1422 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1423 // %hi/%lo relocation 1424 SDValue BAHi = DAG.getBlockAddress(BA, MVT::i32, true, 1425 MipsII::MO_ABS_HI); 1426 SDValue BALo = DAG.getBlockAddress(BA, MVT::i32, true, 1427 MipsII::MO_ABS_LO); 1428 SDValue Hi = DAG.getNode(MipsISD::Hi, dl, MVT::i32, BAHi); 1429 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALo); 1430 return DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1431 } 1432 1433 SDValue BAGOTOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1434 MipsII::MO_GOT); 1435 BAGOTOffset = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, BAGOTOffset); 1436 SDValue BALOOffset = DAG.getBlockAddress(BA, MVT::i32, true, 1437 MipsII::MO_ABS_LO); 1438 SDValue Load = DAG.getLoad(MVT::i32, dl, 1439 DAG.getEntryNode(), BAGOTOffset, 1440 MachinePointerInfo(), false, false, 0); 1441 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, BALOOffset); 1442 return DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1443 } 1444 1445 SDValue MipsTargetLowering:: 1446 LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const 1447 { 1448 // If the relocation model is PIC, use the General Dynamic TLS Model, 1449 // otherwise use the Initial Exec or Local Exec TLS Model. 1450 // TODO: implement Local Dynamic TLS model 1451 1452 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 1453 DebugLoc dl = GA->getDebugLoc(); 1454 const GlobalValue *GV = GA->getGlobal(); 1455 EVT PtrVT = getPointerTy(); 1456 1457 if (getTargetMachine().getRelocationModel() == Reloc::PIC_) { 1458 // General Dynamic TLS Model 1459 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 1460 0, MipsII::MO_TLSGD); 1461 SDValue Tlsgd = DAG.getNode(MipsISD::TlsGd, dl, MVT::i32, TGA); 1462 SDValue GP = DAG.getRegister(Mips::GP, MVT::i32); 1463 SDValue Argument = DAG.getNode(ISD::ADD, dl, MVT::i32, GP, Tlsgd); 1464 1465 ArgListTy Args; 1466 ArgListEntry Entry; 1467 Entry.Node = Argument; 1468 Entry.Ty = (Type *) Type::getInt32Ty(*DAG.getContext()); 1469 Args.push_back(Entry); 1470 std::pair<SDValue, SDValue> CallResult = 1471 LowerCallTo(DAG.getEntryNode(), 1472 (Type *) Type::getInt32Ty(*DAG.getContext()), 1473 false, false, false, false, 0, CallingConv::C, false, true, 1474 DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, 1475 dl); 1476 1477 return CallResult.first; 1478 } 1479 1480 SDValue Offset; 1481 if (GV->isDeclaration()) { 1482 // Initial Exec TLS Model 1483 SDValue TGA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1484 MipsII::MO_GOTTPREL); 1485 Offset = DAG.getLoad(MVT::i32, dl, 1486 DAG.getEntryNode(), TGA, MachinePointerInfo(), 1487 false, false, 0); 1488 } else { 1489 // Local Exec TLS Model 1490 SDVTList VTs = DAG.getVTList(MVT::i32); 1491 SDValue TGAHi = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1492 MipsII::MO_TPREL_HI); 1493 SDValue TGALo = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0, 1494 MipsII::MO_TPREL_LO); 1495 SDValue Hi = DAG.getNode(MipsISD::TprelHi, dl, VTs, &TGAHi, 1); 1496 SDValue Lo = DAG.getNode(MipsISD::TprelLo, dl, MVT::i32, TGALo); 1497 Offset = DAG.getNode(ISD::ADD, dl, MVT::i32, Hi, Lo); 1498 } 1499 1500 SDValue ThreadPointer = DAG.getNode(MipsISD::ThreadPointer, dl, PtrVT); 1501 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 1502 } 1503 1504 SDValue MipsTargetLowering:: 1505 LowerJumpTable(SDValue Op, SelectionDAG &DAG) const 1506 { 1507 SDValue ResNode; 1508 SDValue HiPart; 1509 // FIXME there isn't actually debug info here 1510 DebugLoc dl = Op.getDebugLoc(); 1511 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1512 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HI; 1513 1514 EVT PtrVT = Op.getValueType(); 1515 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 1516 1517 SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag); 1518 1519 if (!IsPIC) { 1520 SDValue Ops[] = { JTI }; 1521 HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1); 1522 } else {// Emit Load from Global Pointer 1523 JTI = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, JTI); 1524 HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI, 1525 MachinePointerInfo(), 1526 false, false, 0); 1527 } 1528 1529 SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, 1530 MipsII::MO_ABS_LO); 1531 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); 1532 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1533 1534 return ResNode; 1535 } 1536 1537 SDValue MipsTargetLowering:: 1538 LowerConstantPool(SDValue Op, SelectionDAG &DAG) const 1539 { 1540 SDValue ResNode; 1541 ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op); 1542 const Constant *C = N->getConstVal(); 1543 // FIXME there isn't actually debug info here 1544 DebugLoc dl = Op.getDebugLoc(); 1545 1546 // gp_rel relocation 1547 // FIXME: we should reference the constant pool using small data sections, 1548 // but the asm printer currently doesn't support this feature without 1549 // hacking it. This feature should come soon so we can uncomment the 1550 // stuff below. 1551 //if (IsInSmallSection(C->getType())) { 1552 // SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP); 1553 // SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32); 1554 // ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode); 1555 1556 if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 1557 SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1558 N->getOffset(), MipsII::MO_ABS_HI); 1559 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1560 N->getOffset(), MipsII::MO_ABS_LO); 1561 SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); 1562 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1563 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); 1564 } else { 1565 SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1566 N->getOffset(), MipsII::MO_GOT); 1567 CP = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, CP); 1568 SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), 1569 CP, MachinePointerInfo::getConstantPool(), 1570 false, false, 0); 1571 SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), 1572 N->getOffset(), MipsII::MO_ABS_LO); 1573 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); 1574 ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); 1575 } 1576 1577 return ResNode; 1578 } 1579 1580 SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 1581 MachineFunction &MF = DAG.getMachineFunction(); 1582 MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>(); 1583 1584 DebugLoc dl = Op.getDebugLoc(); 1585 SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 1586 getPointerTy()); 1587 1588 // vastart just stores the address of the VarArgsFrameIndex slot into the 1589 // memory location argument. 1590 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 1591 return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1), 1592 MachinePointerInfo(SV), 1593 false, false, 0); 1594 } 1595 1596 static SDValue LowerFCOPYSIGN32(SDValue Op, SelectionDAG &DAG) { 1597 // FIXME: Use ext/ins instructions if target architecture is Mips32r2. 1598 DebugLoc dl = Op.getDebugLoc(); 1599 SDValue Op0 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(0)); 1600 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op.getOperand(1)); 1601 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op0, 1602 DAG.getConstant(0x7fffffff, MVT::i32)); 1603 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op1, 1604 DAG.getConstant(0x80000000, MVT::i32)); 1605 SDValue Result = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1606 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Result); 1607 } 1608 1609 static SDValue LowerFCOPYSIGN64(SDValue Op, SelectionDAG &DAG, bool isLittle) { 1610 // FIXME: 1611 // Use ext/ins instructions if target architecture is Mips32r2. 1612 // Eliminate redundant mfc1 and mtc1 instructions. 1613 unsigned LoIdx = 0, HiIdx = 1; 1614 1615 if (!isLittle) 1616 std::swap(LoIdx, HiIdx); 1617 1618 DebugLoc dl = Op.getDebugLoc(); 1619 SDValue Word0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1620 Op.getOperand(0), 1621 DAG.getConstant(LoIdx, MVT::i32)); 1622 SDValue Hi0 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1623 Op.getOperand(0), DAG.getConstant(HiIdx, MVT::i32)); 1624 SDValue Hi1 = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1625 Op.getOperand(1), DAG.getConstant(HiIdx, MVT::i32)); 1626 SDValue And0 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi0, 1627 DAG.getConstant(0x7fffffff, MVT::i32)); 1628 SDValue And1 = DAG.getNode(ISD::AND, dl, MVT::i32, Hi1, 1629 DAG.getConstant(0x80000000, MVT::i32)); 1630 SDValue Word1 = DAG.getNode(ISD::OR, dl, MVT::i32, And0, And1); 1631 1632 if (!isLittle) 1633 std::swap(Word0, Word1); 1634 1635 return DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, Word0, Word1); 1636 } 1637 1638 SDValue MipsTargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) 1639 const { 1640 EVT Ty = Op.getValueType(); 1641 1642 assert(Ty == MVT::f32 || Ty == MVT::f64); 1643 1644 if (Ty == MVT::f32) 1645 return LowerFCOPYSIGN32(Op, DAG); 1646 else 1647 return LowerFCOPYSIGN64(Op, DAG, Subtarget->isLittle()); 1648 } 1649 1650 SDValue MipsTargetLowering:: 1651 LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 1652 // check the depth 1653 assert((cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue() == 0) && 1654 "Frame address can only be determined for current frame."); 1655 1656 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 1657 MFI->setFrameAddressIsTaken(true); 1658 EVT VT = Op.getValueType(); 1659 DebugLoc dl = Op.getDebugLoc(); 1660 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, Mips::FP, VT); 1661 return FrameAddr; 1662 } 1663 1664 // TODO: set SType according to the desired memory barrier behavior. 1665 SDValue MipsTargetLowering::LowerMEMBARRIER(SDValue Op, 1666 SelectionDAG& DAG) const { 1667 unsigned SType = 0; 1668 DebugLoc dl = Op.getDebugLoc(); 1669 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1670 DAG.getConstant(SType, MVT::i32)); 1671 } 1672 1673 SDValue MipsTargetLowering::LowerATOMIC_FENCE(SDValue Op, 1674 SelectionDAG& DAG) const { 1675 // FIXME: Need pseudo-fence for 'singlethread' fences 1676 // FIXME: Set SType for weaker fences where supported/appropriate. 1677 unsigned SType = 0; 1678 DebugLoc dl = Op.getDebugLoc(); 1679 return DAG.getNode(MipsISD::Sync, dl, MVT::Other, Op.getOperand(0), 1680 DAG.getConstant(SType, MVT::i32)); 1681 } 1682 1683 //===----------------------------------------------------------------------===// 1684 // Calling Convention Implementation 1685 //===----------------------------------------------------------------------===// 1686 1687 #include "MipsGenCallingConv.inc" 1688 1689 //===----------------------------------------------------------------------===// 1690 // TODO: Implement a generic logic using tblgen that can support this. 1691 // Mips O32 ABI rules: 1692 // --- 1693 // i32 - Passed in A0, A1, A2, A3 and stack 1694 // f32 - Only passed in f32 registers if no int reg has been used yet to hold 1695 // an argument. Otherwise, passed in A1, A2, A3 and stack. 1696 // f64 - Only passed in two aliased f32 registers if no int reg has been used 1697 // yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is 1698 // not used, it must be shadowed. If only A3 is avaiable, shadow it and 1699 // go to stack. 1700 // 1701 // For vararg functions, all arguments are passed in A0, A1, A2, A3 and stack. 1702 //===----------------------------------------------------------------------===// 1703 1704 static bool CC_MipsO32(unsigned ValNo, MVT ValVT, 1705 MVT LocVT, CCValAssign::LocInfo LocInfo, 1706 ISD::ArgFlagsTy ArgFlags, CCState &State) { 1707 1708 static const unsigned IntRegsSize=4, FloatRegsSize=2; 1709 1710 static const unsigned IntRegs[] = { 1711 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1712 }; 1713 static const unsigned F32Regs[] = { 1714 Mips::F12, Mips::F14 1715 }; 1716 static const unsigned F64Regs[] = { 1717 Mips::D6, Mips::D7 1718 }; 1719 1720 // ByVal Args 1721 if (ArgFlags.isByVal()) { 1722 State.HandleByVal(ValNo, ValVT, LocVT, LocInfo, 1723 1 /*MinSize*/, 4 /*MinAlign*/, ArgFlags); 1724 unsigned NextReg = (State.getNextStackOffset() + 3) / 4; 1725 for (unsigned r = State.getFirstUnallocated(IntRegs, IntRegsSize); 1726 r < std::min(IntRegsSize, NextReg); ++r) 1727 State.AllocateReg(IntRegs[r]); 1728 return false; 1729 } 1730 1731 // Promote i8 and i16 1732 if (LocVT == MVT::i8 || LocVT == MVT::i16) { 1733 LocVT = MVT::i32; 1734 if (ArgFlags.isSExt()) 1735 LocInfo = CCValAssign::SExt; 1736 else if (ArgFlags.isZExt()) 1737 LocInfo = CCValAssign::ZExt; 1738 else 1739 LocInfo = CCValAssign::AExt; 1740 } 1741 1742 unsigned Reg; 1743 1744 // f32 and f64 are allocated in A0, A1, A2, A3 when either of the following 1745 // is true: function is vararg, argument is 3rd or higher, there is previous 1746 // argument which is not f32 or f64. 1747 bool AllocateFloatsInIntReg = State.isVarArg() || ValNo > 1 1748 || State.getFirstUnallocated(F32Regs, FloatRegsSize) != ValNo; 1749 unsigned OrigAlign = ArgFlags.getOrigAlign(); 1750 bool isI64 = (ValVT == MVT::i32 && OrigAlign == 8); 1751 1752 if (ValVT == MVT::i32 || (ValVT == MVT::f32 && AllocateFloatsInIntReg)) { 1753 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1754 // If this is the first part of an i64 arg, 1755 // the allocated register must be either A0 or A2. 1756 if (isI64 && (Reg == Mips::A1 || Reg == Mips::A3)) 1757 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1758 LocVT = MVT::i32; 1759 } else if (ValVT == MVT::f64 && AllocateFloatsInIntReg) { 1760 // Allocate int register and shadow next int register. If first 1761 // available register is Mips::A1 or Mips::A3, shadow it too. 1762 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1763 if (Reg == Mips::A1 || Reg == Mips::A3) 1764 Reg = State.AllocateReg(IntRegs, IntRegsSize); 1765 State.AllocateReg(IntRegs, IntRegsSize); 1766 LocVT = MVT::i32; 1767 } else if (ValVT.isFloatingPoint() && !AllocateFloatsInIntReg) { 1768 // we are guaranteed to find an available float register 1769 if (ValVT == MVT::f32) { 1770 Reg = State.AllocateReg(F32Regs, FloatRegsSize); 1771 // Shadow int register 1772 State.AllocateReg(IntRegs, IntRegsSize); 1773 } else { 1774 Reg = State.AllocateReg(F64Regs, FloatRegsSize); 1775 // Shadow int registers 1776 unsigned Reg2 = State.AllocateReg(IntRegs, IntRegsSize); 1777 if (Reg2 == Mips::A1 || Reg2 == Mips::A3) 1778 State.AllocateReg(IntRegs, IntRegsSize); 1779 State.AllocateReg(IntRegs, IntRegsSize); 1780 } 1781 } else 1782 llvm_unreachable("Cannot handle this ValVT."); 1783 1784 unsigned SizeInBytes = ValVT.getSizeInBits() >> 3; 1785 unsigned Offset = State.AllocateStack(SizeInBytes, OrigAlign); 1786 1787 if (!Reg) 1788 State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); 1789 else 1790 State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo)); 1791 1792 return false; // CC must always match 1793 } 1794 1795 //===----------------------------------------------------------------------===// 1796 // Call Calling Convention Implementation 1797 //===----------------------------------------------------------------------===// 1798 1799 static const unsigned O32IntRegsSize = 4; 1800 1801 static const unsigned O32IntRegs[] = { 1802 Mips::A0, Mips::A1, Mips::A2, Mips::A3 1803 }; 1804 1805 // Return next O32 integer argument register. 1806 static unsigned getNextIntArgReg(unsigned Reg) { 1807 assert((Reg == Mips::A0) || (Reg == Mips::A2)); 1808 return (Reg == Mips::A0) ? Mips::A1 : Mips::A3; 1809 } 1810 1811 // Write ByVal Arg to arg registers and stack. 1812 static void 1813 WriteByValArg(SDValue& ByValChain, SDValue Chain, DebugLoc dl, 1814 SmallVector<std::pair<unsigned, SDValue>, 16>& RegsToPass, 1815 SmallVector<SDValue, 8>& MemOpChains, int& LastFI, 1816 MachineFrameInfo *MFI, SelectionDAG &DAG, SDValue Arg, 1817 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags, 1818 MVT PtrType, bool isLittle) { 1819 unsigned LocMemOffset = VA.getLocMemOffset(); 1820 unsigned Offset = 0; 1821 uint32_t RemainingSize = Flags.getByValSize(); 1822 unsigned ByValAlign = Flags.getByValAlign(); 1823 1824 // Copy the first 4 words of byval arg to registers A0 - A3. 1825 // FIXME: Use a stricter alignment if it enables better optimization in passes 1826 // run later. 1827 for (; RemainingSize >= 4 && LocMemOffset < 4 * 4; 1828 Offset += 4, RemainingSize -= 4, LocMemOffset += 4) { 1829 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1830 DAG.getConstant(Offset, MVT::i32)); 1831 SDValue LoadVal = DAG.getLoad(MVT::i32, dl, Chain, LoadPtr, 1832 MachinePointerInfo(), 1833 false, false, std::min(ByValAlign, 1834 (unsigned )4)); 1835 MemOpChains.push_back(LoadVal.getValue(1)); 1836 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1837 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1838 } 1839 1840 if (RemainingSize == 0) 1841 return; 1842 1843 // If there still is a register available for argument passing, write the 1844 // remaining part of the structure to it using subword loads and shifts. 1845 if (LocMemOffset < 4 * 4) { 1846 assert(RemainingSize <= 3 && RemainingSize >= 1 && 1847 "There must be one to three bytes remaining."); 1848 unsigned LoadSize = (RemainingSize == 3 ? 2 : RemainingSize); 1849 SDValue LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1850 DAG.getConstant(Offset, MVT::i32)); 1851 unsigned Alignment = std::min(ByValAlign, (unsigned )4); 1852 SDValue LoadVal = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1853 LoadPtr, MachinePointerInfo(), 1854 MVT::getIntegerVT(LoadSize * 8), false, 1855 false, Alignment); 1856 MemOpChains.push_back(LoadVal.getValue(1)); 1857 1858 // If target is big endian, shift it to the most significant half-word or 1859 // byte. 1860 if (!isLittle) 1861 LoadVal = DAG.getNode(ISD::SHL, dl, MVT::i32, LoadVal, 1862 DAG.getConstant(32 - LoadSize * 8, MVT::i32)); 1863 1864 Offset += LoadSize; 1865 RemainingSize -= LoadSize; 1866 1867 // Read second subword if necessary. 1868 if (RemainingSize != 0) { 1869 assert(RemainingSize == 1 && "There must be one byte remaining."); 1870 LoadPtr = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1871 DAG.getConstant(Offset, MVT::i32)); 1872 unsigned Alignment = std::min(ByValAlign, (unsigned )2); 1873 SDValue Subword = DAG.getExtLoad(ISD::ZEXTLOAD, dl, MVT::i32, Chain, 1874 LoadPtr, MachinePointerInfo(), 1875 MVT::i8, false, false, Alignment); 1876 MemOpChains.push_back(Subword.getValue(1)); 1877 // Insert the loaded byte to LoadVal. 1878 // FIXME: Use INS if supported by target. 1879 unsigned ShiftAmt = isLittle ? 16 : 8; 1880 SDValue Shift = DAG.getNode(ISD::SHL, dl, MVT::i32, Subword, 1881 DAG.getConstant(ShiftAmt, MVT::i32)); 1882 LoadVal = DAG.getNode(ISD::OR, dl, MVT::i32, LoadVal, Shift); 1883 } 1884 1885 unsigned DstReg = O32IntRegs[LocMemOffset / 4]; 1886 RegsToPass.push_back(std::make_pair(DstReg, LoadVal)); 1887 return; 1888 } 1889 1890 // Create a fixed object on stack at offset LocMemOffset and copy 1891 // remaining part of byval arg to it using memcpy. 1892 SDValue Src = DAG.getNode(ISD::ADD, dl, MVT::i32, Arg, 1893 DAG.getConstant(Offset, MVT::i32)); 1894 LastFI = MFI->CreateFixedObject(RemainingSize, LocMemOffset, true); 1895 SDValue Dst = DAG.getFrameIndex(LastFI, PtrType); 1896 ByValChain = DAG.getMemcpy(ByValChain, dl, Dst, Src, 1897 DAG.getConstant(RemainingSize, MVT::i32), 1898 std::min(ByValAlign, (unsigned)4), 1899 /*isVolatile=*/false, /*AlwaysInline=*/false, 1900 MachinePointerInfo(0), MachinePointerInfo(0)); 1901 } 1902 1903 /// LowerCall - functions arguments are copied from virtual regs to 1904 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted. 1905 /// TODO: isTailCall. 1906 SDValue 1907 MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee, 1908 CallingConv::ID CallConv, bool isVarArg, 1909 bool &isTailCall, 1910 const SmallVectorImpl<ISD::OutputArg> &Outs, 1911 const SmallVectorImpl<SDValue> &OutVals, 1912 const SmallVectorImpl<ISD::InputArg> &Ins, 1913 DebugLoc dl, SelectionDAG &DAG, 1914 SmallVectorImpl<SDValue> &InVals) const { 1915 // MIPs target does not yet support tail call optimization. 1916 isTailCall = false; 1917 1918 MachineFunction &MF = DAG.getMachineFunction(); 1919 MachineFrameInfo *MFI = MF.getFrameInfo(); 1920 const TargetFrameLowering *TFL = MF.getTarget().getFrameLowering(); 1921 bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_; 1922 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 1923 1924 // Analyze operands of the call, assigning locations to each operand. 1925 SmallVector<CCValAssign, 16> ArgLocs; 1926 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1927 getTargetMachine(), ArgLocs, *DAG.getContext()); 1928 1929 if (Subtarget->isABI_O32()) 1930 CCInfo.AnalyzeCallOperands(Outs, CC_MipsO32); 1931 else 1932 CCInfo.AnalyzeCallOperands(Outs, CC_Mips); 1933 1934 // Get a count of how many bytes are to be pushed on the stack. 1935 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 1936 1937 // Chain is the output chain of the last Load/Store or CopyToReg node. 1938 // ByValChain is the output chain of the last Memcpy node created for copying 1939 // byval arguments to the stack. 1940 SDValue Chain, CallSeqStart, ByValChain; 1941 SDValue NextStackOffsetVal = DAG.getIntPtrConstant(NextStackOffset, true); 1942 Chain = CallSeqStart = DAG.getCALLSEQ_START(InChain, NextStackOffsetVal); 1943 ByValChain = InChain; 1944 1945 // If this is the first call, create a stack frame object that points to 1946 // a location to which .cprestore saves $gp. 1947 if (IsPIC && !MipsFI->getGPFI()) 1948 MipsFI->setGPFI(MFI->CreateFixedObject(4, 0, true)); 1949 1950 // Get the frame index of the stack frame object that points to the location 1951 // of dynamically allocated area on the stack. 1952 int DynAllocFI = MipsFI->getDynAllocFI(); 1953 1954 // Update size of the maximum argument space. 1955 // For O32, a minimum of four words (16 bytes) of argument space is 1956 // allocated. 1957 if (Subtarget->isABI_O32()) 1958 NextStackOffset = std::max(NextStackOffset, (unsigned)16); 1959 1960 unsigned MaxCallFrameSize = MipsFI->getMaxCallFrameSize(); 1961 1962 if (MaxCallFrameSize < NextStackOffset) { 1963 MipsFI->setMaxCallFrameSize(NextStackOffset); 1964 1965 // Set the offsets relative to $sp of the $gp restore slot and dynamically 1966 // allocated stack space. These offsets must be aligned to a boundary 1967 // determined by the stack alignment of the ABI. 1968 unsigned StackAlignment = TFL->getStackAlignment(); 1969 NextStackOffset = (NextStackOffset + StackAlignment - 1) / 1970 StackAlignment * StackAlignment; 1971 1972 if (IsPIC) 1973 MFI->setObjectOffset(MipsFI->getGPFI(), NextStackOffset); 1974 1975 MFI->setObjectOffset(DynAllocFI, NextStackOffset); 1976 } 1977 1978 // With EABI is it possible to have 16 args on registers. 1979 SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass; 1980 SmallVector<SDValue, 8> MemOpChains; 1981 1982 int FirstFI = -MFI->getNumFixedObjects() - 1, LastFI = 0; 1983 1984 // Walk the register/memloc assignments, inserting copies/loads. 1985 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1986 SDValue Arg = OutVals[i]; 1987 CCValAssign &VA = ArgLocs[i]; 1988 1989 // Promote the value if needed. 1990 switch (VA.getLocInfo()) { 1991 default: llvm_unreachable("Unknown loc info!"); 1992 case CCValAssign::Full: 1993 if (Subtarget->isABI_O32() && VA.isRegLoc()) { 1994 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32) 1995 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg); 1996 if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) { 1997 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 1998 Arg, DAG.getConstant(0, MVT::i32)); 1999 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, dl, MVT::i32, 2000 Arg, DAG.getConstant(1, MVT::i32)); 2001 if (!Subtarget->isLittle()) 2002 std::swap(Lo, Hi); 2003 unsigned LocRegLo = VA.getLocReg(); 2004 unsigned LocRegHigh = getNextIntArgReg(LocRegLo); 2005 RegsToPass.push_back(std::make_pair(LocRegLo, Lo)); 2006 RegsToPass.push_back(std::make_pair(LocRegHigh, Hi)); 2007 continue; 2008 } 2009 } 2010 break; 2011 case CCValAssign::SExt: 2012 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); 2013 break; 2014 case CCValAssign::ZExt: 2015 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); 2016 break; 2017 case CCValAssign::AExt: 2018 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); 2019 break; 2020 } 2021 2022 // Arguments that can be passed on register must be kept at 2023 // RegsToPass vector 2024 if (VA.isRegLoc()) { 2025 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2026 continue; 2027 } 2028 2029 // Register can't get to this point... 2030 assert(VA.isMemLoc()); 2031 2032 // ByVal Arg. 2033 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2034 if (Flags.isByVal()) { 2035 assert(Subtarget->isABI_O32() && 2036 "No support for ByVal args by ABIs other than O32 yet."); 2037 assert(Flags.getByValSize() && 2038 "ByVal args of size 0 should have been ignored by front-end."); 2039 WriteByValArg(ByValChain, Chain, dl, RegsToPass, MemOpChains, LastFI, MFI, 2040 DAG, Arg, VA, Flags, getPointerTy(), Subtarget->isLittle()); 2041 continue; 2042 } 2043 2044 // Create the frame index object for this incoming parameter 2045 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2046 VA.getLocMemOffset(), true); 2047 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2048 2049 // emit ISD::STORE whichs stores the 2050 // parameter value to a stack Location 2051 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff, 2052 MachinePointerInfo(), 2053 false, false, 0)); 2054 } 2055 2056 // Extend range of indices of frame objects for outgoing arguments that were 2057 // created during this function call. Skip this step if no such objects were 2058 // created. 2059 if (LastFI) 2060 MipsFI->extendOutArgFIRange(FirstFI, LastFI); 2061 2062 // If a memcpy has been created to copy a byval arg to a stack, replace the 2063 // chain input of CallSeqStart with ByValChain. 2064 if (InChain != ByValChain) 2065 DAG.UpdateNodeOperands(CallSeqStart.getNode(), ByValChain, 2066 NextStackOffsetVal); 2067 2068 // Transform all store nodes into one single node because all store 2069 // nodes are independent of each other. 2070 if (!MemOpChains.empty()) 2071 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2072 &MemOpChains[0], MemOpChains.size()); 2073 2074 // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every 2075 // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol 2076 // node so that legalize doesn't hack it. 2077 unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG; 2078 bool LoadSymAddr = false; 2079 SDValue CalleeLo; 2080 2081 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2082 if (IsPIC && G->getGlobal()->hasInternalLinkage()) { 2083 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2084 getPointerTy(), 0,MipsII:: MO_GOT); 2085 CalleeLo = DAG.getTargetGlobalAddress(G->getGlobal(), dl, getPointerTy(), 2086 0, MipsII::MO_ABS_LO); 2087 } else { 2088 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl, 2089 getPointerTy(), 0, OpFlag); 2090 } 2091 2092 LoadSymAddr = true; 2093 } 2094 else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2095 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), 2096 getPointerTy(), OpFlag); 2097 LoadSymAddr = true; 2098 } 2099 2100 SDValue InFlag; 2101 2102 // Create nodes that load address of callee and copy it to T9 2103 if (IsPIC) { 2104 if (LoadSymAddr) { 2105 // Load callee address 2106 Callee = DAG.getNode(MipsISD::WrapperPIC, dl, MVT::i32, Callee); 2107 SDValue LoadValue = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), Callee, 2108 MachinePointerInfo::getGOT(), 2109 false, false, 0); 2110 2111 // Use GOT+LO if callee has internal linkage. 2112 if (CalleeLo.getNode()) { 2113 SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CalleeLo); 2114 Callee = DAG.getNode(ISD::ADD, dl, MVT::i32, LoadValue, Lo); 2115 } else 2116 Callee = LoadValue; 2117 } 2118 2119 // copy to T9 2120 Chain = DAG.getCopyToReg(Chain, dl, Mips::T9, Callee, SDValue(0, 0)); 2121 InFlag = Chain.getValue(1); 2122 Callee = DAG.getRegister(Mips::T9, MVT::i32); 2123 } 2124 2125 // Build a sequence of copy-to-reg nodes chained together with token 2126 // chain and flag operands which copy the outgoing args into registers. 2127 // The InFlag in necessary since all emitted instructions must be 2128 // stuck together. 2129 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2130 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2131 RegsToPass[i].second, InFlag); 2132 InFlag = Chain.getValue(1); 2133 } 2134 2135 // MipsJmpLink = #chain, #target_address, #opt_in_flags... 2136 // = Chain, Callee, Reg#1, Reg#2, ... 2137 // 2138 // Returns a chain & a flag for retval copy to use. 2139 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2140 SmallVector<SDValue, 8> Ops; 2141 Ops.push_back(Chain); 2142 Ops.push_back(Callee); 2143 2144 // Add argument registers to the end of the list so that they are 2145 // known live into the call. 2146 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2147 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2148 RegsToPass[i].second.getValueType())); 2149 2150 if (InFlag.getNode()) 2151 Ops.push_back(InFlag); 2152 2153 Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size()); 2154 InFlag = Chain.getValue(1); 2155 2156 // Create the CALLSEQ_END node. 2157 Chain = DAG.getCALLSEQ_END(Chain, 2158 DAG.getIntPtrConstant(NextStackOffset, true), 2159 DAG.getIntPtrConstant(0, true), InFlag); 2160 InFlag = Chain.getValue(1); 2161 2162 // Handle result values, copying them out of physregs into vregs that we 2163 // return. 2164 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2165 Ins, dl, DAG, InVals); 2166 } 2167 2168 /// LowerCallResult - Lower the result values of a call into the 2169 /// appropriate copies out of appropriate physical registers. 2170 SDValue 2171 MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 2172 CallingConv::ID CallConv, bool isVarArg, 2173 const SmallVectorImpl<ISD::InputArg> &Ins, 2174 DebugLoc dl, SelectionDAG &DAG, 2175 SmallVectorImpl<SDValue> &InVals) const { 2176 // Assign locations to each value returned by this call. 2177 SmallVector<CCValAssign, 16> RVLocs; 2178 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2179 getTargetMachine(), RVLocs, *DAG.getContext()); 2180 2181 CCInfo.AnalyzeCallResult(Ins, RetCC_Mips); 2182 2183 // Copy all of the result registers out of their specified physreg. 2184 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2185 Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(), 2186 RVLocs[i].getValVT(), InFlag).getValue(1); 2187 InFlag = Chain.getValue(2); 2188 InVals.push_back(Chain.getValue(0)); 2189 } 2190 2191 return Chain; 2192 } 2193 2194 //===----------------------------------------------------------------------===// 2195 // Formal Arguments Calling Convention Implementation 2196 //===----------------------------------------------------------------------===// 2197 static void ReadByValArg(MachineFunction &MF, SDValue Chain, DebugLoc dl, 2198 std::vector<SDValue>& OutChains, 2199 SelectionDAG &DAG, unsigned NumWords, SDValue FIN, 2200 const CCValAssign &VA, const ISD::ArgFlagsTy& Flags) { 2201 unsigned LocMem = VA.getLocMemOffset(); 2202 unsigned FirstWord = LocMem / 4; 2203 2204 // copy register A0 - A3 to frame object 2205 for (unsigned i = 0; i < NumWords; ++i) { 2206 unsigned CurWord = FirstWord + i; 2207 if (CurWord >= O32IntRegsSize) 2208 break; 2209 2210 unsigned SrcReg = O32IntRegs[CurWord]; 2211 unsigned Reg = AddLiveIn(MF, SrcReg, Mips::CPURegsRegisterClass); 2212 SDValue StorePtr = DAG.getNode(ISD::ADD, dl, MVT::i32, FIN, 2213 DAG.getConstant(i * 4, MVT::i32)); 2214 SDValue Store = DAG.getStore(Chain, dl, DAG.getRegister(Reg, MVT::i32), 2215 StorePtr, MachinePointerInfo(), false, 2216 false, 0); 2217 OutChains.push_back(Store); 2218 } 2219 } 2220 2221 /// LowerFormalArguments - transform physical registers into virtual registers 2222 /// and generate load operations for arguments places on the stack. 2223 SDValue 2224 MipsTargetLowering::LowerFormalArguments(SDValue Chain, 2225 CallingConv::ID CallConv, 2226 bool isVarArg, 2227 const SmallVectorImpl<ISD::InputArg> 2228 &Ins, 2229 DebugLoc dl, SelectionDAG &DAG, 2230 SmallVectorImpl<SDValue> &InVals) 2231 const { 2232 MachineFunction &MF = DAG.getMachineFunction(); 2233 MachineFrameInfo *MFI = MF.getFrameInfo(); 2234 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2235 2236 MipsFI->setVarArgsFrameIndex(0); 2237 2238 // Used with vargs to acumulate store chains. 2239 std::vector<SDValue> OutChains; 2240 2241 // Assign locations to all of the incoming arguments. 2242 SmallVector<CCValAssign, 16> ArgLocs; 2243 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2244 getTargetMachine(), ArgLocs, *DAG.getContext()); 2245 2246 if (Subtarget->isABI_O32()) 2247 CCInfo.AnalyzeFormalArguments(Ins, CC_MipsO32); 2248 else 2249 CCInfo.AnalyzeFormalArguments(Ins, CC_Mips); 2250 2251 int LastFI = 0;// MipsFI->LastInArgFI is 0 at the entry of this function. 2252 2253 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2254 CCValAssign &VA = ArgLocs[i]; 2255 2256 // Arguments stored on registers 2257 if (VA.isRegLoc()) { 2258 EVT RegVT = VA.getLocVT(); 2259 unsigned ArgReg = VA.getLocReg(); 2260 TargetRegisterClass *RC = 0; 2261 2262 if (RegVT == MVT::i32) 2263 RC = Mips::CPURegsRegisterClass; 2264 else if (RegVT == MVT::i64) 2265 RC = Mips::CPU64RegsRegisterClass; 2266 else if (RegVT == MVT::f32) 2267 RC = Mips::FGR32RegisterClass; 2268 else if (RegVT == MVT::f64) 2269 RC = HasMips64 ? Mips::FGR64RegisterClass : Mips::AFGR64RegisterClass; 2270 else 2271 llvm_unreachable("RegVT not supported by FormalArguments Lowering"); 2272 2273 // Transform the arguments stored on 2274 // physical registers into virtual ones 2275 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgReg, RC); 2276 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 2277 2278 // If this is an 8 or 16-bit value, it has been passed promoted 2279 // to 32 bits. Insert an assert[sz]ext to capture this, then 2280 // truncate to the right size. 2281 if (VA.getLocInfo() != CCValAssign::Full) { 2282 unsigned Opcode = 0; 2283 if (VA.getLocInfo() == CCValAssign::SExt) 2284 Opcode = ISD::AssertSext; 2285 else if (VA.getLocInfo() == CCValAssign::ZExt) 2286 Opcode = ISD::AssertZext; 2287 if (Opcode) 2288 ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue, 2289 DAG.getValueType(VA.getValVT())); 2290 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 2291 } 2292 2293 // Handle O32 ABI cases: i32->f32 and (i32,i32)->f64 2294 if (Subtarget->isABI_O32()) { 2295 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32) 2296 ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue); 2297 if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) { 2298 unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(), 2299 getNextIntArgReg(ArgReg), RC); 2300 SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT); 2301 if (!Subtarget->isLittle()) 2302 std::swap(ArgValue, ArgValue2); 2303 ArgValue = DAG.getNode(MipsISD::BuildPairF64, dl, MVT::f64, 2304 ArgValue, ArgValue2); 2305 } 2306 } 2307 2308 InVals.push_back(ArgValue); 2309 } else { // VA.isRegLoc() 2310 2311 // sanity check 2312 assert(VA.isMemLoc()); 2313 2314 ISD::ArgFlagsTy Flags = Ins[i].Flags; 2315 2316 if (Flags.isByVal()) { 2317 assert(Subtarget->isABI_O32() && 2318 "No support for ByVal args by ABIs other than O32 yet."); 2319 assert(Flags.getByValSize() && 2320 "ByVal args of size 0 should have been ignored by front-end."); 2321 unsigned NumWords = (Flags.getByValSize() + 3) / 4; 2322 LastFI = MFI->CreateFixedObject(NumWords * 4, VA.getLocMemOffset(), 2323 true); 2324 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2325 InVals.push_back(FIN); 2326 ReadByValArg(MF, Chain, dl, OutChains, DAG, NumWords, FIN, VA, Flags); 2327 2328 continue; 2329 } 2330 2331 // The stack pointer offset is relative to the caller stack frame. 2332 LastFI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8, 2333 VA.getLocMemOffset(), true); 2334 2335 // Create load nodes to retrieve arguments from the stack 2336 SDValue FIN = DAG.getFrameIndex(LastFI, getPointerTy()); 2337 InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN, 2338 MachinePointerInfo::getFixedStack(LastFI), 2339 false, false, 0)); 2340 } 2341 } 2342 2343 // The mips ABIs for returning structs by value requires that we copy 2344 // the sret argument into $v0 for the return. Save the argument into 2345 // a virtual register so that we can access it from the return points. 2346 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2347 unsigned Reg = MipsFI->getSRetReturnReg(); 2348 if (!Reg) { 2349 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); 2350 MipsFI->setSRetReturnReg(Reg); 2351 } 2352 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 2353 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 2354 } 2355 2356 if (isVarArg && Subtarget->isABI_O32()) { 2357 // Record the frame index of the first variable argument 2358 // which is a value necessary to VASTART. 2359 unsigned NextStackOffset = CCInfo.getNextStackOffset(); 2360 assert(NextStackOffset % 4 == 0 && 2361 "NextStackOffset must be aligned to 4-byte boundaries."); 2362 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2363 MipsFI->setVarArgsFrameIndex(LastFI); 2364 2365 // If NextStackOffset is smaller than o32's 16-byte reserved argument area, 2366 // copy the integer registers that have not been used for argument passing 2367 // to the caller's stack frame. 2368 for (; NextStackOffset < 16; NextStackOffset += 4) { 2369 TargetRegisterClass *RC = Mips::CPURegsRegisterClass; 2370 unsigned Idx = NextStackOffset / 4; 2371 unsigned Reg = AddLiveIn(DAG.getMachineFunction(), O32IntRegs[Idx], RC); 2372 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32); 2373 LastFI = MFI->CreateFixedObject(4, NextStackOffset, true); 2374 SDValue PtrOff = DAG.getFrameIndex(LastFI, getPointerTy()); 2375 OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff, 2376 MachinePointerInfo(), 2377 false, false, 0)); 2378 } 2379 } 2380 2381 MipsFI->setLastInArgFI(LastFI); 2382 2383 // All stores are grouped in one node to allow the matching between 2384 // the size of Ins and InVals. This only happens when on varg functions 2385 if (!OutChains.empty()) { 2386 OutChains.push_back(Chain); 2387 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2388 &OutChains[0], OutChains.size()); 2389 } 2390 2391 return Chain; 2392 } 2393 2394 //===----------------------------------------------------------------------===// 2395 // Return Value Calling Convention Implementation 2396 //===----------------------------------------------------------------------===// 2397 2398 SDValue 2399 MipsTargetLowering::LowerReturn(SDValue Chain, 2400 CallingConv::ID CallConv, bool isVarArg, 2401 const SmallVectorImpl<ISD::OutputArg> &Outs, 2402 const SmallVectorImpl<SDValue> &OutVals, 2403 DebugLoc dl, SelectionDAG &DAG) const { 2404 2405 // CCValAssign - represent the assignment of 2406 // the return value to a location 2407 SmallVector<CCValAssign, 16> RVLocs; 2408 2409 // CCState - Info about the registers and stack slot. 2410 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 2411 getTargetMachine(), RVLocs, *DAG.getContext()); 2412 2413 // Analize return values. 2414 CCInfo.AnalyzeReturn(Outs, RetCC_Mips); 2415 2416 // If this is the first return lowered for this function, add 2417 // the regs to the liveout set for the function. 2418 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) { 2419 for (unsigned i = 0; i != RVLocs.size(); ++i) 2420 if (RVLocs[i].isRegLoc()) 2421 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg()); 2422 } 2423 2424 SDValue Flag; 2425 2426 // Copy the result values into the output registers. 2427 for (unsigned i = 0; i != RVLocs.size(); ++i) { 2428 CCValAssign &VA = RVLocs[i]; 2429 assert(VA.isRegLoc() && "Can only return in registers!"); 2430 2431 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), 2432 OutVals[i], Flag); 2433 2434 // guarantee that all emitted copies are 2435 // stuck together, avoiding something bad 2436 Flag = Chain.getValue(1); 2437 } 2438 2439 // The mips ABIs for returning structs by value requires that we copy 2440 // the sret argument into $v0 for the return. We saved the argument into 2441 // a virtual register in the entry block, so now we copy the value out 2442 // and into $v0. 2443 if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 2444 MachineFunction &MF = DAG.getMachineFunction(); 2445 MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>(); 2446 unsigned Reg = MipsFI->getSRetReturnReg(); 2447 2448 if (!Reg) 2449 llvm_unreachable("sret virtual register not created in the entry block"); 2450 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 2451 2452 Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag); 2453 Flag = Chain.getValue(1); 2454 } 2455 2456 // Return on Mips is always a "jr $ra" 2457 if (Flag.getNode()) 2458 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2459 Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag); 2460 else // Return Void 2461 return DAG.getNode(MipsISD::Ret, dl, MVT::Other, 2462 Chain, DAG.getRegister(Mips::RA, MVT::i32)); 2463 } 2464 2465 //===----------------------------------------------------------------------===// 2466 // Mips Inline Assembly Support 2467 //===----------------------------------------------------------------------===// 2468 2469 /// getConstraintType - Given a constraint letter, return the type of 2470 /// constraint it is for this target. 2471 MipsTargetLowering::ConstraintType MipsTargetLowering:: 2472 getConstraintType(const std::string &Constraint) const 2473 { 2474 // Mips specific constrainy 2475 // GCC config/mips/constraints.md 2476 // 2477 // 'd' : An address register. Equivalent to r 2478 // unless generating MIPS16 code. 2479 // 'y' : Equivalent to r; retained for 2480 // backwards compatibility. 2481 // 'f' : Floating Point registers. 2482 if (Constraint.size() == 1) { 2483 switch (Constraint[0]) { 2484 default : break; 2485 case 'd': 2486 case 'y': 2487 case 'f': 2488 return C_RegisterClass; 2489 break; 2490 } 2491 } 2492 return TargetLowering::getConstraintType(Constraint); 2493 } 2494 2495 /// Examine constraint type and operand type and determine a weight value. 2496 /// This object must already have been set up with the operand type 2497 /// and the current alternative constraint selected. 2498 TargetLowering::ConstraintWeight 2499 MipsTargetLowering::getSingleConstraintMatchWeight( 2500 AsmOperandInfo &info, const char *constraint) const { 2501 ConstraintWeight weight = CW_Invalid; 2502 Value *CallOperandVal = info.CallOperandVal; 2503 // If we don't have a value, we can't do a match, 2504 // but allow it at the lowest weight. 2505 if (CallOperandVal == NULL) 2506 return CW_Default; 2507 Type *type = CallOperandVal->getType(); 2508 // Look at the constraint type. 2509 switch (*constraint) { 2510 default: 2511 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 2512 break; 2513 case 'd': 2514 case 'y': 2515 if (type->isIntegerTy()) 2516 weight = CW_Register; 2517 break; 2518 case 'f': 2519 if (type->isFloatTy()) 2520 weight = CW_Register; 2521 break; 2522 } 2523 return weight; 2524 } 2525 2526 /// Given a register class constraint, like 'r', if this corresponds directly 2527 /// to an LLVM register class, return a register of 0 and the register class 2528 /// pointer. 2529 std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering:: 2530 getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const 2531 { 2532 if (Constraint.size() == 1) { 2533 switch (Constraint[0]) { 2534 case 'd': // Address register. Same as 'r' unless generating MIPS16 code. 2535 case 'y': // Same as 'r'. Exists for compatibility. 2536 case 'r': 2537 return std::make_pair(0U, Mips::CPURegsRegisterClass); 2538 case 'f': 2539 if (VT == MVT::f32) 2540 return std::make_pair(0U, Mips::FGR32RegisterClass); 2541 if (VT == MVT::f64) 2542 if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit())) 2543 return std::make_pair(0U, Mips::AFGR64RegisterClass); 2544 break; 2545 } 2546 } 2547 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 2548 } 2549 2550 bool 2551 MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const { 2552 // The Mips target isn't yet aware of offsets. 2553 return false; 2554 } 2555 2556 bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 2557 if (VT != MVT::f32 && VT != MVT::f64) 2558 return false; 2559 if (Imm.isNegZero()) 2560 return false; 2561 return Imm.isZero(); 2562 } 2563
