1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the SelectionDAGISel class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CodeGen/GCStrategy.h" 15 #include "ScheduleDAGSDNodes.h" 16 #include "SelectionDAGBuilder.h" 17 #include "llvm/ADT/PostOrderIterator.h" 18 #include "llvm/ADT/Statistic.h" 19 #include "llvm/Analysis/AliasAnalysis.h" 20 #include "llvm/Analysis/BranchProbabilityInfo.h" 21 #include "llvm/Analysis/CFG.h" 22 #include "llvm/Analysis/TargetLibraryInfo.h" 23 #include "llvm/CodeGen/Analysis.h" 24 #include "llvm/CodeGen/FastISel.h" 25 #include "llvm/CodeGen/FunctionLoweringInfo.h" 26 #include "llvm/CodeGen/GCMetadata.h" 27 #include "llvm/CodeGen/MachineFrameInfo.h" 28 #include "llvm/CodeGen/MachineFunction.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineModuleInfo.h" 31 #include "llvm/CodeGen/MachineRegisterInfo.h" 32 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 33 #include "llvm/CodeGen/SchedulerRegistry.h" 34 #include "llvm/CodeGen/SelectionDAG.h" 35 #include "llvm/CodeGen/SelectionDAGISel.h" 36 #include "llvm/CodeGen/WinEHFuncInfo.h" 37 #include "llvm/IR/Constants.h" 38 #include "llvm/IR/DebugInfo.h" 39 #include "llvm/IR/Function.h" 40 #include "llvm/IR/InlineAsm.h" 41 #include "llvm/IR/Instructions.h" 42 #include "llvm/IR/IntrinsicInst.h" 43 #include "llvm/IR/Intrinsics.h" 44 #include "llvm/IR/LLVMContext.h" 45 #include "llvm/IR/Module.h" 46 #include "llvm/MC/MCAsmInfo.h" 47 #include "llvm/Support/Compiler.h" 48 #include "llvm/Support/Debug.h" 49 #include "llvm/Support/ErrorHandling.h" 50 #include "llvm/Support/Timer.h" 51 #include "llvm/Support/raw_ostream.h" 52 #include "llvm/Target/TargetInstrInfo.h" 53 #include "llvm/Target/TargetIntrinsicInfo.h" 54 #include "llvm/Target/TargetLowering.h" 55 #include "llvm/Target/TargetMachine.h" 56 #include "llvm/Target/TargetOptions.h" 57 #include "llvm/Target/TargetRegisterInfo.h" 58 #include "llvm/Target/TargetSubtargetInfo.h" 59 #include "llvm/Transforms/Utils/BasicBlockUtils.h" 60 #include <algorithm> 61 using namespace llvm; 62 63 #define DEBUG_TYPE "isel" 64 65 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 66 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 67 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 68 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 69 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 70 STATISTIC(NumEntryBlocks, "Number of entry blocks encountered"); 71 STATISTIC(NumFastIselFailLowerArguments, 72 "Number of entry blocks where fast isel failed to lower arguments"); 73 74 #ifndef NDEBUG 75 static cl::opt<bool> 76 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 77 cl::desc("Enable extra verbose messages in the \"fast\" " 78 "instruction selector")); 79 80 // Terminators 81 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 82 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 83 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 84 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 85 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 86 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 87 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 88 89 // Standard binary operators... 90 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 91 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 92 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 93 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 94 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 95 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 96 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 97 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 98 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 99 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 100 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 101 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 102 103 // Logical operators... 104 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 105 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 106 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 107 108 // Memory instructions... 109 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 110 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 111 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 112 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 113 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 114 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 115 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 116 117 // Convert instructions... 118 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 119 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 120 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 121 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 122 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 123 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 124 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 125 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 126 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 127 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 128 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 129 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 130 131 // Other instructions... 132 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 133 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 134 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 135 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 136 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 137 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 138 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 139 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 140 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 141 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 142 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 143 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 144 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 145 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 146 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 147 148 // Intrinsic instructions... 149 STATISTIC(NumFastIselFailIntrinsicCall, "Fast isel fails on Intrinsic call"); 150 STATISTIC(NumFastIselFailSAddWithOverflow, 151 "Fast isel fails on sadd.with.overflow"); 152 STATISTIC(NumFastIselFailUAddWithOverflow, 153 "Fast isel fails on uadd.with.overflow"); 154 STATISTIC(NumFastIselFailSSubWithOverflow, 155 "Fast isel fails on ssub.with.overflow"); 156 STATISTIC(NumFastIselFailUSubWithOverflow, 157 "Fast isel fails on usub.with.overflow"); 158 STATISTIC(NumFastIselFailSMulWithOverflow, 159 "Fast isel fails on smul.with.overflow"); 160 STATISTIC(NumFastIselFailUMulWithOverflow, 161 "Fast isel fails on umul.with.overflow"); 162 STATISTIC(NumFastIselFailFrameaddress, "Fast isel fails on Frameaddress"); 163 STATISTIC(NumFastIselFailSqrt, "Fast isel fails on sqrt call"); 164 STATISTIC(NumFastIselFailStackMap, "Fast isel fails on StackMap call"); 165 STATISTIC(NumFastIselFailPatchPoint, "Fast isel fails on PatchPoint call"); 166 #endif 167 168 static cl::opt<bool> 169 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 170 cl::desc("Enable verbose messages in the \"fast\" " 171 "instruction selector")); 172 static cl::opt<int> EnableFastISelAbort( 173 "fast-isel-abort", cl::Hidden, 174 cl::desc("Enable abort calls when \"fast\" instruction selection " 175 "fails to lower an instruction: 0 disable the abort, 1 will " 176 "abort but for args, calls and terminators, 2 will also " 177 "abort for argument lowering, and 3 will never fallback " 178 "to SelectionDAG.")); 179 180 static cl::opt<bool> 181 UseMBPI("use-mbpi", 182 cl::desc("use Machine Branch Probability Info"), 183 cl::init(true), cl::Hidden); 184 185 #ifndef NDEBUG 186 static cl::opt<std::string> 187 FilterDAGBasicBlockName("filter-view-dags", cl::Hidden, 188 cl::desc("Only display the basic block whose name " 189 "matches this for all view-*-dags options")); 190 static cl::opt<bool> 191 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 192 cl::desc("Pop up a window to show dags before the first " 193 "dag combine pass")); 194 static cl::opt<bool> 195 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 196 cl::desc("Pop up a window to show dags before legalize types")); 197 static cl::opt<bool> 198 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 199 cl::desc("Pop up a window to show dags before legalize")); 200 static cl::opt<bool> 201 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 202 cl::desc("Pop up a window to show dags before the second " 203 "dag combine pass")); 204 static cl::opt<bool> 205 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 206 cl::desc("Pop up a window to show dags before the post legalize types" 207 " dag combine pass")); 208 static cl::opt<bool> 209 ViewISelDAGs("view-isel-dags", cl::Hidden, 210 cl::desc("Pop up a window to show isel dags as they are selected")); 211 static cl::opt<bool> 212 ViewSchedDAGs("view-sched-dags", cl::Hidden, 213 cl::desc("Pop up a window to show sched dags as they are processed")); 214 static cl::opt<bool> 215 ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 216 cl::desc("Pop up a window to show SUnit dags after they are processed")); 217 #else 218 static const bool ViewDAGCombine1 = false, 219 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 220 ViewDAGCombine2 = false, 221 ViewDAGCombineLT = false, 222 ViewISelDAGs = false, ViewSchedDAGs = false, 223 ViewSUnitDAGs = false; 224 #endif 225 226 //===---------------------------------------------------------------------===// 227 /// 228 /// RegisterScheduler class - Track the registration of instruction schedulers. 229 /// 230 //===---------------------------------------------------------------------===// 231 MachinePassRegistry RegisterScheduler::Registry; 232 233 //===---------------------------------------------------------------------===// 234 /// 235 /// ISHeuristic command line option for instruction schedulers. 236 /// 237 //===---------------------------------------------------------------------===// 238 static cl::opt<RegisterScheduler::FunctionPassCtor, false, 239 RegisterPassParser<RegisterScheduler> > 240 ISHeuristic("pre-RA-sched", 241 cl::init(&createDefaultScheduler), cl::Hidden, 242 cl::desc("Instruction schedulers available (before register" 243 " allocation):")); 244 245 static RegisterScheduler 246 defaultListDAGScheduler("default", "Best scheduler for the target", 247 createDefaultScheduler); 248 249 namespace llvm { 250 //===--------------------------------------------------------------------===// 251 /// \brief This class is used by SelectionDAGISel to temporarily override 252 /// the optimization level on a per-function basis. 253 class OptLevelChanger { 254 SelectionDAGISel &IS; 255 CodeGenOpt::Level SavedOptLevel; 256 bool SavedFastISel; 257 258 public: 259 OptLevelChanger(SelectionDAGISel &ISel, 260 CodeGenOpt::Level NewOptLevel) : IS(ISel) { 261 SavedOptLevel = IS.OptLevel; 262 if (NewOptLevel == SavedOptLevel) 263 return; 264 IS.OptLevel = NewOptLevel; 265 IS.TM.setOptLevel(NewOptLevel); 266 SavedFastISel = IS.TM.Options.EnableFastISel; 267 if (NewOptLevel == CodeGenOpt::None) 268 IS.TM.setFastISel(true); 269 DEBUG(dbgs() << "\nChanging optimization level for Function " 270 << IS.MF->getFunction()->getName() << "\n"); 271 DEBUG(dbgs() << "\tBefore: -O" << SavedOptLevel 272 << " ; After: -O" << NewOptLevel << "\n"); 273 } 274 275 ~OptLevelChanger() { 276 if (IS.OptLevel == SavedOptLevel) 277 return; 278 DEBUG(dbgs() << "\nRestoring optimization level for Function " 279 << IS.MF->getFunction()->getName() << "\n"); 280 DEBUG(dbgs() << "\tBefore: -O" << IS.OptLevel 281 << " ; After: -O" << SavedOptLevel << "\n"); 282 IS.OptLevel = SavedOptLevel; 283 IS.TM.setOptLevel(SavedOptLevel); 284 IS.TM.setFastISel(SavedFastISel); 285 } 286 }; 287 288 //===--------------------------------------------------------------------===// 289 /// createDefaultScheduler - This creates an instruction scheduler appropriate 290 /// for the target. 291 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 292 CodeGenOpt::Level OptLevel) { 293 const TargetLowering *TLI = IS->TLI; 294 const TargetSubtargetInfo &ST = IS->MF->getSubtarget(); 295 296 if (OptLevel == CodeGenOpt::None || 297 (ST.enableMachineScheduler() && ST.enableMachineSchedDefaultSched()) || 298 TLI->getSchedulingPreference() == Sched::Source) 299 return createSourceListDAGScheduler(IS, OptLevel); 300 if (TLI->getSchedulingPreference() == Sched::RegPressure) 301 return createBURRListDAGScheduler(IS, OptLevel); 302 if (TLI->getSchedulingPreference() == Sched::Hybrid) 303 return createHybridListDAGScheduler(IS, OptLevel); 304 if (TLI->getSchedulingPreference() == Sched::VLIW) 305 return createVLIWDAGScheduler(IS, OptLevel); 306 assert(TLI->getSchedulingPreference() == Sched::ILP && 307 "Unknown sched type!"); 308 return createILPListDAGScheduler(IS, OptLevel); 309 } 310 } 311 312 // EmitInstrWithCustomInserter - This method should be implemented by targets 313 // that mark instructions with the 'usesCustomInserter' flag. These 314 // instructions are special in various ways, which require special support to 315 // insert. The specified MachineInstr is created but not inserted into any 316 // basic blocks, and this method is called to expand it into a sequence of 317 // instructions, potentially also creating new basic blocks and control flow. 318 // When new basic blocks are inserted and the edges from MBB to its successors 319 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 320 // DenseMap. 321 MachineBasicBlock * 322 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 323 MachineBasicBlock *MBB) const { 324 #ifndef NDEBUG 325 dbgs() << "If a target marks an instruction with " 326 "'usesCustomInserter', it must implement " 327 "TargetLowering::EmitInstrWithCustomInserter!"; 328 #endif 329 llvm_unreachable(nullptr); 330 } 331 332 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 333 SDNode *Node) const { 334 assert(!MI->hasPostISelHook() && 335 "If a target marks an instruction with 'hasPostISelHook', " 336 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 337 } 338 339 //===----------------------------------------------------------------------===// 340 // SelectionDAGISel code 341 //===----------------------------------------------------------------------===// 342 343 SelectionDAGISel::SelectionDAGISel(TargetMachine &tm, 344 CodeGenOpt::Level OL) : 345 MachineFunctionPass(ID), TM(tm), 346 FuncInfo(new FunctionLoweringInfo()), 347 CurDAG(new SelectionDAG(tm, OL)), 348 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 349 GFI(), 350 OptLevel(OL), 351 DAGSize(0) { 352 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 353 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 354 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 355 initializeTargetLibraryInfoWrapperPassPass( 356 *PassRegistry::getPassRegistry()); 357 } 358 359 SelectionDAGISel::~SelectionDAGISel() { 360 delete SDB; 361 delete CurDAG; 362 delete FuncInfo; 363 } 364 365 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 366 AU.addRequired<AliasAnalysis>(); 367 AU.addPreserved<AliasAnalysis>(); 368 AU.addRequired<GCModuleInfo>(); 369 AU.addPreserved<GCModuleInfo>(); 370 AU.addRequired<TargetLibraryInfoWrapperPass>(); 371 if (UseMBPI && OptLevel != CodeGenOpt::None) 372 AU.addRequired<BranchProbabilityInfo>(); 373 MachineFunctionPass::getAnalysisUsage(AU); 374 } 375 376 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 377 /// may trap on it. In this case we have to split the edge so that the path 378 /// through the predecessor block that doesn't go to the phi block doesn't 379 /// execute the possibly trapping instruction. 380 /// 381 /// This is required for correctness, so it must be done at -O0. 382 /// 383 static void SplitCriticalSideEffectEdges(Function &Fn, AliasAnalysis *AA) { 384 // Loop for blocks with phi nodes. 385 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 386 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 387 if (!PN) continue; 388 389 ReprocessBlock: 390 // For each block with a PHI node, check to see if any of the input values 391 // are potentially trapping constant expressions. Constant expressions are 392 // the only potentially trapping value that can occur as the argument to a 393 // PHI. 394 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 395 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 396 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 397 if (!CE || !CE->canTrap()) continue; 398 399 // The only case we have to worry about is when the edge is critical. 400 // Since this block has a PHI Node, we assume it has multiple input 401 // edges: check to see if the pred has multiple successors. 402 BasicBlock *Pred = PN->getIncomingBlock(i); 403 if (Pred->getTerminator()->getNumSuccessors() == 1) 404 continue; 405 406 // Okay, we have to split this edge. 407 SplitCriticalEdge( 408 Pred->getTerminator(), GetSuccessorNumber(Pred, BB), 409 CriticalEdgeSplittingOptions(AA).setMergeIdenticalEdges()); 410 goto ReprocessBlock; 411 } 412 } 413 } 414 415 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 416 // Do some sanity-checking on the command-line options. 417 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 418 "-fast-isel-verbose requires -fast-isel"); 419 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 420 "-fast-isel-abort > 0 requires -fast-isel"); 421 422 const Function &Fn = *mf.getFunction(); 423 MF = &mf; 424 425 // Reset the target options before resetting the optimization 426 // level below. 427 // FIXME: This is a horrible hack and should be processed via 428 // codegen looking at the optimization level explicitly when 429 // it wants to look at it. 430 TM.resetTargetOptions(Fn); 431 // Reset OptLevel to None for optnone functions. 432 CodeGenOpt::Level NewOptLevel = OptLevel; 433 if (Fn.hasFnAttribute(Attribute::OptimizeNone)) 434 NewOptLevel = CodeGenOpt::None; 435 OptLevelChanger OLC(*this, NewOptLevel); 436 437 TII = MF->getSubtarget().getInstrInfo(); 438 TLI = MF->getSubtarget().getTargetLowering(); 439 RegInfo = &MF->getRegInfo(); 440 AA = &getAnalysis<AliasAnalysis>(); 441 LibInfo = &getAnalysis<TargetLibraryInfoWrapperPass>().getTLI(); 442 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : nullptr; 443 444 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 445 446 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), AA); 447 448 CurDAG->init(*MF); 449 FuncInfo->set(Fn, *MF, CurDAG); 450 451 if (UseMBPI && OptLevel != CodeGenOpt::None) 452 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 453 else 454 FuncInfo->BPI = nullptr; 455 456 SDB->init(GFI, *AA, LibInfo); 457 458 MF->setHasInlineAsm(false); 459 460 SelectAllBasicBlocks(Fn); 461 462 // If the first basic block in the function has live ins that need to be 463 // copied into vregs, emit the copies into the top of the block before 464 // emitting the code for the block. 465 MachineBasicBlock *EntryMBB = MF->begin(); 466 const TargetRegisterInfo &TRI = *MF->getSubtarget().getRegisterInfo(); 467 RegInfo->EmitLiveInCopies(EntryMBB, TRI, *TII); 468 469 DenseMap<unsigned, unsigned> LiveInMap; 470 if (!FuncInfo->ArgDbgValues.empty()) 471 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 472 E = RegInfo->livein_end(); LI != E; ++LI) 473 if (LI->second) 474 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 475 476 // Insert DBG_VALUE instructions for function arguments to the entry block. 477 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 478 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 479 bool hasFI = MI->getOperand(0).isFI(); 480 unsigned Reg = 481 hasFI ? TRI.getFrameRegister(*MF) : MI->getOperand(0).getReg(); 482 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 483 EntryMBB->insert(EntryMBB->begin(), MI); 484 else { 485 MachineInstr *Def = RegInfo->getVRegDef(Reg); 486 if (Def) { 487 MachineBasicBlock::iterator InsertPos = Def; 488 // FIXME: VR def may not be in entry block. 489 Def->getParent()->insert(std::next(InsertPos), MI); 490 } else 491 DEBUG(dbgs() << "Dropping debug info for dead vreg" 492 << TargetRegisterInfo::virtReg2Index(Reg) << "\n"); 493 } 494 495 // If Reg is live-in then update debug info to track its copy in a vreg. 496 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 497 if (LDI != LiveInMap.end()) { 498 assert(!hasFI && "There's no handling of frame pointer updating here yet " 499 "- add if needed"); 500 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 501 MachineBasicBlock::iterator InsertPos = Def; 502 const MDNode *Variable = MI->getDebugVariable(); 503 const MDNode *Expr = MI->getDebugExpression(); 504 DebugLoc DL = MI->getDebugLoc(); 505 bool IsIndirect = MI->isIndirectDebugValue(); 506 unsigned Offset = IsIndirect ? MI->getOperand(1).getImm() : 0; 507 assert(cast<MDLocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && 508 "Expected inlined-at fields to agree"); 509 // Def is never a terminator here, so it is ok to increment InsertPos. 510 BuildMI(*EntryMBB, ++InsertPos, DL, TII->get(TargetOpcode::DBG_VALUE), 511 IsIndirect, LDI->second, Offset, Variable, Expr); 512 513 // If this vreg is directly copied into an exported register then 514 // that COPY instructions also need DBG_VALUE, if it is the only 515 // user of LDI->second. 516 MachineInstr *CopyUseMI = nullptr; 517 for (MachineRegisterInfo::use_instr_iterator 518 UI = RegInfo->use_instr_begin(LDI->second), 519 E = RegInfo->use_instr_end(); UI != E; ) { 520 MachineInstr *UseMI = &*(UI++); 521 if (UseMI->isDebugValue()) continue; 522 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 523 CopyUseMI = UseMI; continue; 524 } 525 // Otherwise this is another use or second copy use. 526 CopyUseMI = nullptr; break; 527 } 528 if (CopyUseMI) { 529 // Use MI's debug location, which describes where Variable was 530 // declared, rather than whatever is attached to CopyUseMI. 531 MachineInstr *NewMI = 532 BuildMI(*MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect, 533 CopyUseMI->getOperand(0).getReg(), Offset, Variable, Expr); 534 MachineBasicBlock::iterator Pos = CopyUseMI; 535 EntryMBB->insertAfter(Pos, NewMI); 536 } 537 } 538 } 539 540 // Determine if there are any calls in this machine function. 541 MachineFrameInfo *MFI = MF->getFrameInfo(); 542 for (const auto &MBB : *MF) { 543 if (MFI->hasCalls() && MF->hasInlineAsm()) 544 break; 545 546 for (const auto &MI : MBB) { 547 const MCInstrDesc &MCID = TII->get(MI.getOpcode()); 548 if ((MCID.isCall() && !MCID.isReturn()) || 549 MI.isStackAligningInlineAsm()) { 550 MFI->setHasCalls(true); 551 } 552 if (MI.isInlineAsm()) { 553 MF->setHasInlineAsm(true); 554 } 555 } 556 } 557 558 // Determine if there is a call to setjmp in the machine function. 559 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 560 561 // Replace forward-declared registers with the registers containing 562 // the desired value. 563 MachineRegisterInfo &MRI = MF->getRegInfo(); 564 for (DenseMap<unsigned, unsigned>::iterator 565 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 566 I != E; ++I) { 567 unsigned From = I->first; 568 unsigned To = I->second; 569 // If To is also scheduled to be replaced, find what its ultimate 570 // replacement is. 571 for (;;) { 572 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 573 if (J == E) break; 574 To = J->second; 575 } 576 // Make sure the new register has a sufficiently constrained register class. 577 if (TargetRegisterInfo::isVirtualRegister(From) && 578 TargetRegisterInfo::isVirtualRegister(To)) 579 MRI.constrainRegClass(To, MRI.getRegClass(From)); 580 // Replace it. 581 MRI.replaceRegWith(From, To); 582 } 583 584 // Freeze the set of reserved registers now that MachineFrameInfo has been 585 // set up. All the information required by getReservedRegs() should be 586 // available now. 587 MRI.freezeReservedRegs(*MF); 588 589 // Release function-specific state. SDB and CurDAG are already cleared 590 // at this point. 591 FuncInfo->clear(); 592 593 DEBUG(dbgs() << "*** MachineFunction at end of ISel ***\n"); 594 DEBUG(MF->print(dbgs())); 595 596 return true; 597 } 598 599 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 600 BasicBlock::const_iterator End, 601 bool &HadTailCall) { 602 // Lower the instructions. If a call is emitted as a tail call, cease emitting 603 // nodes for this block. 604 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 605 SDB->visit(*I); 606 607 // Make sure the root of the DAG is up-to-date. 608 CurDAG->setRoot(SDB->getControlRoot()); 609 HadTailCall = SDB->HasTailCall; 610 SDB->clear(); 611 612 // Final step, emit the lowered DAG as machine code. 613 CodeGenAndEmitDAG(); 614 } 615 616 void SelectionDAGISel::ComputeLiveOutVRegInfo() { 617 SmallPtrSet<SDNode*, 128> VisitedNodes; 618 SmallVector<SDNode*, 128> Worklist; 619 620 Worklist.push_back(CurDAG->getRoot().getNode()); 621 622 APInt KnownZero; 623 APInt KnownOne; 624 625 do { 626 SDNode *N = Worklist.pop_back_val(); 627 628 // If we've already seen this node, ignore it. 629 if (!VisitedNodes.insert(N).second) 630 continue; 631 632 // Otherwise, add all chain operands to the worklist. 633 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 634 if (N->getOperand(i).getValueType() == MVT::Other) 635 Worklist.push_back(N->getOperand(i).getNode()); 636 637 // If this is a CopyToReg with a vreg dest, process it. 638 if (N->getOpcode() != ISD::CopyToReg) 639 continue; 640 641 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 642 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 643 continue; 644 645 // Ignore non-scalar or non-integer values. 646 SDValue Src = N->getOperand(2); 647 EVT SrcVT = Src.getValueType(); 648 if (!SrcVT.isInteger() || SrcVT.isVector()) 649 continue; 650 651 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 652 CurDAG->computeKnownBits(Src, KnownZero, KnownOne); 653 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 654 } while (!Worklist.empty()); 655 } 656 657 void SelectionDAGISel::CodeGenAndEmitDAG() { 658 std::string GroupName; 659 if (TimePassesIsEnabled) 660 GroupName = "Instruction Selection and Scheduling"; 661 std::string BlockName; 662 int BlockNumber = -1; 663 (void)BlockNumber; 664 bool MatchFilterBB = false; (void)MatchFilterBB; 665 #ifndef NDEBUG 666 MatchFilterBB = (FilterDAGBasicBlockName.empty() || 667 FilterDAGBasicBlockName == 668 FuncInfo->MBB->getBasicBlock()->getName().str()); 669 #endif 670 #ifdef NDEBUG 671 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 672 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 673 ViewSUnitDAGs) 674 #endif 675 { 676 BlockNumber = FuncInfo->MBB->getNumber(); 677 BlockName = 678 (MF->getName() + ":" + FuncInfo->MBB->getBasicBlock()->getName()).str(); 679 } 680 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 681 << " '" << BlockName << "'\n"; CurDAG->dump()); 682 683 if (ViewDAGCombine1 && MatchFilterBB) 684 CurDAG->viewGraph("dag-combine1 input for " + BlockName); 685 686 // Run the DAG combiner in pre-legalize mode. 687 { 688 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 689 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 690 } 691 692 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 693 << " '" << BlockName << "'\n"; CurDAG->dump()); 694 695 // Second step, hack on the DAG until it only uses operations and types that 696 // the target supports. 697 if (ViewLegalizeTypesDAGs && MatchFilterBB) 698 CurDAG->viewGraph("legalize-types input for " + BlockName); 699 700 bool Changed; 701 { 702 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 703 Changed = CurDAG->LegalizeTypes(); 704 } 705 706 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 707 << " '" << BlockName << "'\n"; CurDAG->dump()); 708 709 CurDAG->NewNodesMustHaveLegalTypes = true; 710 711 if (Changed) { 712 if (ViewDAGCombineLT && MatchFilterBB) 713 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 714 715 // Run the DAG combiner in post-type-legalize mode. 716 { 717 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 718 TimePassesIsEnabled); 719 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 720 } 721 722 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 723 << " '" << BlockName << "'\n"; CurDAG->dump()); 724 725 } 726 727 { 728 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 729 Changed = CurDAG->LegalizeVectors(); 730 } 731 732 if (Changed) { 733 { 734 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 735 CurDAG->LegalizeTypes(); 736 } 737 738 if (ViewDAGCombineLT && MatchFilterBB) 739 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 740 741 // Run the DAG combiner in post-type-legalize mode. 742 { 743 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 744 TimePassesIsEnabled); 745 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 746 } 747 748 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 749 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 750 } 751 752 if (ViewLegalizeDAGs && MatchFilterBB) 753 CurDAG->viewGraph("legalize input for " + BlockName); 754 755 { 756 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 757 CurDAG->Legalize(); 758 } 759 760 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 761 << " '" << BlockName << "'\n"; CurDAG->dump()); 762 763 if (ViewDAGCombine2 && MatchFilterBB) 764 CurDAG->viewGraph("dag-combine2 input for " + BlockName); 765 766 // Run the DAG combiner in post-legalize mode. 767 { 768 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 769 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 770 } 771 772 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 773 << " '" << BlockName << "'\n"; CurDAG->dump()); 774 775 if (OptLevel != CodeGenOpt::None) 776 ComputeLiveOutVRegInfo(); 777 778 if (ViewISelDAGs && MatchFilterBB) 779 CurDAG->viewGraph("isel input for " + BlockName); 780 781 // Third, instruction select all of the operations to machine code, adding the 782 // code to the MachineBasicBlock. 783 { 784 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 785 DoInstructionSelection(); 786 } 787 788 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 789 << " '" << BlockName << "'\n"; CurDAG->dump()); 790 791 if (ViewSchedDAGs && MatchFilterBB) 792 CurDAG->viewGraph("scheduler input for " + BlockName); 793 794 // Schedule machine code. 795 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 796 { 797 NamedRegionTimer T("Instruction Scheduling", GroupName, 798 TimePassesIsEnabled); 799 Scheduler->Run(CurDAG, FuncInfo->MBB); 800 } 801 802 if (ViewSUnitDAGs && MatchFilterBB) Scheduler->viewGraph(); 803 804 // Emit machine code to BB. This can change 'BB' to the last block being 805 // inserted into. 806 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 807 { 808 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 809 810 // FuncInfo->InsertPt is passed by reference and set to the end of the 811 // scheduled instructions. 812 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 813 } 814 815 // If the block was split, make sure we update any references that are used to 816 // update PHI nodes later on. 817 if (FirstMBB != LastMBB) 818 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 819 820 // Free the scheduler state. 821 { 822 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 823 TimePassesIsEnabled); 824 delete Scheduler; 825 } 826 827 // Free the SelectionDAG state, now that we're finished with it. 828 CurDAG->clear(); 829 } 830 831 namespace { 832 /// ISelUpdater - helper class to handle updates of the instruction selection 833 /// graph. 834 class ISelUpdater : public SelectionDAG::DAGUpdateListener { 835 SelectionDAG::allnodes_iterator &ISelPosition; 836 public: 837 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 838 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 839 840 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 841 /// deleted is the current ISelPosition node, update ISelPosition. 842 /// 843 void NodeDeleted(SDNode *N, SDNode *E) override { 844 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 845 ++ISelPosition; 846 } 847 }; 848 } // end anonymous namespace 849 850 void SelectionDAGISel::DoInstructionSelection() { 851 DEBUG(dbgs() << "===== Instruction selection begins: BB#" 852 << FuncInfo->MBB->getNumber() 853 << " '" << FuncInfo->MBB->getName() << "'\n"); 854 855 PreprocessISelDAG(); 856 857 // Select target instructions for the DAG. 858 { 859 // Number all nodes with a topological order and set DAGSize. 860 DAGSize = CurDAG->AssignTopologicalOrder(); 861 862 // Create a dummy node (which is not added to allnodes), that adds 863 // a reference to the root node, preventing it from being deleted, 864 // and tracking any changes of the root. 865 HandleSDNode Dummy(CurDAG->getRoot()); 866 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 867 ++ISelPosition; 868 869 // Make sure that ISelPosition gets properly updated when nodes are deleted 870 // in calls made from this function. 871 ISelUpdater ISU(*CurDAG, ISelPosition); 872 873 // The AllNodes list is now topological-sorted. Visit the 874 // nodes by starting at the end of the list (the root of the 875 // graph) and preceding back toward the beginning (the entry 876 // node). 877 while (ISelPosition != CurDAG->allnodes_begin()) { 878 SDNode *Node = --ISelPosition; 879 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 880 // but there are currently some corner cases that it misses. Also, this 881 // makes it theoretically possible to disable the DAGCombiner. 882 if (Node->use_empty()) 883 continue; 884 885 SDNode *ResNode = Select(Node); 886 887 // FIXME: This is pretty gross. 'Select' should be changed to not return 888 // anything at all and this code should be nuked with a tactical strike. 889 890 // If node should not be replaced, continue with the next one. 891 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 892 continue; 893 // Replace node. 894 if (ResNode) { 895 ReplaceUses(Node, ResNode); 896 } 897 898 // If after the replacement this node is not used any more, 899 // remove this dead node. 900 if (Node->use_empty()) // Don't delete EntryToken, etc. 901 CurDAG->RemoveDeadNode(Node); 902 } 903 904 CurDAG->setRoot(Dummy.getValue()); 905 } 906 907 DEBUG(dbgs() << "===== Instruction selection ends:\n"); 908 909 PostprocessISelDAG(); 910 } 911 912 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 913 /// do other setup for EH landing-pad blocks. 914 void SelectionDAGISel::PrepareEHLandingPad() { 915 MachineBasicBlock *MBB = FuncInfo->MBB; 916 917 const TargetRegisterClass *PtrRC = TLI->getRegClassFor(TLI->getPointerTy()); 918 919 // Add a label to mark the beginning of the landing pad. Deletion of the 920 // landing pad can thus be detected via the MachineModuleInfo. 921 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 922 923 // Assign the call site to the landing pad's begin label. 924 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 925 926 const MCInstrDesc &II = TII->get(TargetOpcode::EH_LABEL); 927 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 928 .addSym(Label); 929 930 // If this is an MSVC-style personality function, we need to split the landing 931 // pad into several BBs. 932 const BasicBlock *LLVMBB = MBB->getBasicBlock(); 933 const LandingPadInst *LPadInst = LLVMBB->getLandingPadInst(); 934 MF->getMMI().addPersonality( 935 MBB, cast<Function>(LPadInst->getPersonalityFn()->stripPointerCasts())); 936 EHPersonality Personality = MF->getMMI().getPersonalityType(); 937 938 if (isMSVCEHPersonality(Personality)) { 939 SmallVector<MachineBasicBlock *, 4> ClauseBBs; 940 const IntrinsicInst *Actions = 941 dyn_cast<IntrinsicInst>(LLVMBB->getFirstInsertionPt()); 942 // Get all invoke BBs that unwind to this landingpad. 943 SmallVector<MachineBasicBlock *, 4> InvokeBBs(MBB->pred_begin(), 944 MBB->pred_end()); 945 if (Actions && Actions->getIntrinsicID() == Intrinsic::eh_actions) { 946 // If this is a call to llvm.eh.actions followed by indirectbr, then we've 947 // run WinEHPrepare, and we should remove this block from the machine CFG. 948 // Mark the targets of the indirectbr as landingpads instead. 949 for (const BasicBlock *LLVMSucc : successors(LLVMBB)) { 950 MachineBasicBlock *ClauseBB = FuncInfo->MBBMap[LLVMSucc]; 951 // Add the edge from the invoke to the clause. 952 for (MachineBasicBlock *InvokeBB : InvokeBBs) 953 InvokeBB->addSuccessor(ClauseBB); 954 } 955 } else { 956 // Otherwise, we haven't done the preparation, and we need to invent some 957 // clause basic blocks that branch into the landingpad. 958 // FIXME: Remove this code once SEH preparation works. 959 960 // Make virtual registers and a series of labels that fill in values for 961 // the clauses. 962 auto &RI = MF->getRegInfo(); 963 FuncInfo->ExceptionSelectorVirtReg = RI.createVirtualRegister(PtrRC); 964 965 // Emit separate machine basic blocks with separate labels for each clause 966 // before the main landing pad block. 967 MachineInstrBuilder SelectorPHI = BuildMI( 968 *MBB, MBB->begin(), SDB->getCurDebugLoc(), 969 TII->get(TargetOpcode::PHI), FuncInfo->ExceptionSelectorVirtReg); 970 for (unsigned I = 0, E = LPadInst->getNumClauses(); I != E; ++I) { 971 // Skip filter clauses, we can't implement them. 972 if (LPadInst->isFilter(I)) 973 continue; 974 975 MachineBasicBlock *ClauseBB = MF->CreateMachineBasicBlock(LLVMBB); 976 MF->insert(MBB, ClauseBB); 977 978 // Add the edge from the invoke to the clause. 979 for (MachineBasicBlock *InvokeBB : InvokeBBs) 980 InvokeBB->addSuccessor(ClauseBB); 981 982 // Mark the clause as a landing pad or MI passes will delete it. 983 ClauseBB->setIsLandingPad(); 984 985 GlobalValue *ClauseGV = ExtractTypeInfo(LPadInst->getClause(I)); 986 987 // Start the BB with a label. 988 MCSymbol *ClauseLabel = MF->getMMI().addClauseForLandingPad(MBB); 989 BuildMI(*ClauseBB, ClauseBB->begin(), SDB->getCurDebugLoc(), II) 990 .addSym(ClauseLabel); 991 992 // Construct a simple BB that defines a register with the typeid 993 // constant. 994 FuncInfo->MBB = ClauseBB; 995 FuncInfo->InsertPt = ClauseBB->end(); 996 unsigned VReg = SDB->visitLandingPadClauseBB(ClauseGV, MBB); 997 CurDAG->setRoot(SDB->getRoot()); 998 SDB->clear(); 999 CodeGenAndEmitDAG(); 1000 1001 // Add the typeid virtual register to the phi in the main landing pad. 1002 SelectorPHI.addReg(VReg).addMBB(ClauseBB); 1003 } 1004 } 1005 1006 // Remove the edge from the invoke to the lpad. 1007 for (MachineBasicBlock *InvokeBB : InvokeBBs) 1008 InvokeBB->removeSuccessor(MBB); 1009 1010 // Restore FuncInfo back to its previous state and select the main landing 1011 // pad block. 1012 FuncInfo->MBB = MBB; 1013 FuncInfo->InsertPt = MBB->end(); 1014 1015 // Transfer EH state number assigned to the IR block to the MBB. 1016 if (Personality == EHPersonality::MSVC_CXX) { 1017 WinEHFuncInfo &FI = MF->getMMI().getWinEHFuncInfo(MF->getFunction()); 1018 MF->getMMI().addWinEHState(MBB, FI.LandingPadStateMap[LPadInst]); 1019 } 1020 return; 1021 } 1022 1023 // Mark exception register as live in. 1024 if (unsigned Reg = TLI->getExceptionPointerRegister()) 1025 FuncInfo->ExceptionPointerVirtReg = MBB->addLiveIn(Reg, PtrRC); 1026 1027 // Mark exception selector register as live in. 1028 if (unsigned Reg = TLI->getExceptionSelectorRegister()) 1029 FuncInfo->ExceptionSelectorVirtReg = MBB->addLiveIn(Reg, PtrRC); 1030 } 1031 1032 /// isFoldedOrDeadInstruction - Return true if the specified instruction is 1033 /// side-effect free and is either dead or folded into a generated instruction. 1034 /// Return false if it needs to be emitted. 1035 static bool isFoldedOrDeadInstruction(const Instruction *I, 1036 FunctionLoweringInfo *FuncInfo) { 1037 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 1038 !isa<TerminatorInst>(I) && // Terminators aren't folded. 1039 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 1040 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 1041 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 1042 } 1043 1044 #ifndef NDEBUG 1045 // Collect per Instruction statistics for fast-isel misses. Only those 1046 // instructions that cause the bail are accounted for. It does not account for 1047 // instructions higher in the block. Thus, summing the per instructions stats 1048 // will not add up to what is reported by NumFastIselFailures. 1049 static void collectFailStats(const Instruction *I) { 1050 switch (I->getOpcode()) { 1051 default: assert (0 && "<Invalid operator> "); 1052 1053 // Terminators 1054 case Instruction::Ret: NumFastIselFailRet++; return; 1055 case Instruction::Br: NumFastIselFailBr++; return; 1056 case Instruction::Switch: NumFastIselFailSwitch++; return; 1057 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 1058 case Instruction::Invoke: NumFastIselFailInvoke++; return; 1059 case Instruction::Resume: NumFastIselFailResume++; return; 1060 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 1061 1062 // Standard binary operators... 1063 case Instruction::Add: NumFastIselFailAdd++; return; 1064 case Instruction::FAdd: NumFastIselFailFAdd++; return; 1065 case Instruction::Sub: NumFastIselFailSub++; return; 1066 case Instruction::FSub: NumFastIselFailFSub++; return; 1067 case Instruction::Mul: NumFastIselFailMul++; return; 1068 case Instruction::FMul: NumFastIselFailFMul++; return; 1069 case Instruction::UDiv: NumFastIselFailUDiv++; return; 1070 case Instruction::SDiv: NumFastIselFailSDiv++; return; 1071 case Instruction::FDiv: NumFastIselFailFDiv++; return; 1072 case Instruction::URem: NumFastIselFailURem++; return; 1073 case Instruction::SRem: NumFastIselFailSRem++; return; 1074 case Instruction::FRem: NumFastIselFailFRem++; return; 1075 1076 // Logical operators... 1077 case Instruction::And: NumFastIselFailAnd++; return; 1078 case Instruction::Or: NumFastIselFailOr++; return; 1079 case Instruction::Xor: NumFastIselFailXor++; return; 1080 1081 // Memory instructions... 1082 case Instruction::Alloca: NumFastIselFailAlloca++; return; 1083 case Instruction::Load: NumFastIselFailLoad++; return; 1084 case Instruction::Store: NumFastIselFailStore++; return; 1085 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 1086 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 1087 case Instruction::Fence: NumFastIselFailFence++; return; 1088 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 1089 1090 // Convert instructions... 1091 case Instruction::Trunc: NumFastIselFailTrunc++; return; 1092 case Instruction::ZExt: NumFastIselFailZExt++; return; 1093 case Instruction::SExt: NumFastIselFailSExt++; return; 1094 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 1095 case Instruction::FPExt: NumFastIselFailFPExt++; return; 1096 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 1097 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 1098 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 1099 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 1100 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 1101 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 1102 case Instruction::BitCast: NumFastIselFailBitCast++; return; 1103 1104 // Other instructions... 1105 case Instruction::ICmp: NumFastIselFailICmp++; return; 1106 case Instruction::FCmp: NumFastIselFailFCmp++; return; 1107 case Instruction::PHI: NumFastIselFailPHI++; return; 1108 case Instruction::Select: NumFastIselFailSelect++; return; 1109 case Instruction::Call: { 1110 if (auto const *Intrinsic = dyn_cast<IntrinsicInst>(I)) { 1111 switch (Intrinsic->getIntrinsicID()) { 1112 default: 1113 NumFastIselFailIntrinsicCall++; return; 1114 case Intrinsic::sadd_with_overflow: 1115 NumFastIselFailSAddWithOverflow++; return; 1116 case Intrinsic::uadd_with_overflow: 1117 NumFastIselFailUAddWithOverflow++; return; 1118 case Intrinsic::ssub_with_overflow: 1119 NumFastIselFailSSubWithOverflow++; return; 1120 case Intrinsic::usub_with_overflow: 1121 NumFastIselFailUSubWithOverflow++; return; 1122 case Intrinsic::smul_with_overflow: 1123 NumFastIselFailSMulWithOverflow++; return; 1124 case Intrinsic::umul_with_overflow: 1125 NumFastIselFailUMulWithOverflow++; return; 1126 case Intrinsic::frameaddress: 1127 NumFastIselFailFrameaddress++; return; 1128 case Intrinsic::sqrt: 1129 NumFastIselFailSqrt++; return; 1130 case Intrinsic::experimental_stackmap: 1131 NumFastIselFailStackMap++; return; 1132 case Intrinsic::experimental_patchpoint_void: // fall-through 1133 case Intrinsic::experimental_patchpoint_i64: 1134 NumFastIselFailPatchPoint++; return; 1135 } 1136 } 1137 NumFastIselFailCall++; 1138 return; 1139 } 1140 case Instruction::Shl: NumFastIselFailShl++; return; 1141 case Instruction::LShr: NumFastIselFailLShr++; return; 1142 case Instruction::AShr: NumFastIselFailAShr++; return; 1143 case Instruction::VAArg: NumFastIselFailVAArg++; return; 1144 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 1145 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 1146 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 1147 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 1148 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 1149 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 1150 } 1151 } 1152 #endif 1153 1154 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 1155 // Initialize the Fast-ISel state, if needed. 1156 FastISel *FastIS = nullptr; 1157 if (TM.Options.EnableFastISel) 1158 FastIS = TLI->createFastISel(*FuncInfo, LibInfo); 1159 1160 // Iterate over all basic blocks in the function. 1161 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 1162 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 1163 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 1164 const BasicBlock *LLVMBB = *I; 1165 1166 if (OptLevel != CodeGenOpt::None) { 1167 bool AllPredsVisited = true; 1168 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 1169 PI != PE; ++PI) { 1170 if (!FuncInfo->VisitedBBs.count(*PI)) { 1171 AllPredsVisited = false; 1172 break; 1173 } 1174 } 1175 1176 if (AllPredsVisited) { 1177 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1178 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1179 FuncInfo->ComputePHILiveOutRegInfo(PN); 1180 } else { 1181 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1182 const PHINode *PN = dyn_cast<PHINode>(I); ++I) 1183 FuncInfo->InvalidatePHILiveOutRegInfo(PN); 1184 } 1185 1186 FuncInfo->VisitedBBs.insert(LLVMBB); 1187 } 1188 1189 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1190 BasicBlock::const_iterator const End = LLVMBB->end(); 1191 BasicBlock::const_iterator BI = End; 1192 1193 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1194 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1195 1196 // Setup an EH landing-pad block. 1197 FuncInfo->ExceptionPointerVirtReg = 0; 1198 FuncInfo->ExceptionSelectorVirtReg = 0; 1199 if (LLVMBB->isLandingPad()) 1200 PrepareEHLandingPad(); 1201 1202 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1203 if (FastIS) { 1204 FastIS->startNewBlock(); 1205 1206 // Emit code for any incoming arguments. This must happen before 1207 // beginning FastISel on the entry block. 1208 if (LLVMBB == &Fn.getEntryBlock()) { 1209 ++NumEntryBlocks; 1210 1211 // Lower any arguments needed in this block if this is the entry block. 1212 if (!FastIS->lowerArguments()) { 1213 // Fast isel failed to lower these arguments 1214 ++NumFastIselFailLowerArguments; 1215 if (EnableFastISelAbort > 1) 1216 report_fatal_error("FastISel didn't lower all arguments"); 1217 1218 // Use SelectionDAG argument lowering 1219 LowerArguments(Fn); 1220 CurDAG->setRoot(SDB->getControlRoot()); 1221 SDB->clear(); 1222 CodeGenAndEmitDAG(); 1223 } 1224 1225 // If we inserted any instructions at the beginning, make a note of 1226 // where they are, so we can be sure to emit subsequent instructions 1227 // after them. 1228 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1229 FastIS->setLastLocalValue(std::prev(FuncInfo->InsertPt)); 1230 else 1231 FastIS->setLastLocalValue(nullptr); 1232 } 1233 1234 unsigned NumFastIselRemaining = std::distance(Begin, End); 1235 // Do FastISel on as many instructions as possible. 1236 for (; BI != Begin; --BI) { 1237 const Instruction *Inst = std::prev(BI); 1238 1239 // If we no longer require this instruction, skip it. 1240 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1241 --NumFastIselRemaining; 1242 continue; 1243 } 1244 1245 // Bottom-up: reset the insert pos at the top, after any local-value 1246 // instructions. 1247 FastIS->recomputeInsertPt(); 1248 1249 // Try to select the instruction with FastISel. 1250 if (FastIS->selectInstruction(Inst)) { 1251 --NumFastIselRemaining; 1252 ++NumFastIselSuccess; 1253 // If fast isel succeeded, skip over all the folded instructions, and 1254 // then see if there is a load right before the selected instructions. 1255 // Try to fold the load if so. 1256 const Instruction *BeforeInst = Inst; 1257 while (BeforeInst != Begin) { 1258 BeforeInst = std::prev(BasicBlock::const_iterator(BeforeInst)); 1259 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1260 break; 1261 } 1262 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1263 BeforeInst->hasOneUse() && 1264 FastIS->tryToFoldLoad(cast<LoadInst>(BeforeInst), Inst)) { 1265 // If we succeeded, don't re-select the load. 1266 BI = std::next(BasicBlock::const_iterator(BeforeInst)); 1267 --NumFastIselRemaining; 1268 ++NumFastIselSuccess; 1269 } 1270 continue; 1271 } 1272 1273 #ifndef NDEBUG 1274 if (EnableFastISelVerbose2) 1275 collectFailStats(Inst); 1276 #endif 1277 1278 // Then handle certain instructions as single-LLVM-Instruction blocks. 1279 if (isa<CallInst>(Inst)) { 1280 1281 if (EnableFastISelVerbose || EnableFastISelAbort) { 1282 dbgs() << "FastISel missed call: "; 1283 Inst->dump(); 1284 } 1285 if (EnableFastISelAbort > 2) 1286 // FastISel selector couldn't handle something and bailed. 1287 // For the purpose of debugging, just abort. 1288 report_fatal_error("FastISel didn't select the entire block"); 1289 1290 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1291 unsigned &R = FuncInfo->ValueMap[Inst]; 1292 if (!R) 1293 R = FuncInfo->CreateRegs(Inst->getType()); 1294 } 1295 1296 bool HadTailCall = false; 1297 MachineBasicBlock::iterator SavedInsertPt = FuncInfo->InsertPt; 1298 SelectBasicBlock(Inst, BI, HadTailCall); 1299 1300 // If the call was emitted as a tail call, we're done with the block. 1301 // We also need to delete any previously emitted instructions. 1302 if (HadTailCall) { 1303 FastIS->removeDeadCode(SavedInsertPt, FuncInfo->MBB->end()); 1304 --BI; 1305 break; 1306 } 1307 1308 // Recompute NumFastIselRemaining as Selection DAG instruction 1309 // selection may have handled the call, input args, etc. 1310 unsigned RemainingNow = std::distance(Begin, BI); 1311 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1312 NumFastIselRemaining = RemainingNow; 1313 continue; 1314 } 1315 1316 bool ShouldAbort = EnableFastISelAbort; 1317 if (EnableFastISelVerbose || EnableFastISelAbort) { 1318 if (isa<TerminatorInst>(Inst)) { 1319 // Use a different message for terminator misses. 1320 dbgs() << "FastISel missed terminator: "; 1321 // Don't abort unless for terminator unless the level is really high 1322 ShouldAbort = (EnableFastISelAbort > 2); 1323 } else { 1324 dbgs() << "FastISel miss: "; 1325 } 1326 Inst->dump(); 1327 } 1328 if (ShouldAbort) 1329 // FastISel selector couldn't handle something and bailed. 1330 // For the purpose of debugging, just abort. 1331 report_fatal_error("FastISel didn't select the entire block"); 1332 1333 NumFastIselFailures += NumFastIselRemaining; 1334 break; 1335 } 1336 1337 FastIS->recomputeInsertPt(); 1338 } else { 1339 // Lower any arguments needed in this block if this is the entry block. 1340 if (LLVMBB == &Fn.getEntryBlock()) { 1341 ++NumEntryBlocks; 1342 LowerArguments(Fn); 1343 } 1344 } 1345 1346 if (Begin != BI) 1347 ++NumDAGBlocks; 1348 else 1349 ++NumFastIselBlocks; 1350 1351 if (Begin != BI) { 1352 // Run SelectionDAG instruction selection on the remainder of the block 1353 // not handled by FastISel. If FastISel is not run, this is the entire 1354 // block. 1355 bool HadTailCall; 1356 SelectBasicBlock(Begin, BI, HadTailCall); 1357 } 1358 1359 FinishBasicBlock(); 1360 FuncInfo->PHINodesToUpdate.clear(); 1361 } 1362 1363 delete FastIS; 1364 SDB->clearDanglingDebugInfo(); 1365 SDB->SPDescriptor.resetPerFunctionState(); 1366 } 1367 1368 /// Given that the input MI is before a partial terminator sequence TSeq, return 1369 /// true if M + TSeq also a partial terminator sequence. 1370 /// 1371 /// A Terminator sequence is a sequence of MachineInstrs which at this point in 1372 /// lowering copy vregs into physical registers, which are then passed into 1373 /// terminator instructors so we can satisfy ABI constraints. A partial 1374 /// terminator sequence is an improper subset of a terminator sequence (i.e. it 1375 /// may be the whole terminator sequence). 1376 static bool MIIsInTerminatorSequence(const MachineInstr *MI) { 1377 // If we do not have a copy or an implicit def, we return true if and only if 1378 // MI is a debug value. 1379 if (!MI->isCopy() && !MI->isImplicitDef()) 1380 // Sometimes DBG_VALUE MI sneak in between the copies from the vregs to the 1381 // physical registers if there is debug info associated with the terminator 1382 // of our mbb. We want to include said debug info in our terminator 1383 // sequence, so we return true in that case. 1384 return MI->isDebugValue(); 1385 1386 // We have left the terminator sequence if we are not doing one of the 1387 // following: 1388 // 1389 // 1. Copying a vreg into a physical register. 1390 // 2. Copying a vreg into a vreg. 1391 // 3. Defining a register via an implicit def. 1392 1393 // OPI should always be a register definition... 1394 MachineInstr::const_mop_iterator OPI = MI->operands_begin(); 1395 if (!OPI->isReg() || !OPI->isDef()) 1396 return false; 1397 1398 // Defining any register via an implicit def is always ok. 1399 if (MI->isImplicitDef()) 1400 return true; 1401 1402 // Grab the copy source... 1403 MachineInstr::const_mop_iterator OPI2 = OPI; 1404 ++OPI2; 1405 assert(OPI2 != MI->operands_end() 1406 && "Should have a copy implying we should have 2 arguments."); 1407 1408 // Make sure that the copy dest is not a vreg when the copy source is a 1409 // physical register. 1410 if (!OPI2->isReg() || 1411 (!TargetRegisterInfo::isPhysicalRegister(OPI->getReg()) && 1412 TargetRegisterInfo::isPhysicalRegister(OPI2->getReg()))) 1413 return false; 1414 1415 return true; 1416 } 1417 1418 /// Find the split point at which to splice the end of BB into its success stack 1419 /// protector check machine basic block. 1420 /// 1421 /// On many platforms, due to ABI constraints, terminators, even before register 1422 /// allocation, use physical registers. This creates an issue for us since 1423 /// physical registers at this point can not travel across basic 1424 /// blocks. Luckily, selectiondag always moves physical registers into vregs 1425 /// when they enter functions and moves them through a sequence of copies back 1426 /// into the physical registers right before the terminator creating a 1427 /// ``Terminator Sequence''. This function is searching for the beginning of the 1428 /// terminator sequence so that we can ensure that we splice off not just the 1429 /// terminator, but additionally the copies that move the vregs into the 1430 /// physical registers. 1431 static MachineBasicBlock::iterator 1432 FindSplitPointForStackProtector(MachineBasicBlock *BB, DebugLoc DL) { 1433 MachineBasicBlock::iterator SplitPoint = BB->getFirstTerminator(); 1434 // 1435 if (SplitPoint == BB->begin()) 1436 return SplitPoint; 1437 1438 MachineBasicBlock::iterator Start = BB->begin(); 1439 MachineBasicBlock::iterator Previous = SplitPoint; 1440 --Previous; 1441 1442 while (MIIsInTerminatorSequence(Previous)) { 1443 SplitPoint = Previous; 1444 if (Previous == Start) 1445 break; 1446 --Previous; 1447 } 1448 1449 return SplitPoint; 1450 } 1451 1452 void 1453 SelectionDAGISel::FinishBasicBlock() { 1454 1455 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1456 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1457 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1458 dbgs() << "Node " << i << " : (" 1459 << FuncInfo->PHINodesToUpdate[i].first 1460 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1461 1462 const bool MustUpdatePHINodes = SDB->SwitchCases.empty() && 1463 SDB->JTCases.empty() && 1464 SDB->BitTestCases.empty(); 1465 1466 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1467 // PHI nodes in successors. 1468 if (MustUpdatePHINodes) { 1469 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1470 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1471 assert(PHI->isPHI() && 1472 "This is not a machine PHI node that we are updating!"); 1473 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1474 continue; 1475 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1476 } 1477 } 1478 1479 // Handle stack protector. 1480 if (SDB->SPDescriptor.shouldEmitStackProtector()) { 1481 MachineBasicBlock *ParentMBB = SDB->SPDescriptor.getParentMBB(); 1482 MachineBasicBlock *SuccessMBB = SDB->SPDescriptor.getSuccessMBB(); 1483 1484 // Find the split point to split the parent mbb. At the same time copy all 1485 // physical registers used in the tail of parent mbb into virtual registers 1486 // before the split point and back into physical registers after the split 1487 // point. This prevents us needing to deal with Live-ins and many other 1488 // register allocation issues caused by us splitting the parent mbb. The 1489 // register allocator will clean up said virtual copies later on. 1490 MachineBasicBlock::iterator SplitPoint = 1491 FindSplitPointForStackProtector(ParentMBB, SDB->getCurDebugLoc()); 1492 1493 // Splice the terminator of ParentMBB into SuccessMBB. 1494 SuccessMBB->splice(SuccessMBB->end(), ParentMBB, 1495 SplitPoint, 1496 ParentMBB->end()); 1497 1498 // Add compare/jump on neq/jump to the parent BB. 1499 FuncInfo->MBB = ParentMBB; 1500 FuncInfo->InsertPt = ParentMBB->end(); 1501 SDB->visitSPDescriptorParent(SDB->SPDescriptor, ParentMBB); 1502 CurDAG->setRoot(SDB->getRoot()); 1503 SDB->clear(); 1504 CodeGenAndEmitDAG(); 1505 1506 // CodeGen Failure MBB if we have not codegened it yet. 1507 MachineBasicBlock *FailureMBB = SDB->SPDescriptor.getFailureMBB(); 1508 if (!FailureMBB->size()) { 1509 FuncInfo->MBB = FailureMBB; 1510 FuncInfo->InsertPt = FailureMBB->end(); 1511 SDB->visitSPDescriptorFailure(SDB->SPDescriptor); 1512 CurDAG->setRoot(SDB->getRoot()); 1513 SDB->clear(); 1514 CodeGenAndEmitDAG(); 1515 } 1516 1517 // Clear the Per-BB State. 1518 SDB->SPDescriptor.resetPerBBState(); 1519 } 1520 1521 // If we updated PHI Nodes, return early. 1522 if (MustUpdatePHINodes) 1523 return; 1524 1525 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1526 // Lower header first, if it wasn't already lowered 1527 if (!SDB->BitTestCases[i].Emitted) { 1528 // Set the current basic block to the mbb we wish to insert the code into 1529 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1530 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1531 // Emit the code 1532 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1533 CurDAG->setRoot(SDB->getRoot()); 1534 SDB->clear(); 1535 CodeGenAndEmitDAG(); 1536 } 1537 1538 uint32_t UnhandledWeight = 0; 1539 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1540 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1541 1542 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1543 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1544 // Set the current basic block to the mbb we wish to insert the code into 1545 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1546 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1547 // Emit the code 1548 if (j+1 != ej) 1549 SDB->visitBitTestCase(SDB->BitTestCases[i], 1550 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1551 UnhandledWeight, 1552 SDB->BitTestCases[i].Reg, 1553 SDB->BitTestCases[i].Cases[j], 1554 FuncInfo->MBB); 1555 else 1556 SDB->visitBitTestCase(SDB->BitTestCases[i], 1557 SDB->BitTestCases[i].Default, 1558 UnhandledWeight, 1559 SDB->BitTestCases[i].Reg, 1560 SDB->BitTestCases[i].Cases[j], 1561 FuncInfo->MBB); 1562 1563 1564 CurDAG->setRoot(SDB->getRoot()); 1565 SDB->clear(); 1566 CodeGenAndEmitDAG(); 1567 } 1568 1569 // Update PHI Nodes 1570 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1571 pi != pe; ++pi) { 1572 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1573 MachineBasicBlock *PHIBB = PHI->getParent(); 1574 assert(PHI->isPHI() && 1575 "This is not a machine PHI node that we are updating!"); 1576 // This is "default" BB. We have two jumps to it. From "header" BB and 1577 // from last "case" BB. 1578 if (PHIBB == SDB->BitTestCases[i].Default) 1579 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1580 .addMBB(SDB->BitTestCases[i].Parent) 1581 .addReg(FuncInfo->PHINodesToUpdate[pi].second) 1582 .addMBB(SDB->BitTestCases[i].Cases.back().ThisBB); 1583 // One of "cases" BB. 1584 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1585 j != ej; ++j) { 1586 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1587 if (cBB->isSuccessor(PHIBB)) 1588 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(cBB); 1589 } 1590 } 1591 } 1592 SDB->BitTestCases.clear(); 1593 1594 // If the JumpTable record is filled in, then we need to emit a jump table. 1595 // Updating the PHI nodes is tricky in this case, since we need to determine 1596 // whether the PHI is a successor of the range check MBB or the jump table MBB 1597 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1598 // Lower header first, if it wasn't already lowered 1599 if (!SDB->JTCases[i].first.Emitted) { 1600 // Set the current basic block to the mbb we wish to insert the code into 1601 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1602 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1603 // Emit the code 1604 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1605 FuncInfo->MBB); 1606 CurDAG->setRoot(SDB->getRoot()); 1607 SDB->clear(); 1608 CodeGenAndEmitDAG(); 1609 } 1610 1611 // Set the current basic block to the mbb we wish to insert the code into 1612 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1613 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1614 // Emit the code 1615 SDB->visitJumpTable(SDB->JTCases[i].second); 1616 CurDAG->setRoot(SDB->getRoot()); 1617 SDB->clear(); 1618 CodeGenAndEmitDAG(); 1619 1620 // Update PHI Nodes 1621 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1622 pi != pe; ++pi) { 1623 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[pi].first); 1624 MachineBasicBlock *PHIBB = PHI->getParent(); 1625 assert(PHI->isPHI() && 1626 "This is not a machine PHI node that we are updating!"); 1627 // "default" BB. We can go there only from header BB. 1628 if (PHIBB == SDB->JTCases[i].second.Default) 1629 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second) 1630 .addMBB(SDB->JTCases[i].first.HeaderBB); 1631 // JT BB. Just iterate over successors here 1632 if (FuncInfo->MBB->isSuccessor(PHIBB)) 1633 PHI.addReg(FuncInfo->PHINodesToUpdate[pi].second).addMBB(FuncInfo->MBB); 1634 } 1635 } 1636 SDB->JTCases.clear(); 1637 1638 // If the switch block involved a branch to one of the actual successors, we 1639 // need to update PHI nodes in that block. 1640 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1641 MachineInstrBuilder PHI(*MF, FuncInfo->PHINodesToUpdate[i].first); 1642 assert(PHI->isPHI() && 1643 "This is not a machine PHI node that we are updating!"); 1644 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) 1645 PHI.addReg(FuncInfo->PHINodesToUpdate[i].second).addMBB(FuncInfo->MBB); 1646 } 1647 1648 // If we generated any switch lowering information, build and codegen any 1649 // additional DAGs necessary. 1650 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1651 // Set the current basic block to the mbb we wish to insert the code into 1652 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1653 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1654 1655 // Determine the unique successors. 1656 SmallVector<MachineBasicBlock *, 2> Succs; 1657 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1658 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1659 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1660 1661 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1662 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1663 CurDAG->setRoot(SDB->getRoot()); 1664 SDB->clear(); 1665 CodeGenAndEmitDAG(); 1666 1667 // Remember the last block, now that any splitting is done, for use in 1668 // populating PHI nodes in successors. 1669 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1670 1671 // Handle any PHI nodes in successors of this chunk, as if we were coming 1672 // from the original BB before switch expansion. Note that PHI nodes can 1673 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1674 // handle them the right number of times. 1675 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1676 FuncInfo->MBB = Succs[i]; 1677 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1678 // FuncInfo->MBB may have been removed from the CFG if a branch was 1679 // constant folded. 1680 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1681 for (MachineBasicBlock::iterator 1682 MBBI = FuncInfo->MBB->begin(), MBBE = FuncInfo->MBB->end(); 1683 MBBI != MBBE && MBBI->isPHI(); ++MBBI) { 1684 MachineInstrBuilder PHI(*MF, MBBI); 1685 // This value for this PHI node is recorded in PHINodesToUpdate. 1686 for (unsigned pn = 0; ; ++pn) { 1687 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1688 "Didn't find PHI entry!"); 1689 if (FuncInfo->PHINodesToUpdate[pn].first == PHI) { 1690 PHI.addReg(FuncInfo->PHINodesToUpdate[pn].second).addMBB(ThisBB); 1691 break; 1692 } 1693 } 1694 } 1695 } 1696 } 1697 } 1698 SDB->SwitchCases.clear(); 1699 } 1700 1701 1702 /// Create the scheduler. If a specific scheduler was specified 1703 /// via the SchedulerRegistry, use it, otherwise select the 1704 /// one preferred by the target. 1705 /// 1706 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1707 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1708 1709 if (!Ctor) { 1710 Ctor = ISHeuristic; 1711 RegisterScheduler::setDefault(Ctor); 1712 } 1713 1714 return Ctor(this, OptLevel); 1715 } 1716 1717 //===----------------------------------------------------------------------===// 1718 // Helper functions used by the generated instruction selector. 1719 //===----------------------------------------------------------------------===// 1720 // Calls to these methods are generated by tblgen. 1721 1722 /// CheckAndMask - The isel is trying to match something like (and X, 255). If 1723 /// the dag combiner simplified the 255, we still want to match. RHS is the 1724 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1725 /// specified in the .td file (e.g. 255). 1726 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1727 int64_t DesiredMaskS) const { 1728 const APInt &ActualMask = RHS->getAPIntValue(); 1729 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1730 1731 // If the actual mask exactly matches, success! 1732 if (ActualMask == DesiredMask) 1733 return true; 1734 1735 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1736 if (ActualMask.intersects(~DesiredMask)) 1737 return false; 1738 1739 // Otherwise, the DAG Combiner may have proven that the value coming in is 1740 // either already zero or is not demanded. Check for known zero input bits. 1741 APInt NeededMask = DesiredMask & ~ActualMask; 1742 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1743 return true; 1744 1745 // TODO: check to see if missing bits are just not demanded. 1746 1747 // Otherwise, this pattern doesn't match. 1748 return false; 1749 } 1750 1751 /// CheckOrMask - The isel is trying to match something like (or X, 255). If 1752 /// the dag combiner simplified the 255, we still want to match. RHS is the 1753 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1754 /// specified in the .td file (e.g. 255). 1755 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1756 int64_t DesiredMaskS) const { 1757 const APInt &ActualMask = RHS->getAPIntValue(); 1758 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1759 1760 // If the actual mask exactly matches, success! 1761 if (ActualMask == DesiredMask) 1762 return true; 1763 1764 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1765 if (ActualMask.intersects(~DesiredMask)) 1766 return false; 1767 1768 // Otherwise, the DAG Combiner may have proven that the value coming in is 1769 // either already zero or is not demanded. Check for known zero input bits. 1770 APInt NeededMask = DesiredMask & ~ActualMask; 1771 1772 APInt KnownZero, KnownOne; 1773 CurDAG->computeKnownBits(LHS, KnownZero, KnownOne); 1774 1775 // If all the missing bits in the or are already known to be set, match! 1776 if ((NeededMask & KnownOne) == NeededMask) 1777 return true; 1778 1779 // TODO: check to see if missing bits are just not demanded. 1780 1781 // Otherwise, this pattern doesn't match. 1782 return false; 1783 } 1784 1785 1786 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1787 /// by tblgen. Others should not call it. 1788 void SelectionDAGISel:: 1789 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1790 std::vector<SDValue> InOps; 1791 std::swap(InOps, Ops); 1792 1793 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1794 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1795 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1796 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1797 1798 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1799 if (InOps[e-1].getValueType() == MVT::Glue) 1800 --e; // Don't process a glue operand if it is here. 1801 1802 while (i != e) { 1803 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1804 if (!InlineAsm::isMemKind(Flags)) { 1805 // Just skip over this operand, copying the operands verbatim. 1806 Ops.insert(Ops.end(), InOps.begin()+i, 1807 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1808 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1809 } else { 1810 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1811 "Memory operand with multiple values?"); 1812 1813 unsigned TiedToOperand; 1814 if (InlineAsm::isUseOperandTiedToDef(Flags, TiedToOperand)) { 1815 // We need the constraint ID from the operand this is tied to. 1816 unsigned CurOp = InlineAsm::Op_FirstOperand; 1817 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); 1818 for (; TiedToOperand; --TiedToOperand) { 1819 CurOp += InlineAsm::getNumOperandRegisters(Flags)+1; 1820 Flags = cast<ConstantSDNode>(InOps[CurOp])->getZExtValue(); 1821 } 1822 } 1823 1824 // Otherwise, this is a memory operand. Ask the target to select it. 1825 std::vector<SDValue> SelOps; 1826 if (SelectInlineAsmMemoryOperand(InOps[i+1], 1827 InlineAsm::getMemoryConstraintID(Flags), 1828 SelOps)) 1829 report_fatal_error("Could not match memory address. Inline asm" 1830 " failure!"); 1831 1832 // Add this to the output node. 1833 unsigned NewFlags = 1834 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1835 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1836 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1837 i += 2; 1838 } 1839 } 1840 1841 // Add the glue input back if present. 1842 if (e != InOps.size()) 1843 Ops.push_back(InOps.back()); 1844 } 1845 1846 /// findGlueUse - Return use of MVT::Glue value produced by the specified 1847 /// SDNode. 1848 /// 1849 static SDNode *findGlueUse(SDNode *N) { 1850 unsigned FlagResNo = N->getNumValues()-1; 1851 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1852 SDUse &Use = I.getUse(); 1853 if (Use.getResNo() == FlagResNo) 1854 return Use.getUser(); 1855 } 1856 return nullptr; 1857 } 1858 1859 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1860 /// This function recursively traverses up the operand chain, ignoring 1861 /// certain nodes. 1862 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1863 SDNode *Root, SmallPtrSetImpl<SDNode*> &Visited, 1864 bool IgnoreChains) { 1865 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1866 // greater than all of its (recursive) operands. If we scan to a point where 1867 // 'use' is smaller than the node we're scanning for, then we know we will 1868 // never find it. 1869 // 1870 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1871 // happen because we scan down to newly selected nodes in the case of glue 1872 // uses. 1873 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1874 return false; 1875 1876 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1877 // won't fail if we scan it again. 1878 if (!Visited.insert(Use).second) 1879 return false; 1880 1881 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1882 // Ignore chain uses, they are validated by HandleMergeInputChains. 1883 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1884 continue; 1885 1886 SDNode *N = Use->getOperand(i).getNode(); 1887 if (N == Def) { 1888 if (Use == ImmedUse || Use == Root) 1889 continue; // We are not looking for immediate use. 1890 assert(N != Root); 1891 return true; 1892 } 1893 1894 // Traverse up the operand chain. 1895 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1896 return true; 1897 } 1898 return false; 1899 } 1900 1901 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 1902 /// operand node N of U during instruction selection that starts at Root. 1903 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1904 SDNode *Root) const { 1905 if (OptLevel == CodeGenOpt::None) return false; 1906 return N.hasOneUse(); 1907 } 1908 1909 /// IsLegalToFold - Returns true if the specific operand node N of 1910 /// U can be folded during instruction selection that starts at Root. 1911 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1912 CodeGenOpt::Level OptLevel, 1913 bool IgnoreChains) { 1914 if (OptLevel == CodeGenOpt::None) return false; 1915 1916 // If Root use can somehow reach N through a path that that doesn't contain 1917 // U then folding N would create a cycle. e.g. In the following 1918 // diagram, Root can reach N through X. If N is folded into into Root, then 1919 // X is both a predecessor and a successor of U. 1920 // 1921 // [N*] // 1922 // ^ ^ // 1923 // / \ // 1924 // [U*] [X]? // 1925 // ^ ^ // 1926 // \ / // 1927 // \ / // 1928 // [Root*] // 1929 // 1930 // * indicates nodes to be folded together. 1931 // 1932 // If Root produces glue, then it gets (even more) interesting. Since it 1933 // will be "glued" together with its glue use in the scheduler, we need to 1934 // check if it might reach N. 1935 // 1936 // [N*] // 1937 // ^ ^ // 1938 // / \ // 1939 // [U*] [X]? // 1940 // ^ ^ // 1941 // \ \ // 1942 // \ | // 1943 // [Root*] | // 1944 // ^ | // 1945 // f | // 1946 // | / // 1947 // [Y] / // 1948 // ^ / // 1949 // f / // 1950 // | / // 1951 // [GU] // 1952 // 1953 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1954 // (call it Fold), then X is a predecessor of GU and a successor of 1955 // Fold. But since Fold and GU are glued together, this will create 1956 // a cycle in the scheduling graph. 1957 1958 // If the node has glue, walk down the graph to the "lowest" node in the 1959 // glueged set. 1960 EVT VT = Root->getValueType(Root->getNumValues()-1); 1961 while (VT == MVT::Glue) { 1962 SDNode *GU = findGlueUse(Root); 1963 if (!GU) 1964 break; 1965 Root = GU; 1966 VT = Root->getValueType(Root->getNumValues()-1); 1967 1968 // If our query node has a glue result with a use, we've walked up it. If 1969 // the user (which has already been selected) has a chain or indirectly uses 1970 // the chain, our WalkChainUsers predicate will not consider it. Because of 1971 // this, we cannot ignore chains in this predicate. 1972 IgnoreChains = false; 1973 } 1974 1975 1976 SmallPtrSet<SDNode*, 16> Visited; 1977 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1978 } 1979 1980 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1981 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1982 SelectInlineAsmMemoryOperands(Ops); 1983 1984 const EVT VTs[] = {MVT::Other, MVT::Glue}; 1985 SDValue New = CurDAG->getNode(ISD::INLINEASM, SDLoc(N), VTs, Ops); 1986 New->setNodeId(-1); 1987 return New.getNode(); 1988 } 1989 1990 SDNode 1991 *SelectionDAGISel::Select_READ_REGISTER(SDNode *Op) { 1992 SDLoc dl(Op); 1993 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(0)); 1994 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 1995 unsigned Reg = 1996 TLI->getRegisterByName(RegStr->getString().data(), Op->getValueType(0)); 1997 SDValue New = CurDAG->getCopyFromReg( 1998 CurDAG->getEntryNode(), dl, Reg, Op->getValueType(0)); 1999 New->setNodeId(-1); 2000 return New.getNode(); 2001 } 2002 2003 SDNode 2004 *SelectionDAGISel::Select_WRITE_REGISTER(SDNode *Op) { 2005 SDLoc dl(Op); 2006 MDNodeSDNode *MD = dyn_cast<MDNodeSDNode>(Op->getOperand(1)); 2007 const MDString *RegStr = dyn_cast<MDString>(MD->getMD()->getOperand(0)); 2008 unsigned Reg = TLI->getRegisterByName(RegStr->getString().data(), 2009 Op->getOperand(2).getValueType()); 2010 SDValue New = CurDAG->getCopyToReg( 2011 CurDAG->getEntryNode(), dl, Reg, Op->getOperand(2)); 2012 New->setNodeId(-1); 2013 return New.getNode(); 2014 } 2015 2016 2017 2018 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 2019 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 2020 } 2021 2022 /// GetVBR - decode a vbr encoding whose top bit is set. 2023 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 2024 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 2025 assert(Val >= 128 && "Not a VBR"); 2026 Val &= 127; // Remove first vbr bit. 2027 2028 unsigned Shift = 7; 2029 uint64_t NextBits; 2030 do { 2031 NextBits = MatcherTable[Idx++]; 2032 Val |= (NextBits&127) << Shift; 2033 Shift += 7; 2034 } while (NextBits & 128); 2035 2036 return Val; 2037 } 2038 2039 2040 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of 2041 /// interior glue and chain results to use the new glue and chain results. 2042 void SelectionDAGISel:: 2043 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 2044 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 2045 SDValue InputGlue, 2046 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 2047 bool isMorphNodeTo) { 2048 SmallVector<SDNode*, 4> NowDeadNodes; 2049 2050 // Now that all the normal results are replaced, we replace the chain and 2051 // glue results if present. 2052 if (!ChainNodesMatched.empty()) { 2053 assert(InputChain.getNode() && 2054 "Matched input chains but didn't produce a chain"); 2055 // Loop over all of the nodes we matched that produced a chain result. 2056 // Replace all the chain results with the final chain we ended up with. 2057 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2058 SDNode *ChainNode = ChainNodesMatched[i]; 2059 2060 // If this node was already deleted, don't look at it. 2061 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 2062 continue; 2063 2064 // Don't replace the results of the root node if we're doing a 2065 // MorphNodeTo. 2066 if (ChainNode == NodeToMatch && isMorphNodeTo) 2067 continue; 2068 2069 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 2070 if (ChainVal.getValueType() == MVT::Glue) 2071 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 2072 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 2073 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 2074 2075 // If the node became dead and we haven't already seen it, delete it. 2076 if (ChainNode->use_empty() && 2077 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 2078 NowDeadNodes.push_back(ChainNode); 2079 } 2080 } 2081 2082 // If the result produces glue, update any glue results in the matched 2083 // pattern with the glue result. 2084 if (InputGlue.getNode()) { 2085 // Handle any interior nodes explicitly marked. 2086 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 2087 SDNode *FRN = GlueResultNodesMatched[i]; 2088 2089 // If this node was already deleted, don't look at it. 2090 if (FRN->getOpcode() == ISD::DELETED_NODE) 2091 continue; 2092 2093 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 2094 "Doesn't have a glue result"); 2095 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 2096 InputGlue); 2097 2098 // If the node became dead and we haven't already seen it, delete it. 2099 if (FRN->use_empty() && 2100 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 2101 NowDeadNodes.push_back(FRN); 2102 } 2103 } 2104 2105 if (!NowDeadNodes.empty()) 2106 CurDAG->RemoveDeadNodes(NowDeadNodes); 2107 2108 DEBUG(dbgs() << "ISEL: Match complete!\n"); 2109 } 2110 2111 enum ChainResult { 2112 CR_Simple, 2113 CR_InducesCycle, 2114 CR_LeadsToInteriorNode 2115 }; 2116 2117 /// WalkChainUsers - Walk down the users of the specified chained node that is 2118 /// part of the pattern we're matching, looking at all of the users we find. 2119 /// This determines whether something is an interior node, whether we have a 2120 /// non-pattern node in between two pattern nodes (which prevent folding because 2121 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched 2122 /// between pattern nodes (in which case the TF becomes part of the pattern). 2123 /// 2124 /// The walk we do here is guaranteed to be small because we quickly get down to 2125 /// already selected nodes "below" us. 2126 static ChainResult 2127 WalkChainUsers(const SDNode *ChainedNode, 2128 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 2129 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 2130 ChainResult Result = CR_Simple; 2131 2132 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 2133 E = ChainedNode->use_end(); UI != E; ++UI) { 2134 // Make sure the use is of the chain, not some other value we produce. 2135 if (UI.getUse().getValueType() != MVT::Other) continue; 2136 2137 SDNode *User = *UI; 2138 2139 if (User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 2140 continue; 2141 2142 // If we see an already-selected machine node, then we've gone beyond the 2143 // pattern that we're selecting down into the already selected chunk of the 2144 // DAG. 2145 unsigned UserOpcode = User->getOpcode(); 2146 if (User->isMachineOpcode() || 2147 UserOpcode == ISD::CopyToReg || 2148 UserOpcode == ISD::CopyFromReg || 2149 UserOpcode == ISD::INLINEASM || 2150 UserOpcode == ISD::EH_LABEL || 2151 UserOpcode == ISD::LIFETIME_START || 2152 UserOpcode == ISD::LIFETIME_END) { 2153 // If their node ID got reset to -1 then they've already been selected. 2154 // Treat them like a MachineOpcode. 2155 if (User->getNodeId() == -1) 2156 continue; 2157 } 2158 2159 // If we have a TokenFactor, we handle it specially. 2160 if (User->getOpcode() != ISD::TokenFactor) { 2161 // If the node isn't a token factor and isn't part of our pattern, then it 2162 // must be a random chained node in between two nodes we're selecting. 2163 // This happens when we have something like: 2164 // x = load ptr 2165 // call 2166 // y = x+4 2167 // store y -> ptr 2168 // Because we structurally match the load/store as a read/modify/write, 2169 // but the call is chained between them. We cannot fold in this case 2170 // because it would induce a cycle in the graph. 2171 if (!std::count(ChainedNodesInPattern.begin(), 2172 ChainedNodesInPattern.end(), User)) 2173 return CR_InducesCycle; 2174 2175 // Otherwise we found a node that is part of our pattern. For example in: 2176 // x = load ptr 2177 // y = x+4 2178 // store y -> ptr 2179 // This would happen when we're scanning down from the load and see the 2180 // store as a user. Record that there is a use of ChainedNode that is 2181 // part of the pattern and keep scanning uses. 2182 Result = CR_LeadsToInteriorNode; 2183 InteriorChainedNodes.push_back(User); 2184 continue; 2185 } 2186 2187 // If we found a TokenFactor, there are two cases to consider: first if the 2188 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 2189 // uses of the TF are in our pattern) we just want to ignore it. Second, 2190 // the TokenFactor can be sandwiched in between two chained nodes, like so: 2191 // [Load chain] 2192 // ^ 2193 // | 2194 // [Load] 2195 // ^ ^ 2196 // | \ DAG's like cheese 2197 // / \ do you? 2198 // / | 2199 // [TokenFactor] [Op] 2200 // ^ ^ 2201 // | | 2202 // \ / 2203 // \ / 2204 // [Store] 2205 // 2206 // In this case, the TokenFactor becomes part of our match and we rewrite it 2207 // as a new TokenFactor. 2208 // 2209 // To distinguish these two cases, do a recursive walk down the uses. 2210 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 2211 case CR_Simple: 2212 // If the uses of the TokenFactor are just already-selected nodes, ignore 2213 // it, it is "below" our pattern. 2214 continue; 2215 case CR_InducesCycle: 2216 // If the uses of the TokenFactor lead to nodes that are not part of our 2217 // pattern that are not selected, folding would turn this into a cycle, 2218 // bail out now. 2219 return CR_InducesCycle; 2220 case CR_LeadsToInteriorNode: 2221 break; // Otherwise, keep processing. 2222 } 2223 2224 // Okay, we know we're in the interesting interior case. The TokenFactor 2225 // is now going to be considered part of the pattern so that we rewrite its 2226 // uses (it may have uses that are not part of the pattern) with the 2227 // ultimate chain result of the generated code. We will also add its chain 2228 // inputs as inputs to the ultimate TokenFactor we create. 2229 Result = CR_LeadsToInteriorNode; 2230 ChainedNodesInPattern.push_back(User); 2231 InteriorChainedNodes.push_back(User); 2232 continue; 2233 } 2234 2235 return Result; 2236 } 2237 2238 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 2239 /// operation for when the pattern matched at least one node with a chains. The 2240 /// input vector contains a list of all of the chained nodes that we match. We 2241 /// must determine if this is a valid thing to cover (i.e. matching it won't 2242 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 2243 /// be used as the input node chain for the generated nodes. 2244 static SDValue 2245 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 2246 SelectionDAG *CurDAG) { 2247 // Walk all of the chained nodes we've matched, recursively scanning down the 2248 // users of the chain result. This adds any TokenFactor nodes that are caught 2249 // in between chained nodes to the chained and interior nodes list. 2250 SmallVector<SDNode*, 3> InteriorChainedNodes; 2251 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2252 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 2253 InteriorChainedNodes) == CR_InducesCycle) 2254 return SDValue(); // Would induce a cycle. 2255 } 2256 2257 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 2258 // that we are interested in. Form our input TokenFactor node. 2259 SmallVector<SDValue, 3> InputChains; 2260 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 2261 // Add the input chain of this node to the InputChains list (which will be 2262 // the operands of the generated TokenFactor) if it's not an interior node. 2263 SDNode *N = ChainNodesMatched[i]; 2264 if (N->getOpcode() != ISD::TokenFactor) { 2265 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 2266 continue; 2267 2268 // Otherwise, add the input chain. 2269 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 2270 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 2271 InputChains.push_back(InChain); 2272 continue; 2273 } 2274 2275 // If we have a token factor, we want to add all inputs of the token factor 2276 // that are not part of the pattern we're matching. 2277 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 2278 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 2279 N->getOperand(op).getNode())) 2280 InputChains.push_back(N->getOperand(op)); 2281 } 2282 } 2283 2284 if (InputChains.size() == 1) 2285 return InputChains[0]; 2286 return CurDAG->getNode(ISD::TokenFactor, SDLoc(ChainNodesMatched[0]), 2287 MVT::Other, InputChains); 2288 } 2289 2290 /// MorphNode - Handle morphing a node in place for the selector. 2291 SDNode *SelectionDAGISel:: 2292 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 2293 ArrayRef<SDValue> Ops, unsigned EmitNodeInfo) { 2294 // It is possible we're using MorphNodeTo to replace a node with no 2295 // normal results with one that has a normal result (or we could be 2296 // adding a chain) and the input could have glue and chains as well. 2297 // In this case we need to shift the operands down. 2298 // FIXME: This is a horrible hack and broken in obscure cases, no worse 2299 // than the old isel though. 2300 int OldGlueResultNo = -1, OldChainResultNo = -1; 2301 2302 unsigned NTMNumResults = Node->getNumValues(); 2303 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 2304 OldGlueResultNo = NTMNumResults-1; 2305 if (NTMNumResults != 1 && 2306 Node->getValueType(NTMNumResults-2) == MVT::Other) 2307 OldChainResultNo = NTMNumResults-2; 2308 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 2309 OldChainResultNo = NTMNumResults-1; 2310 2311 // Call the underlying SelectionDAG routine to do the transmogrification. Note 2312 // that this deletes operands of the old node that become dead. 2313 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops); 2314 2315 // MorphNodeTo can operate in two ways: if an existing node with the 2316 // specified operands exists, it can just return it. Otherwise, it 2317 // updates the node in place to have the requested operands. 2318 if (Res == Node) { 2319 // If we updated the node in place, reset the node ID. To the isel, 2320 // this should be just like a newly allocated machine node. 2321 Res->setNodeId(-1); 2322 } 2323 2324 unsigned ResNumResults = Res->getNumValues(); 2325 // Move the glue if needed. 2326 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 2327 (unsigned)OldGlueResultNo != ResNumResults-1) 2328 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 2329 SDValue(Res, ResNumResults-1)); 2330 2331 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 2332 --ResNumResults; 2333 2334 // Move the chain reference if needed. 2335 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 2336 (unsigned)OldChainResultNo != ResNumResults-1) 2337 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 2338 SDValue(Res, ResNumResults-1)); 2339 2340 // Otherwise, no replacement happened because the node already exists. Replace 2341 // Uses of the old node with the new one. 2342 if (Res != Node) 2343 CurDAG->ReplaceAllUsesWith(Node, Res); 2344 2345 return Res; 2346 } 2347 2348 /// CheckSame - Implements OP_CheckSame. 2349 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2350 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2351 SDValue N, 2352 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2353 // Accept if it is exactly the same as a previously recorded node. 2354 unsigned RecNo = MatcherTable[MatcherIndex++]; 2355 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2356 return N == RecordedNodes[RecNo].first; 2357 } 2358 2359 /// CheckChildSame - Implements OP_CheckChildXSame. 2360 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2361 CheckChildSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2362 SDValue N, 2363 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes, 2364 unsigned ChildNo) { 2365 if (ChildNo >= N.getNumOperands()) 2366 return false; // Match fails if out of range child #. 2367 return ::CheckSame(MatcherTable, MatcherIndex, N.getOperand(ChildNo), 2368 RecordedNodes); 2369 } 2370 2371 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2372 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2373 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2374 const SelectionDAGISel &SDISel) { 2375 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2376 } 2377 2378 /// CheckNodePredicate - Implements OP_CheckNodePredicate. 2379 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2380 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2381 const SelectionDAGISel &SDISel, SDNode *N) { 2382 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2383 } 2384 2385 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2386 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2387 SDNode *N) { 2388 uint16_t Opc = MatcherTable[MatcherIndex++]; 2389 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2390 return N->getOpcode() == Opc; 2391 } 2392 2393 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2394 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2395 SDValue N, const TargetLowering *TLI) { 2396 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2397 if (N.getValueType() == VT) return true; 2398 2399 // Handle the case when VT is iPTR. 2400 return VT == MVT::iPTR && N.getValueType() == TLI->getPointerTy(); 2401 } 2402 2403 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2404 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2405 SDValue N, const TargetLowering *TLI, unsigned ChildNo) { 2406 if (ChildNo >= N.getNumOperands()) 2407 return false; // Match fails if out of range child #. 2408 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2409 } 2410 2411 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2412 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2413 SDValue N) { 2414 return cast<CondCodeSDNode>(N)->get() == 2415 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2416 } 2417 2418 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2419 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2420 SDValue N, const TargetLowering *TLI) { 2421 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2422 if (cast<VTSDNode>(N)->getVT() == VT) 2423 return true; 2424 2425 // Handle the case when VT is iPTR. 2426 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI->getPointerTy(); 2427 } 2428 2429 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2430 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2431 SDValue N) { 2432 int64_t Val = MatcherTable[MatcherIndex++]; 2433 if (Val & 128) 2434 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2435 2436 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2437 return C && C->getSExtValue() == Val; 2438 } 2439 2440 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2441 CheckChildInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2442 SDValue N, unsigned ChildNo) { 2443 if (ChildNo >= N.getNumOperands()) 2444 return false; // Match fails if out of range child #. 2445 return ::CheckInteger(MatcherTable, MatcherIndex, N.getOperand(ChildNo)); 2446 } 2447 2448 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2449 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2450 SDValue N, const SelectionDAGISel &SDISel) { 2451 int64_t Val = MatcherTable[MatcherIndex++]; 2452 if (Val & 128) 2453 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2454 2455 if (N->getOpcode() != ISD::AND) return false; 2456 2457 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2458 return C && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2459 } 2460 2461 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2462 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2463 SDValue N, const SelectionDAGISel &SDISel) { 2464 int64_t Val = MatcherTable[MatcherIndex++]; 2465 if (Val & 128) 2466 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2467 2468 if (N->getOpcode() != ISD::OR) return false; 2469 2470 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2471 return C && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2472 } 2473 2474 /// IsPredicateKnownToFail - If we know how and can do so without pushing a 2475 /// scope, evaluate the current node. If the current predicate is known to 2476 /// fail, set Result=true and return anything. If the current predicate is 2477 /// known to pass, set Result=false and return the MatcherIndex to continue 2478 /// with. If the current predicate is unknown, set Result=false and return the 2479 /// MatcherIndex to continue with. 2480 static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2481 unsigned Index, SDValue N, 2482 bool &Result, 2483 const SelectionDAGISel &SDISel, 2484 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2485 switch (Table[Index++]) { 2486 default: 2487 Result = false; 2488 return Index-1; // Could not evaluate this predicate. 2489 case SelectionDAGISel::OPC_CheckSame: 2490 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2491 return Index; 2492 case SelectionDAGISel::OPC_CheckChild0Same: 2493 case SelectionDAGISel::OPC_CheckChild1Same: 2494 case SelectionDAGISel::OPC_CheckChild2Same: 2495 case SelectionDAGISel::OPC_CheckChild3Same: 2496 Result = !::CheckChildSame(Table, Index, N, RecordedNodes, 2497 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Same); 2498 return Index; 2499 case SelectionDAGISel::OPC_CheckPatternPredicate: 2500 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2501 return Index; 2502 case SelectionDAGISel::OPC_CheckPredicate: 2503 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2504 return Index; 2505 case SelectionDAGISel::OPC_CheckOpcode: 2506 Result = !::CheckOpcode(Table, Index, N.getNode()); 2507 return Index; 2508 case SelectionDAGISel::OPC_CheckType: 2509 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2510 return Index; 2511 case SelectionDAGISel::OPC_CheckChild0Type: 2512 case SelectionDAGISel::OPC_CheckChild1Type: 2513 case SelectionDAGISel::OPC_CheckChild2Type: 2514 case SelectionDAGISel::OPC_CheckChild3Type: 2515 case SelectionDAGISel::OPC_CheckChild4Type: 2516 case SelectionDAGISel::OPC_CheckChild5Type: 2517 case SelectionDAGISel::OPC_CheckChild6Type: 2518 case SelectionDAGISel::OPC_CheckChild7Type: 2519 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2520 Table[Index - 1] - 2521 SelectionDAGISel::OPC_CheckChild0Type); 2522 return Index; 2523 case SelectionDAGISel::OPC_CheckCondCode: 2524 Result = !::CheckCondCode(Table, Index, N); 2525 return Index; 2526 case SelectionDAGISel::OPC_CheckValueType: 2527 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2528 return Index; 2529 case SelectionDAGISel::OPC_CheckInteger: 2530 Result = !::CheckInteger(Table, Index, N); 2531 return Index; 2532 case SelectionDAGISel::OPC_CheckChild0Integer: 2533 case SelectionDAGISel::OPC_CheckChild1Integer: 2534 case SelectionDAGISel::OPC_CheckChild2Integer: 2535 case SelectionDAGISel::OPC_CheckChild3Integer: 2536 case SelectionDAGISel::OPC_CheckChild4Integer: 2537 Result = !::CheckChildInteger(Table, Index, N, 2538 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Integer); 2539 return Index; 2540 case SelectionDAGISel::OPC_CheckAndImm: 2541 Result = !::CheckAndImm(Table, Index, N, SDISel); 2542 return Index; 2543 case SelectionDAGISel::OPC_CheckOrImm: 2544 Result = !::CheckOrImm(Table, Index, N, SDISel); 2545 return Index; 2546 } 2547 } 2548 2549 namespace { 2550 2551 struct MatchScope { 2552 /// FailIndex - If this match fails, this is the index to continue with. 2553 unsigned FailIndex; 2554 2555 /// NodeStack - The node stack when the scope was formed. 2556 SmallVector<SDValue, 4> NodeStack; 2557 2558 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2559 unsigned NumRecordedNodes; 2560 2561 /// NumMatchedMemRefs - The number of matched memref entries. 2562 unsigned NumMatchedMemRefs; 2563 2564 /// InputChain/InputGlue - The current chain/glue 2565 SDValue InputChain, InputGlue; 2566 2567 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2568 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2569 }; 2570 2571 /// \\brief A DAG update listener to keep the matching state 2572 /// (i.e. RecordedNodes and MatchScope) uptodate if the target is allowed to 2573 /// change the DAG while matching. X86 addressing mode matcher is an example 2574 /// for this. 2575 class MatchStateUpdater : public SelectionDAG::DAGUpdateListener 2576 { 2577 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes; 2578 SmallVectorImpl<MatchScope> &MatchScopes; 2579 public: 2580 MatchStateUpdater(SelectionDAG &DAG, 2581 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RN, 2582 SmallVectorImpl<MatchScope> &MS) : 2583 SelectionDAG::DAGUpdateListener(DAG), 2584 RecordedNodes(RN), MatchScopes(MS) { } 2585 2586 void NodeDeleted(SDNode *N, SDNode *E) override { 2587 // Some early-returns here to avoid the search if we deleted the node or 2588 // if the update comes from MorphNodeTo (MorphNodeTo is the last thing we 2589 // do, so it's unnecessary to update matching state at that point). 2590 // Neither of these can occur currently because we only install this 2591 // update listener during matching a complex patterns. 2592 if (!E || E->isMachineOpcode()) 2593 return; 2594 // Performing linear search here does not matter because we almost never 2595 // run this code. You'd have to have a CSE during complex pattern 2596 // matching. 2597 for (auto &I : RecordedNodes) 2598 if (I.first.getNode() == N) 2599 I.first.setNode(E); 2600 2601 for (auto &I : MatchScopes) 2602 for (auto &J : I.NodeStack) 2603 if (J.getNode() == N) 2604 J.setNode(E); 2605 } 2606 }; 2607 } 2608 2609 SDNode *SelectionDAGISel:: 2610 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2611 unsigned TableSize) { 2612 // FIXME: Should these even be selected? Handle these cases in the caller? 2613 switch (NodeToMatch->getOpcode()) { 2614 default: 2615 break; 2616 case ISD::EntryToken: // These nodes remain the same. 2617 case ISD::BasicBlock: 2618 case ISD::Register: 2619 case ISD::RegisterMask: 2620 case ISD::HANDLENODE: 2621 case ISD::MDNODE_SDNODE: 2622 case ISD::TargetConstant: 2623 case ISD::TargetConstantFP: 2624 case ISD::TargetConstantPool: 2625 case ISD::TargetFrameIndex: 2626 case ISD::TargetExternalSymbol: 2627 case ISD::TargetBlockAddress: 2628 case ISD::TargetJumpTable: 2629 case ISD::TargetGlobalTLSAddress: 2630 case ISD::TargetGlobalAddress: 2631 case ISD::TokenFactor: 2632 case ISD::CopyFromReg: 2633 case ISD::CopyToReg: 2634 case ISD::EH_LABEL: 2635 case ISD::LIFETIME_START: 2636 case ISD::LIFETIME_END: 2637 NodeToMatch->setNodeId(-1); // Mark selected. 2638 return nullptr; 2639 case ISD::AssertSext: 2640 case ISD::AssertZext: 2641 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2642 NodeToMatch->getOperand(0)); 2643 return nullptr; 2644 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2645 case ISD::READ_REGISTER: return Select_READ_REGISTER(NodeToMatch); 2646 case ISD::WRITE_REGISTER: return Select_WRITE_REGISTER(NodeToMatch); 2647 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2648 } 2649 2650 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2651 2652 // Set up the node stack with NodeToMatch as the only node on the stack. 2653 SmallVector<SDValue, 8> NodeStack; 2654 SDValue N = SDValue(NodeToMatch, 0); 2655 NodeStack.push_back(N); 2656 2657 // MatchScopes - Scopes used when matching, if a match failure happens, this 2658 // indicates where to continue checking. 2659 SmallVector<MatchScope, 8> MatchScopes; 2660 2661 // RecordedNodes - This is the set of nodes that have been recorded by the 2662 // state machine. The second value is the parent of the node, or null if the 2663 // root is recorded. 2664 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2665 2666 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2667 // pattern. 2668 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2669 2670 // These are the current input chain and glue for use when generating nodes. 2671 // Various Emit operations change these. For example, emitting a copytoreg 2672 // uses and updates these. 2673 SDValue InputChain, InputGlue; 2674 2675 // ChainNodesMatched - If a pattern matches nodes that have input/output 2676 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2677 // which ones they are. The result is captured into this list so that we can 2678 // update the chain results when the pattern is complete. 2679 SmallVector<SDNode*, 3> ChainNodesMatched; 2680 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2681 2682 DEBUG(dbgs() << "ISEL: Starting pattern match on root node: "; 2683 NodeToMatch->dump(CurDAG); 2684 dbgs() << '\n'); 2685 2686 // Determine where to start the interpreter. Normally we start at opcode #0, 2687 // but if the state machine starts with an OPC_SwitchOpcode, then we 2688 // accelerate the first lookup (which is guaranteed to be hot) with the 2689 // OpcodeOffset table. 2690 unsigned MatcherIndex = 0; 2691 2692 if (!OpcodeOffset.empty()) { 2693 // Already computed the OpcodeOffset table, just index into it. 2694 if (N.getOpcode() < OpcodeOffset.size()) 2695 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2696 DEBUG(dbgs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2697 2698 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2699 // Otherwise, the table isn't computed, but the state machine does start 2700 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2701 // is the first time we're selecting an instruction. 2702 unsigned Idx = 1; 2703 while (1) { 2704 // Get the size of this case. 2705 unsigned CaseSize = MatcherTable[Idx++]; 2706 if (CaseSize & 128) 2707 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2708 if (CaseSize == 0) break; 2709 2710 // Get the opcode, add the index to the table. 2711 uint16_t Opc = MatcherTable[Idx++]; 2712 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2713 if (Opc >= OpcodeOffset.size()) 2714 OpcodeOffset.resize((Opc+1)*2); 2715 OpcodeOffset[Opc] = Idx; 2716 Idx += CaseSize; 2717 } 2718 2719 // Okay, do the lookup for the first opcode. 2720 if (N.getOpcode() < OpcodeOffset.size()) 2721 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2722 } 2723 2724 while (1) { 2725 assert(MatcherIndex < TableSize && "Invalid index"); 2726 #ifndef NDEBUG 2727 unsigned CurrentOpcodeIndex = MatcherIndex; 2728 #endif 2729 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2730 switch (Opcode) { 2731 case OPC_Scope: { 2732 // Okay, the semantics of this operation are that we should push a scope 2733 // then evaluate the first child. However, pushing a scope only to have 2734 // the first check fail (which then pops it) is inefficient. If we can 2735 // determine immediately that the first check (or first several) will 2736 // immediately fail, don't even bother pushing a scope for them. 2737 unsigned FailIndex; 2738 2739 while (1) { 2740 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2741 if (NumToSkip & 128) 2742 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2743 // Found the end of the scope with no match. 2744 if (NumToSkip == 0) { 2745 FailIndex = 0; 2746 break; 2747 } 2748 2749 FailIndex = MatcherIndex+NumToSkip; 2750 2751 unsigned MatcherIndexOfPredicate = MatcherIndex; 2752 (void)MatcherIndexOfPredicate; // silence warning. 2753 2754 // If we can't evaluate this predicate without pushing a scope (e.g. if 2755 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2756 // push the scope and evaluate the full predicate chain. 2757 bool Result; 2758 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2759 Result, *this, RecordedNodes); 2760 if (!Result) 2761 break; 2762 2763 DEBUG(dbgs() << " Skipped scope entry (due to false predicate) at " 2764 << "index " << MatcherIndexOfPredicate 2765 << ", continuing at " << FailIndex << "\n"); 2766 ++NumDAGIselRetries; 2767 2768 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2769 // move to the next case. 2770 MatcherIndex = FailIndex; 2771 } 2772 2773 // If the whole scope failed to match, bail. 2774 if (FailIndex == 0) break; 2775 2776 // Push a MatchScope which indicates where to go if the first child fails 2777 // to match. 2778 MatchScope NewEntry; 2779 NewEntry.FailIndex = FailIndex; 2780 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2781 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2782 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2783 NewEntry.InputChain = InputChain; 2784 NewEntry.InputGlue = InputGlue; 2785 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2786 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2787 MatchScopes.push_back(NewEntry); 2788 continue; 2789 } 2790 case OPC_RecordNode: { 2791 // Remember this node, it may end up being an operand in the pattern. 2792 SDNode *Parent = nullptr; 2793 if (NodeStack.size() > 1) 2794 Parent = NodeStack[NodeStack.size()-2].getNode(); 2795 RecordedNodes.push_back(std::make_pair(N, Parent)); 2796 continue; 2797 } 2798 2799 case OPC_RecordChild0: case OPC_RecordChild1: 2800 case OPC_RecordChild2: case OPC_RecordChild3: 2801 case OPC_RecordChild4: case OPC_RecordChild5: 2802 case OPC_RecordChild6: case OPC_RecordChild7: { 2803 unsigned ChildNo = Opcode-OPC_RecordChild0; 2804 if (ChildNo >= N.getNumOperands()) 2805 break; // Match fails if out of range child #. 2806 2807 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2808 N.getNode())); 2809 continue; 2810 } 2811 case OPC_RecordMemRef: 2812 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2813 continue; 2814 2815 case OPC_CaptureGlueInput: 2816 // If the current node has an input glue, capture it in InputGlue. 2817 if (N->getNumOperands() != 0 && 2818 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2819 InputGlue = N->getOperand(N->getNumOperands()-1); 2820 continue; 2821 2822 case OPC_MoveChild: { 2823 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2824 if (ChildNo >= N.getNumOperands()) 2825 break; // Match fails if out of range child #. 2826 N = N.getOperand(ChildNo); 2827 NodeStack.push_back(N); 2828 continue; 2829 } 2830 2831 case OPC_MoveParent: 2832 // Pop the current node off the NodeStack. 2833 NodeStack.pop_back(); 2834 assert(!NodeStack.empty() && "Node stack imbalance!"); 2835 N = NodeStack.back(); 2836 continue; 2837 2838 case OPC_CheckSame: 2839 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2840 continue; 2841 2842 case OPC_CheckChild0Same: case OPC_CheckChild1Same: 2843 case OPC_CheckChild2Same: case OPC_CheckChild3Same: 2844 if (!::CheckChildSame(MatcherTable, MatcherIndex, N, RecordedNodes, 2845 Opcode-OPC_CheckChild0Same)) 2846 break; 2847 continue; 2848 2849 case OPC_CheckPatternPredicate: 2850 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2851 continue; 2852 case OPC_CheckPredicate: 2853 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2854 N.getNode())) 2855 break; 2856 continue; 2857 case OPC_CheckComplexPat: { 2858 unsigned CPNum = MatcherTable[MatcherIndex++]; 2859 unsigned RecNo = MatcherTable[MatcherIndex++]; 2860 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2861 2862 // If target can modify DAG during matching, keep the matching state 2863 // consistent. 2864 std::unique_ptr<MatchStateUpdater> MSU; 2865 if (ComplexPatternFuncMutatesDAG()) 2866 MSU.reset(new MatchStateUpdater(*CurDAG, RecordedNodes, 2867 MatchScopes)); 2868 2869 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2870 RecordedNodes[RecNo].first, CPNum, 2871 RecordedNodes)) 2872 break; 2873 continue; 2874 } 2875 case OPC_CheckOpcode: 2876 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2877 continue; 2878 2879 case OPC_CheckType: 2880 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) 2881 break; 2882 continue; 2883 2884 case OPC_SwitchOpcode: { 2885 unsigned CurNodeOpcode = N.getOpcode(); 2886 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2887 unsigned CaseSize; 2888 while (1) { 2889 // Get the size of this case. 2890 CaseSize = MatcherTable[MatcherIndex++]; 2891 if (CaseSize & 128) 2892 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2893 if (CaseSize == 0) break; 2894 2895 uint16_t Opc = MatcherTable[MatcherIndex++]; 2896 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2897 2898 // If the opcode matches, then we will execute this case. 2899 if (CurNodeOpcode == Opc) 2900 break; 2901 2902 // Otherwise, skip over this case. 2903 MatcherIndex += CaseSize; 2904 } 2905 2906 // If no cases matched, bail out. 2907 if (CaseSize == 0) break; 2908 2909 // Otherwise, execute the case we found. 2910 DEBUG(dbgs() << " OpcodeSwitch from " << SwitchStart 2911 << " to " << MatcherIndex << "\n"); 2912 continue; 2913 } 2914 2915 case OPC_SwitchType: { 2916 MVT CurNodeVT = N.getSimpleValueType(); 2917 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2918 unsigned CaseSize; 2919 while (1) { 2920 // Get the size of this case. 2921 CaseSize = MatcherTable[MatcherIndex++]; 2922 if (CaseSize & 128) 2923 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2924 if (CaseSize == 0) break; 2925 2926 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2927 if (CaseVT == MVT::iPTR) 2928 CaseVT = TLI->getPointerTy(); 2929 2930 // If the VT matches, then we will execute this case. 2931 if (CurNodeVT == CaseVT) 2932 break; 2933 2934 // Otherwise, skip over this case. 2935 MatcherIndex += CaseSize; 2936 } 2937 2938 // If no cases matched, bail out. 2939 if (CaseSize == 0) break; 2940 2941 // Otherwise, execute the case we found. 2942 DEBUG(dbgs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2943 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2944 continue; 2945 } 2946 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2947 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2948 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2949 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2950 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2951 Opcode-OPC_CheckChild0Type)) 2952 break; 2953 continue; 2954 case OPC_CheckCondCode: 2955 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2956 continue; 2957 case OPC_CheckValueType: 2958 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) 2959 break; 2960 continue; 2961 case OPC_CheckInteger: 2962 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2963 continue; 2964 case OPC_CheckChild0Integer: case OPC_CheckChild1Integer: 2965 case OPC_CheckChild2Integer: case OPC_CheckChild3Integer: 2966 case OPC_CheckChild4Integer: 2967 if (!::CheckChildInteger(MatcherTable, MatcherIndex, N, 2968 Opcode-OPC_CheckChild0Integer)) break; 2969 continue; 2970 case OPC_CheckAndImm: 2971 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2972 continue; 2973 case OPC_CheckOrImm: 2974 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2975 continue; 2976 2977 case OPC_CheckFoldableChainNode: { 2978 assert(NodeStack.size() != 1 && "No parent node"); 2979 // Verify that all intermediate nodes between the root and this one have 2980 // a single use. 2981 bool HasMultipleUses = false; 2982 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2983 if (!NodeStack[i].hasOneUse()) { 2984 HasMultipleUses = true; 2985 break; 2986 } 2987 if (HasMultipleUses) break; 2988 2989 // Check to see that the target thinks this is profitable to fold and that 2990 // we can fold it without inducing cycles in the graph. 2991 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2992 NodeToMatch) || 2993 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2994 NodeToMatch, OptLevel, 2995 true/*We validate our own chains*/)) 2996 break; 2997 2998 continue; 2999 } 3000 case OPC_EmitInteger: { 3001 MVT::SimpleValueType VT = 3002 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3003 int64_t Val = MatcherTable[MatcherIndex++]; 3004 if (Val & 128) 3005 Val = GetVBR(Val, MatcherTable, MatcherIndex); 3006 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 3007 CurDAG->getTargetConstant(Val, VT), nullptr)); 3008 continue; 3009 } 3010 case OPC_EmitRegister: { 3011 MVT::SimpleValueType VT = 3012 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3013 unsigned RegNo = MatcherTable[MatcherIndex++]; 3014 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 3015 CurDAG->getRegister(RegNo, VT), nullptr)); 3016 continue; 3017 } 3018 case OPC_EmitRegister2: { 3019 // For targets w/ more than 256 register names, the register enum 3020 // values are stored in two bytes in the matcher table (just like 3021 // opcodes). 3022 MVT::SimpleValueType VT = 3023 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3024 unsigned RegNo = MatcherTable[MatcherIndex++]; 3025 RegNo |= MatcherTable[MatcherIndex++] << 8; 3026 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 3027 CurDAG->getRegister(RegNo, VT), nullptr)); 3028 continue; 3029 } 3030 3031 case OPC_EmitConvertToTarget: { 3032 // Convert from IMM/FPIMM to target version. 3033 unsigned RecNo = MatcherTable[MatcherIndex++]; 3034 assert(RecNo < RecordedNodes.size() && "Invalid EmitConvertToTarget"); 3035 SDValue Imm = RecordedNodes[RecNo].first; 3036 3037 if (Imm->getOpcode() == ISD::Constant) { 3038 const ConstantInt *Val=cast<ConstantSDNode>(Imm)->getConstantIntValue(); 3039 Imm = CurDAG->getConstant(*Val, Imm.getValueType(), true); 3040 } else if (Imm->getOpcode() == ISD::ConstantFP) { 3041 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 3042 Imm = CurDAG->getConstantFP(*Val, Imm.getValueType(), true); 3043 } 3044 3045 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 3046 continue; 3047 } 3048 3049 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 3050 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 3051 // These are space-optimized forms of OPC_EmitMergeInputChains. 3052 assert(!InputChain.getNode() && 3053 "EmitMergeInputChains should be the first chain producing node"); 3054 assert(ChainNodesMatched.empty() && 3055 "Should only have one EmitMergeInputChains per match"); 3056 3057 // Read all of the chained nodes. 3058 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 3059 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 3060 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3061 3062 // FIXME: What if other value results of the node have uses not matched 3063 // by this pattern? 3064 if (ChainNodesMatched.back() != NodeToMatch && 3065 !RecordedNodes[RecNo].first.hasOneUse()) { 3066 ChainNodesMatched.clear(); 3067 break; 3068 } 3069 3070 // Merge the input chains if they are not intra-pattern references. 3071 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 3072 3073 if (!InputChain.getNode()) 3074 break; // Failed to merge. 3075 continue; 3076 } 3077 3078 case OPC_EmitMergeInputChains: { 3079 assert(!InputChain.getNode() && 3080 "EmitMergeInputChains should be the first chain producing node"); 3081 // This node gets a list of nodes we matched in the input that have 3082 // chains. We want to token factor all of the input chains to these nodes 3083 // together. However, if any of the input chains is actually one of the 3084 // nodes matched in this pattern, then we have an intra-match reference. 3085 // Ignore these because the newly token factored chain should not refer to 3086 // the old nodes. 3087 unsigned NumChains = MatcherTable[MatcherIndex++]; 3088 assert(NumChains != 0 && "Can't TF zero chains"); 3089 3090 assert(ChainNodesMatched.empty() && 3091 "Should only have one EmitMergeInputChains per match"); 3092 3093 // Read all of the chained nodes. 3094 for (unsigned i = 0; i != NumChains; ++i) { 3095 unsigned RecNo = MatcherTable[MatcherIndex++]; 3096 assert(RecNo < RecordedNodes.size() && "Invalid EmitMergeInputChains"); 3097 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3098 3099 // FIXME: What if other value results of the node have uses not matched 3100 // by this pattern? 3101 if (ChainNodesMatched.back() != NodeToMatch && 3102 !RecordedNodes[RecNo].first.hasOneUse()) { 3103 ChainNodesMatched.clear(); 3104 break; 3105 } 3106 } 3107 3108 // If the inner loop broke out, the match fails. 3109 if (ChainNodesMatched.empty()) 3110 break; 3111 3112 // Merge the input chains if they are not intra-pattern references. 3113 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 3114 3115 if (!InputChain.getNode()) 3116 break; // Failed to merge. 3117 3118 continue; 3119 } 3120 3121 case OPC_EmitCopyToReg: { 3122 unsigned RecNo = MatcherTable[MatcherIndex++]; 3123 assert(RecNo < RecordedNodes.size() && "Invalid EmitCopyToReg"); 3124 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 3125 3126 if (!InputChain.getNode()) 3127 InputChain = CurDAG->getEntryNode(); 3128 3129 InputChain = CurDAG->getCopyToReg(InputChain, SDLoc(NodeToMatch), 3130 DestPhysReg, RecordedNodes[RecNo].first, 3131 InputGlue); 3132 3133 InputGlue = InputChain.getValue(1); 3134 continue; 3135 } 3136 3137 case OPC_EmitNodeXForm: { 3138 unsigned XFormNo = MatcherTable[MatcherIndex++]; 3139 unsigned RecNo = MatcherTable[MatcherIndex++]; 3140 assert(RecNo < RecordedNodes.size() && "Invalid EmitNodeXForm"); 3141 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 3142 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, nullptr)); 3143 continue; 3144 } 3145 3146 case OPC_EmitNode: 3147 case OPC_MorphNodeTo: { 3148 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 3149 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 3150 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 3151 // Get the result VT list. 3152 unsigned NumVTs = MatcherTable[MatcherIndex++]; 3153 SmallVector<EVT, 4> VTs; 3154 for (unsigned i = 0; i != NumVTs; ++i) { 3155 MVT::SimpleValueType VT = 3156 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 3157 if (VT == MVT::iPTR) 3158 VT = TLI->getPointerTy().SimpleTy; 3159 VTs.push_back(VT); 3160 } 3161 3162 if (EmitNodeInfo & OPFL_Chain) 3163 VTs.push_back(MVT::Other); 3164 if (EmitNodeInfo & OPFL_GlueOutput) 3165 VTs.push_back(MVT::Glue); 3166 3167 // This is hot code, so optimize the two most common cases of 1 and 2 3168 // results. 3169 SDVTList VTList; 3170 if (VTs.size() == 1) 3171 VTList = CurDAG->getVTList(VTs[0]); 3172 else if (VTs.size() == 2) 3173 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 3174 else 3175 VTList = CurDAG->getVTList(VTs); 3176 3177 // Get the operand list. 3178 unsigned NumOps = MatcherTable[MatcherIndex++]; 3179 SmallVector<SDValue, 8> Ops; 3180 for (unsigned i = 0; i != NumOps; ++i) { 3181 unsigned RecNo = MatcherTable[MatcherIndex++]; 3182 if (RecNo & 128) 3183 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3184 3185 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 3186 Ops.push_back(RecordedNodes[RecNo].first); 3187 } 3188 3189 // If there are variadic operands to add, handle them now. 3190 if (EmitNodeInfo & OPFL_VariadicInfo) { 3191 // Determine the start index to copy from. 3192 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 3193 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 3194 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 3195 "Invalid variadic node"); 3196 // Copy all of the variadic operands, not including a potential glue 3197 // input. 3198 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 3199 i != e; ++i) { 3200 SDValue V = NodeToMatch->getOperand(i); 3201 if (V.getValueType() == MVT::Glue) break; 3202 Ops.push_back(V); 3203 } 3204 } 3205 3206 // If this has chain/glue inputs, add them. 3207 if (EmitNodeInfo & OPFL_Chain) 3208 Ops.push_back(InputChain); 3209 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != nullptr) 3210 Ops.push_back(InputGlue); 3211 3212 // Create the node. 3213 SDNode *Res = nullptr; 3214 if (Opcode != OPC_MorphNodeTo) { 3215 // If this is a normal EmitNode command, just create the new node and 3216 // add the results to the RecordedNodes list. 3217 Res = CurDAG->getMachineNode(TargetOpc, SDLoc(NodeToMatch), 3218 VTList, Ops); 3219 3220 // Add all the non-glue/non-chain results to the RecordedNodes list. 3221 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 3222 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 3223 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 3224 nullptr)); 3225 } 3226 3227 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 3228 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops, EmitNodeInfo); 3229 } else { 3230 // NodeToMatch was eliminated by CSE when the target changed the DAG. 3231 // We will visit the equivalent node later. 3232 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 3233 return nullptr; 3234 } 3235 3236 // If the node had chain/glue results, update our notion of the current 3237 // chain and glue. 3238 if (EmitNodeInfo & OPFL_GlueOutput) { 3239 InputGlue = SDValue(Res, VTs.size()-1); 3240 if (EmitNodeInfo & OPFL_Chain) 3241 InputChain = SDValue(Res, VTs.size()-2); 3242 } else if (EmitNodeInfo & OPFL_Chain) 3243 InputChain = SDValue(Res, VTs.size()-1); 3244 3245 // If the OPFL_MemRefs glue is set on this node, slap all of the 3246 // accumulated memrefs onto it. 3247 // 3248 // FIXME: This is vastly incorrect for patterns with multiple outputs 3249 // instructions that access memory and for ComplexPatterns that match 3250 // loads. 3251 if (EmitNodeInfo & OPFL_MemRefs) { 3252 // Only attach load or store memory operands if the generated 3253 // instruction may load or store. 3254 const MCInstrDesc &MCID = TII->get(TargetOpc); 3255 bool mayLoad = MCID.mayLoad(); 3256 bool mayStore = MCID.mayStore(); 3257 3258 unsigned NumMemRefs = 0; 3259 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3260 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3261 if ((*I)->isLoad()) { 3262 if (mayLoad) 3263 ++NumMemRefs; 3264 } else if ((*I)->isStore()) { 3265 if (mayStore) 3266 ++NumMemRefs; 3267 } else { 3268 ++NumMemRefs; 3269 } 3270 } 3271 3272 MachineSDNode::mmo_iterator MemRefs = 3273 MF->allocateMemRefsArray(NumMemRefs); 3274 3275 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 3276 for (SmallVectorImpl<MachineMemOperand *>::const_iterator I = 3277 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 3278 if ((*I)->isLoad()) { 3279 if (mayLoad) 3280 *MemRefsPos++ = *I; 3281 } else if ((*I)->isStore()) { 3282 if (mayStore) 3283 *MemRefsPos++ = *I; 3284 } else { 3285 *MemRefsPos++ = *I; 3286 } 3287 } 3288 3289 cast<MachineSDNode>(Res) 3290 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 3291 } 3292 3293 DEBUG(dbgs() << " " 3294 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 3295 << " node: "; Res->dump(CurDAG); dbgs() << "\n"); 3296 3297 // If this was a MorphNodeTo then we're completely done! 3298 if (Opcode == OPC_MorphNodeTo) { 3299 // Update chain and glue uses. 3300 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3301 InputGlue, GlueResultNodesMatched, true); 3302 return Res; 3303 } 3304 3305 continue; 3306 } 3307 3308 case OPC_MarkGlueResults: { 3309 unsigned NumNodes = MatcherTable[MatcherIndex++]; 3310 3311 // Read and remember all the glue-result nodes. 3312 for (unsigned i = 0; i != NumNodes; ++i) { 3313 unsigned RecNo = MatcherTable[MatcherIndex++]; 3314 if (RecNo & 128) 3315 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 3316 3317 assert(RecNo < RecordedNodes.size() && "Invalid MarkGlueResults"); 3318 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 3319 } 3320 continue; 3321 } 3322 3323 case OPC_CompleteMatch: { 3324 // The match has been completed, and any new nodes (if any) have been 3325 // created. Patch up references to the matched dag to use the newly 3326 // created nodes. 3327 unsigned NumResults = MatcherTable[MatcherIndex++]; 3328 3329 for (unsigned i = 0; i != NumResults; ++i) { 3330 unsigned ResSlot = MatcherTable[MatcherIndex++]; 3331 if (ResSlot & 128) 3332 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 3333 3334 assert(ResSlot < RecordedNodes.size() && "Invalid CompleteMatch"); 3335 SDValue Res = RecordedNodes[ResSlot].first; 3336 3337 assert(i < NodeToMatch->getNumValues() && 3338 NodeToMatch->getValueType(i) != MVT::Other && 3339 NodeToMatch->getValueType(i) != MVT::Glue && 3340 "Invalid number of results to complete!"); 3341 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 3342 NodeToMatch->getValueType(i) == MVT::iPTR || 3343 Res.getValueType() == MVT::iPTR || 3344 NodeToMatch->getValueType(i).getSizeInBits() == 3345 Res.getValueType().getSizeInBits()) && 3346 "invalid replacement"); 3347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 3348 } 3349 3350 // If the root node defines glue, add it to the glue nodes to update list. 3351 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 3352 GlueResultNodesMatched.push_back(NodeToMatch); 3353 3354 // Update chain and glue uses. 3355 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 3356 InputGlue, GlueResultNodesMatched, false); 3357 3358 assert(NodeToMatch->use_empty() && 3359 "Didn't replace all uses of the node?"); 3360 3361 // FIXME: We just return here, which interacts correctly with SelectRoot 3362 // above. We should fix this to not return an SDNode* anymore. 3363 return nullptr; 3364 } 3365 } 3366 3367 // If the code reached this point, then the match failed. See if there is 3368 // another child to try in the current 'Scope', otherwise pop it until we 3369 // find a case to check. 3370 DEBUG(dbgs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 3371 ++NumDAGIselRetries; 3372 while (1) { 3373 if (MatchScopes.empty()) { 3374 CannotYetSelect(NodeToMatch); 3375 return nullptr; 3376 } 3377 3378 // Restore the interpreter state back to the point where the scope was 3379 // formed. 3380 MatchScope &LastScope = MatchScopes.back(); 3381 RecordedNodes.resize(LastScope.NumRecordedNodes); 3382 NodeStack.clear(); 3383 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 3384 N = NodeStack.back(); 3385 3386 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 3387 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 3388 MatcherIndex = LastScope.FailIndex; 3389 3390 DEBUG(dbgs() << " Continuing at " << MatcherIndex << "\n"); 3391 3392 InputChain = LastScope.InputChain; 3393 InputGlue = LastScope.InputGlue; 3394 if (!LastScope.HasChainNodesMatched) 3395 ChainNodesMatched.clear(); 3396 if (!LastScope.HasGlueResultNodesMatched) 3397 GlueResultNodesMatched.clear(); 3398 3399 // Check to see what the offset is at the new MatcherIndex. If it is zero 3400 // we have reached the end of this scope, otherwise we have another child 3401 // in the current scope to try. 3402 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 3403 if (NumToSkip & 128) 3404 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 3405 3406 // If we have another child in this scope to match, update FailIndex and 3407 // try it. 3408 if (NumToSkip != 0) { 3409 LastScope.FailIndex = MatcherIndex+NumToSkip; 3410 break; 3411 } 3412 3413 // End of this scope, pop it and try the next child in the containing 3414 // scope. 3415 MatchScopes.pop_back(); 3416 } 3417 } 3418 } 3419 3420 3421 3422 void SelectionDAGISel::CannotYetSelect(SDNode *N) { 3423 std::string msg; 3424 raw_string_ostream Msg(msg); 3425 Msg << "Cannot select: "; 3426 3427 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 3428 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 3429 N->getOpcode() != ISD::INTRINSIC_VOID) { 3430 N->printrFull(Msg, CurDAG); 3431 Msg << "\nIn function: " << MF->getName(); 3432 } else { 3433 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 3434 unsigned iid = 3435 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3436 if (iid < Intrinsic::num_intrinsics) 3437 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3438 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3439 Msg << "target intrinsic %" << TII->getName(iid); 3440 else 3441 Msg << "unknown intrinsic #" << iid; 3442 } 3443 report_fatal_error(Msg.str()); 3444 } 3445 3446 char SelectionDAGISel::ID = 0; 3447