| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 28 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
29 : Mips::J),
45 if ((Opc == Mips::LW) || (Opc == Mips::LD) ||
46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
67 if ((Opc == Mips::SW) || (Opc == Mips::SD) ||
68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164))
[all...] |
| Mips16InstrInfo.cpp | 35 : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
67 if (Mips::CPU16RegsRegClass.contains(DestReg) &&
68 Mips::GPR32RegClass.contains(SrcReg))
69 Opc = Mips::MoveR3216;
70 else if (Mips::GPR32RegClass.contains(DestReg) &&
71 Mips::CPU16RegsRegClass.contains(SrcReg))
72 Opc = Mips::Move32R16;
73 else if ((SrcReg == Mips::HI0) &&
74 (Mips::CPU16RegsRegClass.contains(DestReg)))
75 Opc = Mips::Mfhi16, SrcReg = 0
[all...] |
| MipsRegisterInfo.cpp | 1 //===-- MipsRegisterInfo.cpp - MIPS Register Information -== --------------===//
10 // This file contains the MIPS implementation of the TargetRegisterInfo class.
15 #include "Mips.h"
42 #define DEBUG_TYPE "mips-reg-info"
47 MipsRegisterInfo::MipsRegisterInfo() : MipsGenRegisterInfo(Mips::RA) {}
49 unsigned MipsRegisterInfo::getPICCallReg() { return Mips::T9; }
55 return ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
64 case Mips::GPR32RegClassID:
65 case Mips::GPR64RegClassID
[all...] |
| MipsOptionRecord.h | 11 // ELF files. Arbitrary information (e.g. register usage) can be stored in Mips
12 // specific ELF sections like .Mips.options. Specific records should subclass
15 // about .Mips.option can be found in the SysV ABI and the 64-bit ELF Object
46 GPR32RegClass = &(TRI->getRegClass(Mips::GPR32RegClassID));
47 GPR64RegClass = &(TRI->getRegClass(Mips::GPR64RegClassID));
48 FGR32RegClass = &(TRI->getRegClass(Mips::FGR32RegClassID));
49 FGR64RegClass = &(TRI->getRegClass(Mips::FGR64RegClassID));
50 AFGR64RegClass = &(TRI->getRegClass(Mips::AFGR64RegClassID));
51 MSA128BRegClass = &(TRI->getRegClass(Mips::MSA128BRegClassID));
52 COP0RegClass = &(TRI->getRegClass(Mips::COP0RegClassID))
[all...] |
| MipsSERegisterInfo.cpp | 16 #include "Mips.h"
43 #define DEBUG_TYPE "mips-reg-info"
60 return &Mips::GPR32RegClass;
63 return &Mips::GPR64RegClass;
71 case Mips::LD_B:
72 case Mips::ST_B:
74 case Mips::LD_H:
75 case Mips::ST_H:
77 case Mips::LD_W:
78 case Mips::ST_W
[all...] |
| MipsLongBranch.cpp | 16 #include "Mips.h"
33 #define DEBUG_TYPE "mips-long-branch"
38 "skip-mips-long-branch",
40 cl::desc("MIPS: Skip long branch pass."),
44 "force-mips-long-branch",
46 cl::desc("MIPS: Expand all branches to long format."),
71 return "Mips Long Branch";
276 unsigned BalOp = Subtarget.hasMips32r6() ? Mips::BAL : Mips::BAL_BR;
295 BuildMI(*LongBrMBB, Pos, DL, TII->get(Mips::ADDiu), Mips::SP
[all...] |
| Mips16ISelLowering.cpp | 27 #define DEBUG_TYPE "mips-lower"
33 "pseudos for Mips 16"),
128 addRegisterClass(MVT::i32, &Mips::CPU16RegsRegClass);
175 case Mips::SelBeqZ:
176 return emitSel16(Mips::BeqzRxImm16, MI, BB);
177 case Mips::SelBneZ:
178 return emitSel16(Mips::BnezRxImm16, MI, BB);
179 case Mips::SelTBteqZCmpi:
180 return emitSeliT16(Mips::Bteqz16, Mips::CmpiRxImmX16, MI, BB)
[all...] |
| MipsMachineFunction.cpp | 1 //===-- MipsMachineFunctionInfo.cpp - Private data used for Mips ----------===//
24 FixGlobalBaseReg("mips-fix-global-base-reg", cl::Hidden, cl::init(true),
43 ? &Mips::CPU16RegsRegClass
45 ? &Mips::GPRMM16RegClass
49 ? &Mips::GPR64RegClass
50 : &Mips::GPR32RegClass;
62 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
70 ? &Mips::GPR64RegClass
71 : &Mips::GPR32RegClass;
83 const TargetRegisterClass *RC = &Mips::GPR32RegClass
[all...] |
| MipsSEFrameLowering.cpp | 38 if (Mips::ACC64RegClass.contains(Src))
39 return std::make_pair((unsigned)Mips::PseudoMFHI,
40 (unsigned)Mips::PseudoMFLO);
42 if (Mips::ACC64DSPRegClass.contains(Src))
43 return std::make_pair((unsigned)Mips::MFHI_DSP, (unsigned)Mips::MFLO_DSP);
45 if (Mips::ACC128RegClass.contains(Src))
46 return std::make_pair((unsigned)Mips::PseudoMFHI64,
47 (unsigned)Mips::PseudoMFLO64);
100 case Mips::LOAD_CCOND_DSP
[all...] |
| MipsAsmPrinter.cpp | 1 //===-- MipsAsmPrinter.cpp - Mips LLVM Assembly Printer -------------------===//
11 // of machine-dependent LLVM code to GAS-format MIPS assembly language.
18 #include "Mips.h"
54 #define DEBUG_TYPE "mips-asm-printer"
105 TmpInst0.setOpcode(Mips::JALR64);
109 TmpInst0.setOpcode(Mips::JALR);
113 TmpInst0.setOpcode(Mips::JR_MM);
116 TmpInst0.setOpcode(Mips::JR);
122 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO
[all...] |
| Mips16FrameLowering.cpp | 57 TII.makeFrame(Mips::SP, StackSize, MBB, MBBI);
82 BuildMI(MBB, MBBI, dl, TII.get(Mips::MoveR3216), Mips::S0)
83 .addReg(Mips::SP).setMIFlag(MachineInstr::FrameSetup);
100 BuildMI(MBB, MBBI, dl, TII.get(Mips::Move32R16), Mips::SP)
101 .addReg(Mips::S0);
105 TII.restoreFrame(Mips::SP, StackSize, MBB, MBBI);
128 bool IsRAAndRetAddrIsTaken = (Reg == Mips::RA)
167 bool SaveS2 = Reserved[Mips::S2]
[all...] |
| MipsSEISelDAGToDAG.cpp | 16 #include "Mips.h"
37 #define DEBUG_TYPE "mips-isel"
53 MIB.addReg(Mips::DSPPos, Flag);
56 MIB.addReg(Mips::DSPSCount, Flag);
59 MIB.addReg(Mips::DSPCarry, Flag);
62 MIB.addReg(Mips::DSPOutFlag, Flag);
65 MIB.addReg(Mips::DSPCCond, Flag);
68 MIB.addReg(Mips::DSPEFI, Flag);
75 case 0: return Mips::MSAIR;
76 case 1: return Mips::MSACSR
[all...] |
| MipsFastISel.cpp | 1 //===-- MipsastISel.cpp - Mips FastISel implementation
241 Opc = Mips::AND;
244 Opc = Mips::OR;
247 Opc = Mips::XOR;
265 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
284 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass);
285 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Mips::LEA_ADDiu),
298 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
308 unsigned Opc = Mips::ADDiu;
309 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm)
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsABIInfo.cpp | 1 //===---- MipsABIInfo.cpp - Information about MIPS ABI's ------------------===//
19 static const MCPhysReg O32IntRegs[4] = {Mips::A0, Mips::A1, Mips::A2, Mips::A3};
22 Mips::A0_64, Mips::A1_64, Mips::A2_64, Mips::A3_64,
23 Mips::T0_64, Mips::T1_64, Mips::T2_64, Mips::T3_64}
[all...] |
| MipsAsmBackend.cpp | 1 //===-- MipsAsmBackend.cpp - Mips Asm Backend ----------------------------===//
46 case Mips::fixup_Mips_LO16:
47 case Mips::fixup_Mips_GPREL16:
48 case Mips::fixup_Mips_GPOFF_HI:
49 case Mips::fixup_Mips_GPOFF_LO:
50 case Mips::fixup_Mips_GOT_PAGE:
51 case Mips::fixup_Mips_GOT_OFST:
52 case Mips::fixup_Mips_GOT_DISP:
53 case Mips::fixup_Mips_GOT_LO16:
54 case Mips::fixup_Mips_CALL_LO16
[all...] |
| MipsNaClELFStreamer.cpp | 1 //===-- MipsNaClELFStreamer.cpp - ELF Object Output for Mips NaCl ---------===//
10 // This file implements MCELFStreamer for Mips NaCl. It emits .o object files
20 #include "Mips.h"
27 #define DEBUG_TYPE "mips-mc-nacl"
31 const unsigned IndirectBranchMaskReg = Mips::T6;
32 const unsigned LoadStoreStackMaskReg = Mips::T7;
51 if (MI.getOpcode() == Mips::JALR) {
55 return MI.getOperand(0).getReg() == Mips::ZERO;
57 return MI.getOpcode() == Mips::JR;
62 && MI.getOperand(0).getReg() == Mips::SP)
[all...] |
| MipsABIFlagsSection.cpp | 1 //===-- MipsABIFlagsSection.cpp - Mips ELF ABI Flags Section ---*- C++ -*--===//
17 return Mips::Val_GNU_MIPS_ABI_FP_ANY;
19 return Mips::Val_GNU_MIPS_ABI_FP_SOFT;
21 return Mips::Val_GNU_MIPS_ABI_FP_XX;
23 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
26 return OddSPReg ? Mips::Val_GNU_MIPS_ABI_FP_64
27 : Mips::Val_GNU_MIPS_ABI_FP_64A;
28 return Mips::Val_GNU_MIPS_ABI_FP_DOUBLE;
49 return (uint8_t)Mips::AFL_REG_32;
|
| MipsMCCodeEmitter.cpp | 1 //===-- MipsMCCodeEmitter.cpp - Convert Mips Code to Machine Code ---------===//
69 case Mips::DSLL:
70 Inst.setOpcode(Mips::DSLL32);
72 case Mips::DSRL:
73 Inst.setOpcode(Mips::DSRL32);
75 case Mips::DSRA:
76 Inst.setOpcode(Mips::DSRA32);
78 case Mips::DROTR:
79 Inst.setOpcode(Mips::DROTR32);
88 if (Opcode == Mips::DEXT
[all...] |
| MipsELFObjectWriter.cpp | 1 //===-- MipsELFObjectWriter.cpp - Mips ELF Writer -------------------------===//
71 case Mips::fixup_Mips_NONE:
73 case Mips::fixup_Mips_16:
76 case Mips::fixup_Mips_32:
83 case Mips::fixup_Mips_Branch_PCRel:
84 case Mips::fixup_Mips_PC16:
86 case Mips::fixup_MICROMIPS_PC7_S1:
88 case Mips::fixup_MICROMIPS_PC10_S1:
90 case Mips::fixup_MICROMIPS_PC16_S1:
92 case Mips::fixup_MIPS_PC19_S2
[all...] |
| MipsABIFlagsSection.h | 1 //===-- MipsABIFlagsSection.h - Mips ELF ABI Flags Section -----*- C++ -*--===//
29 // The revision of ISA: 0 for MIPS V and below, 1-n otherwise.
32 Mips::AFL_REG GPRSize;
34 Mips::AFL_REG CPR1Size;
36 Mips::AFL_REG CPR2Size;
52 : Version(0), ISALevel(0), ISARevision(0), GPRSize(Mips::AFL_REG_NONE),
53 CPR1Size(Mips::AFL_REG_NONE), CPR2Size(Mips::AFL_REG_NONE),
71 Value |= (uint32_t)Mips::AFL_FLAGS1_ODDSPREG;
130 GPRSize = P.isGP64bit() ? Mips::AFL_REG_64 : Mips::AFL_REG_32
[all...] |
| /external/llvm/lib/Target/Mips/InstPrinter/ |
| MipsInstPrinter.cpp | 1 //===-- MipsInstPrinter.cpp - Convert Mips MCInst to assembly syntax ------===//
10 // This class prints an Mips MCInst to a .s file.
37 const char* Mips::MipsFCCToString(Mips::CondCode CC) {
84 case Mips::RDHWR:
85 case Mips::RDHWR64:
89 case Mips::Save16:
94 case Mips::SaveX16:
99 case Mips::Restore16:
104 case Mips::RestoreX16
[all...] |
| /build/target/product/ |
| sdk_phone_mips.mk | 34 PRODUCT_MODEL := Android SDK for Mips
|
| /external/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 1 //===-- MipsAsmParser.cpp - Parse Mips assembly to MCInst instructions ----===//
38 #define DEBUG_TYPE "mips-asm-parser"
93 Mips::FeatureMips1, Mips::FeatureMips2, Mips::FeatureMips3,
94 Mips::FeatureMips3_32, Mips::FeatureMips3_32r2, Mips::FeatureMips4,
95 Mips::FeatureMips4_32, Mips::FeatureMips4_32r2, Mips::FeatureMips5
[all...] |
| /external/llvm/host/include/llvm/Config/ |
| Targets.def | 27 LLVM_TARGET(Mips)
|
| /frameworks/compile/mclinker/lib/Target/Mips/ |
| MipsAbiFlags.cpp | 108 llvm_unreachable("Unknown MIPS architecture flag");
132 llvm_unreachable("Unknown MIPS architecture flag");
139 return llvm::Mips::AFL_EXT_NONE;
140 case llvm::ELF::EF_MIPS_MACH_3900: return llvm::Mips::AFL_EXT_3900;
141 case llvm::ELF::EF_MIPS_MACH_4010: return llvm::Mips::AFL_EXT_4010;
142 case llvm::ELF::EF_MIPS_MACH_4100: return llvm::Mips::AFL_EXT_4010;
143 case llvm::ELF::EF_MIPS_MACH_4111: return llvm::Mips::AFL_EXT_4111;
144 case llvm::ELF::EF_MIPS_MACH_4120: return llvm::Mips::AFL_EXT_4120;
145 case llvm::ELF::EF_MIPS_MACH_4650: return llvm::Mips::AFL_EXT_4650;
146 case llvm::ELF::EF_MIPS_MACH_5400: return llvm::Mips::AFL_EXT_5400
[all...] |
