1 //===-- ARMFastISel.cpp - ARM FastISel implementation ---------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the ARM-specific support for the FastISel class. Some 11 // of the target-specific code is generated by tablegen in the file 12 // ARMGenFastISel.inc, which is #included here. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "ARM.h" 17 #include "ARMBaseInstrInfo.h" 18 #include "ARMCallingConv.h" 19 #include "ARMConstantPoolValue.h" 20 #include "ARMSubtarget.h" 21 #include "ARMTargetMachine.h" 22 #include "MCTargetDesc/ARMAddressingModes.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/CodeGen/Analysis.h" 25 #include "llvm/CodeGen/FastISel.h" 26 #include "llvm/CodeGen/FunctionLoweringInfo.h" 27 #include "llvm/CodeGen/MachineConstantPool.h" 28 #include "llvm/CodeGen/MachineFrameInfo.h" 29 #include "llvm/CodeGen/MachineInstrBuilder.h" 30 #include "llvm/CodeGen/MachineMemOperand.h" 31 #include "llvm/CodeGen/MachineModuleInfo.h" 32 #include "llvm/CodeGen/MachineRegisterInfo.h" 33 #include "llvm/IR/CallingConv.h" 34 #include "llvm/IR/DataLayout.h" 35 #include "llvm/IR/DerivedTypes.h" 36 #include "llvm/IR/GlobalVariable.h" 37 #include "llvm/IR/Instructions.h" 38 #include "llvm/IR/IntrinsicInst.h" 39 #include "llvm/IR/Module.h" 40 #include "llvm/IR/Operator.h" 41 #include "llvm/Support/CallSite.h" 42 #include "llvm/Support/CommandLine.h" 43 #include "llvm/Support/ErrorHandling.h" 44 #include "llvm/Support/GetElementPtrTypeIterator.h" 45 #include "llvm/Target/TargetInstrInfo.h" 46 #include "llvm/Target/TargetLowering.h" 47 #include "llvm/Target/TargetMachine.h" 48 #include "llvm/Target/TargetOptions.h" 49 using namespace llvm; 50 51 extern cl::opt<bool> EnableARMLongCalls; 52 53 namespace { 54 55 // All possible address modes, plus some. 56 typedef struct Address { 57 enum { 58 RegBase, 59 FrameIndexBase 60 } BaseType; 61 62 union { 63 unsigned Reg; 64 int FI; 65 } Base; 66 67 int Offset; 68 69 // Innocuous defaults for our address. 70 Address() 71 : BaseType(RegBase), Offset(0) { 72 Base.Reg = 0; 73 } 74 } Address; 75 76 class ARMFastISel : public FastISel { 77 78 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can 79 /// make the right decision when generating code for different targets. 80 const ARMSubtarget *Subtarget; 81 const TargetMachine &TM; 82 const TargetInstrInfo &TII; 83 const TargetLowering &TLI; 84 ARMFunctionInfo *AFI; 85 86 // Convenience variables to avoid some queries. 87 bool isThumb2; 88 LLVMContext *Context; 89 90 public: 91 explicit ARMFastISel(FunctionLoweringInfo &funcInfo, 92 const TargetLibraryInfo *libInfo) 93 : FastISel(funcInfo, libInfo), 94 TM(funcInfo.MF->getTarget()), 95 TII(*TM.getInstrInfo()), 96 TLI(*TM.getTargetLowering()) { 97 Subtarget = &TM.getSubtarget<ARMSubtarget>(); 98 AFI = funcInfo.MF->getInfo<ARMFunctionInfo>(); 99 isThumb2 = AFI->isThumbFunction(); 100 Context = &funcInfo.Fn->getContext(); 101 } 102 103 // Code from FastISel.cpp. 104 private: 105 unsigned FastEmitInst_(unsigned MachineInstOpcode, 106 const TargetRegisterClass *RC); 107 unsigned FastEmitInst_r(unsigned MachineInstOpcode, 108 const TargetRegisterClass *RC, 109 unsigned Op0, bool Op0IsKill); 110 unsigned FastEmitInst_rr(unsigned MachineInstOpcode, 111 const TargetRegisterClass *RC, 112 unsigned Op0, bool Op0IsKill, 113 unsigned Op1, bool Op1IsKill); 114 unsigned FastEmitInst_rrr(unsigned MachineInstOpcode, 115 const TargetRegisterClass *RC, 116 unsigned Op0, bool Op0IsKill, 117 unsigned Op1, bool Op1IsKill, 118 unsigned Op2, bool Op2IsKill); 119 unsigned FastEmitInst_ri(unsigned MachineInstOpcode, 120 const TargetRegisterClass *RC, 121 unsigned Op0, bool Op0IsKill, 122 uint64_t Imm); 123 unsigned FastEmitInst_rf(unsigned MachineInstOpcode, 124 const TargetRegisterClass *RC, 125 unsigned Op0, bool Op0IsKill, 126 const ConstantFP *FPImm); 127 unsigned FastEmitInst_rri(unsigned MachineInstOpcode, 128 const TargetRegisterClass *RC, 129 unsigned Op0, bool Op0IsKill, 130 unsigned Op1, bool Op1IsKill, 131 uint64_t Imm); 132 unsigned FastEmitInst_i(unsigned MachineInstOpcode, 133 const TargetRegisterClass *RC, 134 uint64_t Imm); 135 unsigned FastEmitInst_ii(unsigned MachineInstOpcode, 136 const TargetRegisterClass *RC, 137 uint64_t Imm1, uint64_t Imm2); 138 139 unsigned FastEmitInst_extractsubreg(MVT RetVT, 140 unsigned Op0, bool Op0IsKill, 141 uint32_t Idx); 142 143 // Backend specific FastISel code. 144 private: 145 virtual bool TargetSelectInstruction(const Instruction *I); 146 virtual unsigned TargetMaterializeConstant(const Constant *C); 147 virtual unsigned TargetMaterializeAlloca(const AllocaInst *AI); 148 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 149 const LoadInst *LI); 150 virtual bool FastLowerArguments(); 151 private: 152 #include "ARMGenFastISel.inc" 153 154 // Instruction selection routines. 155 private: 156 bool SelectLoad(const Instruction *I); 157 bool SelectStore(const Instruction *I); 158 bool SelectBranch(const Instruction *I); 159 bool SelectIndirectBr(const Instruction *I); 160 bool SelectCmp(const Instruction *I); 161 bool SelectFPExt(const Instruction *I); 162 bool SelectFPTrunc(const Instruction *I); 163 bool SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode); 164 bool SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode); 165 bool SelectIToFP(const Instruction *I, bool isSigned); 166 bool SelectFPToI(const Instruction *I, bool isSigned); 167 bool SelectDiv(const Instruction *I, bool isSigned); 168 bool SelectRem(const Instruction *I, bool isSigned); 169 bool SelectCall(const Instruction *I, const char *IntrMemName); 170 bool SelectIntrinsicCall(const IntrinsicInst &I); 171 bool SelectSelect(const Instruction *I); 172 bool SelectRet(const Instruction *I); 173 bool SelectTrunc(const Instruction *I); 174 bool SelectIntExt(const Instruction *I); 175 bool SelectShift(const Instruction *I, ARM_AM::ShiftOpc ShiftTy); 176 177 // Utility routines. 178 private: 179 bool isTypeLegal(Type *Ty, MVT &VT); 180 bool isLoadTypeLegal(Type *Ty, MVT &VT); 181 bool ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, 182 bool isZExt); 183 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 184 unsigned Alignment = 0, bool isZExt = true, 185 bool allocReg = true); 186 bool ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, 187 unsigned Alignment = 0); 188 bool ARMComputeAddress(const Value *Obj, Address &Addr); 189 void ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3); 190 bool ARMIsMemCpySmall(uint64_t Len); 191 bool ARMTryEmitSmallMemCpy(Address Dest, Address Src, uint64_t Len, 192 unsigned Alignment); 193 unsigned ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, bool isZExt); 194 unsigned ARMMaterializeFP(const ConstantFP *CFP, MVT VT); 195 unsigned ARMMaterializeInt(const Constant *C, MVT VT); 196 unsigned ARMMaterializeGV(const GlobalValue *GV, MVT VT); 197 unsigned ARMMoveToFPReg(MVT VT, unsigned SrcReg); 198 unsigned ARMMoveToIntReg(MVT VT, unsigned SrcReg); 199 unsigned ARMSelectCallOp(bool UseReg); 200 unsigned ARMLowerPICELF(const GlobalValue *GV, unsigned Align, MVT VT); 201 202 // Call handling routines. 203 private: 204 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, 205 bool Return, 206 bool isVarArg); 207 bool ProcessCallArgs(SmallVectorImpl<Value*> &Args, 208 SmallVectorImpl<unsigned> &ArgRegs, 209 SmallVectorImpl<MVT> &ArgVTs, 210 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 211 SmallVectorImpl<unsigned> &RegArgs, 212 CallingConv::ID CC, 213 unsigned &NumBytes, 214 bool isVarArg); 215 unsigned getLibcallReg(const Twine &Name); 216 bool FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 217 const Instruction *I, CallingConv::ID CC, 218 unsigned &NumBytes, bool isVarArg); 219 bool ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call); 220 221 // OptionalDef handling routines. 222 private: 223 bool isARMNEONPred(const MachineInstr *MI); 224 bool DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR); 225 const MachineInstrBuilder &AddOptionalDefs(const MachineInstrBuilder &MIB); 226 void AddLoadStoreOperands(MVT VT, Address &Addr, 227 const MachineInstrBuilder &MIB, 228 unsigned Flags, bool useAM3); 229 }; 230 231 } // end anonymous namespace 232 233 #include "ARMGenCallingConv.inc" 234 235 // DefinesOptionalPredicate - This is different from DefinesPredicate in that 236 // we don't care about implicit defs here, just places we'll need to add a 237 // default CCReg argument. Sets CPSR if we're setting CPSR instead of CCR. 238 bool ARMFastISel::DefinesOptionalPredicate(MachineInstr *MI, bool *CPSR) { 239 if (!MI->hasOptionalDef()) 240 return false; 241 242 // Look to see if our OptionalDef is defining CPSR or CCR. 243 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 244 const MachineOperand &MO = MI->getOperand(i); 245 if (!MO.isReg() || !MO.isDef()) continue; 246 if (MO.getReg() == ARM::CPSR) 247 *CPSR = true; 248 } 249 return true; 250 } 251 252 bool ARMFastISel::isARMNEONPred(const MachineInstr *MI) { 253 const MCInstrDesc &MCID = MI->getDesc(); 254 255 // If we're a thumb2 or not NEON function we were handled via isPredicable. 256 if ((MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainNEON || 257 AFI->isThumb2Function()) 258 return false; 259 260 for (unsigned i = 0, e = MCID.getNumOperands(); i != e; ++i) 261 if (MCID.OpInfo[i].isPredicate()) 262 return true; 263 264 return false; 265 } 266 267 // If the machine is predicable go ahead and add the predicate operands, if 268 // it needs default CC operands add those. 269 // TODO: If we want to support thumb1 then we'll need to deal with optional 270 // CPSR defs that need to be added before the remaining operands. See s_cc_out 271 // for descriptions why. 272 const MachineInstrBuilder & 273 ARMFastISel::AddOptionalDefs(const MachineInstrBuilder &MIB) { 274 MachineInstr *MI = &*MIB; 275 276 // Do we use a predicate? or... 277 // Are we NEON in ARM mode and have a predicate operand? If so, I know 278 // we're not predicable but add it anyways. 279 if (TII.isPredicable(MI) || isARMNEONPred(MI)) 280 AddDefaultPred(MIB); 281 282 // Do we optionally set a predicate? Preds is size > 0 iff the predicate 283 // defines CPSR. All other OptionalDefines in ARM are the CCR register. 284 bool CPSR = false; 285 if (DefinesOptionalPredicate(MI, &CPSR)) { 286 if (CPSR) 287 AddDefaultT1CC(MIB); 288 else 289 AddDefaultCC(MIB); 290 } 291 return MIB; 292 } 293 294 unsigned ARMFastISel::FastEmitInst_(unsigned MachineInstOpcode, 295 const TargetRegisterClass* RC) { 296 unsigned ResultReg = createResultReg(RC); 297 const MCInstrDesc &II = TII.get(MachineInstOpcode); 298 299 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)); 300 return ResultReg; 301 } 302 303 unsigned ARMFastISel::FastEmitInst_r(unsigned MachineInstOpcode, 304 const TargetRegisterClass *RC, 305 unsigned Op0, bool Op0IsKill) { 306 unsigned ResultReg = createResultReg(RC); 307 const MCInstrDesc &II = TII.get(MachineInstOpcode); 308 309 if (II.getNumDefs() >= 1) { 310 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 311 .addReg(Op0, Op0IsKill * RegState::Kill)); 312 } else { 313 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 314 .addReg(Op0, Op0IsKill * RegState::Kill)); 315 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 316 TII.get(TargetOpcode::COPY), ResultReg) 317 .addReg(II.ImplicitDefs[0])); 318 } 319 return ResultReg; 320 } 321 322 unsigned ARMFastISel::FastEmitInst_rr(unsigned MachineInstOpcode, 323 const TargetRegisterClass *RC, 324 unsigned Op0, bool Op0IsKill, 325 unsigned Op1, bool Op1IsKill) { 326 unsigned ResultReg = createResultReg(RC); 327 const MCInstrDesc &II = TII.get(MachineInstOpcode); 328 329 if (II.getNumDefs() >= 1) { 330 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 331 .addReg(Op0, Op0IsKill * RegState::Kill) 332 .addReg(Op1, Op1IsKill * RegState::Kill)); 333 } else { 334 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 335 .addReg(Op0, Op0IsKill * RegState::Kill) 336 .addReg(Op1, Op1IsKill * RegState::Kill)); 337 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 338 TII.get(TargetOpcode::COPY), ResultReg) 339 .addReg(II.ImplicitDefs[0])); 340 } 341 return ResultReg; 342 } 343 344 unsigned ARMFastISel::FastEmitInst_rrr(unsigned MachineInstOpcode, 345 const TargetRegisterClass *RC, 346 unsigned Op0, bool Op0IsKill, 347 unsigned Op1, bool Op1IsKill, 348 unsigned Op2, bool Op2IsKill) { 349 unsigned ResultReg = createResultReg(RC); 350 const MCInstrDesc &II = TII.get(MachineInstOpcode); 351 352 if (II.getNumDefs() >= 1) { 353 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 354 .addReg(Op0, Op0IsKill * RegState::Kill) 355 .addReg(Op1, Op1IsKill * RegState::Kill) 356 .addReg(Op2, Op2IsKill * RegState::Kill)); 357 } else { 358 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 359 .addReg(Op0, Op0IsKill * RegState::Kill) 360 .addReg(Op1, Op1IsKill * RegState::Kill) 361 .addReg(Op2, Op2IsKill * RegState::Kill)); 362 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 363 TII.get(TargetOpcode::COPY), ResultReg) 364 .addReg(II.ImplicitDefs[0])); 365 } 366 return ResultReg; 367 } 368 369 unsigned ARMFastISel::FastEmitInst_ri(unsigned MachineInstOpcode, 370 const TargetRegisterClass *RC, 371 unsigned Op0, bool Op0IsKill, 372 uint64_t Imm) { 373 unsigned ResultReg = createResultReg(RC); 374 const MCInstrDesc &II = TII.get(MachineInstOpcode); 375 376 if (II.getNumDefs() >= 1) { 377 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 378 .addReg(Op0, Op0IsKill * RegState::Kill) 379 .addImm(Imm)); 380 } else { 381 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 382 .addReg(Op0, Op0IsKill * RegState::Kill) 383 .addImm(Imm)); 384 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 385 TII.get(TargetOpcode::COPY), ResultReg) 386 .addReg(II.ImplicitDefs[0])); 387 } 388 return ResultReg; 389 } 390 391 unsigned ARMFastISel::FastEmitInst_rf(unsigned MachineInstOpcode, 392 const TargetRegisterClass *RC, 393 unsigned Op0, bool Op0IsKill, 394 const ConstantFP *FPImm) { 395 unsigned ResultReg = createResultReg(RC); 396 const MCInstrDesc &II = TII.get(MachineInstOpcode); 397 398 if (II.getNumDefs() >= 1) { 399 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 400 .addReg(Op0, Op0IsKill * RegState::Kill) 401 .addFPImm(FPImm)); 402 } else { 403 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 404 .addReg(Op0, Op0IsKill * RegState::Kill) 405 .addFPImm(FPImm)); 406 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 407 TII.get(TargetOpcode::COPY), ResultReg) 408 .addReg(II.ImplicitDefs[0])); 409 } 410 return ResultReg; 411 } 412 413 unsigned ARMFastISel::FastEmitInst_rri(unsigned MachineInstOpcode, 414 const TargetRegisterClass *RC, 415 unsigned Op0, bool Op0IsKill, 416 unsigned Op1, bool Op1IsKill, 417 uint64_t Imm) { 418 unsigned ResultReg = createResultReg(RC); 419 const MCInstrDesc &II = TII.get(MachineInstOpcode); 420 421 if (II.getNumDefs() >= 1) { 422 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 423 .addReg(Op0, Op0IsKill * RegState::Kill) 424 .addReg(Op1, Op1IsKill * RegState::Kill) 425 .addImm(Imm)); 426 } else { 427 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 428 .addReg(Op0, Op0IsKill * RegState::Kill) 429 .addReg(Op1, Op1IsKill * RegState::Kill) 430 .addImm(Imm)); 431 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 432 TII.get(TargetOpcode::COPY), ResultReg) 433 .addReg(II.ImplicitDefs[0])); 434 } 435 return ResultReg; 436 } 437 438 unsigned ARMFastISel::FastEmitInst_i(unsigned MachineInstOpcode, 439 const TargetRegisterClass *RC, 440 uint64_t Imm) { 441 unsigned ResultReg = createResultReg(RC); 442 const MCInstrDesc &II = TII.get(MachineInstOpcode); 443 444 if (II.getNumDefs() >= 1) { 445 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 446 .addImm(Imm)); 447 } else { 448 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 449 .addImm(Imm)); 450 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 451 TII.get(TargetOpcode::COPY), ResultReg) 452 .addReg(II.ImplicitDefs[0])); 453 } 454 return ResultReg; 455 } 456 457 unsigned ARMFastISel::FastEmitInst_ii(unsigned MachineInstOpcode, 458 const TargetRegisterClass *RC, 459 uint64_t Imm1, uint64_t Imm2) { 460 unsigned ResultReg = createResultReg(RC); 461 const MCInstrDesc &II = TII.get(MachineInstOpcode); 462 463 if (II.getNumDefs() >= 1) { 464 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg) 465 .addImm(Imm1).addImm(Imm2)); 466 } else { 467 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II) 468 .addImm(Imm1).addImm(Imm2)); 469 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 470 TII.get(TargetOpcode::COPY), 471 ResultReg) 472 .addReg(II.ImplicitDefs[0])); 473 } 474 return ResultReg; 475 } 476 477 unsigned ARMFastISel::FastEmitInst_extractsubreg(MVT RetVT, 478 unsigned Op0, bool Op0IsKill, 479 uint32_t Idx) { 480 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); 481 assert(TargetRegisterInfo::isVirtualRegister(Op0) && 482 "Cannot yet extract from physregs"); 483 484 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 485 DL, TII.get(TargetOpcode::COPY), ResultReg) 486 .addReg(Op0, getKillRegState(Op0IsKill), Idx)); 487 return ResultReg; 488 } 489 490 // TODO: Don't worry about 64-bit now, but when this is fixed remove the 491 // checks from the various callers. 492 unsigned ARMFastISel::ARMMoveToFPReg(MVT VT, unsigned SrcReg) { 493 if (VT == MVT::f64) return 0; 494 495 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 496 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 497 TII.get(ARM::VMOVSR), MoveReg) 498 .addReg(SrcReg)); 499 return MoveReg; 500 } 501 502 unsigned ARMFastISel::ARMMoveToIntReg(MVT VT, unsigned SrcReg) { 503 if (VT == MVT::i64) return 0; 504 505 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); 506 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 507 TII.get(ARM::VMOVRS), MoveReg) 508 .addReg(SrcReg)); 509 return MoveReg; 510 } 511 512 // For double width floating point we need to materialize two constants 513 // (the high and the low) into integer registers then use a move to get 514 // the combined constant into an FP reg. 515 unsigned ARMFastISel::ARMMaterializeFP(const ConstantFP *CFP, MVT VT) { 516 const APFloat Val = CFP->getValueAPF(); 517 bool is64bit = VT == MVT::f64; 518 519 // This checks to see if we can use VFP3 instructions to materialize 520 // a constant, otherwise we have to go through the constant pool. 521 if (TLI.isFPImmLegal(Val, VT)) { 522 int Imm; 523 unsigned Opc; 524 if (is64bit) { 525 Imm = ARM_AM::getFP64Imm(Val); 526 Opc = ARM::FCONSTD; 527 } else { 528 Imm = ARM_AM::getFP32Imm(Val); 529 Opc = ARM::FCONSTS; 530 } 531 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 532 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 533 DestReg) 534 .addImm(Imm)); 535 return DestReg; 536 } 537 538 // Require VFP2 for loading fp constants. 539 if (!Subtarget->hasVFP2()) return false; 540 541 // MachineConstantPool wants an explicit alignment. 542 unsigned Align = TD.getPrefTypeAlignment(CFP->getType()); 543 if (Align == 0) { 544 // TODO: Figure out if this is correct. 545 Align = TD.getTypeAllocSize(CFP->getType()); 546 } 547 unsigned Idx = MCP.getConstantPoolIndex(cast<Constant>(CFP), Align); 548 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 549 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; 550 551 // The extra reg is for addrmode5. 552 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 553 DestReg) 554 .addConstantPoolIndex(Idx) 555 .addReg(0)); 556 return DestReg; 557 } 558 559 unsigned ARMFastISel::ARMMaterializeInt(const Constant *C, MVT VT) { 560 561 if (VT != MVT::i32 && VT != MVT::i16 && VT != MVT::i8 && VT != MVT::i1) 562 return false; 563 564 // If we can do this in a single instruction without a constant pool entry 565 // do so now. 566 const ConstantInt *CI = cast<ConstantInt>(C); 567 if (Subtarget->hasV6T2Ops() && isUInt<16>(CI->getZExtValue())) { 568 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; 569 const TargetRegisterClass *RC = isThumb2 ? &ARM::rGPRRegClass : 570 &ARM::GPRRegClass; 571 unsigned ImmReg = createResultReg(RC); 572 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 573 TII.get(Opc), ImmReg) 574 .addImm(CI->getZExtValue())); 575 return ImmReg; 576 } 577 578 // Use MVN to emit negative constants. 579 if (VT == MVT::i32 && Subtarget->hasV6T2Ops() && CI->isNegative()) { 580 unsigned Imm = (unsigned)~(CI->getSExtValue()); 581 bool UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 582 (ARM_AM::getSOImmVal(Imm) != -1); 583 if (UseImm) { 584 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; 585 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); 586 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 587 TII.get(Opc), ImmReg) 588 .addImm(Imm)); 589 return ImmReg; 590 } 591 } 592 593 // Load from constant pool. For now 32-bit only. 594 if (VT != MVT::i32) 595 return false; 596 597 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); 598 599 // MachineConstantPool wants an explicit alignment. 600 unsigned Align = TD.getPrefTypeAlignment(C->getType()); 601 if (Align == 0) { 602 // TODO: Figure out if this is correct. 603 Align = TD.getTypeAllocSize(C->getType()); 604 } 605 unsigned Idx = MCP.getConstantPoolIndex(C, Align); 606 607 if (isThumb2) 608 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 609 TII.get(ARM::t2LDRpci), DestReg) 610 .addConstantPoolIndex(Idx)); 611 else 612 // The extra immediate is for addrmode2. 613 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 614 TII.get(ARM::LDRcp), DestReg) 615 .addConstantPoolIndex(Idx) 616 .addImm(0)); 617 618 return DestReg; 619 } 620 621 unsigned ARMFastISel::ARMMaterializeGV(const GlobalValue *GV, MVT VT) { 622 // For now 32-bit only. 623 if (VT != MVT::i32) return 0; 624 625 Reloc::Model RelocM = TM.getRelocationModel(); 626 bool IsIndirect = Subtarget->GVIsIndirectSymbol(GV, RelocM); 627 const TargetRegisterClass *RC = isThumb2 ? 628 (const TargetRegisterClass*)&ARM::rGPRRegClass : 629 (const TargetRegisterClass*)&ARM::GPRRegClass; 630 unsigned DestReg = createResultReg(RC); 631 632 // FastISel TLS support on non-Darwin is broken, punt to SelectionDAG. 633 const GlobalVariable *GVar = dyn_cast<GlobalVariable>(GV); 634 bool IsThreadLocal = GVar && GVar->isThreadLocal(); 635 if (!Subtarget->isTargetDarwin() && IsThreadLocal) return 0; 636 637 // Use movw+movt when possible, it avoids constant pool entries. 638 // Darwin targets don't support movt with Reloc::Static, see 639 // ARMTargetLowering::LowerGlobalAddressDarwin. Other targets only support 640 // static movt relocations. 641 if (Subtarget->useMovt() && 642 Subtarget->isTargetDarwin() == (RelocM != Reloc::Static)) { 643 unsigned Opc; 644 switch (RelocM) { 645 case Reloc::PIC_: 646 Opc = isThumb2 ? ARM::t2MOV_ga_pcrel : ARM::MOV_ga_pcrel; 647 break; 648 case Reloc::DynamicNoPIC: 649 Opc = isThumb2 ? ARM::t2MOV_ga_dyn : ARM::MOV_ga_dyn; 650 break; 651 default: 652 Opc = isThumb2 ? ARM::t2MOVi32imm : ARM::MOVi32imm; 653 break; 654 } 655 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 656 DestReg).addGlobalAddress(GV)); 657 } else { 658 // MachineConstantPool wants an explicit alignment. 659 unsigned Align = TD.getPrefTypeAlignment(GV->getType()); 660 if (Align == 0) { 661 // TODO: Figure out if this is correct. 662 Align = TD.getTypeAllocSize(GV->getType()); 663 } 664 665 if (Subtarget->isTargetELF() && RelocM == Reloc::PIC_) 666 return ARMLowerPICELF(GV, Align, VT); 667 668 // Grab index. 669 unsigned PCAdj = (RelocM != Reloc::PIC_) ? 0 : 670 (Subtarget->isThumb() ? 4 : 8); 671 unsigned Id = AFI->createPICLabelUId(); 672 ARMConstantPoolValue *CPV = ARMConstantPoolConstant::Create(GV, Id, 673 ARMCP::CPValue, 674 PCAdj); 675 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); 676 677 // Load value. 678 MachineInstrBuilder MIB; 679 if (isThumb2) { 680 unsigned Opc = (RelocM!=Reloc::PIC_) ? ARM::t2LDRpci : ARM::t2LDRpci_pic; 681 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), DestReg) 682 .addConstantPoolIndex(Idx); 683 if (RelocM == Reloc::PIC_) 684 MIB.addImm(Id); 685 AddOptionalDefs(MIB); 686 } else { 687 // The extra immediate is for addrmode2. 688 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRcp), 689 DestReg) 690 .addConstantPoolIndex(Idx) 691 .addImm(0); 692 AddOptionalDefs(MIB); 693 694 if (RelocM == Reloc::PIC_) { 695 unsigned Opc = IsIndirect ? ARM::PICLDR : ARM::PICADD; 696 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 697 698 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 699 DL, TII.get(Opc), NewDestReg) 700 .addReg(DestReg) 701 .addImm(Id); 702 AddOptionalDefs(MIB); 703 return NewDestReg; 704 } 705 } 706 } 707 708 if (IsIndirect) { 709 MachineInstrBuilder MIB; 710 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); 711 if (isThumb2) 712 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 713 TII.get(ARM::t2LDRi12), NewDestReg) 714 .addReg(DestReg) 715 .addImm(0); 716 else 717 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(ARM::LDRi12), 718 NewDestReg) 719 .addReg(DestReg) 720 .addImm(0); 721 DestReg = NewDestReg; 722 AddOptionalDefs(MIB); 723 } 724 725 return DestReg; 726 } 727 728 unsigned ARMFastISel::TargetMaterializeConstant(const Constant *C) { 729 EVT CEVT = TLI.getValueType(C->getType(), true); 730 731 // Only handle simple types. 732 if (!CEVT.isSimple()) return 0; 733 MVT VT = CEVT.getSimpleVT(); 734 735 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 736 return ARMMaterializeFP(CFP, VT); 737 else if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 738 return ARMMaterializeGV(GV, VT); 739 else if (isa<ConstantInt>(C)) 740 return ARMMaterializeInt(C, VT); 741 742 return 0; 743 } 744 745 // TODO: unsigned ARMFastISel::TargetMaterializeFloatZero(const ConstantFP *CF); 746 747 unsigned ARMFastISel::TargetMaterializeAlloca(const AllocaInst *AI) { 748 // Don't handle dynamic allocas. 749 if (!FuncInfo.StaticAllocaMap.count(AI)) return 0; 750 751 MVT VT; 752 if (!isLoadTypeLegal(AI->getType(), VT)) return 0; 753 754 DenseMap<const AllocaInst*, int>::iterator SI = 755 FuncInfo.StaticAllocaMap.find(AI); 756 757 // This will get lowered later into the correct offsets and registers 758 // via rewriteXFrameIndex. 759 if (SI != FuncInfo.StaticAllocaMap.end()) { 760 const TargetRegisterClass* RC = TLI.getRegClassFor(VT); 761 unsigned ResultReg = createResultReg(RC); 762 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 763 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 764 TII.get(Opc), ResultReg) 765 .addFrameIndex(SI->second) 766 .addImm(0)); 767 return ResultReg; 768 } 769 770 return 0; 771 } 772 773 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { 774 EVT evt = TLI.getValueType(Ty, true); 775 776 // Only handle simple types. 777 if (evt == MVT::Other || !evt.isSimple()) return false; 778 VT = evt.getSimpleVT(); 779 780 // Handle all legal types, i.e. a register that will directly hold this 781 // value. 782 return TLI.isTypeLegal(VT); 783 } 784 785 bool ARMFastISel::isLoadTypeLegal(Type *Ty, MVT &VT) { 786 if (isTypeLegal(Ty, VT)) return true; 787 788 // If this is a type than can be sign or zero-extended to a basic operation 789 // go ahead and accept it now. 790 if (VT == MVT::i1 || VT == MVT::i8 || VT == MVT::i16) 791 return true; 792 793 return false; 794 } 795 796 // Computes the address to get to an object. 797 bool ARMFastISel::ARMComputeAddress(const Value *Obj, Address &Addr) { 798 // Some boilerplate from the X86 FastISel. 799 const User *U = NULL; 800 unsigned Opcode = Instruction::UserOp1; 801 if (const Instruction *I = dyn_cast<Instruction>(Obj)) { 802 // Don't walk into other basic blocks unless the object is an alloca from 803 // another block, otherwise it may not have a virtual register assigned. 804 if (FuncInfo.StaticAllocaMap.count(static_cast<const AllocaInst *>(Obj)) || 805 FuncInfo.MBBMap[I->getParent()] == FuncInfo.MBB) { 806 Opcode = I->getOpcode(); 807 U = I; 808 } 809 } else if (const ConstantExpr *C = dyn_cast<ConstantExpr>(Obj)) { 810 Opcode = C->getOpcode(); 811 U = C; 812 } 813 814 if (PointerType *Ty = dyn_cast<PointerType>(Obj->getType())) 815 if (Ty->getAddressSpace() > 255) 816 // Fast instruction selection doesn't support the special 817 // address spaces. 818 return false; 819 820 switch (Opcode) { 821 default: 822 break; 823 case Instruction::BitCast: 824 // Look through bitcasts. 825 return ARMComputeAddress(U->getOperand(0), Addr); 826 case Instruction::IntToPtr: 827 // Look past no-op inttoptrs. 828 if (TLI.getValueType(U->getOperand(0)->getType()) == TLI.getPointerTy()) 829 return ARMComputeAddress(U->getOperand(0), Addr); 830 break; 831 case Instruction::PtrToInt: 832 // Look past no-op ptrtoints. 833 if (TLI.getValueType(U->getType()) == TLI.getPointerTy()) 834 return ARMComputeAddress(U->getOperand(0), Addr); 835 break; 836 case Instruction::GetElementPtr: { 837 Address SavedAddr = Addr; 838 int TmpOffset = Addr.Offset; 839 840 // Iterate through the GEP folding the constants into offsets where 841 // we can. 842 gep_type_iterator GTI = gep_type_begin(U); 843 for (User::const_op_iterator i = U->op_begin() + 1, e = U->op_end(); 844 i != e; ++i, ++GTI) { 845 const Value *Op = *i; 846 if (StructType *STy = dyn_cast<StructType>(*GTI)) { 847 const StructLayout *SL = TD.getStructLayout(STy); 848 unsigned Idx = cast<ConstantInt>(Op)->getZExtValue(); 849 TmpOffset += SL->getElementOffset(Idx); 850 } else { 851 uint64_t S = TD.getTypeAllocSize(GTI.getIndexedType()); 852 for (;;) { 853 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Op)) { 854 // Constant-offset addressing. 855 TmpOffset += CI->getSExtValue() * S; 856 break; 857 } 858 if (isa<AddOperator>(Op) && 859 (!isa<Instruction>(Op) || 860 FuncInfo.MBBMap[cast<Instruction>(Op)->getParent()] 861 == FuncInfo.MBB) && 862 isa<ConstantInt>(cast<AddOperator>(Op)->getOperand(1))) { 863 // An add (in the same block) with a constant operand. Fold the 864 // constant. 865 ConstantInt *CI = 866 cast<ConstantInt>(cast<AddOperator>(Op)->getOperand(1)); 867 TmpOffset += CI->getSExtValue() * S; 868 // Iterate on the other operand. 869 Op = cast<AddOperator>(Op)->getOperand(0); 870 continue; 871 } 872 // Unsupported 873 goto unsupported_gep; 874 } 875 } 876 } 877 878 // Try to grab the base operand now. 879 Addr.Offset = TmpOffset; 880 if (ARMComputeAddress(U->getOperand(0), Addr)) return true; 881 882 // We failed, restore everything and try the other options. 883 Addr = SavedAddr; 884 885 unsupported_gep: 886 break; 887 } 888 case Instruction::Alloca: { 889 const AllocaInst *AI = cast<AllocaInst>(Obj); 890 DenseMap<const AllocaInst*, int>::iterator SI = 891 FuncInfo.StaticAllocaMap.find(AI); 892 if (SI != FuncInfo.StaticAllocaMap.end()) { 893 Addr.BaseType = Address::FrameIndexBase; 894 Addr.Base.FI = SI->second; 895 return true; 896 } 897 break; 898 } 899 } 900 901 // Try to get this in a register if nothing else has worked. 902 if (Addr.Base.Reg == 0) Addr.Base.Reg = getRegForValue(Obj); 903 return Addr.Base.Reg != 0; 904 } 905 906 void ARMFastISel::ARMSimplifyAddress(Address &Addr, MVT VT, bool useAM3) { 907 bool needsLowering = false; 908 switch (VT.SimpleTy) { 909 default: llvm_unreachable("Unhandled load/store type!"); 910 case MVT::i1: 911 case MVT::i8: 912 case MVT::i16: 913 case MVT::i32: 914 if (!useAM3) { 915 // Integer loads/stores handle 12-bit offsets. 916 needsLowering = ((Addr.Offset & 0xfff) != Addr.Offset); 917 // Handle negative offsets. 918 if (needsLowering && isThumb2) 919 needsLowering = !(Subtarget->hasV6T2Ops() && Addr.Offset < 0 && 920 Addr.Offset > -256); 921 } else { 922 // ARM halfword load/stores and signed byte loads use +/-imm8 offsets. 923 needsLowering = (Addr.Offset > 255 || Addr.Offset < -255); 924 } 925 break; 926 case MVT::f32: 927 case MVT::f64: 928 // Floating point operands handle 8-bit offsets. 929 needsLowering = ((Addr.Offset & 0xff) != Addr.Offset); 930 break; 931 } 932 933 // If this is a stack pointer and the offset needs to be simplified then 934 // put the alloca address into a register, set the base type back to 935 // register and continue. This should almost never happen. 936 if (needsLowering && Addr.BaseType == Address::FrameIndexBase) { 937 const TargetRegisterClass *RC = isThumb2 ? 938 (const TargetRegisterClass*)&ARM::tGPRRegClass : 939 (const TargetRegisterClass*)&ARM::GPRRegClass; 940 unsigned ResultReg = createResultReg(RC); 941 unsigned Opc = isThumb2 ? ARM::t2ADDri : ARM::ADDri; 942 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 943 TII.get(Opc), ResultReg) 944 .addFrameIndex(Addr.Base.FI) 945 .addImm(0)); 946 Addr.Base.Reg = ResultReg; 947 Addr.BaseType = Address::RegBase; 948 } 949 950 // Since the offset is too large for the load/store instruction 951 // get the reg+offset into a register. 952 if (needsLowering) { 953 Addr.Base.Reg = FastEmit_ri_(MVT::i32, ISD::ADD, Addr.Base.Reg, 954 /*Op0IsKill*/false, Addr.Offset, MVT::i32); 955 Addr.Offset = 0; 956 } 957 } 958 959 void ARMFastISel::AddLoadStoreOperands(MVT VT, Address &Addr, 960 const MachineInstrBuilder &MIB, 961 unsigned Flags, bool useAM3) { 962 // addrmode5 output depends on the selection dag addressing dividing the 963 // offset by 4 that it then later multiplies. Do this here as well. 964 if (VT.SimpleTy == MVT::f32 || VT.SimpleTy == MVT::f64) 965 Addr.Offset /= 4; 966 967 // Frame base works a bit differently. Handle it separately. 968 if (Addr.BaseType == Address::FrameIndexBase) { 969 int FI = Addr.Base.FI; 970 int Offset = Addr.Offset; 971 MachineMemOperand *MMO = 972 FuncInfo.MF->getMachineMemOperand( 973 MachinePointerInfo::getFixedStack(FI, Offset), 974 Flags, 975 MFI.getObjectSize(FI), 976 MFI.getObjectAlignment(FI)); 977 // Now add the rest of the operands. 978 MIB.addFrameIndex(FI); 979 980 // ARM halfword load/stores and signed byte loads need an additional 981 // operand. 982 if (useAM3) { 983 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; 984 MIB.addReg(0); 985 MIB.addImm(Imm); 986 } else { 987 MIB.addImm(Addr.Offset); 988 } 989 MIB.addMemOperand(MMO); 990 } else { 991 // Now add the rest of the operands. 992 MIB.addReg(Addr.Base.Reg); 993 994 // ARM halfword load/stores and signed byte loads need an additional 995 // operand. 996 if (useAM3) { 997 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; 998 MIB.addReg(0); 999 MIB.addImm(Imm); 1000 } else { 1001 MIB.addImm(Addr.Offset); 1002 } 1003 } 1004 AddOptionalDefs(MIB); 1005 } 1006 1007 bool ARMFastISel::ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, 1008 unsigned Alignment, bool isZExt, bool allocReg) { 1009 unsigned Opc; 1010 bool useAM3 = false; 1011 bool needVMOV = false; 1012 const TargetRegisterClass *RC; 1013 switch (VT.SimpleTy) { 1014 // This is mostly going to be Neon/vector support. 1015 default: return false; 1016 case MVT::i1: 1017 case MVT::i8: 1018 if (isThumb2) { 1019 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1020 Opc = isZExt ? ARM::t2LDRBi8 : ARM::t2LDRSBi8; 1021 else 1022 Opc = isZExt ? ARM::t2LDRBi12 : ARM::t2LDRSBi12; 1023 } else { 1024 if (isZExt) { 1025 Opc = ARM::LDRBi12; 1026 } else { 1027 Opc = ARM::LDRSB; 1028 useAM3 = true; 1029 } 1030 } 1031 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 1032 break; 1033 case MVT::i16: 1034 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) 1035 return false; 1036 1037 if (isThumb2) { 1038 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1039 Opc = isZExt ? ARM::t2LDRHi8 : ARM::t2LDRSHi8; 1040 else 1041 Opc = isZExt ? ARM::t2LDRHi12 : ARM::t2LDRSHi12; 1042 } else { 1043 Opc = isZExt ? ARM::LDRH : ARM::LDRSH; 1044 useAM3 = true; 1045 } 1046 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 1047 break; 1048 case MVT::i32: 1049 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) 1050 return false; 1051 1052 if (isThumb2) { 1053 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1054 Opc = ARM::t2LDRi8; 1055 else 1056 Opc = ARM::t2LDRi12; 1057 } else { 1058 Opc = ARM::LDRi12; 1059 } 1060 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 1061 break; 1062 case MVT::f32: 1063 if (!Subtarget->hasVFP2()) return false; 1064 // Unaligned loads need special handling. Floats require word-alignment. 1065 if (Alignment && Alignment < 4) { 1066 needVMOV = true; 1067 VT = MVT::i32; 1068 Opc = isThumb2 ? ARM::t2LDRi12 : ARM::LDRi12; 1069 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRnopcRegClass; 1070 } else { 1071 Opc = ARM::VLDRS; 1072 RC = TLI.getRegClassFor(VT); 1073 } 1074 break; 1075 case MVT::f64: 1076 if (!Subtarget->hasVFP2()) return false; 1077 // FIXME: Unaligned loads need special handling. Doublewords require 1078 // word-alignment. 1079 if (Alignment && Alignment < 4) 1080 return false; 1081 1082 Opc = ARM::VLDRD; 1083 RC = TLI.getRegClassFor(VT); 1084 break; 1085 } 1086 // Simplify this down to something we can handle. 1087 ARMSimplifyAddress(Addr, VT, useAM3); 1088 1089 // Create the base instruction, then add the operands. 1090 if (allocReg) 1091 ResultReg = createResultReg(RC); 1092 assert (ResultReg > 255 && "Expected an allocated virtual register."); 1093 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1094 TII.get(Opc), ResultReg); 1095 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOLoad, useAM3); 1096 1097 // If we had an unaligned load of a float we've converted it to an regular 1098 // load. Now we must move from the GRP to the FP register. 1099 if (needVMOV) { 1100 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 1101 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1102 TII.get(ARM::VMOVSR), MoveReg) 1103 .addReg(ResultReg)); 1104 ResultReg = MoveReg; 1105 } 1106 return true; 1107 } 1108 1109 bool ARMFastISel::SelectLoad(const Instruction *I) { 1110 // Atomic loads need special handling. 1111 if (cast<LoadInst>(I)->isAtomic()) 1112 return false; 1113 1114 // Verify we have a legal type before going any further. 1115 MVT VT; 1116 if (!isLoadTypeLegal(I->getType(), VT)) 1117 return false; 1118 1119 // See if we can handle this address. 1120 Address Addr; 1121 if (!ARMComputeAddress(I->getOperand(0), Addr)) return false; 1122 1123 unsigned ResultReg; 1124 if (!ARMEmitLoad(VT, ResultReg, Addr, cast<LoadInst>(I)->getAlignment())) 1125 return false; 1126 UpdateValueMap(I, ResultReg); 1127 return true; 1128 } 1129 1130 bool ARMFastISel::ARMEmitStore(MVT VT, unsigned SrcReg, Address &Addr, 1131 unsigned Alignment) { 1132 unsigned StrOpc; 1133 bool useAM3 = false; 1134 switch (VT.SimpleTy) { 1135 // This is mostly going to be Neon/vector support. 1136 default: return false; 1137 case MVT::i1: { 1138 unsigned Res = createResultReg(isThumb2 ? 1139 (const TargetRegisterClass*)&ARM::tGPRRegClass : 1140 (const TargetRegisterClass*)&ARM::GPRRegClass); 1141 unsigned Opc = isThumb2 ? ARM::t2ANDri : ARM::ANDri; 1142 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1143 TII.get(Opc), Res) 1144 .addReg(SrcReg).addImm(1)); 1145 SrcReg = Res; 1146 } // Fallthrough here. 1147 case MVT::i8: 1148 if (isThumb2) { 1149 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1150 StrOpc = ARM::t2STRBi8; 1151 else 1152 StrOpc = ARM::t2STRBi12; 1153 } else { 1154 StrOpc = ARM::STRBi12; 1155 } 1156 break; 1157 case MVT::i16: 1158 if (Alignment && Alignment < 2 && !Subtarget->allowsUnalignedMem()) 1159 return false; 1160 1161 if (isThumb2) { 1162 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1163 StrOpc = ARM::t2STRHi8; 1164 else 1165 StrOpc = ARM::t2STRHi12; 1166 } else { 1167 StrOpc = ARM::STRH; 1168 useAM3 = true; 1169 } 1170 break; 1171 case MVT::i32: 1172 if (Alignment && Alignment < 4 && !Subtarget->allowsUnalignedMem()) 1173 return false; 1174 1175 if (isThumb2) { 1176 if (Addr.Offset < 0 && Addr.Offset > -256 && Subtarget->hasV6T2Ops()) 1177 StrOpc = ARM::t2STRi8; 1178 else 1179 StrOpc = ARM::t2STRi12; 1180 } else { 1181 StrOpc = ARM::STRi12; 1182 } 1183 break; 1184 case MVT::f32: 1185 if (!Subtarget->hasVFP2()) return false; 1186 // Unaligned stores need special handling. Floats require word-alignment. 1187 if (Alignment && Alignment < 4) { 1188 unsigned MoveReg = createResultReg(TLI.getRegClassFor(MVT::i32)); 1189 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1190 TII.get(ARM::VMOVRS), MoveReg) 1191 .addReg(SrcReg)); 1192 SrcReg = MoveReg; 1193 VT = MVT::i32; 1194 StrOpc = isThumb2 ? ARM::t2STRi12 : ARM::STRi12; 1195 } else { 1196 StrOpc = ARM::VSTRS; 1197 } 1198 break; 1199 case MVT::f64: 1200 if (!Subtarget->hasVFP2()) return false; 1201 // FIXME: Unaligned stores need special handling. Doublewords require 1202 // word-alignment. 1203 if (Alignment && Alignment < 4) 1204 return false; 1205 1206 StrOpc = ARM::VSTRD; 1207 break; 1208 } 1209 // Simplify this down to something we can handle. 1210 ARMSimplifyAddress(Addr, VT, useAM3); 1211 1212 // Create the base instruction, then add the operands. 1213 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1214 TII.get(StrOpc)) 1215 .addReg(SrcReg); 1216 AddLoadStoreOperands(VT, Addr, MIB, MachineMemOperand::MOStore, useAM3); 1217 return true; 1218 } 1219 1220 bool ARMFastISel::SelectStore(const Instruction *I) { 1221 Value *Op0 = I->getOperand(0); 1222 unsigned SrcReg = 0; 1223 1224 // Atomic stores need special handling. 1225 if (cast<StoreInst>(I)->isAtomic()) 1226 return false; 1227 1228 // Verify we have a legal type before going any further. 1229 MVT VT; 1230 if (!isLoadTypeLegal(I->getOperand(0)->getType(), VT)) 1231 return false; 1232 1233 // Get the value to be stored into a register. 1234 SrcReg = getRegForValue(Op0); 1235 if (SrcReg == 0) return false; 1236 1237 // See if we can handle this address. 1238 Address Addr; 1239 if (!ARMComputeAddress(I->getOperand(1), Addr)) 1240 return false; 1241 1242 if (!ARMEmitStore(VT, SrcReg, Addr, cast<StoreInst>(I)->getAlignment())) 1243 return false; 1244 return true; 1245 } 1246 1247 static ARMCC::CondCodes getComparePred(CmpInst::Predicate Pred) { 1248 switch (Pred) { 1249 // Needs two compares... 1250 case CmpInst::FCMP_ONE: 1251 case CmpInst::FCMP_UEQ: 1252 default: 1253 // AL is our "false" for now. The other two need more compares. 1254 return ARMCC::AL; 1255 case CmpInst::ICMP_EQ: 1256 case CmpInst::FCMP_OEQ: 1257 return ARMCC::EQ; 1258 case CmpInst::ICMP_SGT: 1259 case CmpInst::FCMP_OGT: 1260 return ARMCC::GT; 1261 case CmpInst::ICMP_SGE: 1262 case CmpInst::FCMP_OGE: 1263 return ARMCC::GE; 1264 case CmpInst::ICMP_UGT: 1265 case CmpInst::FCMP_UGT: 1266 return ARMCC::HI; 1267 case CmpInst::FCMP_OLT: 1268 return ARMCC::MI; 1269 case CmpInst::ICMP_ULE: 1270 case CmpInst::FCMP_OLE: 1271 return ARMCC::LS; 1272 case CmpInst::FCMP_ORD: 1273 return ARMCC::VC; 1274 case CmpInst::FCMP_UNO: 1275 return ARMCC::VS; 1276 case CmpInst::FCMP_UGE: 1277 return ARMCC::PL; 1278 case CmpInst::ICMP_SLT: 1279 case CmpInst::FCMP_ULT: 1280 return ARMCC::LT; 1281 case CmpInst::ICMP_SLE: 1282 case CmpInst::FCMP_ULE: 1283 return ARMCC::LE; 1284 case CmpInst::FCMP_UNE: 1285 case CmpInst::ICMP_NE: 1286 return ARMCC::NE; 1287 case CmpInst::ICMP_UGE: 1288 return ARMCC::HS; 1289 case CmpInst::ICMP_ULT: 1290 return ARMCC::LO; 1291 } 1292 } 1293 1294 bool ARMFastISel::SelectBranch(const Instruction *I) { 1295 const BranchInst *BI = cast<BranchInst>(I); 1296 MachineBasicBlock *TBB = FuncInfo.MBBMap[BI->getSuccessor(0)]; 1297 MachineBasicBlock *FBB = FuncInfo.MBBMap[BI->getSuccessor(1)]; 1298 1299 // Simple branch support. 1300 1301 // If we can, avoid recomputing the compare - redoing it could lead to wonky 1302 // behavior. 1303 if (const CmpInst *CI = dyn_cast<CmpInst>(BI->getCondition())) { 1304 if (CI->hasOneUse() && (CI->getParent() == I->getParent())) { 1305 1306 // Get the compare predicate. 1307 // Try to take advantage of fallthrough opportunities. 1308 CmpInst::Predicate Predicate = CI->getPredicate(); 1309 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1310 std::swap(TBB, FBB); 1311 Predicate = CmpInst::getInversePredicate(Predicate); 1312 } 1313 1314 ARMCC::CondCodes ARMPred = getComparePred(Predicate); 1315 1316 // We may not handle every CC for now. 1317 if (ARMPred == ARMCC::AL) return false; 1318 1319 // Emit the compare. 1320 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) 1321 return false; 1322 1323 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1324 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1325 .addMBB(TBB).addImm(ARMPred).addReg(ARM::CPSR); 1326 FastEmitBranch(FBB, DL); 1327 FuncInfo.MBB->addSuccessor(TBB); 1328 return true; 1329 } 1330 } else if (TruncInst *TI = dyn_cast<TruncInst>(BI->getCondition())) { 1331 MVT SourceVT; 1332 if (TI->hasOneUse() && TI->getParent() == I->getParent() && 1333 (isLoadTypeLegal(TI->getOperand(0)->getType(), SourceVT))) { 1334 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1335 unsigned OpReg = getRegForValue(TI->getOperand(0)); 1336 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1337 TII.get(TstOpc)) 1338 .addReg(OpReg).addImm(1)); 1339 1340 unsigned CCMode = ARMCC::NE; 1341 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1342 std::swap(TBB, FBB); 1343 CCMode = ARMCC::EQ; 1344 } 1345 1346 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1347 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1348 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1349 1350 FastEmitBranch(FBB, DL); 1351 FuncInfo.MBB->addSuccessor(TBB); 1352 return true; 1353 } 1354 } else if (const ConstantInt *CI = 1355 dyn_cast<ConstantInt>(BI->getCondition())) { 1356 uint64_t Imm = CI->getZExtValue(); 1357 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB; 1358 FastEmitBranch(Target, DL); 1359 return true; 1360 } 1361 1362 unsigned CmpReg = getRegForValue(BI->getCondition()); 1363 if (CmpReg == 0) return false; 1364 1365 // We've been divorced from our compare! Our block was split, and 1366 // now our compare lives in a predecessor block. We musn't 1367 // re-compare here, as the children of the compare aren't guaranteed 1368 // live across the block boundary (we *could* check for this). 1369 // Regardless, the compare has been done in the predecessor block, 1370 // and it left a value for us in a virtual register. Ergo, we test 1371 // the one-bit value left in the virtual register. 1372 unsigned TstOpc = isThumb2 ? ARM::t2TSTri : ARM::TSTri; 1373 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TstOpc)) 1374 .addReg(CmpReg).addImm(1)); 1375 1376 unsigned CCMode = ARMCC::NE; 1377 if (FuncInfo.MBB->isLayoutSuccessor(TBB)) { 1378 std::swap(TBB, FBB); 1379 CCMode = ARMCC::EQ; 1380 } 1381 1382 unsigned BrOpc = isThumb2 ? ARM::t2Bcc : ARM::Bcc; 1383 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BrOpc)) 1384 .addMBB(TBB).addImm(CCMode).addReg(ARM::CPSR); 1385 FastEmitBranch(FBB, DL); 1386 FuncInfo.MBB->addSuccessor(TBB); 1387 return true; 1388 } 1389 1390 bool ARMFastISel::SelectIndirectBr(const Instruction *I) { 1391 unsigned AddrReg = getRegForValue(I->getOperand(0)); 1392 if (AddrReg == 0) return false; 1393 1394 unsigned Opc = isThumb2 ? ARM::tBRIND : ARM::BX; 1395 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc)) 1396 .addReg(AddrReg)); 1397 1398 const IndirectBrInst *IB = cast<IndirectBrInst>(I); 1399 for (unsigned i = 0, e = IB->getNumSuccessors(); i != e; ++i) 1400 FuncInfo.MBB->addSuccessor(FuncInfo.MBBMap[IB->getSuccessor(i)]); 1401 1402 return true; 1403 } 1404 1405 bool ARMFastISel::ARMEmitCmp(const Value *Src1Value, const Value *Src2Value, 1406 bool isZExt) { 1407 Type *Ty = Src1Value->getType(); 1408 EVT SrcEVT = TLI.getValueType(Ty, true); 1409 if (!SrcEVT.isSimple()) return false; 1410 MVT SrcVT = SrcEVT.getSimpleVT(); 1411 1412 bool isFloat = (Ty->isFloatTy() || Ty->isDoubleTy()); 1413 if (isFloat && !Subtarget->hasVFP2()) 1414 return false; 1415 1416 // Check to see if the 2nd operand is a constant that we can encode directly 1417 // in the compare. 1418 int Imm = 0; 1419 bool UseImm = false; 1420 bool isNegativeImm = false; 1421 // FIXME: At -O0 we don't have anything that canonicalizes operand order. 1422 // Thus, Src1Value may be a ConstantInt, but we're missing it. 1423 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(Src2Value)) { 1424 if (SrcVT == MVT::i32 || SrcVT == MVT::i16 || SrcVT == MVT::i8 || 1425 SrcVT == MVT::i1) { 1426 const APInt &CIVal = ConstInt->getValue(); 1427 Imm = (isZExt) ? (int)CIVal.getZExtValue() : (int)CIVal.getSExtValue(); 1428 // For INT_MIN/LONG_MIN (i.e., 0x80000000) we need to use a cmp, rather 1429 // then a cmn, because there is no way to represent 2147483648 as a 1430 // signed 32-bit int. 1431 if (Imm < 0 && Imm != (int)0x80000000) { 1432 isNegativeImm = true; 1433 Imm = -Imm; 1434 } 1435 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1436 (ARM_AM::getSOImmVal(Imm) != -1); 1437 } 1438 } else if (const ConstantFP *ConstFP = dyn_cast<ConstantFP>(Src2Value)) { 1439 if (SrcVT == MVT::f32 || SrcVT == MVT::f64) 1440 if (ConstFP->isZero() && !ConstFP->isNegative()) 1441 UseImm = true; 1442 } 1443 1444 unsigned CmpOpc; 1445 bool isICmp = true; 1446 bool needsExt = false; 1447 switch (SrcVT.SimpleTy) { 1448 default: return false; 1449 // TODO: Verify compares. 1450 case MVT::f32: 1451 isICmp = false; 1452 CmpOpc = UseImm ? ARM::VCMPEZS : ARM::VCMPES; 1453 break; 1454 case MVT::f64: 1455 isICmp = false; 1456 CmpOpc = UseImm ? ARM::VCMPEZD : ARM::VCMPED; 1457 break; 1458 case MVT::i1: 1459 case MVT::i8: 1460 case MVT::i16: 1461 needsExt = true; 1462 // Intentional fall-through. 1463 case MVT::i32: 1464 if (isThumb2) { 1465 if (!UseImm) 1466 CmpOpc = ARM::t2CMPrr; 1467 else 1468 CmpOpc = isNegativeImm ? ARM::t2CMNri : ARM::t2CMPri; 1469 } else { 1470 if (!UseImm) 1471 CmpOpc = ARM::CMPrr; 1472 else 1473 CmpOpc = isNegativeImm ? ARM::CMNri : ARM::CMPri; 1474 } 1475 break; 1476 } 1477 1478 unsigned SrcReg1 = getRegForValue(Src1Value); 1479 if (SrcReg1 == 0) return false; 1480 1481 unsigned SrcReg2 = 0; 1482 if (!UseImm) { 1483 SrcReg2 = getRegForValue(Src2Value); 1484 if (SrcReg2 == 0) return false; 1485 } 1486 1487 // We have i1, i8, or i16, we need to either zero extend or sign extend. 1488 if (needsExt) { 1489 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt); 1490 if (SrcReg1 == 0) return false; 1491 if (!UseImm) { 1492 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt); 1493 if (SrcReg2 == 0) return false; 1494 } 1495 } 1496 1497 if (!UseImm) { 1498 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1499 TII.get(CmpOpc)) 1500 .addReg(SrcReg1).addReg(SrcReg2)); 1501 } else { 1502 MachineInstrBuilder MIB; 1503 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 1504 .addReg(SrcReg1); 1505 1506 // Only add immediate for icmp as the immediate for fcmp is an implicit 0.0. 1507 if (isICmp) 1508 MIB.addImm(Imm); 1509 AddOptionalDefs(MIB); 1510 } 1511 1512 // For floating point we need to move the result to a comparison register 1513 // that we can then use for branches. 1514 if (Ty->isFloatTy() || Ty->isDoubleTy()) 1515 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1516 TII.get(ARM::FMSTAT))); 1517 return true; 1518 } 1519 1520 bool ARMFastISel::SelectCmp(const Instruction *I) { 1521 const CmpInst *CI = cast<CmpInst>(I); 1522 1523 // Get the compare predicate. 1524 ARMCC::CondCodes ARMPred = getComparePred(CI->getPredicate()); 1525 1526 // We may not handle every CC for now. 1527 if (ARMPred == ARMCC::AL) return false; 1528 1529 // Emit the compare. 1530 if (!ARMEmitCmp(CI->getOperand(0), CI->getOperand(1), CI->isUnsigned())) 1531 return false; 1532 1533 // Now set a register based on the comparison. Explicitly set the predicates 1534 // here. 1535 unsigned MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1536 const TargetRegisterClass *RC = isThumb2 ? 1537 (const TargetRegisterClass*)&ARM::rGPRRegClass : 1538 (const TargetRegisterClass*)&ARM::GPRRegClass; 1539 unsigned DestReg = createResultReg(RC); 1540 Constant *Zero = ConstantInt::get(Type::getInt32Ty(*Context), 0); 1541 unsigned ZeroReg = TargetMaterializeConstant(Zero); 1542 // ARMEmitCmp emits a FMSTAT when necessary, so it's always safe to use CPSR. 1543 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), DestReg) 1544 .addReg(ZeroReg).addImm(1) 1545 .addImm(ARMPred).addReg(ARM::CPSR); 1546 1547 UpdateValueMap(I, DestReg); 1548 return true; 1549 } 1550 1551 bool ARMFastISel::SelectFPExt(const Instruction *I) { 1552 // Make sure we have VFP and that we're extending float to double. 1553 if (!Subtarget->hasVFP2()) return false; 1554 1555 Value *V = I->getOperand(0); 1556 if (!I->getType()->isDoubleTy() || 1557 !V->getType()->isFloatTy()) return false; 1558 1559 unsigned Op = getRegForValue(V); 1560 if (Op == 0) return false; 1561 1562 unsigned Result = createResultReg(&ARM::DPRRegClass); 1563 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1564 TII.get(ARM::VCVTDS), Result) 1565 .addReg(Op)); 1566 UpdateValueMap(I, Result); 1567 return true; 1568 } 1569 1570 bool ARMFastISel::SelectFPTrunc(const Instruction *I) { 1571 // Make sure we have VFP and that we're truncating double to float. 1572 if (!Subtarget->hasVFP2()) return false; 1573 1574 Value *V = I->getOperand(0); 1575 if (!(I->getType()->isFloatTy() && 1576 V->getType()->isDoubleTy())) return false; 1577 1578 unsigned Op = getRegForValue(V); 1579 if (Op == 0) return false; 1580 1581 unsigned Result = createResultReg(&ARM::SPRRegClass); 1582 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1583 TII.get(ARM::VCVTSD), Result) 1584 .addReg(Op)); 1585 UpdateValueMap(I, Result); 1586 return true; 1587 } 1588 1589 bool ARMFastISel::SelectIToFP(const Instruction *I, bool isSigned) { 1590 // Make sure we have VFP. 1591 if (!Subtarget->hasVFP2()) return false; 1592 1593 MVT DstVT; 1594 Type *Ty = I->getType(); 1595 if (!isTypeLegal(Ty, DstVT)) 1596 return false; 1597 1598 Value *Src = I->getOperand(0); 1599 EVT SrcEVT = TLI.getValueType(Src->getType(), true); 1600 if (!SrcEVT.isSimple()) 1601 return false; 1602 MVT SrcVT = SrcEVT.getSimpleVT(); 1603 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 1604 return false; 1605 1606 unsigned SrcReg = getRegForValue(Src); 1607 if (SrcReg == 0) return false; 1608 1609 // Handle sign-extension. 1610 if (SrcVT == MVT::i16 || SrcVT == MVT::i8) { 1611 SrcReg = ARMEmitIntExt(SrcVT, SrcReg, MVT::i32, 1612 /*isZExt*/!isSigned); 1613 if (SrcReg == 0) return false; 1614 } 1615 1616 // The conversion routine works on fp-reg to fp-reg and the operand above 1617 // was an integer, move it to the fp registers if possible. 1618 unsigned FP = ARMMoveToFPReg(MVT::f32, SrcReg); 1619 if (FP == 0) return false; 1620 1621 unsigned Opc; 1622 if (Ty->isFloatTy()) Opc = isSigned ? ARM::VSITOS : ARM::VUITOS; 1623 else if (Ty->isDoubleTy()) Opc = isSigned ? ARM::VSITOD : ARM::VUITOD; 1624 else return false; 1625 1626 unsigned ResultReg = createResultReg(TLI.getRegClassFor(DstVT)); 1627 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1628 ResultReg) 1629 .addReg(FP)); 1630 UpdateValueMap(I, ResultReg); 1631 return true; 1632 } 1633 1634 bool ARMFastISel::SelectFPToI(const Instruction *I, bool isSigned) { 1635 // Make sure we have VFP. 1636 if (!Subtarget->hasVFP2()) return false; 1637 1638 MVT DstVT; 1639 Type *RetTy = I->getType(); 1640 if (!isTypeLegal(RetTy, DstVT)) 1641 return false; 1642 1643 unsigned Op = getRegForValue(I->getOperand(0)); 1644 if (Op == 0) return false; 1645 1646 unsigned Opc; 1647 Type *OpTy = I->getOperand(0)->getType(); 1648 if (OpTy->isFloatTy()) Opc = isSigned ? ARM::VTOSIZS : ARM::VTOUIZS; 1649 else if (OpTy->isDoubleTy()) Opc = isSigned ? ARM::VTOSIZD : ARM::VTOUIZD; 1650 else return false; 1651 1652 // f64->s32/u32 or f32->s32/u32 both need an intermediate f32 reg. 1653 unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::f32)); 1654 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), 1655 ResultReg) 1656 .addReg(Op)); 1657 1658 // This result needs to be in an integer register, but the conversion only 1659 // takes place in fp-regs. 1660 unsigned IntReg = ARMMoveToIntReg(DstVT, ResultReg); 1661 if (IntReg == 0) return false; 1662 1663 UpdateValueMap(I, IntReg); 1664 return true; 1665 } 1666 1667 bool ARMFastISel::SelectSelect(const Instruction *I) { 1668 MVT VT; 1669 if (!isTypeLegal(I->getType(), VT)) 1670 return false; 1671 1672 // Things need to be register sized for register moves. 1673 if (VT != MVT::i32) return false; 1674 1675 unsigned CondReg = getRegForValue(I->getOperand(0)); 1676 if (CondReg == 0) return false; 1677 unsigned Op1Reg = getRegForValue(I->getOperand(1)); 1678 if (Op1Reg == 0) return false; 1679 1680 // Check to see if we can use an immediate in the conditional move. 1681 int Imm = 0; 1682 bool UseImm = false; 1683 bool isNegativeImm = false; 1684 if (const ConstantInt *ConstInt = dyn_cast<ConstantInt>(I->getOperand(2))) { 1685 assert (VT == MVT::i32 && "Expecting an i32."); 1686 Imm = (int)ConstInt->getValue().getZExtValue(); 1687 if (Imm < 0) { 1688 isNegativeImm = true; 1689 Imm = ~Imm; 1690 } 1691 UseImm = isThumb2 ? (ARM_AM::getT2SOImmVal(Imm) != -1) : 1692 (ARM_AM::getSOImmVal(Imm) != -1); 1693 } 1694 1695 unsigned Op2Reg = 0; 1696 if (!UseImm) { 1697 Op2Reg = getRegForValue(I->getOperand(2)); 1698 if (Op2Reg == 0) return false; 1699 } 1700 1701 unsigned CmpOpc = isThumb2 ? ARM::t2CMPri : ARM::CMPri; 1702 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CmpOpc)) 1703 .addReg(CondReg).addImm(0)); 1704 1705 unsigned MovCCOpc; 1706 const TargetRegisterClass *RC; 1707 if (!UseImm) { 1708 RC = isThumb2 ? &ARM::tGPRRegClass : &ARM::GPRRegClass; 1709 MovCCOpc = isThumb2 ? ARM::t2MOVCCr : ARM::MOVCCr; 1710 } else { 1711 RC = isThumb2 ? &ARM::rGPRRegClass : &ARM::GPRRegClass; 1712 if (!isNegativeImm) 1713 MovCCOpc = isThumb2 ? ARM::t2MOVCCi : ARM::MOVCCi; 1714 else 1715 MovCCOpc = isThumb2 ? ARM::t2MVNCCi : ARM::MVNCCi; 1716 } 1717 unsigned ResultReg = createResultReg(RC); 1718 if (!UseImm) 1719 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg) 1720 .addReg(Op2Reg).addReg(Op1Reg).addImm(ARMCC::NE).addReg(ARM::CPSR); 1721 else 1722 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(MovCCOpc), ResultReg) 1723 .addReg(Op1Reg).addImm(Imm).addImm(ARMCC::EQ).addReg(ARM::CPSR); 1724 UpdateValueMap(I, ResultReg); 1725 return true; 1726 } 1727 1728 bool ARMFastISel::SelectDiv(const Instruction *I, bool isSigned) { 1729 MVT VT; 1730 Type *Ty = I->getType(); 1731 if (!isTypeLegal(Ty, VT)) 1732 return false; 1733 1734 // If we have integer div support we should have selected this automagically. 1735 // In case we have a real miss go ahead and return false and we'll pick 1736 // it up later. 1737 if (Subtarget->hasDivide()) return false; 1738 1739 // Otherwise emit a libcall. 1740 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1741 if (VT == MVT::i8) 1742 LC = isSigned ? RTLIB::SDIV_I8 : RTLIB::UDIV_I8; 1743 else if (VT == MVT::i16) 1744 LC = isSigned ? RTLIB::SDIV_I16 : RTLIB::UDIV_I16; 1745 else if (VT == MVT::i32) 1746 LC = isSigned ? RTLIB::SDIV_I32 : RTLIB::UDIV_I32; 1747 else if (VT == MVT::i64) 1748 LC = isSigned ? RTLIB::SDIV_I64 : RTLIB::UDIV_I64; 1749 else if (VT == MVT::i128) 1750 LC = isSigned ? RTLIB::SDIV_I128 : RTLIB::UDIV_I128; 1751 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!"); 1752 1753 return ARMEmitLibcall(I, LC); 1754 } 1755 1756 bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) { 1757 MVT VT; 1758 Type *Ty = I->getType(); 1759 if (!isTypeLegal(Ty, VT)) 1760 return false; 1761 1762 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 1763 if (VT == MVT::i8) 1764 LC = isSigned ? RTLIB::SREM_I8 : RTLIB::UREM_I8; 1765 else if (VT == MVT::i16) 1766 LC = isSigned ? RTLIB::SREM_I16 : RTLIB::UREM_I16; 1767 else if (VT == MVT::i32) 1768 LC = isSigned ? RTLIB::SREM_I32 : RTLIB::UREM_I32; 1769 else if (VT == MVT::i64) 1770 LC = isSigned ? RTLIB::SREM_I64 : RTLIB::UREM_I64; 1771 else if (VT == MVT::i128) 1772 LC = isSigned ? RTLIB::SREM_I128 : RTLIB::UREM_I128; 1773 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!"); 1774 1775 return ARMEmitLibcall(I, LC); 1776 } 1777 1778 bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { 1779 EVT DestVT = TLI.getValueType(I->getType(), true); 1780 1781 // We can get here in the case when we have a binary operation on a non-legal 1782 // type and the target independent selector doesn't know how to handle it. 1783 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 1784 return false; 1785 1786 unsigned Opc; 1787 switch (ISDOpcode) { 1788 default: return false; 1789 case ISD::ADD: 1790 Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; 1791 break; 1792 case ISD::OR: 1793 Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; 1794 break; 1795 case ISD::SUB: 1796 Opc = isThumb2 ? ARM::t2SUBrr : ARM::SUBrr; 1797 break; 1798 } 1799 1800 unsigned SrcReg1 = getRegForValue(I->getOperand(0)); 1801 if (SrcReg1 == 0) return false; 1802 1803 // TODO: Often the 2nd operand is an immediate, which can be encoded directly 1804 // in the instruction, rather then materializing the value in a register. 1805 unsigned SrcReg2 = getRegForValue(I->getOperand(1)); 1806 if (SrcReg2 == 0) return false; 1807 1808 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); 1809 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1810 TII.get(Opc), ResultReg) 1811 .addReg(SrcReg1).addReg(SrcReg2)); 1812 UpdateValueMap(I, ResultReg); 1813 return true; 1814 } 1815 1816 bool ARMFastISel::SelectBinaryFPOp(const Instruction *I, unsigned ISDOpcode) { 1817 EVT FPVT = TLI.getValueType(I->getType(), true); 1818 if (!FPVT.isSimple()) return false; 1819 MVT VT = FPVT.getSimpleVT(); 1820 1821 // We can get here in the case when we want to use NEON for our fp 1822 // operations, but can't figure out how to. Just use the vfp instructions 1823 // if we have them. 1824 // FIXME: It'd be nice to use NEON instructions. 1825 Type *Ty = I->getType(); 1826 bool isFloat = (Ty->isDoubleTy() || Ty->isFloatTy()); 1827 if (isFloat && !Subtarget->hasVFP2()) 1828 return false; 1829 1830 unsigned Opc; 1831 bool is64bit = VT == MVT::f64 || VT == MVT::i64; 1832 switch (ISDOpcode) { 1833 default: return false; 1834 case ISD::FADD: 1835 Opc = is64bit ? ARM::VADDD : ARM::VADDS; 1836 break; 1837 case ISD::FSUB: 1838 Opc = is64bit ? ARM::VSUBD : ARM::VSUBS; 1839 break; 1840 case ISD::FMUL: 1841 Opc = is64bit ? ARM::VMULD : ARM::VMULS; 1842 break; 1843 } 1844 unsigned Op1 = getRegForValue(I->getOperand(0)); 1845 if (Op1 == 0) return false; 1846 1847 unsigned Op2 = getRegForValue(I->getOperand(1)); 1848 if (Op2 == 0) return false; 1849 1850 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT.SimpleTy)); 1851 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1852 TII.get(Opc), ResultReg) 1853 .addReg(Op1).addReg(Op2)); 1854 UpdateValueMap(I, ResultReg); 1855 return true; 1856 } 1857 1858 // Call Handling Code 1859 1860 // This is largely taken directly from CCAssignFnForNode 1861 // TODO: We may not support all of this. 1862 CCAssignFn *ARMFastISel::CCAssignFnForCall(CallingConv::ID CC, 1863 bool Return, 1864 bool isVarArg) { 1865 switch (CC) { 1866 default: 1867 llvm_unreachable("Unsupported calling convention"); 1868 case CallingConv::Fast: 1869 if (Subtarget->hasVFP2() && !isVarArg) { 1870 if (!Subtarget->isAAPCS_ABI()) 1871 return (Return ? RetFastCC_ARM_APCS : FastCC_ARM_APCS); 1872 // For AAPCS ABI targets, just use VFP variant of the calling convention. 1873 return (Return ? RetCC_ARM_AAPCS_VFP : CC_ARM_AAPCS_VFP); 1874 } 1875 // Fallthrough 1876 case CallingConv::C: 1877 // Use target triple & subtarget features to do actual dispatch. 1878 if (Subtarget->isAAPCS_ABI()) { 1879 if (Subtarget->hasVFP2() && 1880 TM.Options.FloatABIType == FloatABI::Hard && !isVarArg) 1881 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1882 else 1883 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1884 } else 1885 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1886 case CallingConv::ARM_AAPCS_VFP: 1887 if (!isVarArg) 1888 return (Return ? RetCC_ARM_AAPCS_VFP: CC_ARM_AAPCS_VFP); 1889 // Fall through to soft float variant, variadic functions don't 1890 // use hard floating point ABI. 1891 case CallingConv::ARM_AAPCS: 1892 return (Return ? RetCC_ARM_AAPCS: CC_ARM_AAPCS); 1893 case CallingConv::ARM_APCS: 1894 return (Return ? RetCC_ARM_APCS: CC_ARM_APCS); 1895 case CallingConv::GHC: 1896 if (Return) 1897 llvm_unreachable("Can't return in GHC call convention"); 1898 else 1899 return CC_ARM_APCS_GHC; 1900 } 1901 } 1902 1903 bool ARMFastISel::ProcessCallArgs(SmallVectorImpl<Value*> &Args, 1904 SmallVectorImpl<unsigned> &ArgRegs, 1905 SmallVectorImpl<MVT> &ArgVTs, 1906 SmallVectorImpl<ISD::ArgFlagsTy> &ArgFlags, 1907 SmallVectorImpl<unsigned> &RegArgs, 1908 CallingConv::ID CC, 1909 unsigned &NumBytes, 1910 bool isVarArg) { 1911 SmallVector<CCValAssign, 16> ArgLocs; 1912 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, ArgLocs, *Context); 1913 CCInfo.AnalyzeCallOperands(ArgVTs, ArgFlags, 1914 CCAssignFnForCall(CC, false, isVarArg)); 1915 1916 // Check that we can handle all of the arguments. If we can't, then bail out 1917 // now before we add code to the MBB. 1918 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1919 CCValAssign &VA = ArgLocs[i]; 1920 MVT ArgVT = ArgVTs[VA.getValNo()]; 1921 1922 // We don't handle NEON/vector parameters yet. 1923 if (ArgVT.isVector() || ArgVT.getSizeInBits() > 64) 1924 return false; 1925 1926 // Now copy/store arg to correct locations. 1927 if (VA.isRegLoc() && !VA.needsCustom()) { 1928 continue; 1929 } else if (VA.needsCustom()) { 1930 // TODO: We need custom lowering for vector (v2f64) args. 1931 if (VA.getLocVT() != MVT::f64 || 1932 // TODO: Only handle register args for now. 1933 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) 1934 return false; 1935 } else { 1936 switch (static_cast<EVT>(ArgVT).getSimpleVT().SimpleTy) { 1937 default: 1938 return false; 1939 case MVT::i1: 1940 case MVT::i8: 1941 case MVT::i16: 1942 case MVT::i32: 1943 break; 1944 case MVT::f32: 1945 if (!Subtarget->hasVFP2()) 1946 return false; 1947 break; 1948 case MVT::f64: 1949 if (!Subtarget->hasVFP2()) 1950 return false; 1951 break; 1952 } 1953 } 1954 } 1955 1956 // At the point, we are able to handle the call's arguments in fast isel. 1957 1958 // Get a count of how many bytes are to be pushed on the stack. 1959 NumBytes = CCInfo.getNextStackOffset(); 1960 1961 // Issue CALLSEQ_START 1962 unsigned AdjStackDown = TII.getCallFrameSetupOpcode(); 1963 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 1964 TII.get(AdjStackDown)) 1965 .addImm(NumBytes)); 1966 1967 // Process the args. 1968 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1969 CCValAssign &VA = ArgLocs[i]; 1970 unsigned Arg = ArgRegs[VA.getValNo()]; 1971 MVT ArgVT = ArgVTs[VA.getValNo()]; 1972 1973 assert((!ArgVT.isVector() && ArgVT.getSizeInBits() <= 64) && 1974 "We don't handle NEON/vector parameters yet."); 1975 1976 // Handle arg promotion, etc. 1977 switch (VA.getLocInfo()) { 1978 case CCValAssign::Full: break; 1979 case CCValAssign::SExt: { 1980 MVT DestVT = VA.getLocVT(); 1981 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/false); 1982 assert (Arg != 0 && "Failed to emit a sext"); 1983 ArgVT = DestVT; 1984 break; 1985 } 1986 case CCValAssign::AExt: 1987 // Intentional fall-through. Handle AExt and ZExt. 1988 case CCValAssign::ZExt: { 1989 MVT DestVT = VA.getLocVT(); 1990 Arg = ARMEmitIntExt(ArgVT, Arg, DestVT, /*isZExt*/true); 1991 assert (Arg != 0 && "Failed to emit a zext"); 1992 ArgVT = DestVT; 1993 break; 1994 } 1995 case CCValAssign::BCvt: { 1996 unsigned BC = FastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg, 1997 /*TODO: Kill=*/false); 1998 assert(BC != 0 && "Failed to emit a bitcast!"); 1999 Arg = BC; 2000 ArgVT = VA.getLocVT(); 2001 break; 2002 } 2003 default: llvm_unreachable("Unknown arg promotion!"); 2004 } 2005 2006 // Now copy/store arg to correct locations. 2007 if (VA.isRegLoc() && !VA.needsCustom()) { 2008 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 2009 VA.getLocReg()) 2010 .addReg(Arg); 2011 RegArgs.push_back(VA.getLocReg()); 2012 } else if (VA.needsCustom()) { 2013 // TODO: We need custom lowering for vector (v2f64) args. 2014 assert(VA.getLocVT() == MVT::f64 && 2015 "Custom lowering for v2f64 args not available"); 2016 2017 CCValAssign &NextVA = ArgLocs[++i]; 2018 2019 assert(VA.isRegLoc() && NextVA.isRegLoc() && 2020 "We only handle register args!"); 2021 2022 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2023 TII.get(ARM::VMOVRRD), VA.getLocReg()) 2024 .addReg(NextVA.getLocReg(), RegState::Define) 2025 .addReg(Arg)); 2026 RegArgs.push_back(VA.getLocReg()); 2027 RegArgs.push_back(NextVA.getLocReg()); 2028 } else { 2029 assert(VA.isMemLoc()); 2030 // Need to store on the stack. 2031 Address Addr; 2032 Addr.BaseType = Address::RegBase; 2033 Addr.Base.Reg = ARM::SP; 2034 Addr.Offset = VA.getLocMemOffset(); 2035 2036 bool EmitRet = ARMEmitStore(ArgVT, Arg, Addr); (void)EmitRet; 2037 assert(EmitRet && "Could not emit a store for argument!"); 2038 } 2039 } 2040 2041 return true; 2042 } 2043 2044 bool ARMFastISel::FinishCall(MVT RetVT, SmallVectorImpl<unsigned> &UsedRegs, 2045 const Instruction *I, CallingConv::ID CC, 2046 unsigned &NumBytes, bool isVarArg) { 2047 // Issue CALLSEQ_END 2048 unsigned AdjStackUp = TII.getCallFrameDestroyOpcode(); 2049 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2050 TII.get(AdjStackUp)) 2051 .addImm(NumBytes).addImm(0)); 2052 2053 // Now the return value. 2054 if (RetVT != MVT::isVoid) { 2055 SmallVector<CCValAssign, 16> RVLocs; 2056 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 2057 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); 2058 2059 // Copy all of the result registers out of their specified physreg. 2060 if (RVLocs.size() == 2 && RetVT == MVT::f64) { 2061 // For this move we copy into two registers and then move into the 2062 // double fp reg we want. 2063 MVT DestVT = RVLocs[0].getValVT(); 2064 const TargetRegisterClass* DstRC = TLI.getRegClassFor(DestVT); 2065 unsigned ResultReg = createResultReg(DstRC); 2066 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2067 TII.get(ARM::VMOVDRR), ResultReg) 2068 .addReg(RVLocs[0].getLocReg()) 2069 .addReg(RVLocs[1].getLocReg())); 2070 2071 UsedRegs.push_back(RVLocs[0].getLocReg()); 2072 UsedRegs.push_back(RVLocs[1].getLocReg()); 2073 2074 // Finally update the result. 2075 UpdateValueMap(I, ResultReg); 2076 } else { 2077 assert(RVLocs.size() == 1 &&"Can't handle non-double multi-reg retvals!"); 2078 MVT CopyVT = RVLocs[0].getValVT(); 2079 2080 // Special handling for extended integers. 2081 if (RetVT == MVT::i1 || RetVT == MVT::i8 || RetVT == MVT::i16) 2082 CopyVT = MVT::i32; 2083 2084 const TargetRegisterClass* DstRC = TLI.getRegClassFor(CopyVT); 2085 2086 unsigned ResultReg = createResultReg(DstRC); 2087 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 2088 ResultReg).addReg(RVLocs[0].getLocReg()); 2089 UsedRegs.push_back(RVLocs[0].getLocReg()); 2090 2091 // Finally update the result. 2092 UpdateValueMap(I, ResultReg); 2093 } 2094 } 2095 2096 return true; 2097 } 2098 2099 bool ARMFastISel::SelectRet(const Instruction *I) { 2100 const ReturnInst *Ret = cast<ReturnInst>(I); 2101 const Function &F = *I->getParent()->getParent(); 2102 2103 if (!FuncInfo.CanLowerReturn) 2104 return false; 2105 2106 // Build a list of return value registers. 2107 SmallVector<unsigned, 4> RetRegs; 2108 2109 CallingConv::ID CC = F.getCallingConv(); 2110 if (Ret->getNumOperands() > 0) { 2111 SmallVector<ISD::OutputArg, 4> Outs; 2112 GetReturnInfo(F.getReturnType(), F.getAttributes(), Outs, TLI); 2113 2114 // Analyze operands of the call, assigning locations to each operand. 2115 SmallVector<CCValAssign, 16> ValLocs; 2116 CCState CCInfo(CC, F.isVarArg(), *FuncInfo.MF, TM, ValLocs,I->getContext()); 2117 CCInfo.AnalyzeReturn(Outs, CCAssignFnForCall(CC, true /* is Ret */, 2118 F.isVarArg())); 2119 2120 const Value *RV = Ret->getOperand(0); 2121 unsigned Reg = getRegForValue(RV); 2122 if (Reg == 0) 2123 return false; 2124 2125 // Only handle a single return value for now. 2126 if (ValLocs.size() != 1) 2127 return false; 2128 2129 CCValAssign &VA = ValLocs[0]; 2130 2131 // Don't bother handling odd stuff for now. 2132 if (VA.getLocInfo() != CCValAssign::Full) 2133 return false; 2134 // Only handle register returns for now. 2135 if (!VA.isRegLoc()) 2136 return false; 2137 2138 unsigned SrcReg = Reg + VA.getValNo(); 2139 EVT RVEVT = TLI.getValueType(RV->getType()); 2140 if (!RVEVT.isSimple()) return false; 2141 MVT RVVT = RVEVT.getSimpleVT(); 2142 MVT DestVT = VA.getValVT(); 2143 // Special handling for extended integers. 2144 if (RVVT != DestVT) { 2145 if (RVVT != MVT::i1 && RVVT != MVT::i8 && RVVT != MVT::i16) 2146 return false; 2147 2148 assert(DestVT == MVT::i32 && "ARM should always ext to i32"); 2149 2150 // Perform extension if flagged as either zext or sext. Otherwise, do 2151 // nothing. 2152 if (Outs[0].Flags.isZExt() || Outs[0].Flags.isSExt()) { 2153 SrcReg = ARMEmitIntExt(RVVT, SrcReg, DestVT, Outs[0].Flags.isZExt()); 2154 if (SrcReg == 0) return false; 2155 } 2156 } 2157 2158 // Make the copy. 2159 unsigned DstReg = VA.getLocReg(); 2160 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); 2161 // Avoid a cross-class copy. This is very unlikely. 2162 if (!SrcRC->contains(DstReg)) 2163 return false; 2164 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 2165 DstReg).addReg(SrcReg); 2166 2167 // Add register to return instruction. 2168 RetRegs.push_back(VA.getLocReg()); 2169 } 2170 2171 unsigned RetOpc = isThumb2 ? ARM::tBX_RET : ARM::BX_RET; 2172 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2173 TII.get(RetOpc)); 2174 AddOptionalDefs(MIB); 2175 for (unsigned i = 0, e = RetRegs.size(); i != e; ++i) 2176 MIB.addReg(RetRegs[i], RegState::Implicit); 2177 return true; 2178 } 2179 2180 unsigned ARMFastISel::ARMSelectCallOp(bool UseReg) { 2181 if (UseReg) 2182 return isThumb2 ? ARM::tBLXr : ARM::BLX; 2183 else 2184 return isThumb2 ? ARM::tBL : ARM::BL; 2185 } 2186 2187 unsigned ARMFastISel::getLibcallReg(const Twine &Name) { 2188 // Manually compute the global's type to avoid building it when unnecessary. 2189 Type *GVTy = Type::getInt32PtrTy(*Context, /*AS=*/0); 2190 EVT LCREVT = TLI.getValueType(GVTy); 2191 if (!LCREVT.isSimple()) return 0; 2192 2193 GlobalValue *GV = new GlobalVariable(Type::getInt32Ty(*Context), false, 2194 GlobalValue::ExternalLinkage, 0, Name); 2195 assert(GV->getType() == GVTy && "We miscomputed the type for the global!"); 2196 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); 2197 } 2198 2199 // A quick function that will emit a call for a named libcall in F with the 2200 // vector of passed arguments for the Instruction in I. We can assume that we 2201 // can emit a call for any libcall we can produce. This is an abridged version 2202 // of the full call infrastructure since we won't need to worry about things 2203 // like computed function pointers or strange arguments at call sites. 2204 // TODO: Try to unify this and the normal call bits for ARM, then try to unify 2205 // with X86. 2206 bool ARMFastISel::ARMEmitLibcall(const Instruction *I, RTLIB::Libcall Call) { 2207 CallingConv::ID CC = TLI.getLibcallCallingConv(Call); 2208 2209 // Handle *simple* calls for now. 2210 Type *RetTy = I->getType(); 2211 MVT RetVT; 2212 if (RetTy->isVoidTy()) 2213 RetVT = MVT::isVoid; 2214 else if (!isTypeLegal(RetTy, RetVT)) 2215 return false; 2216 2217 // Can't handle non-double multi-reg retvals. 2218 if (RetVT != MVT::isVoid && RetVT != MVT::i32) { 2219 SmallVector<CCValAssign, 16> RVLocs; 2220 CCState CCInfo(CC, false, *FuncInfo.MF, TM, RVLocs, *Context); 2221 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, false)); 2222 if (RVLocs.size() >= 2 && RetVT != MVT::f64) 2223 return false; 2224 } 2225 2226 // Set up the argument vectors. 2227 SmallVector<Value*, 8> Args; 2228 SmallVector<unsigned, 8> ArgRegs; 2229 SmallVector<MVT, 8> ArgVTs; 2230 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 2231 Args.reserve(I->getNumOperands()); 2232 ArgRegs.reserve(I->getNumOperands()); 2233 ArgVTs.reserve(I->getNumOperands()); 2234 ArgFlags.reserve(I->getNumOperands()); 2235 for (unsigned i = 0; i < I->getNumOperands(); ++i) { 2236 Value *Op = I->getOperand(i); 2237 unsigned Arg = getRegForValue(Op); 2238 if (Arg == 0) return false; 2239 2240 Type *ArgTy = Op->getType(); 2241 MVT ArgVT; 2242 if (!isTypeLegal(ArgTy, ArgVT)) return false; 2243 2244 ISD::ArgFlagsTy Flags; 2245 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 2246 Flags.setOrigAlign(OriginalAlignment); 2247 2248 Args.push_back(Op); 2249 ArgRegs.push_back(Arg); 2250 ArgVTs.push_back(ArgVT); 2251 ArgFlags.push_back(Flags); 2252 } 2253 2254 // Handle the arguments now that we've gotten them. 2255 SmallVector<unsigned, 4> RegArgs; 2256 unsigned NumBytes; 2257 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 2258 RegArgs, CC, NumBytes, false)) 2259 return false; 2260 2261 unsigned CalleeReg = 0; 2262 if (EnableARMLongCalls) { 2263 CalleeReg = getLibcallReg(TLI.getLibcallName(Call)); 2264 if (CalleeReg == 0) return false; 2265 } 2266 2267 // Issue the call. 2268 unsigned CallOpc = ARMSelectCallOp(EnableARMLongCalls); 2269 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2270 DL, TII.get(CallOpc)); 2271 // BL / BLX don't take a predicate, but tBL / tBLX do. 2272 if (isThumb2) 2273 AddDefaultPred(MIB); 2274 if (EnableARMLongCalls) 2275 MIB.addReg(CalleeReg); 2276 else 2277 MIB.addExternalSymbol(TLI.getLibcallName(Call)); 2278 2279 // Add implicit physical register uses to the call. 2280 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 2281 MIB.addReg(RegArgs[i], RegState::Implicit); 2282 2283 // Add a register mask with the call-preserved registers. 2284 // Proper defs for return values will be added by setPhysRegsDeadExcept(). 2285 MIB.addRegMask(TRI.getCallPreservedMask(CC)); 2286 2287 // Finish off the call including any return values. 2288 SmallVector<unsigned, 4> UsedRegs; 2289 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, false)) return false; 2290 2291 // Set all unused physreg defs as dead. 2292 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 2293 2294 return true; 2295 } 2296 2297 bool ARMFastISel::SelectCall(const Instruction *I, 2298 const char *IntrMemName = 0) { 2299 const CallInst *CI = cast<CallInst>(I); 2300 const Value *Callee = CI->getCalledValue(); 2301 2302 // Can't handle inline asm. 2303 if (isa<InlineAsm>(Callee)) return false; 2304 2305 // Allow SelectionDAG isel to handle tail calls. 2306 if (CI->isTailCall()) return false; 2307 2308 // Check the calling convention. 2309 ImmutableCallSite CS(CI); 2310 CallingConv::ID CC = CS.getCallingConv(); 2311 2312 // TODO: Avoid some calling conventions? 2313 2314 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 2315 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 2316 bool isVarArg = FTy->isVarArg(); 2317 2318 // Handle *simple* calls for now. 2319 Type *RetTy = I->getType(); 2320 MVT RetVT; 2321 if (RetTy->isVoidTy()) 2322 RetVT = MVT::isVoid; 2323 else if (!isTypeLegal(RetTy, RetVT) && RetVT != MVT::i16 && 2324 RetVT != MVT::i8 && RetVT != MVT::i1) 2325 return false; 2326 2327 // Can't handle non-double multi-reg retvals. 2328 if (RetVT != MVT::isVoid && RetVT != MVT::i1 && RetVT != MVT::i8 && 2329 RetVT != MVT::i16 && RetVT != MVT::i32) { 2330 SmallVector<CCValAssign, 16> RVLocs; 2331 CCState CCInfo(CC, isVarArg, *FuncInfo.MF, TM, RVLocs, *Context); 2332 CCInfo.AnalyzeCallResult(RetVT, CCAssignFnForCall(CC, true, isVarArg)); 2333 if (RVLocs.size() >= 2 && RetVT != MVT::f64) 2334 return false; 2335 } 2336 2337 // Set up the argument vectors. 2338 SmallVector<Value*, 8> Args; 2339 SmallVector<unsigned, 8> ArgRegs; 2340 SmallVector<MVT, 8> ArgVTs; 2341 SmallVector<ISD::ArgFlagsTy, 8> ArgFlags; 2342 unsigned arg_size = CS.arg_size(); 2343 Args.reserve(arg_size); 2344 ArgRegs.reserve(arg_size); 2345 ArgVTs.reserve(arg_size); 2346 ArgFlags.reserve(arg_size); 2347 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 2348 i != e; ++i) { 2349 // If we're lowering a memory intrinsic instead of a regular call, skip the 2350 // last two arguments, which shouldn't be passed to the underlying function. 2351 if (IntrMemName && e-i <= 2) 2352 break; 2353 2354 ISD::ArgFlagsTy Flags; 2355 unsigned AttrInd = i - CS.arg_begin() + 1; 2356 if (CS.paramHasAttr(AttrInd, Attribute::SExt)) 2357 Flags.setSExt(); 2358 if (CS.paramHasAttr(AttrInd, Attribute::ZExt)) 2359 Flags.setZExt(); 2360 2361 // FIXME: Only handle *easy* calls for now. 2362 if (CS.paramHasAttr(AttrInd, Attribute::InReg) || 2363 CS.paramHasAttr(AttrInd, Attribute::StructRet) || 2364 CS.paramHasAttr(AttrInd, Attribute::Nest) || 2365 CS.paramHasAttr(AttrInd, Attribute::ByVal)) 2366 return false; 2367 2368 Type *ArgTy = (*i)->getType(); 2369 MVT ArgVT; 2370 if (!isTypeLegal(ArgTy, ArgVT) && ArgVT != MVT::i16 && ArgVT != MVT::i8 && 2371 ArgVT != MVT::i1) 2372 return false; 2373 2374 unsigned Arg = getRegForValue(*i); 2375 if (Arg == 0) 2376 return false; 2377 2378 unsigned OriginalAlignment = TD.getABITypeAlignment(ArgTy); 2379 Flags.setOrigAlign(OriginalAlignment); 2380 2381 Args.push_back(*i); 2382 ArgRegs.push_back(Arg); 2383 ArgVTs.push_back(ArgVT); 2384 ArgFlags.push_back(Flags); 2385 } 2386 2387 // Handle the arguments now that we've gotten them. 2388 SmallVector<unsigned, 4> RegArgs; 2389 unsigned NumBytes; 2390 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, 2391 RegArgs, CC, NumBytes, isVarArg)) 2392 return false; 2393 2394 bool UseReg = false; 2395 const GlobalValue *GV = dyn_cast<GlobalValue>(Callee); 2396 if (!GV || EnableARMLongCalls) UseReg = true; 2397 2398 unsigned CalleeReg = 0; 2399 if (UseReg) { 2400 if (IntrMemName) 2401 CalleeReg = getLibcallReg(IntrMemName); 2402 else 2403 CalleeReg = getRegForValue(Callee); 2404 2405 if (CalleeReg == 0) return false; 2406 } 2407 2408 // Issue the call. 2409 unsigned CallOpc = ARMSelectCallOp(UseReg); 2410 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2411 DL, TII.get(CallOpc)); 2412 2413 // ARM calls don't take a predicate, but tBL / tBLX do. 2414 if(isThumb2) 2415 AddDefaultPred(MIB); 2416 if (UseReg) 2417 MIB.addReg(CalleeReg); 2418 else if (!IntrMemName) 2419 MIB.addGlobalAddress(GV, 0, 0); 2420 else 2421 MIB.addExternalSymbol(IntrMemName, 0); 2422 2423 // Add implicit physical register uses to the call. 2424 for (unsigned i = 0, e = RegArgs.size(); i != e; ++i) 2425 MIB.addReg(RegArgs[i], RegState::Implicit); 2426 2427 // Add a register mask with the call-preserved registers. 2428 // Proper defs for return values will be added by setPhysRegsDeadExcept(). 2429 MIB.addRegMask(TRI.getCallPreservedMask(CC)); 2430 2431 // Finish off the call including any return values. 2432 SmallVector<unsigned, 4> UsedRegs; 2433 if (!FinishCall(RetVT, UsedRegs, I, CC, NumBytes, isVarArg)) 2434 return false; 2435 2436 // Set all unused physreg defs as dead. 2437 static_cast<MachineInstr *>(MIB)->setPhysRegsDeadExcept(UsedRegs, TRI); 2438 2439 return true; 2440 } 2441 2442 bool ARMFastISel::ARMIsMemCpySmall(uint64_t Len) { 2443 return Len <= 16; 2444 } 2445 2446 bool ARMFastISel::ARMTryEmitSmallMemCpy(Address Dest, Address Src, 2447 uint64_t Len, unsigned Alignment) { 2448 // Make sure we don't bloat code by inlining very large memcpy's. 2449 if (!ARMIsMemCpySmall(Len)) 2450 return false; 2451 2452 while (Len) { 2453 MVT VT; 2454 if (!Alignment || Alignment >= 4) { 2455 if (Len >= 4) 2456 VT = MVT::i32; 2457 else if (Len >= 2) 2458 VT = MVT::i16; 2459 else { 2460 assert (Len == 1 && "Expected a length of 1!"); 2461 VT = MVT::i8; 2462 } 2463 } else { 2464 // Bound based on alignment. 2465 if (Len >= 2 && Alignment == 2) 2466 VT = MVT::i16; 2467 else { 2468 VT = MVT::i8; 2469 } 2470 } 2471 2472 bool RV; 2473 unsigned ResultReg; 2474 RV = ARMEmitLoad(VT, ResultReg, Src); 2475 assert (RV == true && "Should be able to handle this load."); 2476 RV = ARMEmitStore(VT, ResultReg, Dest); 2477 assert (RV == true && "Should be able to handle this store."); 2478 (void)RV; 2479 2480 unsigned Size = VT.getSizeInBits()/8; 2481 Len -= Size; 2482 Dest.Offset += Size; 2483 Src.Offset += Size; 2484 } 2485 2486 return true; 2487 } 2488 2489 bool ARMFastISel::SelectIntrinsicCall(const IntrinsicInst &I) { 2490 // FIXME: Handle more intrinsics. 2491 switch (I.getIntrinsicID()) { 2492 default: return false; 2493 case Intrinsic::frameaddress: { 2494 MachineFrameInfo *MFI = FuncInfo.MF->getFrameInfo(); 2495 MFI->setFrameAddressIsTaken(true); 2496 2497 unsigned LdrOpc; 2498 const TargetRegisterClass *RC; 2499 if (isThumb2) { 2500 LdrOpc = ARM::t2LDRi12; 2501 RC = (const TargetRegisterClass*)&ARM::tGPRRegClass; 2502 } else { 2503 LdrOpc = ARM::LDRi12; 2504 RC = (const TargetRegisterClass*)&ARM::GPRRegClass; 2505 } 2506 2507 const ARMBaseRegisterInfo *RegInfo = 2508 static_cast<const ARMBaseRegisterInfo*>(TM.getRegisterInfo()); 2509 unsigned FramePtr = RegInfo->getFrameRegister(*(FuncInfo.MF)); 2510 unsigned SrcReg = FramePtr; 2511 2512 // Recursively load frame address 2513 // ldr r0 [fp] 2514 // ldr r0 [r0] 2515 // ldr r0 [r0] 2516 // ... 2517 unsigned DestReg; 2518 unsigned Depth = cast<ConstantInt>(I.getOperand(0))->getZExtValue(); 2519 while (Depth--) { 2520 DestReg = createResultReg(RC); 2521 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2522 TII.get(LdrOpc), DestReg) 2523 .addReg(SrcReg).addImm(0)); 2524 SrcReg = DestReg; 2525 } 2526 UpdateValueMap(&I, SrcReg); 2527 return true; 2528 } 2529 case Intrinsic::memcpy: 2530 case Intrinsic::memmove: { 2531 const MemTransferInst &MTI = cast<MemTransferInst>(I); 2532 // Don't handle volatile. 2533 if (MTI.isVolatile()) 2534 return false; 2535 2536 // Disable inlining for memmove before calls to ComputeAddress. Otherwise, 2537 // we would emit dead code because we don't currently handle memmoves. 2538 bool isMemCpy = (I.getIntrinsicID() == Intrinsic::memcpy); 2539 if (isa<ConstantInt>(MTI.getLength()) && isMemCpy) { 2540 // Small memcpy's are common enough that we want to do them without a call 2541 // if possible. 2542 uint64_t Len = cast<ConstantInt>(MTI.getLength())->getZExtValue(); 2543 if (ARMIsMemCpySmall(Len)) { 2544 Address Dest, Src; 2545 if (!ARMComputeAddress(MTI.getRawDest(), Dest) || 2546 !ARMComputeAddress(MTI.getRawSource(), Src)) 2547 return false; 2548 unsigned Alignment = MTI.getAlignment(); 2549 if (ARMTryEmitSmallMemCpy(Dest, Src, Len, Alignment)) 2550 return true; 2551 } 2552 } 2553 2554 if (!MTI.getLength()->getType()->isIntegerTy(32)) 2555 return false; 2556 2557 if (MTI.getSourceAddressSpace() > 255 || MTI.getDestAddressSpace() > 255) 2558 return false; 2559 2560 const char *IntrMemName = isa<MemCpyInst>(I) ? "memcpy" : "memmove"; 2561 return SelectCall(&I, IntrMemName); 2562 } 2563 case Intrinsic::memset: { 2564 const MemSetInst &MSI = cast<MemSetInst>(I); 2565 // Don't handle volatile. 2566 if (MSI.isVolatile()) 2567 return false; 2568 2569 if (!MSI.getLength()->getType()->isIntegerTy(32)) 2570 return false; 2571 2572 if (MSI.getDestAddressSpace() > 255) 2573 return false; 2574 2575 return SelectCall(&I, "memset"); 2576 } 2577 case Intrinsic::trap: { 2578 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get( 2579 Subtarget->useNaClTrap() ? ARM::TRAPNaCl : ARM::TRAP)); 2580 return true; 2581 } 2582 } 2583 } 2584 2585 bool ARMFastISel::SelectTrunc(const Instruction *I) { 2586 // The high bits for a type smaller than the register size are assumed to be 2587 // undefined. 2588 Value *Op = I->getOperand(0); 2589 2590 EVT SrcVT, DestVT; 2591 SrcVT = TLI.getValueType(Op->getType(), true); 2592 DestVT = TLI.getValueType(I->getType(), true); 2593 2594 if (SrcVT != MVT::i32 && SrcVT != MVT::i16 && SrcVT != MVT::i8) 2595 return false; 2596 if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) 2597 return false; 2598 2599 unsigned SrcReg = getRegForValue(Op); 2600 if (!SrcReg) return false; 2601 2602 // Because the high bits are undefined, a truncate doesn't generate 2603 // any code. 2604 UpdateValueMap(I, SrcReg); 2605 return true; 2606 } 2607 2608 unsigned ARMFastISel::ARMEmitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, 2609 bool isZExt) { 2610 if (DestVT != MVT::i32 && DestVT != MVT::i16 && DestVT != MVT::i8) 2611 return 0; 2612 if (SrcVT != MVT::i16 && SrcVT != MVT::i8 && SrcVT != MVT::i1) 2613 return 0; 2614 2615 // Table of which combinations can be emitted as a single instruction, 2616 // and which will require two. 2617 static const uint8_t isSingleInstrTbl[3][2][2][2] = { 2618 // ARM Thumb 2619 // !hasV6Ops hasV6Ops !hasV6Ops hasV6Ops 2620 // ext: s z s z s z s z 2621 /* 1 */ { { { 0, 1 }, { 0, 1 } }, { { 0, 0 }, { 0, 1 } } }, 2622 /* 8 */ { { { 0, 1 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } }, 2623 /* 16 */ { { { 0, 0 }, { 1, 1 } }, { { 0, 0 }, { 1, 1 } } } 2624 }; 2625 2626 // Target registers for: 2627 // - For ARM can never be PC. 2628 // - For 16-bit Thumb are restricted to lower 8 registers. 2629 // - For 32-bit Thumb are restricted to non-SP and non-PC. 2630 static const TargetRegisterClass *RCTbl[2][2] = { 2631 // Instructions: Two Single 2632 /* ARM */ { &ARM::GPRnopcRegClass, &ARM::GPRnopcRegClass }, 2633 /* Thumb */ { &ARM::tGPRRegClass, &ARM::rGPRRegClass } 2634 }; 2635 2636 // Table governing the instruction(s) to be emitted. 2637 static const struct InstructionTable { 2638 uint32_t Opc : 16; 2639 uint32_t hasS : 1; // Some instructions have an S bit, always set it to 0. 2640 uint32_t Shift : 7; // For shift operand addressing mode, used by MOVsi. 2641 uint32_t Imm : 8; // All instructions have either a shift or a mask. 2642 } IT[2][2][3][2] = { 2643 { // Two instructions (first is left shift, second is in this table). 2644 { // ARM Opc S Shift Imm 2645 /* 1 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 31 }, 2646 /* 1 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 31 } }, 2647 /* 8 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 24 }, 2648 /* 8 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 24 } }, 2649 /* 16 bit sext */ { { ARM::MOVsi , 1, ARM_AM::asr , 16 }, 2650 /* 16 bit zext */ { ARM::MOVsi , 1, ARM_AM::lsr , 16 } } 2651 }, 2652 { // Thumb Opc S Shift Imm 2653 /* 1 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 31 }, 2654 /* 1 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 31 } }, 2655 /* 8 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 24 }, 2656 /* 8 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 24 } }, 2657 /* 16 bit sext */ { { ARM::tASRri , 0, ARM_AM::no_shift, 16 }, 2658 /* 16 bit zext */ { ARM::tLSRri , 0, ARM_AM::no_shift, 16 } } 2659 } 2660 }, 2661 { // Single instruction. 2662 { // ARM Opc S Shift Imm 2663 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, 2664 /* 1 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 1 } }, 2665 /* 8 bit sext */ { { ARM::SXTB , 0, ARM_AM::no_shift, 0 }, 2666 /* 8 bit zext */ { ARM::ANDri , 1, ARM_AM::no_shift, 255 } }, 2667 /* 16 bit sext */ { { ARM::SXTH , 0, ARM_AM::no_shift, 0 }, 2668 /* 16 bit zext */ { ARM::UXTH , 0, ARM_AM::no_shift, 0 } } 2669 }, 2670 { // Thumb Opc S Shift Imm 2671 /* 1 bit sext */ { { ARM::KILL , 0, ARM_AM::no_shift, 0 }, 2672 /* 1 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 1 } }, 2673 /* 8 bit sext */ { { ARM::t2SXTB , 0, ARM_AM::no_shift, 0 }, 2674 /* 8 bit zext */ { ARM::t2ANDri, 1, ARM_AM::no_shift, 255 } }, 2675 /* 16 bit sext */ { { ARM::t2SXTH , 0, ARM_AM::no_shift, 0 }, 2676 /* 16 bit zext */ { ARM::t2UXTH , 0, ARM_AM::no_shift, 0 } } 2677 } 2678 } 2679 }; 2680 2681 unsigned SrcBits = SrcVT.getSizeInBits(); 2682 unsigned DestBits = DestVT.getSizeInBits(); 2683 (void) DestBits; 2684 assert((SrcBits < DestBits) && "can only extend to larger types"); 2685 assert((DestBits == 32 || DestBits == 16 || DestBits == 8) && 2686 "other sizes unimplemented"); 2687 assert((SrcBits == 16 || SrcBits == 8 || SrcBits == 1) && 2688 "other sizes unimplemented"); 2689 2690 bool hasV6Ops = Subtarget->hasV6Ops(); 2691 unsigned Bitness = SrcBits / 8; // {1,8,16}=>{0,1,2} 2692 assert((Bitness < 3) && "sanity-check table bounds"); 2693 2694 bool isSingleInstr = isSingleInstrTbl[Bitness][isThumb2][hasV6Ops][isZExt]; 2695 const TargetRegisterClass *RC = RCTbl[isThumb2][isSingleInstr]; 2696 const InstructionTable *ITP = &IT[isSingleInstr][isThumb2][Bitness][isZExt]; 2697 unsigned Opc = ITP->Opc; 2698 assert(ARM::KILL != Opc && "Invalid table entry"); 2699 unsigned hasS = ITP->hasS; 2700 ARM_AM::ShiftOpc Shift = (ARM_AM::ShiftOpc) ITP->Shift; 2701 assert(((Shift == ARM_AM::no_shift) == (Opc != ARM::MOVsi)) && 2702 "only MOVsi has shift operand addressing mode"); 2703 unsigned Imm = ITP->Imm; 2704 2705 // 16-bit Thumb instructions always set CPSR (unless they're in an IT block). 2706 bool setsCPSR = &ARM::tGPRRegClass == RC; 2707 unsigned LSLOpc = isThumb2 ? ARM::tLSLri : ARM::MOVsi; 2708 unsigned ResultReg; 2709 // MOVsi encodes shift and immediate in shift operand addressing mode. 2710 // The following condition has the same value when emitting two 2711 // instruction sequences: both are shifts. 2712 bool ImmIsSO = (Shift != ARM_AM::no_shift); 2713 2714 // Either one or two instructions are emitted. 2715 // They're always of the form: 2716 // dst = in OP imm 2717 // CPSR is set only by 16-bit Thumb instructions. 2718 // Predicate, if any, is AL. 2719 // S bit, if available, is always 0. 2720 // When two are emitted the first's result will feed as the second's input, 2721 // that value is then dead. 2722 unsigned NumInstrsEmitted = isSingleInstr ? 1 : 2; 2723 for (unsigned Instr = 0; Instr != NumInstrsEmitted; ++Instr) { 2724 ResultReg = createResultReg(RC); 2725 bool isLsl = (0 == Instr) && !isSingleInstr; 2726 unsigned Opcode = isLsl ? LSLOpc : Opc; 2727 ARM_AM::ShiftOpc ShiftAM = isLsl ? ARM_AM::lsl : Shift; 2728 unsigned ImmEnc = ImmIsSO ? ARM_AM::getSORegOpc(ShiftAM, Imm) : Imm; 2729 bool isKill = 1 == Instr; 2730 MachineInstrBuilder MIB = BuildMI( 2731 *FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opcode), ResultReg); 2732 if (setsCPSR) 2733 MIB.addReg(ARM::CPSR, RegState::Define); 2734 AddDefaultPred(MIB.addReg(SrcReg, isKill * RegState::Kill).addImm(ImmEnc)); 2735 if (hasS) 2736 AddDefaultCC(MIB); 2737 // Second instruction consumes the first's result. 2738 SrcReg = ResultReg; 2739 } 2740 2741 return ResultReg; 2742 } 2743 2744 bool ARMFastISel::SelectIntExt(const Instruction *I) { 2745 // On ARM, in general, integer casts don't involve legal types; this code 2746 // handles promotable integers. 2747 Type *DestTy = I->getType(); 2748 Value *Src = I->getOperand(0); 2749 Type *SrcTy = Src->getType(); 2750 2751 bool isZExt = isa<ZExtInst>(I); 2752 unsigned SrcReg = getRegForValue(Src); 2753 if (!SrcReg) return false; 2754 2755 EVT SrcEVT, DestEVT; 2756 SrcEVT = TLI.getValueType(SrcTy, true); 2757 DestEVT = TLI.getValueType(DestTy, true); 2758 if (!SrcEVT.isSimple()) return false; 2759 if (!DestEVT.isSimple()) return false; 2760 2761 MVT SrcVT = SrcEVT.getSimpleVT(); 2762 MVT DestVT = DestEVT.getSimpleVT(); 2763 unsigned ResultReg = ARMEmitIntExt(SrcVT, SrcReg, DestVT, isZExt); 2764 if (ResultReg == 0) return false; 2765 UpdateValueMap(I, ResultReg); 2766 return true; 2767 } 2768 2769 bool ARMFastISel::SelectShift(const Instruction *I, 2770 ARM_AM::ShiftOpc ShiftTy) { 2771 // We handle thumb2 mode by target independent selector 2772 // or SelectionDAG ISel. 2773 if (isThumb2) 2774 return false; 2775 2776 // Only handle i32 now. 2777 EVT DestVT = TLI.getValueType(I->getType(), true); 2778 if (DestVT != MVT::i32) 2779 return false; 2780 2781 unsigned Opc = ARM::MOVsr; 2782 unsigned ShiftImm; 2783 Value *Src2Value = I->getOperand(1); 2784 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Src2Value)) { 2785 ShiftImm = CI->getZExtValue(); 2786 2787 // Fall back to selection DAG isel if the shift amount 2788 // is zero or greater than the width of the value type. 2789 if (ShiftImm == 0 || ShiftImm >=32) 2790 return false; 2791 2792 Opc = ARM::MOVsi; 2793 } 2794 2795 Value *Src1Value = I->getOperand(0); 2796 unsigned Reg1 = getRegForValue(Src1Value); 2797 if (Reg1 == 0) return false; 2798 2799 unsigned Reg2 = 0; 2800 if (Opc == ARM::MOVsr) { 2801 Reg2 = getRegForValue(Src2Value); 2802 if (Reg2 == 0) return false; 2803 } 2804 2805 unsigned ResultReg = createResultReg(&ARM::GPRnopcRegClass); 2806 if(ResultReg == 0) return false; 2807 2808 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2809 TII.get(Opc), ResultReg) 2810 .addReg(Reg1); 2811 2812 if (Opc == ARM::MOVsi) 2813 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, ShiftImm)); 2814 else if (Opc == ARM::MOVsr) { 2815 MIB.addReg(Reg2); 2816 MIB.addImm(ARM_AM::getSORegOpc(ShiftTy, 0)); 2817 } 2818 2819 AddOptionalDefs(MIB); 2820 UpdateValueMap(I, ResultReg); 2821 return true; 2822 } 2823 2824 // TODO: SoftFP support. 2825 bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { 2826 2827 switch (I->getOpcode()) { 2828 case Instruction::Load: 2829 return SelectLoad(I); 2830 case Instruction::Store: 2831 return SelectStore(I); 2832 case Instruction::Br: 2833 return SelectBranch(I); 2834 case Instruction::IndirectBr: 2835 return SelectIndirectBr(I); 2836 case Instruction::ICmp: 2837 case Instruction::FCmp: 2838 return SelectCmp(I); 2839 case Instruction::FPExt: 2840 return SelectFPExt(I); 2841 case Instruction::FPTrunc: 2842 return SelectFPTrunc(I); 2843 case Instruction::SIToFP: 2844 return SelectIToFP(I, /*isSigned*/ true); 2845 case Instruction::UIToFP: 2846 return SelectIToFP(I, /*isSigned*/ false); 2847 case Instruction::FPToSI: 2848 return SelectFPToI(I, /*isSigned*/ true); 2849 case Instruction::FPToUI: 2850 return SelectFPToI(I, /*isSigned*/ false); 2851 case Instruction::Add: 2852 return SelectBinaryIntOp(I, ISD::ADD); 2853 case Instruction::Or: 2854 return SelectBinaryIntOp(I, ISD::OR); 2855 case Instruction::Sub: 2856 return SelectBinaryIntOp(I, ISD::SUB); 2857 case Instruction::FAdd: 2858 return SelectBinaryFPOp(I, ISD::FADD); 2859 case Instruction::FSub: 2860 return SelectBinaryFPOp(I, ISD::FSUB); 2861 case Instruction::FMul: 2862 return SelectBinaryFPOp(I, ISD::FMUL); 2863 case Instruction::SDiv: 2864 return SelectDiv(I, /*isSigned*/ true); 2865 case Instruction::UDiv: 2866 return SelectDiv(I, /*isSigned*/ false); 2867 case Instruction::SRem: 2868 return SelectRem(I, /*isSigned*/ true); 2869 case Instruction::URem: 2870 return SelectRem(I, /*isSigned*/ false); 2871 case Instruction::Call: 2872 if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(I)) 2873 return SelectIntrinsicCall(*II); 2874 return SelectCall(I); 2875 case Instruction::Select: 2876 return SelectSelect(I); 2877 case Instruction::Ret: 2878 return SelectRet(I); 2879 case Instruction::Trunc: 2880 return SelectTrunc(I); 2881 case Instruction::ZExt: 2882 case Instruction::SExt: 2883 return SelectIntExt(I); 2884 case Instruction::Shl: 2885 return SelectShift(I, ARM_AM::lsl); 2886 case Instruction::LShr: 2887 return SelectShift(I, ARM_AM::lsr); 2888 case Instruction::AShr: 2889 return SelectShift(I, ARM_AM::asr); 2890 default: break; 2891 } 2892 return false; 2893 } 2894 2895 namespace { 2896 // This table describes sign- and zero-extend instructions which can be 2897 // folded into a preceding load. All of these extends have an immediate 2898 // (sometimes a mask and sometimes a shift) that's applied after 2899 // extension. 2900 const struct FoldableLoadExtendsStruct { 2901 uint16_t Opc[2]; // ARM, Thumb. 2902 uint8_t ExpectedImm; 2903 uint8_t isZExt : 1; 2904 uint8_t ExpectedVT : 7; 2905 } FoldableLoadExtends[] = { 2906 { { ARM::SXTH, ARM::t2SXTH }, 0, 0, MVT::i16 }, 2907 { { ARM::UXTH, ARM::t2UXTH }, 0, 1, MVT::i16 }, 2908 { { ARM::ANDri, ARM::t2ANDri }, 255, 1, MVT::i8 }, 2909 { { ARM::SXTB, ARM::t2SXTB }, 0, 0, MVT::i8 }, 2910 { { ARM::UXTB, ARM::t2UXTB }, 0, 1, MVT::i8 } 2911 }; 2912 } 2913 2914 /// \brief The specified machine instr operand is a vreg, and that 2915 /// vreg is being provided by the specified load instruction. If possible, 2916 /// try to fold the load as an operand to the instruction, returning true if 2917 /// successful. 2918 bool ARMFastISel::tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo, 2919 const LoadInst *LI) { 2920 // Verify we have a legal type before going any further. 2921 MVT VT; 2922 if (!isLoadTypeLegal(LI->getType(), VT)) 2923 return false; 2924 2925 // Combine load followed by zero- or sign-extend. 2926 // ldrb r1, [r0] ldrb r1, [r0] 2927 // uxtb r2, r1 => 2928 // mov r3, r2 mov r3, r1 2929 if (MI->getNumOperands() < 3 || !MI->getOperand(2).isImm()) 2930 return false; 2931 const uint64_t Imm = MI->getOperand(2).getImm(); 2932 2933 bool Found = false; 2934 bool isZExt; 2935 for (unsigned i = 0, e = array_lengthof(FoldableLoadExtends); 2936 i != e; ++i) { 2937 if (FoldableLoadExtends[i].Opc[isThumb2] == MI->getOpcode() && 2938 (uint64_t)FoldableLoadExtends[i].ExpectedImm == Imm && 2939 MVT((MVT::SimpleValueType)FoldableLoadExtends[i].ExpectedVT) == VT) { 2940 Found = true; 2941 isZExt = FoldableLoadExtends[i].isZExt; 2942 } 2943 } 2944 if (!Found) return false; 2945 2946 // See if we can handle this address. 2947 Address Addr; 2948 if (!ARMComputeAddress(LI->getOperand(0), Addr)) return false; 2949 2950 unsigned ResultReg = MI->getOperand(0).getReg(); 2951 if (!ARMEmitLoad(VT, ResultReg, Addr, LI->getAlignment(), isZExt, false)) 2952 return false; 2953 MI->eraseFromParent(); 2954 return true; 2955 } 2956 2957 unsigned ARMFastISel::ARMLowerPICELF(const GlobalValue *GV, 2958 unsigned Align, MVT VT) { 2959 bool UseGOTOFF = GV->hasLocalLinkage() || GV->hasHiddenVisibility(); 2960 ARMConstantPoolConstant *CPV = 2961 ARMConstantPoolConstant::Create(GV, UseGOTOFF ? ARMCP::GOTOFF : ARMCP::GOT); 2962 unsigned Idx = MCP.getConstantPoolIndex(CPV, Align); 2963 2964 unsigned Opc; 2965 unsigned DestReg1 = createResultReg(TLI.getRegClassFor(VT)); 2966 // Load value. 2967 if (isThumb2) { 2968 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, 2969 TII.get(ARM::t2LDRpci), DestReg1) 2970 .addConstantPoolIndex(Idx)); 2971 Opc = UseGOTOFF ? ARM::t2ADDrr : ARM::t2LDRs; 2972 } else { 2973 // The extra immediate is for addrmode2. 2974 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2975 DL, TII.get(ARM::LDRcp), DestReg1) 2976 .addConstantPoolIndex(Idx).addImm(0)); 2977 Opc = UseGOTOFF ? ARM::ADDrr : ARM::LDRrs; 2978 } 2979 2980 unsigned GlobalBaseReg = AFI->getGlobalBaseReg(); 2981 if (GlobalBaseReg == 0) { 2982 GlobalBaseReg = MRI.createVirtualRegister(TLI.getRegClassFor(VT)); 2983 AFI->setGlobalBaseReg(GlobalBaseReg); 2984 } 2985 2986 unsigned DestReg2 = createResultReg(TLI.getRegClassFor(VT)); 2987 MachineInstrBuilder MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, 2988 DL, TII.get(Opc), DestReg2) 2989 .addReg(DestReg1) 2990 .addReg(GlobalBaseReg); 2991 if (!UseGOTOFF) 2992 MIB.addImm(0); 2993 AddOptionalDefs(MIB); 2994 2995 return DestReg2; 2996 } 2997 2998 bool ARMFastISel::FastLowerArguments() { 2999 if (!FuncInfo.CanLowerReturn) 3000 return false; 3001 3002 const Function *F = FuncInfo.Fn; 3003 if (F->isVarArg()) 3004 return false; 3005 3006 CallingConv::ID CC = F->getCallingConv(); 3007 switch (CC) { 3008 default: 3009 return false; 3010 case CallingConv::Fast: 3011 case CallingConv::C: 3012 case CallingConv::ARM_AAPCS_VFP: 3013 case CallingConv::ARM_AAPCS: 3014 case CallingConv::ARM_APCS: 3015 break; 3016 } 3017 3018 // Only handle simple cases. i.e. Up to 4 i8/i16/i32 scalar arguments 3019 // which are passed in r0 - r3. 3020 unsigned Idx = 1; 3021 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 3022 I != E; ++I, ++Idx) { 3023 if (Idx > 4) 3024 return false; 3025 3026 if (F->getAttributes().hasAttribute(Idx, Attribute::InReg) || 3027 F->getAttributes().hasAttribute(Idx, Attribute::StructRet) || 3028 F->getAttributes().hasAttribute(Idx, Attribute::ByVal)) 3029 return false; 3030 3031 Type *ArgTy = I->getType(); 3032 if (ArgTy->isStructTy() || ArgTy->isArrayTy() || ArgTy->isVectorTy()) 3033 return false; 3034 3035 EVT ArgVT = TLI.getValueType(ArgTy); 3036 if (!ArgVT.isSimple()) return false; 3037 switch (ArgVT.getSimpleVT().SimpleTy) { 3038 case MVT::i8: 3039 case MVT::i16: 3040 case MVT::i32: 3041 break; 3042 default: 3043 return false; 3044 } 3045 } 3046 3047 3048 static const uint16_t GPRArgRegs[] = { 3049 ARM::R0, ARM::R1, ARM::R2, ARM::R3 3050 }; 3051 3052 const TargetRegisterClass *RC = TLI.getRegClassFor(MVT::i32); 3053 Idx = 0; 3054 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 3055 I != E; ++I, ++Idx) { 3056 unsigned SrcReg = GPRArgRegs[Idx]; 3057 unsigned DstReg = FuncInfo.MF->addLiveIn(SrcReg, RC); 3058 // FIXME: Unfortunately it's necessary to emit a copy from the livein copy. 3059 // Without this, EmitLiveInCopies may eliminate the livein if its only 3060 // use is a bitcast (which isn't turned into an instruction). 3061 unsigned ResultReg = createResultReg(RC); 3062 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(TargetOpcode::COPY), 3063 ResultReg).addReg(DstReg, getKillRegState(true)); 3064 UpdateValueMap(I, ResultReg); 3065 } 3066 3067 return true; 3068 } 3069 3070 namespace llvm { 3071 FastISel *ARM::createFastISel(FunctionLoweringInfo &funcInfo, 3072 const TargetLibraryInfo *libInfo) { 3073 const TargetMachine &TM = funcInfo.MF->getTarget(); 3074 3075 const ARMSubtarget *Subtarget = &TM.getSubtarget<ARMSubtarget>(); 3076 // Thumb2 support on iOS; ARM support on iOS, Linux and NaCl. 3077 bool UseFastISel = false; 3078 UseFastISel |= Subtarget->isTargetIOS() && !Subtarget->isThumb1Only(); 3079 UseFastISel |= Subtarget->isTargetLinux() && !Subtarget->isThumb(); 3080 UseFastISel |= Subtarget->isTargetNaCl() && !Subtarget->isThumb(); 3081 3082 if (UseFastISel) { 3083 // iOS always has a FP for backtracking, force other targets 3084 // to keep their FP when doing FastISel. The emitted code is 3085 // currently superior, and in cases like test-suite's lencod 3086 // FastISel isn't quite correct when FP is eliminated. 3087 TM.Options.NoFramePointerElim = true; 3088 return new ARMFastISel(funcInfo, libInfo); 3089 } 3090 return 0; 3091 } 3092 } 3093
