1 //===-- SelectionDAGISel.cpp - Implement the SelectionDAGISel class -------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements the SelectionDAGISel class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "isel" 15 #include "ScheduleDAGSDNodes.h" 16 #include "SelectionDAGBuilder.h" 17 #include "llvm/Constants.h" 18 #include "llvm/DebugInfo.h" 19 #include "llvm/Function.h" 20 #include "llvm/InlineAsm.h" 21 #include "llvm/Instructions.h" 22 #include "llvm/Intrinsics.h" 23 #include "llvm/IntrinsicInst.h" 24 #include "llvm/LLVMContext.h" 25 #include "llvm/Module.h" 26 #include "llvm/Analysis/AliasAnalysis.h" 27 #include "llvm/Analysis/BranchProbabilityInfo.h" 28 #include "llvm/CodeGen/FastISel.h" 29 #include "llvm/CodeGen/FunctionLoweringInfo.h" 30 #include "llvm/CodeGen/GCStrategy.h" 31 #include "llvm/CodeGen/GCMetadata.h" 32 #include "llvm/CodeGen/MachineFrameInfo.h" 33 #include "llvm/CodeGen/MachineFunction.h" 34 #include "llvm/CodeGen/MachineInstrBuilder.h" 35 #include "llvm/CodeGen/MachineModuleInfo.h" 36 #include "llvm/CodeGen/MachineRegisterInfo.h" 37 #include "llvm/CodeGen/ScheduleHazardRecognizer.h" 38 #include "llvm/CodeGen/SchedulerRegistry.h" 39 #include "llvm/CodeGen/SelectionDAG.h" 40 #include "llvm/CodeGen/SelectionDAGISel.h" 41 #include "llvm/Target/TargetRegisterInfo.h" 42 #include "llvm/Target/TargetIntrinsicInfo.h" 43 #include "llvm/Target/TargetInstrInfo.h" 44 #include "llvm/Target/TargetLibraryInfo.h" 45 #include "llvm/Target/TargetLowering.h" 46 #include "llvm/Target/TargetMachine.h" 47 #include "llvm/Target/TargetOptions.h" 48 #include "llvm/Transforms/Utils/BasicBlockUtils.h" 49 #include "llvm/Support/Compiler.h" 50 #include "llvm/Support/Debug.h" 51 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/Timer.h" 53 #include "llvm/Support/raw_ostream.h" 54 #include "llvm/ADT/PostOrderIterator.h" 55 #include "llvm/ADT/Statistic.h" 56 #include <algorithm> 57 using namespace llvm; 58 59 STATISTIC(NumFastIselFailures, "Number of instructions fast isel failed on"); 60 STATISTIC(NumFastIselSuccess, "Number of instructions fast isel selected"); 61 STATISTIC(NumFastIselBlocks, "Number of blocks selected entirely by fast isel"); 62 STATISTIC(NumDAGBlocks, "Number of blocks selected using DAG"); 63 STATISTIC(NumDAGIselRetries,"Number of times dag isel has to try another path"); 64 65 #ifndef NDEBUG 66 static cl::opt<bool> 67 EnableFastISelVerbose2("fast-isel-verbose2", cl::Hidden, 68 cl::desc("Enable extra verbose messages in the \"fast\" " 69 "instruction selector")); 70 // Terminators 71 STATISTIC(NumFastIselFailRet,"Fast isel fails on Ret"); 72 STATISTIC(NumFastIselFailBr,"Fast isel fails on Br"); 73 STATISTIC(NumFastIselFailSwitch,"Fast isel fails on Switch"); 74 STATISTIC(NumFastIselFailIndirectBr,"Fast isel fails on IndirectBr"); 75 STATISTIC(NumFastIselFailInvoke,"Fast isel fails on Invoke"); 76 STATISTIC(NumFastIselFailResume,"Fast isel fails on Resume"); 77 STATISTIC(NumFastIselFailUnreachable,"Fast isel fails on Unreachable"); 78 79 // Standard binary operators... 80 STATISTIC(NumFastIselFailAdd,"Fast isel fails on Add"); 81 STATISTIC(NumFastIselFailFAdd,"Fast isel fails on FAdd"); 82 STATISTIC(NumFastIselFailSub,"Fast isel fails on Sub"); 83 STATISTIC(NumFastIselFailFSub,"Fast isel fails on FSub"); 84 STATISTIC(NumFastIselFailMul,"Fast isel fails on Mul"); 85 STATISTIC(NumFastIselFailFMul,"Fast isel fails on FMul"); 86 STATISTIC(NumFastIselFailUDiv,"Fast isel fails on UDiv"); 87 STATISTIC(NumFastIselFailSDiv,"Fast isel fails on SDiv"); 88 STATISTIC(NumFastIselFailFDiv,"Fast isel fails on FDiv"); 89 STATISTIC(NumFastIselFailURem,"Fast isel fails on URem"); 90 STATISTIC(NumFastIselFailSRem,"Fast isel fails on SRem"); 91 STATISTIC(NumFastIselFailFRem,"Fast isel fails on FRem"); 92 93 // Logical operators... 94 STATISTIC(NumFastIselFailAnd,"Fast isel fails on And"); 95 STATISTIC(NumFastIselFailOr,"Fast isel fails on Or"); 96 STATISTIC(NumFastIselFailXor,"Fast isel fails on Xor"); 97 98 // Memory instructions... 99 STATISTIC(NumFastIselFailAlloca,"Fast isel fails on Alloca"); 100 STATISTIC(NumFastIselFailLoad,"Fast isel fails on Load"); 101 STATISTIC(NumFastIselFailStore,"Fast isel fails on Store"); 102 STATISTIC(NumFastIselFailAtomicCmpXchg,"Fast isel fails on AtomicCmpXchg"); 103 STATISTIC(NumFastIselFailAtomicRMW,"Fast isel fails on AtomicRWM"); 104 STATISTIC(NumFastIselFailFence,"Fast isel fails on Frence"); 105 STATISTIC(NumFastIselFailGetElementPtr,"Fast isel fails on GetElementPtr"); 106 107 // Convert instructions... 108 STATISTIC(NumFastIselFailTrunc,"Fast isel fails on Trunc"); 109 STATISTIC(NumFastIselFailZExt,"Fast isel fails on ZExt"); 110 STATISTIC(NumFastIselFailSExt,"Fast isel fails on SExt"); 111 STATISTIC(NumFastIselFailFPTrunc,"Fast isel fails on FPTrunc"); 112 STATISTIC(NumFastIselFailFPExt,"Fast isel fails on FPExt"); 113 STATISTIC(NumFastIselFailFPToUI,"Fast isel fails on FPToUI"); 114 STATISTIC(NumFastIselFailFPToSI,"Fast isel fails on FPToSI"); 115 STATISTIC(NumFastIselFailUIToFP,"Fast isel fails on UIToFP"); 116 STATISTIC(NumFastIselFailSIToFP,"Fast isel fails on SIToFP"); 117 STATISTIC(NumFastIselFailIntToPtr,"Fast isel fails on IntToPtr"); 118 STATISTIC(NumFastIselFailPtrToInt,"Fast isel fails on PtrToInt"); 119 STATISTIC(NumFastIselFailBitCast,"Fast isel fails on BitCast"); 120 121 // Other instructions... 122 STATISTIC(NumFastIselFailICmp,"Fast isel fails on ICmp"); 123 STATISTIC(NumFastIselFailFCmp,"Fast isel fails on FCmp"); 124 STATISTIC(NumFastIselFailPHI,"Fast isel fails on PHI"); 125 STATISTIC(NumFastIselFailSelect,"Fast isel fails on Select"); 126 STATISTIC(NumFastIselFailCall,"Fast isel fails on Call"); 127 STATISTIC(NumFastIselFailShl,"Fast isel fails on Shl"); 128 STATISTIC(NumFastIselFailLShr,"Fast isel fails on LShr"); 129 STATISTIC(NumFastIselFailAShr,"Fast isel fails on AShr"); 130 STATISTIC(NumFastIselFailVAArg,"Fast isel fails on VAArg"); 131 STATISTIC(NumFastIselFailExtractElement,"Fast isel fails on ExtractElement"); 132 STATISTIC(NumFastIselFailInsertElement,"Fast isel fails on InsertElement"); 133 STATISTIC(NumFastIselFailShuffleVector,"Fast isel fails on ShuffleVector"); 134 STATISTIC(NumFastIselFailExtractValue,"Fast isel fails on ExtractValue"); 135 STATISTIC(NumFastIselFailInsertValue,"Fast isel fails on InsertValue"); 136 STATISTIC(NumFastIselFailLandingPad,"Fast isel fails on LandingPad"); 137 #endif 138 139 static cl::opt<bool> 140 EnableFastISelVerbose("fast-isel-verbose", cl::Hidden, 141 cl::desc("Enable verbose messages in the \"fast\" " 142 "instruction selector")); 143 static cl::opt<bool> 144 EnableFastISelAbort("fast-isel-abort", cl::Hidden, 145 cl::desc("Enable abort calls when \"fast\" instruction fails")); 146 147 static cl::opt<bool> 148 UseMBPI("use-mbpi", 149 cl::desc("use Machine Branch Probability Info"), 150 cl::init(true), cl::Hidden); 151 152 #ifndef NDEBUG 153 static cl::opt<bool> 154 ViewDAGCombine1("view-dag-combine1-dags", cl::Hidden, 155 cl::desc("Pop up a window to show dags before the first " 156 "dag combine pass")); 157 static cl::opt<bool> 158 ViewLegalizeTypesDAGs("view-legalize-types-dags", cl::Hidden, 159 cl::desc("Pop up a window to show dags before legalize types")); 160 static cl::opt<bool> 161 ViewLegalizeDAGs("view-legalize-dags", cl::Hidden, 162 cl::desc("Pop up a window to show dags before legalize")); 163 static cl::opt<bool> 164 ViewDAGCombine2("view-dag-combine2-dags", cl::Hidden, 165 cl::desc("Pop up a window to show dags before the second " 166 "dag combine pass")); 167 static cl::opt<bool> 168 ViewDAGCombineLT("view-dag-combine-lt-dags", cl::Hidden, 169 cl::desc("Pop up a window to show dags before the post legalize types" 170 " dag combine pass")); 171 static cl::opt<bool> 172 ViewISelDAGs("view-isel-dags", cl::Hidden, 173 cl::desc("Pop up a window to show isel dags as they are selected")); 174 static cl::opt<bool> 175 ViewSchedDAGs("view-sched-dags", cl::Hidden, 176 cl::desc("Pop up a window to show sched dags as they are processed")); 177 static cl::opt<bool> 178 ViewSUnitDAGs("view-sunit-dags", cl::Hidden, 179 cl::desc("Pop up a window to show SUnit dags after they are processed")); 180 #else 181 static const bool ViewDAGCombine1 = false, 182 ViewLegalizeTypesDAGs = false, ViewLegalizeDAGs = false, 183 ViewDAGCombine2 = false, 184 ViewDAGCombineLT = false, 185 ViewISelDAGs = false, ViewSchedDAGs = false, 186 ViewSUnitDAGs = false; 187 #endif 188 189 //===---------------------------------------------------------------------===// 190 /// 191 /// RegisterScheduler class - Track the registration of instruction schedulers. 192 /// 193 //===---------------------------------------------------------------------===// 194 MachinePassRegistry RegisterScheduler::Registry; 195 196 //===---------------------------------------------------------------------===// 197 /// 198 /// ISHeuristic command line option for instruction schedulers. 199 /// 200 //===---------------------------------------------------------------------===// 201 static cl::opt<RegisterScheduler::FunctionPassCtor, false, 202 RegisterPassParser<RegisterScheduler> > 203 ISHeuristic("pre-RA-sched", 204 cl::init(&createDefaultScheduler), 205 cl::desc("Instruction schedulers available (before register" 206 " allocation):")); 207 208 static RegisterScheduler 209 defaultListDAGScheduler("default", "Best scheduler for the target", 210 createDefaultScheduler); 211 212 namespace llvm { 213 //===--------------------------------------------------------------------===// 214 /// createDefaultScheduler - This creates an instruction scheduler appropriate 215 /// for the target. 216 ScheduleDAGSDNodes* createDefaultScheduler(SelectionDAGISel *IS, 217 CodeGenOpt::Level OptLevel) { 218 const TargetLowering &TLI = IS->getTargetLowering(); 219 220 if (OptLevel == CodeGenOpt::None || 221 TLI.getSchedulingPreference() == Sched::Source) 222 return createSourceListDAGScheduler(IS, OptLevel); 223 if (TLI.getSchedulingPreference() == Sched::RegPressure) 224 return createBURRListDAGScheduler(IS, OptLevel); 225 if (TLI.getSchedulingPreference() == Sched::Hybrid) 226 return createHybridListDAGScheduler(IS, OptLevel); 227 if (TLI.getSchedulingPreference() == Sched::VLIW) 228 return createVLIWDAGScheduler(IS, OptLevel); 229 assert(TLI.getSchedulingPreference() == Sched::ILP && 230 "Unknown sched type!"); 231 return createILPListDAGScheduler(IS, OptLevel); 232 } 233 } 234 235 // EmitInstrWithCustomInserter - This method should be implemented by targets 236 // that mark instructions with the 'usesCustomInserter' flag. These 237 // instructions are special in various ways, which require special support to 238 // insert. The specified MachineInstr is created but not inserted into any 239 // basic blocks, and this method is called to expand it into a sequence of 240 // instructions, potentially also creating new basic blocks and control flow. 241 // When new basic blocks are inserted and the edges from MBB to its successors 242 // are modified, the method should insert pairs of <OldSucc, NewSucc> into the 243 // DenseMap. 244 MachineBasicBlock * 245 TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 246 MachineBasicBlock *MBB) const { 247 #ifndef NDEBUG 248 dbgs() << "If a target marks an instruction with " 249 "'usesCustomInserter', it must implement " 250 "TargetLowering::EmitInstrWithCustomInserter!"; 251 #endif 252 llvm_unreachable(0); 253 } 254 255 void TargetLowering::AdjustInstrPostInstrSelection(MachineInstr *MI, 256 SDNode *Node) const { 257 assert(!MI->hasPostISelHook() && 258 "If a target marks an instruction with 'hasPostISelHook', " 259 "it must implement TargetLowering::AdjustInstrPostInstrSelection!"); 260 } 261 262 //===----------------------------------------------------------------------===// 263 // SelectionDAGISel code 264 //===----------------------------------------------------------------------===// 265 266 SelectionDAGISel::SelectionDAGISel(const TargetMachine &tm, 267 CodeGenOpt::Level OL) : 268 MachineFunctionPass(ID), TM(tm), TLI(*tm.getTargetLowering()), 269 FuncInfo(new FunctionLoweringInfo(TLI)), 270 CurDAG(new SelectionDAG(tm, OL)), 271 SDB(new SelectionDAGBuilder(*CurDAG, *FuncInfo, OL)), 272 GFI(), 273 OptLevel(OL), 274 DAGSize(0) { 275 initializeGCModuleInfoPass(*PassRegistry::getPassRegistry()); 276 initializeAliasAnalysisAnalysisGroup(*PassRegistry::getPassRegistry()); 277 initializeBranchProbabilityInfoPass(*PassRegistry::getPassRegistry()); 278 initializeTargetLibraryInfoPass(*PassRegistry::getPassRegistry()); 279 } 280 281 SelectionDAGISel::~SelectionDAGISel() { 282 delete SDB; 283 delete CurDAG; 284 delete FuncInfo; 285 } 286 287 void SelectionDAGISel::getAnalysisUsage(AnalysisUsage &AU) const { 288 AU.addRequired<AliasAnalysis>(); 289 AU.addPreserved<AliasAnalysis>(); 290 AU.addRequired<GCModuleInfo>(); 291 AU.addPreserved<GCModuleInfo>(); 292 AU.addRequired<TargetLibraryInfo>(); 293 if (UseMBPI && OptLevel != CodeGenOpt::None) 294 AU.addRequired<BranchProbabilityInfo>(); 295 MachineFunctionPass::getAnalysisUsage(AU); 296 } 297 298 /// SplitCriticalSideEffectEdges - Look for critical edges with a PHI value that 299 /// may trap on it. In this case we have to split the edge so that the path 300 /// through the predecessor block that doesn't go to the phi block doesn't 301 /// execute the possibly trapping instruction. 302 /// 303 /// This is required for correctness, so it must be done at -O0. 304 /// 305 static void SplitCriticalSideEffectEdges(Function &Fn, Pass *SDISel) { 306 // Loop for blocks with phi nodes. 307 for (Function::iterator BB = Fn.begin(), E = Fn.end(); BB != E; ++BB) { 308 PHINode *PN = dyn_cast<PHINode>(BB->begin()); 309 if (PN == 0) continue; 310 311 ReprocessBlock: 312 // For each block with a PHI node, check to see if any of the input values 313 // are potentially trapping constant expressions. Constant expressions are 314 // the only potentially trapping value that can occur as the argument to a 315 // PHI. 316 for (BasicBlock::iterator I = BB->begin(); (PN = dyn_cast<PHINode>(I)); ++I) 317 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) { 318 ConstantExpr *CE = dyn_cast<ConstantExpr>(PN->getIncomingValue(i)); 319 if (CE == 0 || !CE->canTrap()) continue; 320 321 // The only case we have to worry about is when the edge is critical. 322 // Since this block has a PHI Node, we assume it has multiple input 323 // edges: check to see if the pred has multiple successors. 324 BasicBlock *Pred = PN->getIncomingBlock(i); 325 if (Pred->getTerminator()->getNumSuccessors() == 1) 326 continue; 327 328 // Okay, we have to split this edge. 329 SplitCriticalEdge(Pred->getTerminator(), 330 GetSuccessorNumber(Pred, BB), SDISel, true); 331 goto ReprocessBlock; 332 } 333 } 334 } 335 336 bool SelectionDAGISel::runOnMachineFunction(MachineFunction &mf) { 337 // Do some sanity-checking on the command-line options. 338 assert((!EnableFastISelVerbose || TM.Options.EnableFastISel) && 339 "-fast-isel-verbose requires -fast-isel"); 340 assert((!EnableFastISelAbort || TM.Options.EnableFastISel) && 341 "-fast-isel-abort requires -fast-isel"); 342 343 const Function &Fn = *mf.getFunction(); 344 const TargetInstrInfo &TII = *TM.getInstrInfo(); 345 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); 346 347 MF = &mf; 348 RegInfo = &MF->getRegInfo(); 349 AA = &getAnalysis<AliasAnalysis>(); 350 LibInfo = &getAnalysis<TargetLibraryInfo>(); 351 GFI = Fn.hasGC() ? &getAnalysis<GCModuleInfo>().getFunctionInfo(Fn) : 0; 352 353 DEBUG(dbgs() << "\n\n\n=== " << Fn.getName() << "\n"); 354 355 SplitCriticalSideEffectEdges(const_cast<Function&>(Fn), this); 356 357 CurDAG->init(*MF); 358 FuncInfo->set(Fn, *MF); 359 360 if (UseMBPI && OptLevel != CodeGenOpt::None) 361 FuncInfo->BPI = &getAnalysis<BranchProbabilityInfo>(); 362 else 363 FuncInfo->BPI = 0; 364 365 SDB->init(GFI, *AA, LibInfo); 366 367 SelectAllBasicBlocks(Fn); 368 369 // If the first basic block in the function has live ins that need to be 370 // copied into vregs, emit the copies into the top of the block before 371 // emitting the code for the block. 372 MachineBasicBlock *EntryMBB = MF->begin(); 373 RegInfo->EmitLiveInCopies(EntryMBB, TRI, TII); 374 375 DenseMap<unsigned, unsigned> LiveInMap; 376 if (!FuncInfo->ArgDbgValues.empty()) 377 for (MachineRegisterInfo::livein_iterator LI = RegInfo->livein_begin(), 378 E = RegInfo->livein_end(); LI != E; ++LI) 379 if (LI->second) 380 LiveInMap.insert(std::make_pair(LI->first, LI->second)); 381 382 // Insert DBG_VALUE instructions for function arguments to the entry block. 383 for (unsigned i = 0, e = FuncInfo->ArgDbgValues.size(); i != e; ++i) { 384 MachineInstr *MI = FuncInfo->ArgDbgValues[e-i-1]; 385 unsigned Reg = MI->getOperand(0).getReg(); 386 if (TargetRegisterInfo::isPhysicalRegister(Reg)) 387 EntryMBB->insert(EntryMBB->begin(), MI); 388 else { 389 MachineInstr *Def = RegInfo->getVRegDef(Reg); 390 MachineBasicBlock::iterator InsertPos = Def; 391 // FIXME: VR def may not be in entry block. 392 Def->getParent()->insert(llvm::next(InsertPos), MI); 393 } 394 395 // If Reg is live-in then update debug info to track its copy in a vreg. 396 DenseMap<unsigned, unsigned>::iterator LDI = LiveInMap.find(Reg); 397 if (LDI != LiveInMap.end()) { 398 MachineInstr *Def = RegInfo->getVRegDef(LDI->second); 399 MachineBasicBlock::iterator InsertPos = Def; 400 const MDNode *Variable = 401 MI->getOperand(MI->getNumOperands()-1).getMetadata(); 402 unsigned Offset = MI->getOperand(1).getImm(); 403 // Def is never a terminator here, so it is ok to increment InsertPos. 404 BuildMI(*EntryMBB, ++InsertPos, MI->getDebugLoc(), 405 TII.get(TargetOpcode::DBG_VALUE)) 406 .addReg(LDI->second, RegState::Debug) 407 .addImm(Offset).addMetadata(Variable); 408 409 // If this vreg is directly copied into an exported register then 410 // that COPY instructions also need DBG_VALUE, if it is the only 411 // user of LDI->second. 412 MachineInstr *CopyUseMI = NULL; 413 for (MachineRegisterInfo::use_iterator 414 UI = RegInfo->use_begin(LDI->second); 415 MachineInstr *UseMI = UI.skipInstruction();) { 416 if (UseMI->isDebugValue()) continue; 417 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) { 418 CopyUseMI = UseMI; continue; 419 } 420 // Otherwise this is another use or second copy use. 421 CopyUseMI = NULL; break; 422 } 423 if (CopyUseMI) { 424 MachineInstr *NewMI = 425 BuildMI(*MF, CopyUseMI->getDebugLoc(), 426 TII.get(TargetOpcode::DBG_VALUE)) 427 .addReg(CopyUseMI->getOperand(0).getReg(), RegState::Debug) 428 .addImm(Offset).addMetadata(Variable); 429 MachineBasicBlock::iterator Pos = CopyUseMI; 430 EntryMBB->insertAfter(Pos, NewMI); 431 } 432 } 433 } 434 435 // Determine if there are any calls in this machine function. 436 MachineFrameInfo *MFI = MF->getFrameInfo(); 437 if (!MFI->hasCalls()) { 438 for (MachineFunction::const_iterator 439 I = MF->begin(), E = MF->end(); I != E; ++I) { 440 const MachineBasicBlock *MBB = I; 441 for (MachineBasicBlock::const_iterator 442 II = MBB->begin(), IE = MBB->end(); II != IE; ++II) { 443 const MCInstrDesc &MCID = TM.getInstrInfo()->get(II->getOpcode()); 444 445 if ((MCID.isCall() && !MCID.isReturn()) || 446 II->isStackAligningInlineAsm()) { 447 MFI->setHasCalls(true); 448 goto done; 449 } 450 } 451 } 452 } 453 454 done: 455 // Determine if there is a call to setjmp in the machine function. 456 MF->setExposesReturnsTwice(Fn.callsFunctionThatReturnsTwice()); 457 458 // Replace forward-declared registers with the registers containing 459 // the desired value. 460 MachineRegisterInfo &MRI = MF->getRegInfo(); 461 for (DenseMap<unsigned, unsigned>::iterator 462 I = FuncInfo->RegFixups.begin(), E = FuncInfo->RegFixups.end(); 463 I != E; ++I) { 464 unsigned From = I->first; 465 unsigned To = I->second; 466 // If To is also scheduled to be replaced, find what its ultimate 467 // replacement is. 468 for (;;) { 469 DenseMap<unsigned, unsigned>::iterator J = FuncInfo->RegFixups.find(To); 470 if (J == E) break; 471 To = J->second; 472 } 473 // Replace it. 474 MRI.replaceRegWith(From, To); 475 } 476 477 // Release function-specific state. SDB and CurDAG are already cleared 478 // at this point. 479 FuncInfo->clear(); 480 481 return true; 482 } 483 484 void SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin, 485 BasicBlock::const_iterator End, 486 bool &HadTailCall) { 487 // Lower all of the non-terminator instructions. If a call is emitted 488 // as a tail call, cease emitting nodes for this block. Terminators 489 // are handled below. 490 for (BasicBlock::const_iterator I = Begin; I != End && !SDB->HasTailCall; ++I) 491 SDB->visit(*I); 492 493 // Make sure the root of the DAG is up-to-date. 494 CurDAG->setRoot(SDB->getControlRoot()); 495 HadTailCall = SDB->HasTailCall; 496 SDB->clear(); 497 498 // Final step, emit the lowered DAG as machine code. 499 CodeGenAndEmitDAG(); 500 } 501 502 void SelectionDAGISel::ComputeLiveOutVRegInfo() { 503 SmallPtrSet<SDNode*, 128> VisitedNodes; 504 SmallVector<SDNode*, 128> Worklist; 505 506 Worklist.push_back(CurDAG->getRoot().getNode()); 507 508 APInt KnownZero; 509 APInt KnownOne; 510 511 do { 512 SDNode *N = Worklist.pop_back_val(); 513 514 // If we've already seen this node, ignore it. 515 if (!VisitedNodes.insert(N)) 516 continue; 517 518 // Otherwise, add all chain operands to the worklist. 519 for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) 520 if (N->getOperand(i).getValueType() == MVT::Other) 521 Worklist.push_back(N->getOperand(i).getNode()); 522 523 // If this is a CopyToReg with a vreg dest, process it. 524 if (N->getOpcode() != ISD::CopyToReg) 525 continue; 526 527 unsigned DestReg = cast<RegisterSDNode>(N->getOperand(1))->getReg(); 528 if (!TargetRegisterInfo::isVirtualRegister(DestReg)) 529 continue; 530 531 // Ignore non-scalar or non-integer values. 532 SDValue Src = N->getOperand(2); 533 EVT SrcVT = Src.getValueType(); 534 if (!SrcVT.isInteger() || SrcVT.isVector()) 535 continue; 536 537 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src); 538 CurDAG->ComputeMaskedBits(Src, KnownZero, KnownOne); 539 FuncInfo->AddLiveOutRegInfo(DestReg, NumSignBits, KnownZero, KnownOne); 540 } while (!Worklist.empty()); 541 } 542 543 void SelectionDAGISel::CodeGenAndEmitDAG() { 544 std::string GroupName; 545 if (TimePassesIsEnabled) 546 GroupName = "Instruction Selection and Scheduling"; 547 std::string BlockName; 548 int BlockNumber = -1; 549 (void)BlockNumber; 550 #ifdef NDEBUG 551 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs || 552 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs || 553 ViewSUnitDAGs) 554 #endif 555 { 556 BlockNumber = FuncInfo->MBB->getNumber(); 557 BlockName = MF->getName().str() + ":" + 558 FuncInfo->MBB->getBasicBlock()->getName().str(); 559 } 560 DEBUG(dbgs() << "Initial selection DAG: BB#" << BlockNumber 561 << " '" << BlockName << "'\n"; CurDAG->dump()); 562 563 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName); 564 565 // Run the DAG combiner in pre-legalize mode. 566 { 567 NamedRegionTimer T("DAG Combining 1", GroupName, TimePassesIsEnabled); 568 CurDAG->Combine(BeforeLegalizeTypes, *AA, OptLevel); 569 } 570 571 DEBUG(dbgs() << "Optimized lowered selection DAG: BB#" << BlockNumber 572 << " '" << BlockName << "'\n"; CurDAG->dump()); 573 574 // Second step, hack on the DAG until it only uses operations and types that 575 // the target supports. 576 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " + 577 BlockName); 578 579 bool Changed; 580 { 581 NamedRegionTimer T("Type Legalization", GroupName, TimePassesIsEnabled); 582 Changed = CurDAG->LegalizeTypes(); 583 } 584 585 DEBUG(dbgs() << "Type-legalized selection DAG: BB#" << BlockNumber 586 << " '" << BlockName << "'\n"; CurDAG->dump()); 587 588 if (Changed) { 589 if (ViewDAGCombineLT) 590 CurDAG->viewGraph("dag-combine-lt input for " + BlockName); 591 592 // Run the DAG combiner in post-type-legalize mode. 593 { 594 NamedRegionTimer T("DAG Combining after legalize types", GroupName, 595 TimePassesIsEnabled); 596 CurDAG->Combine(AfterLegalizeTypes, *AA, OptLevel); 597 } 598 599 DEBUG(dbgs() << "Optimized type-legalized selection DAG: BB#" << BlockNumber 600 << " '" << BlockName << "'\n"; CurDAG->dump()); 601 } 602 603 { 604 NamedRegionTimer T("Vector Legalization", GroupName, TimePassesIsEnabled); 605 Changed = CurDAG->LegalizeVectors(); 606 } 607 608 if (Changed) { 609 { 610 NamedRegionTimer T("Type Legalization 2", GroupName, TimePassesIsEnabled); 611 CurDAG->LegalizeTypes(); 612 } 613 614 if (ViewDAGCombineLT) 615 CurDAG->viewGraph("dag-combine-lv input for " + BlockName); 616 617 // Run the DAG combiner in post-type-legalize mode. 618 { 619 NamedRegionTimer T("DAG Combining after legalize vectors", GroupName, 620 TimePassesIsEnabled); 621 CurDAG->Combine(AfterLegalizeVectorOps, *AA, OptLevel); 622 } 623 624 DEBUG(dbgs() << "Optimized vector-legalized selection DAG: BB#" 625 << BlockNumber << " '" << BlockName << "'\n"; CurDAG->dump()); 626 } 627 628 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName); 629 630 { 631 NamedRegionTimer T("DAG Legalization", GroupName, TimePassesIsEnabled); 632 CurDAG->Legalize(); 633 } 634 635 DEBUG(dbgs() << "Legalized selection DAG: BB#" << BlockNumber 636 << " '" << BlockName << "'\n"; CurDAG->dump()); 637 638 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName); 639 640 // Run the DAG combiner in post-legalize mode. 641 { 642 NamedRegionTimer T("DAG Combining 2", GroupName, TimePassesIsEnabled); 643 CurDAG->Combine(AfterLegalizeDAG, *AA, OptLevel); 644 } 645 646 DEBUG(dbgs() << "Optimized legalized selection DAG: BB#" << BlockNumber 647 << " '" << BlockName << "'\n"; CurDAG->dump()); 648 649 if (OptLevel != CodeGenOpt::None) 650 ComputeLiveOutVRegInfo(); 651 652 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName); 653 654 // Third, instruction select all of the operations to machine code, adding the 655 // code to the MachineBasicBlock. 656 { 657 NamedRegionTimer T("Instruction Selection", GroupName, TimePassesIsEnabled); 658 DoInstructionSelection(); 659 } 660 661 DEBUG(dbgs() << "Selected selection DAG: BB#" << BlockNumber 662 << " '" << BlockName << "'\n"; CurDAG->dump()); 663 664 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName); 665 666 // Schedule machine code. 667 ScheduleDAGSDNodes *Scheduler = CreateScheduler(); 668 { 669 NamedRegionTimer T("Instruction Scheduling", GroupName, 670 TimePassesIsEnabled); 671 Scheduler->Run(CurDAG, FuncInfo->MBB); 672 } 673 674 if (ViewSUnitDAGs) Scheduler->viewGraph(); 675 676 // Emit machine code to BB. This can change 'BB' to the last block being 677 // inserted into. 678 MachineBasicBlock *FirstMBB = FuncInfo->MBB, *LastMBB; 679 { 680 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled); 681 682 // FuncInfo->InsertPt is passed by reference and set to the end of the 683 // scheduled instructions. 684 LastMBB = FuncInfo->MBB = Scheduler->EmitSchedule(FuncInfo->InsertPt); 685 } 686 687 // If the block was split, make sure we update any references that are used to 688 // update PHI nodes later on. 689 if (FirstMBB != LastMBB) 690 SDB->UpdateSplitBlock(FirstMBB, LastMBB); 691 692 // Free the scheduler state. 693 { 694 NamedRegionTimer T("Instruction Scheduling Cleanup", GroupName, 695 TimePassesIsEnabled); 696 delete Scheduler; 697 } 698 699 // Free the SelectionDAG state, now that we're finished with it. 700 CurDAG->clear(); 701 } 702 703 namespace { 704 /// ISelUpdater - helper class to handle updates of the instruction selection 705 /// graph. 706 class ISelUpdater : public SelectionDAG::DAGUpdateListener { 707 SelectionDAG::allnodes_iterator &ISelPosition; 708 public: 709 ISelUpdater(SelectionDAG &DAG, SelectionDAG::allnodes_iterator &isp) 710 : SelectionDAG::DAGUpdateListener(DAG), ISelPosition(isp) {} 711 712 /// NodeDeleted - Handle nodes deleted from the graph. If the node being 713 /// deleted is the current ISelPosition node, update ISelPosition. 714 /// 715 virtual void NodeDeleted(SDNode *N, SDNode *E) { 716 if (ISelPosition == SelectionDAG::allnodes_iterator(N)) 717 ++ISelPosition; 718 } 719 }; 720 } // end anonymous namespace 721 722 void SelectionDAGISel::DoInstructionSelection() { 723 DEBUG(errs() << "===== Instruction selection begins: BB#" 724 << FuncInfo->MBB->getNumber() 725 << " '" << FuncInfo->MBB->getName() << "'\n"); 726 727 PreprocessISelDAG(); 728 729 // Select target instructions for the DAG. 730 { 731 // Number all nodes with a topological order and set DAGSize. 732 DAGSize = CurDAG->AssignTopologicalOrder(); 733 734 // Create a dummy node (which is not added to allnodes), that adds 735 // a reference to the root node, preventing it from being deleted, 736 // and tracking any changes of the root. 737 HandleSDNode Dummy(CurDAG->getRoot()); 738 SelectionDAG::allnodes_iterator ISelPosition (CurDAG->getRoot().getNode()); 739 ++ISelPosition; 740 741 // Make sure that ISelPosition gets properly updated when nodes are deleted 742 // in calls made from this function. 743 ISelUpdater ISU(*CurDAG, ISelPosition); 744 745 // The AllNodes list is now topological-sorted. Visit the 746 // nodes by starting at the end of the list (the root of the 747 // graph) and preceding back toward the beginning (the entry 748 // node). 749 while (ISelPosition != CurDAG->allnodes_begin()) { 750 SDNode *Node = --ISelPosition; 751 // Skip dead nodes. DAGCombiner is expected to eliminate all dead nodes, 752 // but there are currently some corner cases that it misses. Also, this 753 // makes it theoretically possible to disable the DAGCombiner. 754 if (Node->use_empty()) 755 continue; 756 757 SDNode *ResNode = Select(Node); 758 759 // FIXME: This is pretty gross. 'Select' should be changed to not return 760 // anything at all and this code should be nuked with a tactical strike. 761 762 // If node should not be replaced, continue with the next one. 763 if (ResNode == Node || Node->getOpcode() == ISD::DELETED_NODE) 764 continue; 765 // Replace node. 766 if (ResNode) 767 ReplaceUses(Node, ResNode); 768 769 // If after the replacement this node is not used any more, 770 // remove this dead node. 771 if (Node->use_empty()) // Don't delete EntryToken, etc. 772 CurDAG->RemoveDeadNode(Node); 773 } 774 775 CurDAG->setRoot(Dummy.getValue()); 776 } 777 778 DEBUG(errs() << "===== Instruction selection ends:\n"); 779 780 PostprocessISelDAG(); 781 } 782 783 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and 784 /// do other setup for EH landing-pad blocks. 785 void SelectionDAGISel::PrepareEHLandingPad() { 786 MachineBasicBlock *MBB = FuncInfo->MBB; 787 788 // Add a label to mark the beginning of the landing pad. Deletion of the 789 // landing pad can thus be detected via the MachineModuleInfo. 790 MCSymbol *Label = MF->getMMI().addLandingPad(MBB); 791 792 // Assign the call site to the landing pad's begin label. 793 MF->getMMI().setCallSiteLandingPad(Label, SDB->LPadToCallSiteMap[MBB]); 794 795 const MCInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL); 796 BuildMI(*MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II) 797 .addSym(Label); 798 799 // Mark exception register as live in. 800 unsigned Reg = TLI.getExceptionPointerRegister(); 801 if (Reg) MBB->addLiveIn(Reg); 802 803 // Mark exception selector register as live in. 804 Reg = TLI.getExceptionSelectorRegister(); 805 if (Reg) MBB->addLiveIn(Reg); 806 } 807 808 /// TryToFoldFastISelLoad - We're checking to see if we can fold the specified 809 /// load into the specified FoldInst. Note that we could have a sequence where 810 /// multiple LLVM IR instructions are folded into the same machineinstr. For 811 /// example we could have: 812 /// A: x = load i32 *P 813 /// B: y = icmp A, 42 814 /// C: br y, ... 815 /// 816 /// In this scenario, LI is "A", and FoldInst is "C". We know about "B" (and 817 /// any other folded instructions) because it is between A and C. 818 /// 819 /// If we succeed in folding the load into the operation, return true. 820 /// 821 bool SelectionDAGISel::TryToFoldFastISelLoad(const LoadInst *LI, 822 const Instruction *FoldInst, 823 FastISel *FastIS) { 824 // We know that the load has a single use, but don't know what it is. If it 825 // isn't one of the folded instructions, then we can't succeed here. Handle 826 // this by scanning the single-use users of the load until we get to FoldInst. 827 unsigned MaxUsers = 6; // Don't scan down huge single-use chains of instrs. 828 829 const Instruction *TheUser = LI->use_back(); 830 while (TheUser != FoldInst && // Scan up until we find FoldInst. 831 // Stay in the right block. 832 TheUser->getParent() == FoldInst->getParent() && 833 --MaxUsers) { // Don't scan too far. 834 // If there are multiple or no uses of this instruction, then bail out. 835 if (!TheUser->hasOneUse()) 836 return false; 837 838 TheUser = TheUser->use_back(); 839 } 840 841 // If we didn't find the fold instruction, then we failed to collapse the 842 // sequence. 843 if (TheUser != FoldInst) 844 return false; 845 846 // Don't try to fold volatile loads. Target has to deal with alignment 847 // constraints. 848 if (LI->isVolatile()) return false; 849 850 // Figure out which vreg this is going into. If there is no assigned vreg yet 851 // then there actually was no reference to it. Perhaps the load is referenced 852 // by a dead instruction. 853 unsigned LoadReg = FastIS->getRegForValue(LI); 854 if (LoadReg == 0) 855 return false; 856 857 // Check to see what the uses of this vreg are. If it has no uses, or more 858 // than one use (at the machine instr level) then we can't fold it. 859 MachineRegisterInfo::reg_iterator RI = RegInfo->reg_begin(LoadReg); 860 if (RI == RegInfo->reg_end()) 861 return false; 862 863 // See if there is exactly one use of the vreg. If there are multiple uses, 864 // then the instruction got lowered to multiple machine instructions or the 865 // use of the loaded value ended up being multiple operands of the result, in 866 // either case, we can't fold this. 867 MachineRegisterInfo::reg_iterator PostRI = RI; ++PostRI; 868 if (PostRI != RegInfo->reg_end()) 869 return false; 870 871 assert(RI.getOperand().isUse() && 872 "The only use of the vreg must be a use, we haven't emitted the def!"); 873 874 MachineInstr *User = &*RI; 875 876 // Set the insertion point properly. Folding the load can cause generation of 877 // other random instructions (like sign extends) for addressing modes, make 878 // sure they get inserted in a logical place before the new instruction. 879 FuncInfo->InsertPt = User; 880 FuncInfo->MBB = User->getParent(); 881 882 // Ask the target to try folding the load. 883 return FastIS->TryToFoldLoad(User, RI.getOperandNo(), LI); 884 } 885 886 /// isFoldedOrDeadInstruction - Return true if the specified instruction is 887 /// side-effect free and is either dead or folded into a generated instruction. 888 /// Return false if it needs to be emitted. 889 static bool isFoldedOrDeadInstruction(const Instruction *I, 890 FunctionLoweringInfo *FuncInfo) { 891 return !I->mayWriteToMemory() && // Side-effecting instructions aren't folded. 892 !isa<TerminatorInst>(I) && // Terminators aren't folded. 893 !isa<DbgInfoIntrinsic>(I) && // Debug instructions aren't folded. 894 !isa<LandingPadInst>(I) && // Landingpad instructions aren't folded. 895 !FuncInfo->isExportedInst(I); // Exported instrs must be computed. 896 } 897 898 #ifndef NDEBUG 899 // Collect per Instruction statistics for fast-isel misses. Only those 900 // instructions that cause the bail are accounted for. It does not account for 901 // instructions higher in the block. Thus, summing the per instructions stats 902 // will not add up to what is reported by NumFastIselFailures. 903 static void collectFailStats(const Instruction *I) { 904 switch (I->getOpcode()) { 905 default: assert (0 && "<Invalid operator> "); 906 907 // Terminators 908 case Instruction::Ret: NumFastIselFailRet++; return; 909 case Instruction::Br: NumFastIselFailBr++; return; 910 case Instruction::Switch: NumFastIselFailSwitch++; return; 911 case Instruction::IndirectBr: NumFastIselFailIndirectBr++; return; 912 case Instruction::Invoke: NumFastIselFailInvoke++; return; 913 case Instruction::Resume: NumFastIselFailResume++; return; 914 case Instruction::Unreachable: NumFastIselFailUnreachable++; return; 915 916 // Standard binary operators... 917 case Instruction::Add: NumFastIselFailAdd++; return; 918 case Instruction::FAdd: NumFastIselFailFAdd++; return; 919 case Instruction::Sub: NumFastIselFailSub++; return; 920 case Instruction::FSub: NumFastIselFailFSub++; return; 921 case Instruction::Mul: NumFastIselFailMul++; return; 922 case Instruction::FMul: NumFastIselFailFMul++; return; 923 case Instruction::UDiv: NumFastIselFailUDiv++; return; 924 case Instruction::SDiv: NumFastIselFailSDiv++; return; 925 case Instruction::FDiv: NumFastIselFailFDiv++; return; 926 case Instruction::URem: NumFastIselFailURem++; return; 927 case Instruction::SRem: NumFastIselFailSRem++; return; 928 case Instruction::FRem: NumFastIselFailFRem++; return; 929 930 // Logical operators... 931 case Instruction::And: NumFastIselFailAnd++; return; 932 case Instruction::Or: NumFastIselFailOr++; return; 933 case Instruction::Xor: NumFastIselFailXor++; return; 934 935 // Memory instructions... 936 case Instruction::Alloca: NumFastIselFailAlloca++; return; 937 case Instruction::Load: NumFastIselFailLoad++; return; 938 case Instruction::Store: NumFastIselFailStore++; return; 939 case Instruction::AtomicCmpXchg: NumFastIselFailAtomicCmpXchg++; return; 940 case Instruction::AtomicRMW: NumFastIselFailAtomicRMW++; return; 941 case Instruction::Fence: NumFastIselFailFence++; return; 942 case Instruction::GetElementPtr: NumFastIselFailGetElementPtr++; return; 943 944 // Convert instructions... 945 case Instruction::Trunc: NumFastIselFailTrunc++; return; 946 case Instruction::ZExt: NumFastIselFailZExt++; return; 947 case Instruction::SExt: NumFastIselFailSExt++; return; 948 case Instruction::FPTrunc: NumFastIselFailFPTrunc++; return; 949 case Instruction::FPExt: NumFastIselFailFPExt++; return; 950 case Instruction::FPToUI: NumFastIselFailFPToUI++; return; 951 case Instruction::FPToSI: NumFastIselFailFPToSI++; return; 952 case Instruction::UIToFP: NumFastIselFailUIToFP++; return; 953 case Instruction::SIToFP: NumFastIselFailSIToFP++; return; 954 case Instruction::IntToPtr: NumFastIselFailIntToPtr++; return; 955 case Instruction::PtrToInt: NumFastIselFailPtrToInt++; return; 956 case Instruction::BitCast: NumFastIselFailBitCast++; return; 957 958 // Other instructions... 959 case Instruction::ICmp: NumFastIselFailICmp++; return; 960 case Instruction::FCmp: NumFastIselFailFCmp++; return; 961 case Instruction::PHI: NumFastIselFailPHI++; return; 962 case Instruction::Select: NumFastIselFailSelect++; return; 963 case Instruction::Call: NumFastIselFailCall++; return; 964 case Instruction::Shl: NumFastIselFailShl++; return; 965 case Instruction::LShr: NumFastIselFailLShr++; return; 966 case Instruction::AShr: NumFastIselFailAShr++; return; 967 case Instruction::VAArg: NumFastIselFailVAArg++; return; 968 case Instruction::ExtractElement: NumFastIselFailExtractElement++; return; 969 case Instruction::InsertElement: NumFastIselFailInsertElement++; return; 970 case Instruction::ShuffleVector: NumFastIselFailShuffleVector++; return; 971 case Instruction::ExtractValue: NumFastIselFailExtractValue++; return; 972 case Instruction::InsertValue: NumFastIselFailInsertValue++; return; 973 case Instruction::LandingPad: NumFastIselFailLandingPad++; return; 974 } 975 } 976 #endif 977 978 void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) { 979 // Initialize the Fast-ISel state, if needed. 980 FastISel *FastIS = 0; 981 if (TM.Options.EnableFastISel) 982 FastIS = TLI.createFastISel(*FuncInfo, LibInfo); 983 984 // Iterate over all basic blocks in the function. 985 ReversePostOrderTraversal<const Function*> RPOT(&Fn); 986 for (ReversePostOrderTraversal<const Function*>::rpo_iterator 987 I = RPOT.begin(), E = RPOT.end(); I != E; ++I) { 988 const BasicBlock *LLVMBB = *I; 989 990 if (OptLevel != CodeGenOpt::None) { 991 bool AllPredsVisited = true; 992 for (const_pred_iterator PI = pred_begin(LLVMBB), PE = pred_end(LLVMBB); 993 PI != PE; ++PI) { 994 if (!FuncInfo->VisitedBBs.count(*PI)) { 995 AllPredsVisited = false; 996 break; 997 } 998 } 999 1000 if (AllPredsVisited) { 1001 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1002 isa<PHINode>(I); ++I) 1003 FuncInfo->ComputePHILiveOutRegInfo(cast<PHINode>(I)); 1004 } else { 1005 for (BasicBlock::const_iterator I = LLVMBB->begin(); 1006 isa<PHINode>(I); ++I) 1007 FuncInfo->InvalidatePHILiveOutRegInfo(cast<PHINode>(I)); 1008 } 1009 1010 FuncInfo->VisitedBBs.insert(LLVMBB); 1011 } 1012 1013 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB]; 1014 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1015 1016 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI(); 1017 BasicBlock::const_iterator const End = LLVMBB->end(); 1018 BasicBlock::const_iterator BI = End; 1019 1020 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI(); 1021 1022 // Setup an EH landing-pad block. 1023 if (FuncInfo->MBB->isLandingPad()) 1024 PrepareEHLandingPad(); 1025 1026 // Lower any arguments needed in this block if this is the entry block. 1027 if (LLVMBB == &Fn.getEntryBlock()) 1028 LowerArguments(LLVMBB); 1029 1030 // Before doing SelectionDAG ISel, see if FastISel has been requested. 1031 if (FastIS) { 1032 FastIS->startNewBlock(); 1033 1034 // Emit code for any incoming arguments. This must happen before 1035 // beginning FastISel on the entry block. 1036 if (LLVMBB == &Fn.getEntryBlock()) { 1037 CurDAG->setRoot(SDB->getControlRoot()); 1038 SDB->clear(); 1039 CodeGenAndEmitDAG(); 1040 1041 // If we inserted any instructions at the beginning, make a note of 1042 // where they are, so we can be sure to emit subsequent instructions 1043 // after them. 1044 if (FuncInfo->InsertPt != FuncInfo->MBB->begin()) 1045 FastIS->setLastLocalValue(llvm::prior(FuncInfo->InsertPt)); 1046 else 1047 FastIS->setLastLocalValue(0); 1048 } 1049 1050 unsigned NumFastIselRemaining = std::distance(Begin, End); 1051 // Do FastISel on as many instructions as possible. 1052 for (; BI != Begin; --BI) { 1053 const Instruction *Inst = llvm::prior(BI); 1054 1055 // If we no longer require this instruction, skip it. 1056 if (isFoldedOrDeadInstruction(Inst, FuncInfo)) { 1057 --NumFastIselRemaining; 1058 continue; 1059 } 1060 1061 // Bottom-up: reset the insert pos at the top, after any local-value 1062 // instructions. 1063 FastIS->recomputeInsertPt(); 1064 1065 // Try to select the instruction with FastISel. 1066 if (FastIS->SelectInstruction(Inst)) { 1067 --NumFastIselRemaining; 1068 ++NumFastIselSuccess; 1069 // If fast isel succeeded, skip over all the folded instructions, and 1070 // then see if there is a load right before the selected instructions. 1071 // Try to fold the load if so. 1072 const Instruction *BeforeInst = Inst; 1073 while (BeforeInst != Begin) { 1074 BeforeInst = llvm::prior(BasicBlock::const_iterator(BeforeInst)); 1075 if (!isFoldedOrDeadInstruction(BeforeInst, FuncInfo)) 1076 break; 1077 } 1078 if (BeforeInst != Inst && isa<LoadInst>(BeforeInst) && 1079 BeforeInst->hasOneUse() && 1080 TryToFoldFastISelLoad(cast<LoadInst>(BeforeInst), Inst, FastIS)) { 1081 // If we succeeded, don't re-select the load. 1082 BI = llvm::next(BasicBlock::const_iterator(BeforeInst)); 1083 --NumFastIselRemaining; 1084 ++NumFastIselSuccess; 1085 } 1086 continue; 1087 } 1088 1089 #ifndef NDEBUG 1090 if (EnableFastISelVerbose2) 1091 collectFailStats(Inst); 1092 #endif 1093 1094 // Then handle certain instructions as single-LLVM-Instruction blocks. 1095 if (isa<CallInst>(Inst)) { 1096 1097 if (EnableFastISelVerbose || EnableFastISelAbort) { 1098 dbgs() << "FastISel missed call: "; 1099 Inst->dump(); 1100 } 1101 1102 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) { 1103 unsigned &R = FuncInfo->ValueMap[Inst]; 1104 if (!R) 1105 R = FuncInfo->CreateRegs(Inst->getType()); 1106 } 1107 1108 bool HadTailCall = false; 1109 SelectBasicBlock(Inst, BI, HadTailCall); 1110 1111 // Recompute NumFastIselRemaining as Selection DAG instruction 1112 // selection may have handled the call, input args, etc. 1113 unsigned RemainingNow = std::distance(Begin, BI); 1114 NumFastIselFailures += NumFastIselRemaining - RemainingNow; 1115 1116 // If the call was emitted as a tail call, we're done with the block. 1117 if (HadTailCall) { 1118 --BI; 1119 break; 1120 } 1121 1122 NumFastIselRemaining = RemainingNow; 1123 continue; 1124 } 1125 1126 if (isa<TerminatorInst>(Inst) && !isa<BranchInst>(Inst)) { 1127 // Don't abort, and use a different message for terminator misses. 1128 NumFastIselFailures += NumFastIselRemaining; 1129 if (EnableFastISelVerbose || EnableFastISelAbort) { 1130 dbgs() << "FastISel missed terminator: "; 1131 Inst->dump(); 1132 } 1133 } else { 1134 NumFastIselFailures += NumFastIselRemaining; 1135 if (EnableFastISelVerbose || EnableFastISelAbort) { 1136 dbgs() << "FastISel miss: "; 1137 Inst->dump(); 1138 } 1139 if (EnableFastISelAbort) 1140 // The "fast" selector couldn't handle something and bailed. 1141 // For the purpose of debugging, just abort. 1142 llvm_unreachable("FastISel didn't select the entire block"); 1143 } 1144 break; 1145 } 1146 1147 FastIS->recomputeInsertPt(); 1148 } 1149 1150 if (Begin != BI) 1151 ++NumDAGBlocks; 1152 else 1153 ++NumFastIselBlocks; 1154 1155 if (Begin != BI) { 1156 // Run SelectionDAG instruction selection on the remainder of the block 1157 // not handled by FastISel. If FastISel is not run, this is the entire 1158 // block. 1159 bool HadTailCall; 1160 SelectBasicBlock(Begin, BI, HadTailCall); 1161 } 1162 1163 FinishBasicBlock(); 1164 FuncInfo->PHINodesToUpdate.clear(); 1165 } 1166 1167 delete FastIS; 1168 SDB->clearDanglingDebugInfo(); 1169 } 1170 1171 void 1172 SelectionDAGISel::FinishBasicBlock() { 1173 1174 DEBUG(dbgs() << "Total amount of phi nodes to update: " 1175 << FuncInfo->PHINodesToUpdate.size() << "\n"; 1176 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) 1177 dbgs() << "Node " << i << " : (" 1178 << FuncInfo->PHINodesToUpdate[i].first 1179 << ", " << FuncInfo->PHINodesToUpdate[i].second << ")\n"); 1180 1181 // Next, now that we know what the last MBB the LLVM BB expanded is, update 1182 // PHI nodes in successors. 1183 if (SDB->SwitchCases.empty() && 1184 SDB->JTCases.empty() && 1185 SDB->BitTestCases.empty()) { 1186 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1187 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1188 assert(PHI->isPHI() && 1189 "This is not a machine PHI node that we are updating!"); 1190 if (!FuncInfo->MBB->isSuccessor(PHI->getParent())) 1191 continue; 1192 PHI->addOperand( 1193 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1194 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1195 } 1196 return; 1197 } 1198 1199 for (unsigned i = 0, e = SDB->BitTestCases.size(); i != e; ++i) { 1200 // Lower header first, if it wasn't already lowered 1201 if (!SDB->BitTestCases[i].Emitted) { 1202 // Set the current basic block to the mbb we wish to insert the code into 1203 FuncInfo->MBB = SDB->BitTestCases[i].Parent; 1204 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1205 // Emit the code 1206 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB); 1207 CurDAG->setRoot(SDB->getRoot()); 1208 SDB->clear(); 1209 CodeGenAndEmitDAG(); 1210 } 1211 1212 uint32_t UnhandledWeight = 0; 1213 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) 1214 UnhandledWeight += SDB->BitTestCases[i].Cases[j].ExtraWeight; 1215 1216 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) { 1217 UnhandledWeight -= SDB->BitTestCases[i].Cases[j].ExtraWeight; 1218 // Set the current basic block to the mbb we wish to insert the code into 1219 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1220 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1221 // Emit the code 1222 if (j+1 != ej) 1223 SDB->visitBitTestCase(SDB->BitTestCases[i], 1224 SDB->BitTestCases[i].Cases[j+1].ThisBB, 1225 UnhandledWeight, 1226 SDB->BitTestCases[i].Reg, 1227 SDB->BitTestCases[i].Cases[j], 1228 FuncInfo->MBB); 1229 else 1230 SDB->visitBitTestCase(SDB->BitTestCases[i], 1231 SDB->BitTestCases[i].Default, 1232 UnhandledWeight, 1233 SDB->BitTestCases[i].Reg, 1234 SDB->BitTestCases[i].Cases[j], 1235 FuncInfo->MBB); 1236 1237 1238 CurDAG->setRoot(SDB->getRoot()); 1239 SDB->clear(); 1240 CodeGenAndEmitDAG(); 1241 } 1242 1243 // Update PHI Nodes 1244 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1245 pi != pe; ++pi) { 1246 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1247 MachineBasicBlock *PHIBB = PHI->getParent(); 1248 assert(PHI->isPHI() && 1249 "This is not a machine PHI node that we are updating!"); 1250 // This is "default" BB. We have two jumps to it. From "header" BB and 1251 // from last "case" BB. 1252 if (PHIBB == SDB->BitTestCases[i].Default) { 1253 PHI->addOperand(MachineOperand:: 1254 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1255 false)); 1256 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Parent)); 1257 PHI->addOperand(MachineOperand:: 1258 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1259 false)); 1260 PHI->addOperand(MachineOperand::CreateMBB(SDB->BitTestCases[i].Cases. 1261 back().ThisBB)); 1262 } 1263 // One of "cases" BB. 1264 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); 1265 j != ej; ++j) { 1266 MachineBasicBlock* cBB = SDB->BitTestCases[i].Cases[j].ThisBB; 1267 if (cBB->isSuccessor(PHIBB)) { 1268 PHI->addOperand(MachineOperand:: 1269 CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1270 false)); 1271 PHI->addOperand(MachineOperand::CreateMBB(cBB)); 1272 } 1273 } 1274 } 1275 } 1276 SDB->BitTestCases.clear(); 1277 1278 // If the JumpTable record is filled in, then we need to emit a jump table. 1279 // Updating the PHI nodes is tricky in this case, since we need to determine 1280 // whether the PHI is a successor of the range check MBB or the jump table MBB 1281 for (unsigned i = 0, e = SDB->JTCases.size(); i != e; ++i) { 1282 // Lower header first, if it wasn't already lowered 1283 if (!SDB->JTCases[i].first.Emitted) { 1284 // Set the current basic block to the mbb we wish to insert the code into 1285 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB; 1286 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1287 // Emit the code 1288 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first, 1289 FuncInfo->MBB); 1290 CurDAG->setRoot(SDB->getRoot()); 1291 SDB->clear(); 1292 CodeGenAndEmitDAG(); 1293 } 1294 1295 // Set the current basic block to the mbb we wish to insert the code into 1296 FuncInfo->MBB = SDB->JTCases[i].second.MBB; 1297 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1298 // Emit the code 1299 SDB->visitJumpTable(SDB->JTCases[i].second); 1300 CurDAG->setRoot(SDB->getRoot()); 1301 SDB->clear(); 1302 CodeGenAndEmitDAG(); 1303 1304 // Update PHI Nodes 1305 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size(); 1306 pi != pe; ++pi) { 1307 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[pi].first; 1308 MachineBasicBlock *PHIBB = PHI->getParent(); 1309 assert(PHI->isPHI() && 1310 "This is not a machine PHI node that we are updating!"); 1311 // "default" BB. We can go there only from header BB. 1312 if (PHIBB == SDB->JTCases[i].second.Default) { 1313 PHI->addOperand 1314 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1315 false)); 1316 PHI->addOperand 1317 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB)); 1318 } 1319 // JT BB. Just iterate over successors here 1320 if (FuncInfo->MBB->isSuccessor(PHIBB)) { 1321 PHI->addOperand 1322 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second, 1323 false)); 1324 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1325 } 1326 } 1327 } 1328 SDB->JTCases.clear(); 1329 1330 // If the switch block involved a branch to one of the actual successors, we 1331 // need to update PHI nodes in that block. 1332 for (unsigned i = 0, e = FuncInfo->PHINodesToUpdate.size(); i != e; ++i) { 1333 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first; 1334 assert(PHI->isPHI() && 1335 "This is not a machine PHI node that we are updating!"); 1336 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) { 1337 PHI->addOperand( 1338 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false)); 1339 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB)); 1340 } 1341 } 1342 1343 // If we generated any switch lowering information, build and codegen any 1344 // additional DAGs necessary. 1345 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) { 1346 // Set the current basic block to the mbb we wish to insert the code into 1347 FuncInfo->MBB = SDB->SwitchCases[i].ThisBB; 1348 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1349 1350 // Determine the unique successors. 1351 SmallVector<MachineBasicBlock *, 2> Succs; 1352 Succs.push_back(SDB->SwitchCases[i].TrueBB); 1353 if (SDB->SwitchCases[i].TrueBB != SDB->SwitchCases[i].FalseBB) 1354 Succs.push_back(SDB->SwitchCases[i].FalseBB); 1355 1356 // Emit the code. Note that this could result in FuncInfo->MBB being split. 1357 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB); 1358 CurDAG->setRoot(SDB->getRoot()); 1359 SDB->clear(); 1360 CodeGenAndEmitDAG(); 1361 1362 // Remember the last block, now that any splitting is done, for use in 1363 // populating PHI nodes in successors. 1364 MachineBasicBlock *ThisBB = FuncInfo->MBB; 1365 1366 // Handle any PHI nodes in successors of this chunk, as if we were coming 1367 // from the original BB before switch expansion. Note that PHI nodes can 1368 // occur multiple times in PHINodesToUpdate. We have to be very careful to 1369 // handle them the right number of times. 1370 for (unsigned i = 0, e = Succs.size(); i != e; ++i) { 1371 FuncInfo->MBB = Succs[i]; 1372 FuncInfo->InsertPt = FuncInfo->MBB->end(); 1373 // FuncInfo->MBB may have been removed from the CFG if a branch was 1374 // constant folded. 1375 if (ThisBB->isSuccessor(FuncInfo->MBB)) { 1376 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin(); 1377 Phi != FuncInfo->MBB->end() && Phi->isPHI(); 1378 ++Phi) { 1379 // This value for this PHI node is recorded in PHINodesToUpdate. 1380 for (unsigned pn = 0; ; ++pn) { 1381 assert(pn != FuncInfo->PHINodesToUpdate.size() && 1382 "Didn't find PHI entry!"); 1383 if (FuncInfo->PHINodesToUpdate[pn].first == Phi) { 1384 Phi->addOperand(MachineOperand:: 1385 CreateReg(FuncInfo->PHINodesToUpdate[pn].second, 1386 false)); 1387 Phi->addOperand(MachineOperand::CreateMBB(ThisBB)); 1388 break; 1389 } 1390 } 1391 } 1392 } 1393 } 1394 } 1395 SDB->SwitchCases.clear(); 1396 } 1397 1398 1399 /// Create the scheduler. If a specific scheduler was specified 1400 /// via the SchedulerRegistry, use it, otherwise select the 1401 /// one preferred by the target. 1402 /// 1403 ScheduleDAGSDNodes *SelectionDAGISel::CreateScheduler() { 1404 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault(); 1405 1406 if (!Ctor) { 1407 Ctor = ISHeuristic; 1408 RegisterScheduler::setDefault(Ctor); 1409 } 1410 1411 return Ctor(this, OptLevel); 1412 } 1413 1414 //===----------------------------------------------------------------------===// 1415 // Helper functions used by the generated instruction selector. 1416 //===----------------------------------------------------------------------===// 1417 // Calls to these methods are generated by tblgen. 1418 1419 /// CheckAndMask - The isel is trying to match something like (and X, 255). If 1420 /// the dag combiner simplified the 255, we still want to match. RHS is the 1421 /// actual value in the DAG on the RHS of an AND, and DesiredMaskS is the value 1422 /// specified in the .td file (e.g. 255). 1423 bool SelectionDAGISel::CheckAndMask(SDValue LHS, ConstantSDNode *RHS, 1424 int64_t DesiredMaskS) const { 1425 const APInt &ActualMask = RHS->getAPIntValue(); 1426 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1427 1428 // If the actual mask exactly matches, success! 1429 if (ActualMask == DesiredMask) 1430 return true; 1431 1432 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1433 if (ActualMask.intersects(~DesiredMask)) 1434 return false; 1435 1436 // Otherwise, the DAG Combiner may have proven that the value coming in is 1437 // either already zero or is not demanded. Check for known zero input bits. 1438 APInt NeededMask = DesiredMask & ~ActualMask; 1439 if (CurDAG->MaskedValueIsZero(LHS, NeededMask)) 1440 return true; 1441 1442 // TODO: check to see if missing bits are just not demanded. 1443 1444 // Otherwise, this pattern doesn't match. 1445 return false; 1446 } 1447 1448 /// CheckOrMask - The isel is trying to match something like (or X, 255). If 1449 /// the dag combiner simplified the 255, we still want to match. RHS is the 1450 /// actual value in the DAG on the RHS of an OR, and DesiredMaskS is the value 1451 /// specified in the .td file (e.g. 255). 1452 bool SelectionDAGISel::CheckOrMask(SDValue LHS, ConstantSDNode *RHS, 1453 int64_t DesiredMaskS) const { 1454 const APInt &ActualMask = RHS->getAPIntValue(); 1455 const APInt &DesiredMask = APInt(LHS.getValueSizeInBits(), DesiredMaskS); 1456 1457 // If the actual mask exactly matches, success! 1458 if (ActualMask == DesiredMask) 1459 return true; 1460 1461 // If the actual AND mask is allowing unallowed bits, this doesn't match. 1462 if (ActualMask.intersects(~DesiredMask)) 1463 return false; 1464 1465 // Otherwise, the DAG Combiner may have proven that the value coming in is 1466 // either already zero or is not demanded. Check for known zero input bits. 1467 APInt NeededMask = DesiredMask & ~ActualMask; 1468 1469 APInt KnownZero, KnownOne; 1470 CurDAG->ComputeMaskedBits(LHS, KnownZero, KnownOne); 1471 1472 // If all the missing bits in the or are already known to be set, match! 1473 if ((NeededMask & KnownOne) == NeededMask) 1474 return true; 1475 1476 // TODO: check to see if missing bits are just not demanded. 1477 1478 // Otherwise, this pattern doesn't match. 1479 return false; 1480 } 1481 1482 1483 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated 1484 /// by tblgen. Others should not call it. 1485 void SelectionDAGISel:: 1486 SelectInlineAsmMemoryOperands(std::vector<SDValue> &Ops) { 1487 std::vector<SDValue> InOps; 1488 std::swap(InOps, Ops); 1489 1490 Ops.push_back(InOps[InlineAsm::Op_InputChain]); // 0 1491 Ops.push_back(InOps[InlineAsm::Op_AsmString]); // 1 1492 Ops.push_back(InOps[InlineAsm::Op_MDNode]); // 2, !srcloc 1493 Ops.push_back(InOps[InlineAsm::Op_ExtraInfo]); // 3 (SideEffect, AlignStack) 1494 1495 unsigned i = InlineAsm::Op_FirstOperand, e = InOps.size(); 1496 if (InOps[e-1].getValueType() == MVT::Glue) 1497 --e; // Don't process a glue operand if it is here. 1498 1499 while (i != e) { 1500 unsigned Flags = cast<ConstantSDNode>(InOps[i])->getZExtValue(); 1501 if (!InlineAsm::isMemKind(Flags)) { 1502 // Just skip over this operand, copying the operands verbatim. 1503 Ops.insert(Ops.end(), InOps.begin()+i, 1504 InOps.begin()+i+InlineAsm::getNumOperandRegisters(Flags) + 1); 1505 i += InlineAsm::getNumOperandRegisters(Flags) + 1; 1506 } else { 1507 assert(InlineAsm::getNumOperandRegisters(Flags) == 1 && 1508 "Memory operand with multiple values?"); 1509 // Otherwise, this is a memory operand. Ask the target to select it. 1510 std::vector<SDValue> SelOps; 1511 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) 1512 report_fatal_error("Could not match memory address. Inline asm" 1513 " failure!"); 1514 1515 // Add this to the output node. 1516 unsigned NewFlags = 1517 InlineAsm::getFlagWord(InlineAsm::Kind_Mem, SelOps.size()); 1518 Ops.push_back(CurDAG->getTargetConstant(NewFlags, MVT::i32)); 1519 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end()); 1520 i += 2; 1521 } 1522 } 1523 1524 // Add the glue input back if present. 1525 if (e != InOps.size()) 1526 Ops.push_back(InOps.back()); 1527 } 1528 1529 /// findGlueUse - Return use of MVT::Glue value produced by the specified 1530 /// SDNode. 1531 /// 1532 static SDNode *findGlueUse(SDNode *N) { 1533 unsigned FlagResNo = N->getNumValues()-1; 1534 for (SDNode::use_iterator I = N->use_begin(), E = N->use_end(); I != E; ++I) { 1535 SDUse &Use = I.getUse(); 1536 if (Use.getResNo() == FlagResNo) 1537 return Use.getUser(); 1538 } 1539 return NULL; 1540 } 1541 1542 /// findNonImmUse - Return true if "Use" is a non-immediate use of "Def". 1543 /// This function recursively traverses up the operand chain, ignoring 1544 /// certain nodes. 1545 static bool findNonImmUse(SDNode *Use, SDNode* Def, SDNode *ImmedUse, 1546 SDNode *Root, SmallPtrSet<SDNode*, 16> &Visited, 1547 bool IgnoreChains) { 1548 // The NodeID's are given uniques ID's where a node ID is guaranteed to be 1549 // greater than all of its (recursive) operands. If we scan to a point where 1550 // 'use' is smaller than the node we're scanning for, then we know we will 1551 // never find it. 1552 // 1553 // The Use may be -1 (unassigned) if it is a newly allocated node. This can 1554 // happen because we scan down to newly selected nodes in the case of glue 1555 // uses. 1556 if ((Use->getNodeId() < Def->getNodeId() && Use->getNodeId() != -1)) 1557 return false; 1558 1559 // Don't revisit nodes if we already scanned it and didn't fail, we know we 1560 // won't fail if we scan it again. 1561 if (!Visited.insert(Use)) 1562 return false; 1563 1564 for (unsigned i = 0, e = Use->getNumOperands(); i != e; ++i) { 1565 // Ignore chain uses, they are validated by HandleMergeInputChains. 1566 if (Use->getOperand(i).getValueType() == MVT::Other && IgnoreChains) 1567 continue; 1568 1569 SDNode *N = Use->getOperand(i).getNode(); 1570 if (N == Def) { 1571 if (Use == ImmedUse || Use == Root) 1572 continue; // We are not looking for immediate use. 1573 assert(N != Root); 1574 return true; 1575 } 1576 1577 // Traverse up the operand chain. 1578 if (findNonImmUse(N, Def, ImmedUse, Root, Visited, IgnoreChains)) 1579 return true; 1580 } 1581 return false; 1582 } 1583 1584 /// IsProfitableToFold - Returns true if it's profitable to fold the specific 1585 /// operand node N of U during instruction selection that starts at Root. 1586 bool SelectionDAGISel::IsProfitableToFold(SDValue N, SDNode *U, 1587 SDNode *Root) const { 1588 if (OptLevel == CodeGenOpt::None) return false; 1589 return N.hasOneUse(); 1590 } 1591 1592 /// IsLegalToFold - Returns true if the specific operand node N of 1593 /// U can be folded during instruction selection that starts at Root. 1594 bool SelectionDAGISel::IsLegalToFold(SDValue N, SDNode *U, SDNode *Root, 1595 CodeGenOpt::Level OptLevel, 1596 bool IgnoreChains) { 1597 if (OptLevel == CodeGenOpt::None) return false; 1598 1599 // If Root use can somehow reach N through a path that that doesn't contain 1600 // U then folding N would create a cycle. e.g. In the following 1601 // diagram, Root can reach N through X. If N is folded into into Root, then 1602 // X is both a predecessor and a successor of U. 1603 // 1604 // [N*] // 1605 // ^ ^ // 1606 // / \ // 1607 // [U*] [X]? // 1608 // ^ ^ // 1609 // \ / // 1610 // \ / // 1611 // [Root*] // 1612 // 1613 // * indicates nodes to be folded together. 1614 // 1615 // If Root produces glue, then it gets (even more) interesting. Since it 1616 // will be "glued" together with its glue use in the scheduler, we need to 1617 // check if it might reach N. 1618 // 1619 // [N*] // 1620 // ^ ^ // 1621 // / \ // 1622 // [U*] [X]? // 1623 // ^ ^ // 1624 // \ \ // 1625 // \ | // 1626 // [Root*] | // 1627 // ^ | // 1628 // f | // 1629 // | / // 1630 // [Y] / // 1631 // ^ / // 1632 // f / // 1633 // | / // 1634 // [GU] // 1635 // 1636 // If GU (glue use) indirectly reaches N (the load), and Root folds N 1637 // (call it Fold), then X is a predecessor of GU and a successor of 1638 // Fold. But since Fold and GU are glued together, this will create 1639 // a cycle in the scheduling graph. 1640 1641 // If the node has glue, walk down the graph to the "lowest" node in the 1642 // glueged set. 1643 EVT VT = Root->getValueType(Root->getNumValues()-1); 1644 while (VT == MVT::Glue) { 1645 SDNode *GU = findGlueUse(Root); 1646 if (GU == NULL) 1647 break; 1648 Root = GU; 1649 VT = Root->getValueType(Root->getNumValues()-1); 1650 1651 // If our query node has a glue result with a use, we've walked up it. If 1652 // the user (which has already been selected) has a chain or indirectly uses 1653 // the chain, our WalkChainUsers predicate will not consider it. Because of 1654 // this, we cannot ignore chains in this predicate. 1655 IgnoreChains = false; 1656 } 1657 1658 1659 SmallPtrSet<SDNode*, 16> Visited; 1660 return !findNonImmUse(Root, N.getNode(), U, Root, Visited, IgnoreChains); 1661 } 1662 1663 SDNode *SelectionDAGISel::Select_INLINEASM(SDNode *N) { 1664 std::vector<SDValue> Ops(N->op_begin(), N->op_end()); 1665 SelectInlineAsmMemoryOperands(Ops); 1666 1667 std::vector<EVT> VTs; 1668 VTs.push_back(MVT::Other); 1669 VTs.push_back(MVT::Glue); 1670 SDValue New = CurDAG->getNode(ISD::INLINEASM, N->getDebugLoc(), 1671 VTs, &Ops[0], Ops.size()); 1672 New->setNodeId(-1); 1673 return New.getNode(); 1674 } 1675 1676 SDNode *SelectionDAGISel::Select_UNDEF(SDNode *N) { 1677 return CurDAG->SelectNodeTo(N, TargetOpcode::IMPLICIT_DEF,N->getValueType(0)); 1678 } 1679 1680 /// GetVBR - decode a vbr encoding whose top bit is set. 1681 LLVM_ATTRIBUTE_ALWAYS_INLINE static uint64_t 1682 GetVBR(uint64_t Val, const unsigned char *MatcherTable, unsigned &Idx) { 1683 assert(Val >= 128 && "Not a VBR"); 1684 Val &= 127; // Remove first vbr bit. 1685 1686 unsigned Shift = 7; 1687 uint64_t NextBits; 1688 do { 1689 NextBits = MatcherTable[Idx++]; 1690 Val |= (NextBits&127) << Shift; 1691 Shift += 7; 1692 } while (NextBits & 128); 1693 1694 return Val; 1695 } 1696 1697 1698 /// UpdateChainsAndGlue - When a match is complete, this method updates uses of 1699 /// interior glue and chain results to use the new glue and chain results. 1700 void SelectionDAGISel:: 1701 UpdateChainsAndGlue(SDNode *NodeToMatch, SDValue InputChain, 1702 const SmallVectorImpl<SDNode*> &ChainNodesMatched, 1703 SDValue InputGlue, 1704 const SmallVectorImpl<SDNode*> &GlueResultNodesMatched, 1705 bool isMorphNodeTo) { 1706 SmallVector<SDNode*, 4> NowDeadNodes; 1707 1708 // Now that all the normal results are replaced, we replace the chain and 1709 // glue results if present. 1710 if (!ChainNodesMatched.empty()) { 1711 assert(InputChain.getNode() != 0 && 1712 "Matched input chains but didn't produce a chain"); 1713 // Loop over all of the nodes we matched that produced a chain result. 1714 // Replace all the chain results with the final chain we ended up with. 1715 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1716 SDNode *ChainNode = ChainNodesMatched[i]; 1717 1718 // If this node was already deleted, don't look at it. 1719 if (ChainNode->getOpcode() == ISD::DELETED_NODE) 1720 continue; 1721 1722 // Don't replace the results of the root node if we're doing a 1723 // MorphNodeTo. 1724 if (ChainNode == NodeToMatch && isMorphNodeTo) 1725 continue; 1726 1727 SDValue ChainVal = SDValue(ChainNode, ChainNode->getNumValues()-1); 1728 if (ChainVal.getValueType() == MVT::Glue) 1729 ChainVal = ChainVal.getValue(ChainVal->getNumValues()-2); 1730 assert(ChainVal.getValueType() == MVT::Other && "Not a chain?"); 1731 CurDAG->ReplaceAllUsesOfValueWith(ChainVal, InputChain); 1732 1733 // If the node became dead and we haven't already seen it, delete it. 1734 if (ChainNode->use_empty() && 1735 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), ChainNode)) 1736 NowDeadNodes.push_back(ChainNode); 1737 } 1738 } 1739 1740 // If the result produces glue, update any glue results in the matched 1741 // pattern with the glue result. 1742 if (InputGlue.getNode() != 0) { 1743 // Handle any interior nodes explicitly marked. 1744 for (unsigned i = 0, e = GlueResultNodesMatched.size(); i != e; ++i) { 1745 SDNode *FRN = GlueResultNodesMatched[i]; 1746 1747 // If this node was already deleted, don't look at it. 1748 if (FRN->getOpcode() == ISD::DELETED_NODE) 1749 continue; 1750 1751 assert(FRN->getValueType(FRN->getNumValues()-1) == MVT::Glue && 1752 "Doesn't have a glue result"); 1753 CurDAG->ReplaceAllUsesOfValueWith(SDValue(FRN, FRN->getNumValues()-1), 1754 InputGlue); 1755 1756 // If the node became dead and we haven't already seen it, delete it. 1757 if (FRN->use_empty() && 1758 !std::count(NowDeadNodes.begin(), NowDeadNodes.end(), FRN)) 1759 NowDeadNodes.push_back(FRN); 1760 } 1761 } 1762 1763 if (!NowDeadNodes.empty()) 1764 CurDAG->RemoveDeadNodes(NowDeadNodes); 1765 1766 DEBUG(errs() << "ISEL: Match complete!\n"); 1767 } 1768 1769 enum ChainResult { 1770 CR_Simple, 1771 CR_InducesCycle, 1772 CR_LeadsToInteriorNode 1773 }; 1774 1775 /// WalkChainUsers - Walk down the users of the specified chained node that is 1776 /// part of the pattern we're matching, looking at all of the users we find. 1777 /// This determines whether something is an interior node, whether we have a 1778 /// non-pattern node in between two pattern nodes (which prevent folding because 1779 /// it would induce a cycle) and whether we have a TokenFactor node sandwiched 1780 /// between pattern nodes (in which case the TF becomes part of the pattern). 1781 /// 1782 /// The walk we do here is guaranteed to be small because we quickly get down to 1783 /// already selected nodes "below" us. 1784 static ChainResult 1785 WalkChainUsers(const SDNode *ChainedNode, 1786 SmallVectorImpl<SDNode*> &ChainedNodesInPattern, 1787 SmallVectorImpl<SDNode*> &InteriorChainedNodes) { 1788 ChainResult Result = CR_Simple; 1789 1790 for (SDNode::use_iterator UI = ChainedNode->use_begin(), 1791 E = ChainedNode->use_end(); UI != E; ++UI) { 1792 // Make sure the use is of the chain, not some other value we produce. 1793 if (UI.getUse().getValueType() != MVT::Other) continue; 1794 1795 SDNode *User = *UI; 1796 1797 // If we see an already-selected machine node, then we've gone beyond the 1798 // pattern that we're selecting down into the already selected chunk of the 1799 // DAG. 1800 if (User->isMachineOpcode() || 1801 User->getOpcode() == ISD::HANDLENODE) // Root of the graph. 1802 continue; 1803 1804 unsigned UserOpcode = User->getOpcode(); 1805 if (UserOpcode == ISD::CopyToReg || 1806 UserOpcode == ISD::CopyFromReg || 1807 UserOpcode == ISD::INLINEASM || 1808 UserOpcode == ISD::EH_LABEL || 1809 UserOpcode == ISD::LIFETIME_START || 1810 UserOpcode == ISD::LIFETIME_END) { 1811 // If their node ID got reset to -1 then they've already been selected. 1812 // Treat them like a MachineOpcode. 1813 if (User->getNodeId() == -1) 1814 continue; 1815 } 1816 1817 // If we have a TokenFactor, we handle it specially. 1818 if (User->getOpcode() != ISD::TokenFactor) { 1819 // If the node isn't a token factor and isn't part of our pattern, then it 1820 // must be a random chained node in between two nodes we're selecting. 1821 // This happens when we have something like: 1822 // x = load ptr 1823 // call 1824 // y = x+4 1825 // store y -> ptr 1826 // Because we structurally match the load/store as a read/modify/write, 1827 // but the call is chained between them. We cannot fold in this case 1828 // because it would induce a cycle in the graph. 1829 if (!std::count(ChainedNodesInPattern.begin(), 1830 ChainedNodesInPattern.end(), User)) 1831 return CR_InducesCycle; 1832 1833 // Otherwise we found a node that is part of our pattern. For example in: 1834 // x = load ptr 1835 // y = x+4 1836 // store y -> ptr 1837 // This would happen when we're scanning down from the load and see the 1838 // store as a user. Record that there is a use of ChainedNode that is 1839 // part of the pattern and keep scanning uses. 1840 Result = CR_LeadsToInteriorNode; 1841 InteriorChainedNodes.push_back(User); 1842 continue; 1843 } 1844 1845 // If we found a TokenFactor, there are two cases to consider: first if the 1846 // TokenFactor is just hanging "below" the pattern we're matching (i.e. no 1847 // uses of the TF are in our pattern) we just want to ignore it. Second, 1848 // the TokenFactor can be sandwiched in between two chained nodes, like so: 1849 // [Load chain] 1850 // ^ 1851 // | 1852 // [Load] 1853 // ^ ^ 1854 // | \ DAG's like cheese 1855 // / \ do you? 1856 // / | 1857 // [TokenFactor] [Op] 1858 // ^ ^ 1859 // | | 1860 // \ / 1861 // \ / 1862 // [Store] 1863 // 1864 // In this case, the TokenFactor becomes part of our match and we rewrite it 1865 // as a new TokenFactor. 1866 // 1867 // To distinguish these two cases, do a recursive walk down the uses. 1868 switch (WalkChainUsers(User, ChainedNodesInPattern, InteriorChainedNodes)) { 1869 case CR_Simple: 1870 // If the uses of the TokenFactor are just already-selected nodes, ignore 1871 // it, it is "below" our pattern. 1872 continue; 1873 case CR_InducesCycle: 1874 // If the uses of the TokenFactor lead to nodes that are not part of our 1875 // pattern that are not selected, folding would turn this into a cycle, 1876 // bail out now. 1877 return CR_InducesCycle; 1878 case CR_LeadsToInteriorNode: 1879 break; // Otherwise, keep processing. 1880 } 1881 1882 // Okay, we know we're in the interesting interior case. The TokenFactor 1883 // is now going to be considered part of the pattern so that we rewrite its 1884 // uses (it may have uses that are not part of the pattern) with the 1885 // ultimate chain result of the generated code. We will also add its chain 1886 // inputs as inputs to the ultimate TokenFactor we create. 1887 Result = CR_LeadsToInteriorNode; 1888 ChainedNodesInPattern.push_back(User); 1889 InteriorChainedNodes.push_back(User); 1890 continue; 1891 } 1892 1893 return Result; 1894 } 1895 1896 /// HandleMergeInputChains - This implements the OPC_EmitMergeInputChains 1897 /// operation for when the pattern matched at least one node with a chains. The 1898 /// input vector contains a list of all of the chained nodes that we match. We 1899 /// must determine if this is a valid thing to cover (i.e. matching it won't 1900 /// induce cycles in the DAG) and if so, creating a TokenFactor node. that will 1901 /// be used as the input node chain for the generated nodes. 1902 static SDValue 1903 HandleMergeInputChains(SmallVectorImpl<SDNode*> &ChainNodesMatched, 1904 SelectionDAG *CurDAG) { 1905 // Walk all of the chained nodes we've matched, recursively scanning down the 1906 // users of the chain result. This adds any TokenFactor nodes that are caught 1907 // in between chained nodes to the chained and interior nodes list. 1908 SmallVector<SDNode*, 3> InteriorChainedNodes; 1909 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1910 if (WalkChainUsers(ChainNodesMatched[i], ChainNodesMatched, 1911 InteriorChainedNodes) == CR_InducesCycle) 1912 return SDValue(); // Would induce a cycle. 1913 } 1914 1915 // Okay, we have walked all the matched nodes and collected TokenFactor nodes 1916 // that we are interested in. Form our input TokenFactor node. 1917 SmallVector<SDValue, 3> InputChains; 1918 for (unsigned i = 0, e = ChainNodesMatched.size(); i != e; ++i) { 1919 // Add the input chain of this node to the InputChains list (which will be 1920 // the operands of the generated TokenFactor) if it's not an interior node. 1921 SDNode *N = ChainNodesMatched[i]; 1922 if (N->getOpcode() != ISD::TokenFactor) { 1923 if (std::count(InteriorChainedNodes.begin(),InteriorChainedNodes.end(),N)) 1924 continue; 1925 1926 // Otherwise, add the input chain. 1927 SDValue InChain = ChainNodesMatched[i]->getOperand(0); 1928 assert(InChain.getValueType() == MVT::Other && "Not a chain"); 1929 InputChains.push_back(InChain); 1930 continue; 1931 } 1932 1933 // If we have a token factor, we want to add all inputs of the token factor 1934 // that are not part of the pattern we're matching. 1935 for (unsigned op = 0, e = N->getNumOperands(); op != e; ++op) { 1936 if (!std::count(ChainNodesMatched.begin(), ChainNodesMatched.end(), 1937 N->getOperand(op).getNode())) 1938 InputChains.push_back(N->getOperand(op)); 1939 } 1940 } 1941 1942 SDValue Res; 1943 if (InputChains.size() == 1) 1944 return InputChains[0]; 1945 return CurDAG->getNode(ISD::TokenFactor, ChainNodesMatched[0]->getDebugLoc(), 1946 MVT::Other, &InputChains[0], InputChains.size()); 1947 } 1948 1949 /// MorphNode - Handle morphing a node in place for the selector. 1950 SDNode *SelectionDAGISel:: 1951 MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTList, 1952 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo) { 1953 // It is possible we're using MorphNodeTo to replace a node with no 1954 // normal results with one that has a normal result (or we could be 1955 // adding a chain) and the input could have glue and chains as well. 1956 // In this case we need to shift the operands down. 1957 // FIXME: This is a horrible hack and broken in obscure cases, no worse 1958 // than the old isel though. 1959 int OldGlueResultNo = -1, OldChainResultNo = -1; 1960 1961 unsigned NTMNumResults = Node->getNumValues(); 1962 if (Node->getValueType(NTMNumResults-1) == MVT::Glue) { 1963 OldGlueResultNo = NTMNumResults-1; 1964 if (NTMNumResults != 1 && 1965 Node->getValueType(NTMNumResults-2) == MVT::Other) 1966 OldChainResultNo = NTMNumResults-2; 1967 } else if (Node->getValueType(NTMNumResults-1) == MVT::Other) 1968 OldChainResultNo = NTMNumResults-1; 1969 1970 // Call the underlying SelectionDAG routine to do the transmogrification. Note 1971 // that this deletes operands of the old node that become dead. 1972 SDNode *Res = CurDAG->MorphNodeTo(Node, ~TargetOpc, VTList, Ops, NumOps); 1973 1974 // MorphNodeTo can operate in two ways: if an existing node with the 1975 // specified operands exists, it can just return it. Otherwise, it 1976 // updates the node in place to have the requested operands. 1977 if (Res == Node) { 1978 // If we updated the node in place, reset the node ID. To the isel, 1979 // this should be just like a newly allocated machine node. 1980 Res->setNodeId(-1); 1981 } 1982 1983 unsigned ResNumResults = Res->getNumValues(); 1984 // Move the glue if needed. 1985 if ((EmitNodeInfo & OPFL_GlueOutput) && OldGlueResultNo != -1 && 1986 (unsigned)OldGlueResultNo != ResNumResults-1) 1987 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldGlueResultNo), 1988 SDValue(Res, ResNumResults-1)); 1989 1990 if ((EmitNodeInfo & OPFL_GlueOutput) != 0) 1991 --ResNumResults; 1992 1993 // Move the chain reference if needed. 1994 if ((EmitNodeInfo & OPFL_Chain) && OldChainResultNo != -1 && 1995 (unsigned)OldChainResultNo != ResNumResults-1) 1996 CurDAG->ReplaceAllUsesOfValueWith(SDValue(Node, OldChainResultNo), 1997 SDValue(Res, ResNumResults-1)); 1998 1999 // Otherwise, no replacement happened because the node already exists. Replace 2000 // Uses of the old node with the new one. 2001 if (Res != Node) 2002 CurDAG->ReplaceAllUsesWith(Node, Res); 2003 2004 return Res; 2005 } 2006 2007 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2008 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2009 CheckSame(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2010 SDValue N, 2011 const SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2012 // Accept if it is exactly the same as a previously recorded node. 2013 unsigned RecNo = MatcherTable[MatcherIndex++]; 2014 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2015 return N == RecordedNodes[RecNo].first; 2016 } 2017 2018 /// CheckPatternPredicate - Implements OP_CheckPatternPredicate. 2019 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2020 CheckPatternPredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2021 const SelectionDAGISel &SDISel) { 2022 return SDISel.CheckPatternPredicate(MatcherTable[MatcherIndex++]); 2023 } 2024 2025 /// CheckNodePredicate - Implements OP_CheckNodePredicate. 2026 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2027 CheckNodePredicate(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2028 const SelectionDAGISel &SDISel, SDNode *N) { 2029 return SDISel.CheckNodePredicate(N, MatcherTable[MatcherIndex++]); 2030 } 2031 2032 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2033 CheckOpcode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2034 SDNode *N) { 2035 uint16_t Opc = MatcherTable[MatcherIndex++]; 2036 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2037 return N->getOpcode() == Opc; 2038 } 2039 2040 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2041 CheckType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2042 SDValue N, const TargetLowering &TLI) { 2043 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2044 if (N.getValueType() == VT) return true; 2045 2046 // Handle the case when VT is iPTR. 2047 return VT == MVT::iPTR && N.getValueType() == TLI.getPointerTy(); 2048 } 2049 2050 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2051 CheckChildType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2052 SDValue N, const TargetLowering &TLI, 2053 unsigned ChildNo) { 2054 if (ChildNo >= N.getNumOperands()) 2055 return false; // Match fails if out of range child #. 2056 return ::CheckType(MatcherTable, MatcherIndex, N.getOperand(ChildNo), TLI); 2057 } 2058 2059 2060 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2061 CheckCondCode(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2062 SDValue N) { 2063 return cast<CondCodeSDNode>(N)->get() == 2064 (ISD::CondCode)MatcherTable[MatcherIndex++]; 2065 } 2066 2067 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2068 CheckValueType(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2069 SDValue N, const TargetLowering &TLI) { 2070 MVT::SimpleValueType VT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2071 if (cast<VTSDNode>(N)->getVT() == VT) 2072 return true; 2073 2074 // Handle the case when VT is iPTR. 2075 return VT == MVT::iPTR && cast<VTSDNode>(N)->getVT() == TLI.getPointerTy(); 2076 } 2077 2078 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2079 CheckInteger(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2080 SDValue N) { 2081 int64_t Val = MatcherTable[MatcherIndex++]; 2082 if (Val & 128) 2083 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2084 2085 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N); 2086 return C != 0 && C->getSExtValue() == Val; 2087 } 2088 2089 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2090 CheckAndImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2091 SDValue N, const SelectionDAGISel &SDISel) { 2092 int64_t Val = MatcherTable[MatcherIndex++]; 2093 if (Val & 128) 2094 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2095 2096 if (N->getOpcode() != ISD::AND) return false; 2097 2098 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2099 return C != 0 && SDISel.CheckAndMask(N.getOperand(0), C, Val); 2100 } 2101 2102 LLVM_ATTRIBUTE_ALWAYS_INLINE static bool 2103 CheckOrImm(const unsigned char *MatcherTable, unsigned &MatcherIndex, 2104 SDValue N, const SelectionDAGISel &SDISel) { 2105 int64_t Val = MatcherTable[MatcherIndex++]; 2106 if (Val & 128) 2107 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2108 2109 if (N->getOpcode() != ISD::OR) return false; 2110 2111 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 2112 return C != 0 && SDISel.CheckOrMask(N.getOperand(0), C, Val); 2113 } 2114 2115 /// IsPredicateKnownToFail - If we know how and can do so without pushing a 2116 /// scope, evaluate the current node. If the current predicate is known to 2117 /// fail, set Result=true and return anything. If the current predicate is 2118 /// known to pass, set Result=false and return the MatcherIndex to continue 2119 /// with. If the current predicate is unknown, set Result=false and return the 2120 /// MatcherIndex to continue with. 2121 static unsigned IsPredicateKnownToFail(const unsigned char *Table, 2122 unsigned Index, SDValue N, 2123 bool &Result, 2124 const SelectionDAGISel &SDISel, 2125 SmallVectorImpl<std::pair<SDValue, SDNode*> > &RecordedNodes) { 2126 switch (Table[Index++]) { 2127 default: 2128 Result = false; 2129 return Index-1; // Could not evaluate this predicate. 2130 case SelectionDAGISel::OPC_CheckSame: 2131 Result = !::CheckSame(Table, Index, N, RecordedNodes); 2132 return Index; 2133 case SelectionDAGISel::OPC_CheckPatternPredicate: 2134 Result = !::CheckPatternPredicate(Table, Index, SDISel); 2135 return Index; 2136 case SelectionDAGISel::OPC_CheckPredicate: 2137 Result = !::CheckNodePredicate(Table, Index, SDISel, N.getNode()); 2138 return Index; 2139 case SelectionDAGISel::OPC_CheckOpcode: 2140 Result = !::CheckOpcode(Table, Index, N.getNode()); 2141 return Index; 2142 case SelectionDAGISel::OPC_CheckType: 2143 Result = !::CheckType(Table, Index, N, SDISel.TLI); 2144 return Index; 2145 case SelectionDAGISel::OPC_CheckChild0Type: 2146 case SelectionDAGISel::OPC_CheckChild1Type: 2147 case SelectionDAGISel::OPC_CheckChild2Type: 2148 case SelectionDAGISel::OPC_CheckChild3Type: 2149 case SelectionDAGISel::OPC_CheckChild4Type: 2150 case SelectionDAGISel::OPC_CheckChild5Type: 2151 case SelectionDAGISel::OPC_CheckChild6Type: 2152 case SelectionDAGISel::OPC_CheckChild7Type: 2153 Result = !::CheckChildType(Table, Index, N, SDISel.TLI, 2154 Table[Index-1] - SelectionDAGISel::OPC_CheckChild0Type); 2155 return Index; 2156 case SelectionDAGISel::OPC_CheckCondCode: 2157 Result = !::CheckCondCode(Table, Index, N); 2158 return Index; 2159 case SelectionDAGISel::OPC_CheckValueType: 2160 Result = !::CheckValueType(Table, Index, N, SDISel.TLI); 2161 return Index; 2162 case SelectionDAGISel::OPC_CheckInteger: 2163 Result = !::CheckInteger(Table, Index, N); 2164 return Index; 2165 case SelectionDAGISel::OPC_CheckAndImm: 2166 Result = !::CheckAndImm(Table, Index, N, SDISel); 2167 return Index; 2168 case SelectionDAGISel::OPC_CheckOrImm: 2169 Result = !::CheckOrImm(Table, Index, N, SDISel); 2170 return Index; 2171 } 2172 } 2173 2174 namespace { 2175 2176 struct MatchScope { 2177 /// FailIndex - If this match fails, this is the index to continue with. 2178 unsigned FailIndex; 2179 2180 /// NodeStack - The node stack when the scope was formed. 2181 SmallVector<SDValue, 4> NodeStack; 2182 2183 /// NumRecordedNodes - The number of recorded nodes when the scope was formed. 2184 unsigned NumRecordedNodes; 2185 2186 /// NumMatchedMemRefs - The number of matched memref entries. 2187 unsigned NumMatchedMemRefs; 2188 2189 /// InputChain/InputGlue - The current chain/glue 2190 SDValue InputChain, InputGlue; 2191 2192 /// HasChainNodesMatched - True if the ChainNodesMatched list is non-empty. 2193 bool HasChainNodesMatched, HasGlueResultNodesMatched; 2194 }; 2195 2196 } 2197 2198 SDNode *SelectionDAGISel:: 2199 SelectCodeCommon(SDNode *NodeToMatch, const unsigned char *MatcherTable, 2200 unsigned TableSize) { 2201 // FIXME: Should these even be selected? Handle these cases in the caller? 2202 switch (NodeToMatch->getOpcode()) { 2203 default: 2204 break; 2205 case ISD::EntryToken: // These nodes remain the same. 2206 case ISD::BasicBlock: 2207 case ISD::Register: 2208 case ISD::RegisterMask: 2209 //case ISD::VALUETYPE: 2210 //case ISD::CONDCODE: 2211 case ISD::HANDLENODE: 2212 case ISD::MDNODE_SDNODE: 2213 case ISD::TargetConstant: 2214 case ISD::TargetConstantFP: 2215 case ISD::TargetConstantPool: 2216 case ISD::TargetFrameIndex: 2217 case ISD::TargetExternalSymbol: 2218 case ISD::TargetBlockAddress: 2219 case ISD::TargetJumpTable: 2220 case ISD::TargetGlobalTLSAddress: 2221 case ISD::TargetGlobalAddress: 2222 case ISD::TokenFactor: 2223 case ISD::CopyFromReg: 2224 case ISD::CopyToReg: 2225 case ISD::EH_LABEL: 2226 case ISD::LIFETIME_START: 2227 case ISD::LIFETIME_END: 2228 NodeToMatch->setNodeId(-1); // Mark selected. 2229 return 0; 2230 case ISD::AssertSext: 2231 case ISD::AssertZext: 2232 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, 0), 2233 NodeToMatch->getOperand(0)); 2234 return 0; 2235 case ISD::INLINEASM: return Select_INLINEASM(NodeToMatch); 2236 case ISD::UNDEF: return Select_UNDEF(NodeToMatch); 2237 } 2238 2239 assert(!NodeToMatch->isMachineOpcode() && "Node already selected!"); 2240 2241 // Set up the node stack with NodeToMatch as the only node on the stack. 2242 SmallVector<SDValue, 8> NodeStack; 2243 SDValue N = SDValue(NodeToMatch, 0); 2244 NodeStack.push_back(N); 2245 2246 // MatchScopes - Scopes used when matching, if a match failure happens, this 2247 // indicates where to continue checking. 2248 SmallVector<MatchScope, 8> MatchScopes; 2249 2250 // RecordedNodes - This is the set of nodes that have been recorded by the 2251 // state machine. The second value is the parent of the node, or null if the 2252 // root is recorded. 2253 SmallVector<std::pair<SDValue, SDNode*>, 8> RecordedNodes; 2254 2255 // MatchedMemRefs - This is the set of MemRef's we've seen in the input 2256 // pattern. 2257 SmallVector<MachineMemOperand*, 2> MatchedMemRefs; 2258 2259 // These are the current input chain and glue for use when generating nodes. 2260 // Various Emit operations change these. For example, emitting a copytoreg 2261 // uses and updates these. 2262 SDValue InputChain, InputGlue; 2263 2264 // ChainNodesMatched - If a pattern matches nodes that have input/output 2265 // chains, the OPC_EmitMergeInputChains operation is emitted which indicates 2266 // which ones they are. The result is captured into this list so that we can 2267 // update the chain results when the pattern is complete. 2268 SmallVector<SDNode*, 3> ChainNodesMatched; 2269 SmallVector<SDNode*, 3> GlueResultNodesMatched; 2270 2271 DEBUG(errs() << "ISEL: Starting pattern match on root node: "; 2272 NodeToMatch->dump(CurDAG); 2273 errs() << '\n'); 2274 2275 // Determine where to start the interpreter. Normally we start at opcode #0, 2276 // but if the state machine starts with an OPC_SwitchOpcode, then we 2277 // accelerate the first lookup (which is guaranteed to be hot) with the 2278 // OpcodeOffset table. 2279 unsigned MatcherIndex = 0; 2280 2281 if (!OpcodeOffset.empty()) { 2282 // Already computed the OpcodeOffset table, just index into it. 2283 if (N.getOpcode() < OpcodeOffset.size()) 2284 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2285 DEBUG(errs() << " Initial Opcode index to " << MatcherIndex << "\n"); 2286 2287 } else if (MatcherTable[0] == OPC_SwitchOpcode) { 2288 // Otherwise, the table isn't computed, but the state machine does start 2289 // with an OPC_SwitchOpcode instruction. Populate the table now, since this 2290 // is the first time we're selecting an instruction. 2291 unsigned Idx = 1; 2292 while (1) { 2293 // Get the size of this case. 2294 unsigned CaseSize = MatcherTable[Idx++]; 2295 if (CaseSize & 128) 2296 CaseSize = GetVBR(CaseSize, MatcherTable, Idx); 2297 if (CaseSize == 0) break; 2298 2299 // Get the opcode, add the index to the table. 2300 uint16_t Opc = MatcherTable[Idx++]; 2301 Opc |= (unsigned short)MatcherTable[Idx++] << 8; 2302 if (Opc >= OpcodeOffset.size()) 2303 OpcodeOffset.resize((Opc+1)*2); 2304 OpcodeOffset[Opc] = Idx; 2305 Idx += CaseSize; 2306 } 2307 2308 // Okay, do the lookup for the first opcode. 2309 if (N.getOpcode() < OpcodeOffset.size()) 2310 MatcherIndex = OpcodeOffset[N.getOpcode()]; 2311 } 2312 2313 while (1) { 2314 assert(MatcherIndex < TableSize && "Invalid index"); 2315 #ifndef NDEBUG 2316 unsigned CurrentOpcodeIndex = MatcherIndex; 2317 #endif 2318 BuiltinOpcodes Opcode = (BuiltinOpcodes)MatcherTable[MatcherIndex++]; 2319 switch (Opcode) { 2320 case OPC_Scope: { 2321 // Okay, the semantics of this operation are that we should push a scope 2322 // then evaluate the first child. However, pushing a scope only to have 2323 // the first check fail (which then pops it) is inefficient. If we can 2324 // determine immediately that the first check (or first several) will 2325 // immediately fail, don't even bother pushing a scope for them. 2326 unsigned FailIndex; 2327 2328 while (1) { 2329 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2330 if (NumToSkip & 128) 2331 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2332 // Found the end of the scope with no match. 2333 if (NumToSkip == 0) { 2334 FailIndex = 0; 2335 break; 2336 } 2337 2338 FailIndex = MatcherIndex+NumToSkip; 2339 2340 unsigned MatcherIndexOfPredicate = MatcherIndex; 2341 (void)MatcherIndexOfPredicate; // silence warning. 2342 2343 // If we can't evaluate this predicate without pushing a scope (e.g. if 2344 // it is a 'MoveParent') or if the predicate succeeds on this node, we 2345 // push the scope and evaluate the full predicate chain. 2346 bool Result; 2347 MatcherIndex = IsPredicateKnownToFail(MatcherTable, MatcherIndex, N, 2348 Result, *this, RecordedNodes); 2349 if (!Result) 2350 break; 2351 2352 DEBUG(errs() << " Skipped scope entry (due to false predicate) at " 2353 << "index " << MatcherIndexOfPredicate 2354 << ", continuing at " << FailIndex << "\n"); 2355 ++NumDAGIselRetries; 2356 2357 // Otherwise, we know that this case of the Scope is guaranteed to fail, 2358 // move to the next case. 2359 MatcherIndex = FailIndex; 2360 } 2361 2362 // If the whole scope failed to match, bail. 2363 if (FailIndex == 0) break; 2364 2365 // Push a MatchScope which indicates where to go if the first child fails 2366 // to match. 2367 MatchScope NewEntry; 2368 NewEntry.FailIndex = FailIndex; 2369 NewEntry.NodeStack.append(NodeStack.begin(), NodeStack.end()); 2370 NewEntry.NumRecordedNodes = RecordedNodes.size(); 2371 NewEntry.NumMatchedMemRefs = MatchedMemRefs.size(); 2372 NewEntry.InputChain = InputChain; 2373 NewEntry.InputGlue = InputGlue; 2374 NewEntry.HasChainNodesMatched = !ChainNodesMatched.empty(); 2375 NewEntry.HasGlueResultNodesMatched = !GlueResultNodesMatched.empty(); 2376 MatchScopes.push_back(NewEntry); 2377 continue; 2378 } 2379 case OPC_RecordNode: { 2380 // Remember this node, it may end up being an operand in the pattern. 2381 SDNode *Parent = 0; 2382 if (NodeStack.size() > 1) 2383 Parent = NodeStack[NodeStack.size()-2].getNode(); 2384 RecordedNodes.push_back(std::make_pair(N, Parent)); 2385 continue; 2386 } 2387 2388 case OPC_RecordChild0: case OPC_RecordChild1: 2389 case OPC_RecordChild2: case OPC_RecordChild3: 2390 case OPC_RecordChild4: case OPC_RecordChild5: 2391 case OPC_RecordChild6: case OPC_RecordChild7: { 2392 unsigned ChildNo = Opcode-OPC_RecordChild0; 2393 if (ChildNo >= N.getNumOperands()) 2394 break; // Match fails if out of range child #. 2395 2396 RecordedNodes.push_back(std::make_pair(N->getOperand(ChildNo), 2397 N.getNode())); 2398 continue; 2399 } 2400 case OPC_RecordMemRef: 2401 MatchedMemRefs.push_back(cast<MemSDNode>(N)->getMemOperand()); 2402 continue; 2403 2404 case OPC_CaptureGlueInput: 2405 // If the current node has an input glue, capture it in InputGlue. 2406 if (N->getNumOperands() != 0 && 2407 N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Glue) 2408 InputGlue = N->getOperand(N->getNumOperands()-1); 2409 continue; 2410 2411 case OPC_MoveChild: { 2412 unsigned ChildNo = MatcherTable[MatcherIndex++]; 2413 if (ChildNo >= N.getNumOperands()) 2414 break; // Match fails if out of range child #. 2415 N = N.getOperand(ChildNo); 2416 NodeStack.push_back(N); 2417 continue; 2418 } 2419 2420 case OPC_MoveParent: 2421 // Pop the current node off the NodeStack. 2422 NodeStack.pop_back(); 2423 assert(!NodeStack.empty() && "Node stack imbalance!"); 2424 N = NodeStack.back(); 2425 continue; 2426 2427 case OPC_CheckSame: 2428 if (!::CheckSame(MatcherTable, MatcherIndex, N, RecordedNodes)) break; 2429 continue; 2430 case OPC_CheckPatternPredicate: 2431 if (!::CheckPatternPredicate(MatcherTable, MatcherIndex, *this)) break; 2432 continue; 2433 case OPC_CheckPredicate: 2434 if (!::CheckNodePredicate(MatcherTable, MatcherIndex, *this, 2435 N.getNode())) 2436 break; 2437 continue; 2438 case OPC_CheckComplexPat: { 2439 unsigned CPNum = MatcherTable[MatcherIndex++]; 2440 unsigned RecNo = MatcherTable[MatcherIndex++]; 2441 assert(RecNo < RecordedNodes.size() && "Invalid CheckComplexPat"); 2442 if (!CheckComplexPattern(NodeToMatch, RecordedNodes[RecNo].second, 2443 RecordedNodes[RecNo].first, CPNum, 2444 RecordedNodes)) 2445 break; 2446 continue; 2447 } 2448 case OPC_CheckOpcode: 2449 if (!::CheckOpcode(MatcherTable, MatcherIndex, N.getNode())) break; 2450 continue; 2451 2452 case OPC_CheckType: 2453 if (!::CheckType(MatcherTable, MatcherIndex, N, TLI)) break; 2454 continue; 2455 2456 case OPC_SwitchOpcode: { 2457 unsigned CurNodeOpcode = N.getOpcode(); 2458 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2459 unsigned CaseSize; 2460 while (1) { 2461 // Get the size of this case. 2462 CaseSize = MatcherTable[MatcherIndex++]; 2463 if (CaseSize & 128) 2464 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2465 if (CaseSize == 0) break; 2466 2467 uint16_t Opc = MatcherTable[MatcherIndex++]; 2468 Opc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2469 2470 // If the opcode matches, then we will execute this case. 2471 if (CurNodeOpcode == Opc) 2472 break; 2473 2474 // Otherwise, skip over this case. 2475 MatcherIndex += CaseSize; 2476 } 2477 2478 // If no cases matched, bail out. 2479 if (CaseSize == 0) break; 2480 2481 // Otherwise, execute the case we found. 2482 DEBUG(errs() << " OpcodeSwitch from " << SwitchStart 2483 << " to " << MatcherIndex << "\n"); 2484 continue; 2485 } 2486 2487 case OPC_SwitchType: { 2488 MVT CurNodeVT = N.getValueType().getSimpleVT(); 2489 unsigned SwitchStart = MatcherIndex-1; (void)SwitchStart; 2490 unsigned CaseSize; 2491 while (1) { 2492 // Get the size of this case. 2493 CaseSize = MatcherTable[MatcherIndex++]; 2494 if (CaseSize & 128) 2495 CaseSize = GetVBR(CaseSize, MatcherTable, MatcherIndex); 2496 if (CaseSize == 0) break; 2497 2498 MVT CaseVT = (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2499 if (CaseVT == MVT::iPTR) 2500 CaseVT = TLI.getPointerTy(); 2501 2502 // If the VT matches, then we will execute this case. 2503 if (CurNodeVT == CaseVT) 2504 break; 2505 2506 // Otherwise, skip over this case. 2507 MatcherIndex += CaseSize; 2508 } 2509 2510 // If no cases matched, bail out. 2511 if (CaseSize == 0) break; 2512 2513 // Otherwise, execute the case we found. 2514 DEBUG(errs() << " TypeSwitch[" << EVT(CurNodeVT).getEVTString() 2515 << "] from " << SwitchStart << " to " << MatcherIndex<<'\n'); 2516 continue; 2517 } 2518 case OPC_CheckChild0Type: case OPC_CheckChild1Type: 2519 case OPC_CheckChild2Type: case OPC_CheckChild3Type: 2520 case OPC_CheckChild4Type: case OPC_CheckChild5Type: 2521 case OPC_CheckChild6Type: case OPC_CheckChild7Type: 2522 if (!::CheckChildType(MatcherTable, MatcherIndex, N, TLI, 2523 Opcode-OPC_CheckChild0Type)) 2524 break; 2525 continue; 2526 case OPC_CheckCondCode: 2527 if (!::CheckCondCode(MatcherTable, MatcherIndex, N)) break; 2528 continue; 2529 case OPC_CheckValueType: 2530 if (!::CheckValueType(MatcherTable, MatcherIndex, N, TLI)) break; 2531 continue; 2532 case OPC_CheckInteger: 2533 if (!::CheckInteger(MatcherTable, MatcherIndex, N)) break; 2534 continue; 2535 case OPC_CheckAndImm: 2536 if (!::CheckAndImm(MatcherTable, MatcherIndex, N, *this)) break; 2537 continue; 2538 case OPC_CheckOrImm: 2539 if (!::CheckOrImm(MatcherTable, MatcherIndex, N, *this)) break; 2540 continue; 2541 2542 case OPC_CheckFoldableChainNode: { 2543 assert(NodeStack.size() != 1 && "No parent node"); 2544 // Verify that all intermediate nodes between the root and this one have 2545 // a single use. 2546 bool HasMultipleUses = false; 2547 for (unsigned i = 1, e = NodeStack.size()-1; i != e; ++i) 2548 if (!NodeStack[i].hasOneUse()) { 2549 HasMultipleUses = true; 2550 break; 2551 } 2552 if (HasMultipleUses) break; 2553 2554 // Check to see that the target thinks this is profitable to fold and that 2555 // we can fold it without inducing cycles in the graph. 2556 if (!IsProfitableToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2557 NodeToMatch) || 2558 !IsLegalToFold(N, NodeStack[NodeStack.size()-2].getNode(), 2559 NodeToMatch, OptLevel, 2560 true/*We validate our own chains*/)) 2561 break; 2562 2563 continue; 2564 } 2565 case OPC_EmitInteger: { 2566 MVT::SimpleValueType VT = 2567 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2568 int64_t Val = MatcherTable[MatcherIndex++]; 2569 if (Val & 128) 2570 Val = GetVBR(Val, MatcherTable, MatcherIndex); 2571 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2572 CurDAG->getTargetConstant(Val, VT), (SDNode*)0)); 2573 continue; 2574 } 2575 case OPC_EmitRegister: { 2576 MVT::SimpleValueType VT = 2577 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2578 unsigned RegNo = MatcherTable[MatcherIndex++]; 2579 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2580 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2581 continue; 2582 } 2583 case OPC_EmitRegister2: { 2584 // For targets w/ more than 256 register names, the register enum 2585 // values are stored in two bytes in the matcher table (just like 2586 // opcodes). 2587 MVT::SimpleValueType VT = 2588 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2589 unsigned RegNo = MatcherTable[MatcherIndex++]; 2590 RegNo |= MatcherTable[MatcherIndex++] << 8; 2591 RecordedNodes.push_back(std::pair<SDValue, SDNode*>( 2592 CurDAG->getRegister(RegNo, VT), (SDNode*)0)); 2593 continue; 2594 } 2595 2596 case OPC_EmitConvertToTarget: { 2597 // Convert from IMM/FPIMM to target version. 2598 unsigned RecNo = MatcherTable[MatcherIndex++]; 2599 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2600 SDValue Imm = RecordedNodes[RecNo].first; 2601 2602 if (Imm->getOpcode() == ISD::Constant) { 2603 int64_t Val = cast<ConstantSDNode>(Imm)->getZExtValue(); 2604 Imm = CurDAG->getTargetConstant(Val, Imm.getValueType()); 2605 } else if (Imm->getOpcode() == ISD::ConstantFP) { 2606 const ConstantFP *Val=cast<ConstantFPSDNode>(Imm)->getConstantFPValue(); 2607 Imm = CurDAG->getTargetConstantFP(*Val, Imm.getValueType()); 2608 } 2609 2610 RecordedNodes.push_back(std::make_pair(Imm, RecordedNodes[RecNo].second)); 2611 continue; 2612 } 2613 2614 case OPC_EmitMergeInputChains1_0: // OPC_EmitMergeInputChains, 1, 0 2615 case OPC_EmitMergeInputChains1_1: { // OPC_EmitMergeInputChains, 1, 1 2616 // These are space-optimized forms of OPC_EmitMergeInputChains. 2617 assert(InputChain.getNode() == 0 && 2618 "EmitMergeInputChains should be the first chain producing node"); 2619 assert(ChainNodesMatched.empty() && 2620 "Should only have one EmitMergeInputChains per match"); 2621 2622 // Read all of the chained nodes. 2623 unsigned RecNo = Opcode == OPC_EmitMergeInputChains1_1; 2624 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2625 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2626 2627 // FIXME: What if other value results of the node have uses not matched 2628 // by this pattern? 2629 if (ChainNodesMatched.back() != NodeToMatch && 2630 !RecordedNodes[RecNo].first.hasOneUse()) { 2631 ChainNodesMatched.clear(); 2632 break; 2633 } 2634 2635 // Merge the input chains if they are not intra-pattern references. 2636 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2637 2638 if (InputChain.getNode() == 0) 2639 break; // Failed to merge. 2640 continue; 2641 } 2642 2643 case OPC_EmitMergeInputChains: { 2644 assert(InputChain.getNode() == 0 && 2645 "EmitMergeInputChains should be the first chain producing node"); 2646 // This node gets a list of nodes we matched in the input that have 2647 // chains. We want to token factor all of the input chains to these nodes 2648 // together. However, if any of the input chains is actually one of the 2649 // nodes matched in this pattern, then we have an intra-match reference. 2650 // Ignore these because the newly token factored chain should not refer to 2651 // the old nodes. 2652 unsigned NumChains = MatcherTable[MatcherIndex++]; 2653 assert(NumChains != 0 && "Can't TF zero chains"); 2654 2655 assert(ChainNodesMatched.empty() && 2656 "Should only have one EmitMergeInputChains per match"); 2657 2658 // Read all of the chained nodes. 2659 for (unsigned i = 0; i != NumChains; ++i) { 2660 unsigned RecNo = MatcherTable[MatcherIndex++]; 2661 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2662 ChainNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2663 2664 // FIXME: What if other value results of the node have uses not matched 2665 // by this pattern? 2666 if (ChainNodesMatched.back() != NodeToMatch && 2667 !RecordedNodes[RecNo].first.hasOneUse()) { 2668 ChainNodesMatched.clear(); 2669 break; 2670 } 2671 } 2672 2673 // If the inner loop broke out, the match fails. 2674 if (ChainNodesMatched.empty()) 2675 break; 2676 2677 // Merge the input chains if they are not intra-pattern references. 2678 InputChain = HandleMergeInputChains(ChainNodesMatched, CurDAG); 2679 2680 if (InputChain.getNode() == 0) 2681 break; // Failed to merge. 2682 2683 continue; 2684 } 2685 2686 case OPC_EmitCopyToReg: { 2687 unsigned RecNo = MatcherTable[MatcherIndex++]; 2688 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2689 unsigned DestPhysReg = MatcherTable[MatcherIndex++]; 2690 2691 if (InputChain.getNode() == 0) 2692 InputChain = CurDAG->getEntryNode(); 2693 2694 InputChain = CurDAG->getCopyToReg(InputChain, NodeToMatch->getDebugLoc(), 2695 DestPhysReg, RecordedNodes[RecNo].first, 2696 InputGlue); 2697 2698 InputGlue = InputChain.getValue(1); 2699 continue; 2700 } 2701 2702 case OPC_EmitNodeXForm: { 2703 unsigned XFormNo = MatcherTable[MatcherIndex++]; 2704 unsigned RecNo = MatcherTable[MatcherIndex++]; 2705 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2706 SDValue Res = RunSDNodeXForm(RecordedNodes[RecNo].first, XFormNo); 2707 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(Res, (SDNode*) 0)); 2708 continue; 2709 } 2710 2711 case OPC_EmitNode: 2712 case OPC_MorphNodeTo: { 2713 uint16_t TargetOpc = MatcherTable[MatcherIndex++]; 2714 TargetOpc |= (unsigned short)MatcherTable[MatcherIndex++] << 8; 2715 unsigned EmitNodeInfo = MatcherTable[MatcherIndex++]; 2716 // Get the result VT list. 2717 unsigned NumVTs = MatcherTable[MatcherIndex++]; 2718 SmallVector<EVT, 4> VTs; 2719 for (unsigned i = 0; i != NumVTs; ++i) { 2720 MVT::SimpleValueType VT = 2721 (MVT::SimpleValueType)MatcherTable[MatcherIndex++]; 2722 if (VT == MVT::iPTR) VT = TLI.getPointerTy().SimpleTy; 2723 VTs.push_back(VT); 2724 } 2725 2726 if (EmitNodeInfo & OPFL_Chain) 2727 VTs.push_back(MVT::Other); 2728 if (EmitNodeInfo & OPFL_GlueOutput) 2729 VTs.push_back(MVT::Glue); 2730 2731 // This is hot code, so optimize the two most common cases of 1 and 2 2732 // results. 2733 SDVTList VTList; 2734 if (VTs.size() == 1) 2735 VTList = CurDAG->getVTList(VTs[0]); 2736 else if (VTs.size() == 2) 2737 VTList = CurDAG->getVTList(VTs[0], VTs[1]); 2738 else 2739 VTList = CurDAG->getVTList(VTs.data(), VTs.size()); 2740 2741 // Get the operand list. 2742 unsigned NumOps = MatcherTable[MatcherIndex++]; 2743 SmallVector<SDValue, 8> Ops; 2744 for (unsigned i = 0; i != NumOps; ++i) { 2745 unsigned RecNo = MatcherTable[MatcherIndex++]; 2746 if (RecNo & 128) 2747 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2748 2749 assert(RecNo < RecordedNodes.size() && "Invalid EmitNode"); 2750 Ops.push_back(RecordedNodes[RecNo].first); 2751 } 2752 2753 // If there are variadic operands to add, handle them now. 2754 if (EmitNodeInfo & OPFL_VariadicInfo) { 2755 // Determine the start index to copy from. 2756 unsigned FirstOpToCopy = getNumFixedFromVariadicInfo(EmitNodeInfo); 2757 FirstOpToCopy += (EmitNodeInfo & OPFL_Chain) ? 1 : 0; 2758 assert(NodeToMatch->getNumOperands() >= FirstOpToCopy && 2759 "Invalid variadic node"); 2760 // Copy all of the variadic operands, not including a potential glue 2761 // input. 2762 for (unsigned i = FirstOpToCopy, e = NodeToMatch->getNumOperands(); 2763 i != e; ++i) { 2764 SDValue V = NodeToMatch->getOperand(i); 2765 if (V.getValueType() == MVT::Glue) break; 2766 Ops.push_back(V); 2767 } 2768 } 2769 2770 // If this has chain/glue inputs, add them. 2771 if (EmitNodeInfo & OPFL_Chain) 2772 Ops.push_back(InputChain); 2773 if ((EmitNodeInfo & OPFL_GlueInput) && InputGlue.getNode() != 0) 2774 Ops.push_back(InputGlue); 2775 2776 // Create the node. 2777 SDNode *Res = 0; 2778 if (Opcode != OPC_MorphNodeTo) { 2779 // If this is a normal EmitNode command, just create the new node and 2780 // add the results to the RecordedNodes list. 2781 Res = CurDAG->getMachineNode(TargetOpc, NodeToMatch->getDebugLoc(), 2782 VTList, Ops.data(), Ops.size()); 2783 2784 // Add all the non-glue/non-chain results to the RecordedNodes list. 2785 for (unsigned i = 0, e = VTs.size(); i != e; ++i) { 2786 if (VTs[i] == MVT::Other || VTs[i] == MVT::Glue) break; 2787 RecordedNodes.push_back(std::pair<SDValue,SDNode*>(SDValue(Res, i), 2788 (SDNode*) 0)); 2789 } 2790 2791 } else if (NodeToMatch->getOpcode() != ISD::DELETED_NODE) { 2792 Res = MorphNode(NodeToMatch, TargetOpc, VTList, Ops.data(), Ops.size(), 2793 EmitNodeInfo); 2794 } else { 2795 // NodeToMatch was eliminated by CSE when the target changed the DAG. 2796 // We will visit the equivalent node later. 2797 DEBUG(dbgs() << "Node was eliminated by CSE\n"); 2798 return 0; 2799 } 2800 2801 // If the node had chain/glue results, update our notion of the current 2802 // chain and glue. 2803 if (EmitNodeInfo & OPFL_GlueOutput) { 2804 InputGlue = SDValue(Res, VTs.size()-1); 2805 if (EmitNodeInfo & OPFL_Chain) 2806 InputChain = SDValue(Res, VTs.size()-2); 2807 } else if (EmitNodeInfo & OPFL_Chain) 2808 InputChain = SDValue(Res, VTs.size()-1); 2809 2810 // If the OPFL_MemRefs glue is set on this node, slap all of the 2811 // accumulated memrefs onto it. 2812 // 2813 // FIXME: This is vastly incorrect for patterns with multiple outputs 2814 // instructions that access memory and for ComplexPatterns that match 2815 // loads. 2816 if (EmitNodeInfo & OPFL_MemRefs) { 2817 // Only attach load or store memory operands if the generated 2818 // instruction may load or store. 2819 const MCInstrDesc &MCID = TM.getInstrInfo()->get(TargetOpc); 2820 bool mayLoad = MCID.mayLoad(); 2821 bool mayStore = MCID.mayStore(); 2822 2823 unsigned NumMemRefs = 0; 2824 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2825 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2826 if ((*I)->isLoad()) { 2827 if (mayLoad) 2828 ++NumMemRefs; 2829 } else if ((*I)->isStore()) { 2830 if (mayStore) 2831 ++NumMemRefs; 2832 } else { 2833 ++NumMemRefs; 2834 } 2835 } 2836 2837 MachineSDNode::mmo_iterator MemRefs = 2838 MF->allocateMemRefsArray(NumMemRefs); 2839 2840 MachineSDNode::mmo_iterator MemRefsPos = MemRefs; 2841 for (SmallVector<MachineMemOperand*, 2>::const_iterator I = 2842 MatchedMemRefs.begin(), E = MatchedMemRefs.end(); I != E; ++I) { 2843 if ((*I)->isLoad()) { 2844 if (mayLoad) 2845 *MemRefsPos++ = *I; 2846 } else if ((*I)->isStore()) { 2847 if (mayStore) 2848 *MemRefsPos++ = *I; 2849 } else { 2850 *MemRefsPos++ = *I; 2851 } 2852 } 2853 2854 cast<MachineSDNode>(Res) 2855 ->setMemRefs(MemRefs, MemRefs + NumMemRefs); 2856 } 2857 2858 DEBUG(errs() << " " 2859 << (Opcode == OPC_MorphNodeTo ? "Morphed" : "Created") 2860 << " node: "; Res->dump(CurDAG); errs() << "\n"); 2861 2862 // If this was a MorphNodeTo then we're completely done! 2863 if (Opcode == OPC_MorphNodeTo) { 2864 // Update chain and glue uses. 2865 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2866 InputGlue, GlueResultNodesMatched, true); 2867 return Res; 2868 } 2869 2870 continue; 2871 } 2872 2873 case OPC_MarkGlueResults: { 2874 unsigned NumNodes = MatcherTable[MatcherIndex++]; 2875 2876 // Read and remember all the glue-result nodes. 2877 for (unsigned i = 0; i != NumNodes; ++i) { 2878 unsigned RecNo = MatcherTable[MatcherIndex++]; 2879 if (RecNo & 128) 2880 RecNo = GetVBR(RecNo, MatcherTable, MatcherIndex); 2881 2882 assert(RecNo < RecordedNodes.size() && "Invalid CheckSame"); 2883 GlueResultNodesMatched.push_back(RecordedNodes[RecNo].first.getNode()); 2884 } 2885 continue; 2886 } 2887 2888 case OPC_CompleteMatch: { 2889 // The match has been completed, and any new nodes (if any) have been 2890 // created. Patch up references to the matched dag to use the newly 2891 // created nodes. 2892 unsigned NumResults = MatcherTable[MatcherIndex++]; 2893 2894 for (unsigned i = 0; i != NumResults; ++i) { 2895 unsigned ResSlot = MatcherTable[MatcherIndex++]; 2896 if (ResSlot & 128) 2897 ResSlot = GetVBR(ResSlot, MatcherTable, MatcherIndex); 2898 2899 assert(ResSlot < RecordedNodes.size() && "Invalid CheckSame"); 2900 SDValue Res = RecordedNodes[ResSlot].first; 2901 2902 assert(i < NodeToMatch->getNumValues() && 2903 NodeToMatch->getValueType(i) != MVT::Other && 2904 NodeToMatch->getValueType(i) != MVT::Glue && 2905 "Invalid number of results to complete!"); 2906 assert((NodeToMatch->getValueType(i) == Res.getValueType() || 2907 NodeToMatch->getValueType(i) == MVT::iPTR || 2908 Res.getValueType() == MVT::iPTR || 2909 NodeToMatch->getValueType(i).getSizeInBits() == 2910 Res.getValueType().getSizeInBits()) && 2911 "invalid replacement"); 2912 CurDAG->ReplaceAllUsesOfValueWith(SDValue(NodeToMatch, i), Res); 2913 } 2914 2915 // If the root node defines glue, add it to the glue nodes to update list. 2916 if (NodeToMatch->getValueType(NodeToMatch->getNumValues()-1) == MVT::Glue) 2917 GlueResultNodesMatched.push_back(NodeToMatch); 2918 2919 // Update chain and glue uses. 2920 UpdateChainsAndGlue(NodeToMatch, InputChain, ChainNodesMatched, 2921 InputGlue, GlueResultNodesMatched, false); 2922 2923 assert(NodeToMatch->use_empty() && 2924 "Didn't replace all uses of the node?"); 2925 2926 // FIXME: We just return here, which interacts correctly with SelectRoot 2927 // above. We should fix this to not return an SDNode* anymore. 2928 return 0; 2929 } 2930 } 2931 2932 // If the code reached this point, then the match failed. See if there is 2933 // another child to try in the current 'Scope', otherwise pop it until we 2934 // find a case to check. 2935 DEBUG(errs() << " Match failed at index " << CurrentOpcodeIndex << "\n"); 2936 ++NumDAGIselRetries; 2937 while (1) { 2938 if (MatchScopes.empty()) { 2939 CannotYetSelect(NodeToMatch); 2940 return 0; 2941 } 2942 2943 // Restore the interpreter state back to the point where the scope was 2944 // formed. 2945 MatchScope &LastScope = MatchScopes.back(); 2946 RecordedNodes.resize(LastScope.NumRecordedNodes); 2947 NodeStack.clear(); 2948 NodeStack.append(LastScope.NodeStack.begin(), LastScope.NodeStack.end()); 2949 N = NodeStack.back(); 2950 2951 if (LastScope.NumMatchedMemRefs != MatchedMemRefs.size()) 2952 MatchedMemRefs.resize(LastScope.NumMatchedMemRefs); 2953 MatcherIndex = LastScope.FailIndex; 2954 2955 DEBUG(errs() << " Continuing at " << MatcherIndex << "\n"); 2956 2957 InputChain = LastScope.InputChain; 2958 InputGlue = LastScope.InputGlue; 2959 if (!LastScope.HasChainNodesMatched) 2960 ChainNodesMatched.clear(); 2961 if (!LastScope.HasGlueResultNodesMatched) 2962 GlueResultNodesMatched.clear(); 2963 2964 // Check to see what the offset is at the new MatcherIndex. If it is zero 2965 // we have reached the end of this scope, otherwise we have another child 2966 // in the current scope to try. 2967 unsigned NumToSkip = MatcherTable[MatcherIndex++]; 2968 if (NumToSkip & 128) 2969 NumToSkip = GetVBR(NumToSkip, MatcherTable, MatcherIndex); 2970 2971 // If we have another child in this scope to match, update FailIndex and 2972 // try it. 2973 if (NumToSkip != 0) { 2974 LastScope.FailIndex = MatcherIndex+NumToSkip; 2975 break; 2976 } 2977 2978 // End of this scope, pop it and try the next child in the containing 2979 // scope. 2980 MatchScopes.pop_back(); 2981 } 2982 } 2983 } 2984 2985 2986 2987 void SelectionDAGISel::CannotYetSelect(SDNode *N) { 2988 std::string msg; 2989 raw_string_ostream Msg(msg); 2990 Msg << "Cannot select: "; 2991 2992 if (N->getOpcode() != ISD::INTRINSIC_W_CHAIN && 2993 N->getOpcode() != ISD::INTRINSIC_WO_CHAIN && 2994 N->getOpcode() != ISD::INTRINSIC_VOID) { 2995 N->printrFull(Msg, CurDAG); 2996 Msg << "\nIn function: " << MF->getName(); 2997 } else { 2998 bool HasInputChain = N->getOperand(0).getValueType() == MVT::Other; 2999 unsigned iid = 3000 cast<ConstantSDNode>(N->getOperand(HasInputChain))->getZExtValue(); 3001 if (iid < Intrinsic::num_intrinsics) 3002 Msg << "intrinsic %" << Intrinsic::getName((Intrinsic::ID)iid); 3003 else if (const TargetIntrinsicInfo *TII = TM.getIntrinsicInfo()) 3004 Msg << "target intrinsic %" << TII->getName(iid); 3005 else 3006 Msg << "unknown intrinsic #" << iid; 3007 } 3008 report_fatal_error(Msg.str()); 3009 } 3010 3011 char SelectionDAGISel::ID = 0; 3012