1 // Copyright 2015, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_AARCH64_CONSTANTS_AARCH64_H_ 28 #define VIXL_AARCH64_CONSTANTS_AARCH64_H_ 29 30 #include "../globals-vixl.h" 31 32 namespace vixl { 33 namespace aarch64 { 34 35 const unsigned kNumberOfRegisters = 32; 36 const unsigned kNumberOfVRegisters = 32; 37 const unsigned kNumberOfFPRegisters = kNumberOfVRegisters; 38 // Callee saved registers are x21-x30(lr). 39 const int kNumberOfCalleeSavedRegisters = 10; 40 const int kFirstCalleeSavedRegisterIndex = 21; 41 // Callee saved FP registers are d8-d15. 42 const int kNumberOfCalleeSavedFPRegisters = 8; 43 const int kFirstCalleeSavedFPRegisterIndex = 8; 44 45 // clang-format off 46 #define AARCH64_REGISTER_CODE_LIST(R) \ 47 R(0) R(1) R(2) R(3) R(4) R(5) R(6) R(7) \ 48 R(8) R(9) R(10) R(11) R(12) R(13) R(14) R(15) \ 49 R(16) R(17) R(18) R(19) R(20) R(21) R(22) R(23) \ 50 R(24) R(25) R(26) R(27) R(28) R(29) R(30) R(31) 51 52 #define INSTRUCTION_FIELDS_LIST(V_) \ 53 /* Register fields */ \ 54 V_(Rd, 4, 0, ExtractBits) /* Destination register. */ \ 55 V_(Rn, 9, 5, ExtractBits) /* First source register. */ \ 56 V_(Rm, 20, 16, ExtractBits) /* Second source register. */ \ 57 V_(Ra, 14, 10, ExtractBits) /* Third source register. */ \ 58 V_(Rt, 4, 0, ExtractBits) /* Load/store register. */ \ 59 V_(Rt2, 14, 10, ExtractBits) /* Load/store second register. */ \ 60 V_(Rs, 20, 16, ExtractBits) /* Exclusive access status. */ \ 61 \ 62 /* Common bits */ \ 63 V_(SixtyFourBits, 31, 31, ExtractBits) \ 64 V_(FlagsUpdate, 29, 29, ExtractBits) \ 65 \ 66 /* PC relative addressing */ \ 67 V_(ImmPCRelHi, 23, 5, ExtractSignedBits) \ 68 V_(ImmPCRelLo, 30, 29, ExtractBits) \ 69 \ 70 /* Add/subtract/logical shift register */ \ 71 V_(ShiftDP, 23, 22, ExtractBits) \ 72 V_(ImmDPShift, 15, 10, ExtractBits) \ 73 \ 74 /* Add/subtract immediate */ \ 75 V_(ImmAddSub, 21, 10, ExtractBits) \ 76 V_(ShiftAddSub, 23, 22, ExtractBits) \ 77 \ 78 /* Add/substract extend */ \ 79 V_(ImmExtendShift, 12, 10, ExtractBits) \ 80 V_(ExtendMode, 15, 13, ExtractBits) \ 81 \ 82 /* Move wide */ \ 83 V_(ImmMoveWide, 20, 5, ExtractBits) \ 84 V_(ShiftMoveWide, 22, 21, ExtractBits) \ 85 \ 86 /* Logical immediate, bitfield and extract */ \ 87 V_(BitN, 22, 22, ExtractBits) \ 88 V_(ImmRotate, 21, 16, ExtractBits) \ 89 V_(ImmSetBits, 15, 10, ExtractBits) \ 90 V_(ImmR, 21, 16, ExtractBits) \ 91 V_(ImmS, 15, 10, ExtractBits) \ 92 \ 93 /* Test and branch immediate */ \ 94 V_(ImmTestBranch, 18, 5, ExtractSignedBits) \ 95 V_(ImmTestBranchBit40, 23, 19, ExtractBits) \ 96 V_(ImmTestBranchBit5, 31, 31, ExtractBits) \ 97 \ 98 /* Conditionals */ \ 99 V_(Condition, 15, 12, ExtractBits) \ 100 V_(ConditionBranch, 3, 0, ExtractBits) \ 101 V_(Nzcv, 3, 0, ExtractBits) \ 102 V_(ImmCondCmp, 20, 16, ExtractBits) \ 103 V_(ImmCondBranch, 23, 5, ExtractSignedBits) \ 104 \ 105 /* Floating point */ \ 106 V_(FPType, 23, 22, ExtractBits) \ 107 V_(ImmFP, 20, 13, ExtractBits) \ 108 V_(FPScale, 15, 10, ExtractBits) \ 109 \ 110 /* Load Store */ \ 111 V_(ImmLS, 20, 12, ExtractSignedBits) \ 112 V_(ImmLSUnsigned, 21, 10, ExtractBits) \ 113 V_(ImmLSPair, 21, 15, ExtractSignedBits) \ 114 V_(ImmShiftLS, 12, 12, ExtractBits) \ 115 V_(LSOpc, 23, 22, ExtractBits) \ 116 V_(LSVector, 26, 26, ExtractBits) \ 117 V_(LSSize, 31, 30, ExtractBits) \ 118 V_(ImmPrefetchOperation, 4, 0, ExtractBits) \ 119 V_(PrefetchHint, 4, 3, ExtractBits) \ 120 V_(PrefetchTarget, 2, 1, ExtractBits) \ 121 V_(PrefetchStream, 0, 0, ExtractBits) \ 122 \ 123 /* Other immediates */ \ 124 V_(ImmUncondBranch, 25, 0, ExtractSignedBits) \ 125 V_(ImmCmpBranch, 23, 5, ExtractSignedBits) \ 126 V_(ImmLLiteral, 23, 5, ExtractSignedBits) \ 127 V_(ImmException, 20, 5, ExtractBits) \ 128 V_(ImmHint, 11, 5, ExtractBits) \ 129 V_(ImmBarrierDomain, 11, 10, ExtractBits) \ 130 V_(ImmBarrierType, 9, 8, ExtractBits) \ 131 \ 132 /* System (MRS, MSR, SYS) */ \ 133 V_(ImmSystemRegister, 19, 5, ExtractBits) \ 134 V_(SysO0, 19, 19, ExtractBits) \ 135 V_(SysOp, 18, 5, ExtractBits) \ 136 V_(SysOp1, 18, 16, ExtractBits) \ 137 V_(SysOp2, 7, 5, ExtractBits) \ 138 V_(CRn, 15, 12, ExtractBits) \ 139 V_(CRm, 11, 8, ExtractBits) \ 140 \ 141 /* Load-/store-exclusive */ \ 142 V_(LdStXLoad, 22, 22, ExtractBits) \ 143 V_(LdStXNotExclusive, 23, 23, ExtractBits) \ 144 V_(LdStXAcquireRelease, 15, 15, ExtractBits) \ 145 V_(LdStXSizeLog2, 31, 30, ExtractBits) \ 146 V_(LdStXPair, 21, 21, ExtractBits) \ 147 \ 148 /* NEON generic fields */ \ 149 V_(NEONQ, 30, 30, ExtractBits) \ 150 V_(NEONSize, 23, 22, ExtractBits) \ 151 V_(NEONLSSize, 11, 10, ExtractBits) \ 152 V_(NEONS, 12, 12, ExtractBits) \ 153 V_(NEONL, 21, 21, ExtractBits) \ 154 V_(NEONM, 20, 20, ExtractBits) \ 155 V_(NEONH, 11, 11, ExtractBits) \ 156 V_(ImmNEONExt, 14, 11, ExtractBits) \ 157 V_(ImmNEON5, 20, 16, ExtractBits) \ 158 V_(ImmNEON4, 14, 11, ExtractBits) \ 159 \ 160 /* NEON Modified Immediate fields */ \ 161 V_(ImmNEONabc, 18, 16, ExtractBits) \ 162 V_(ImmNEONdefgh, 9, 5, ExtractBits) \ 163 V_(NEONModImmOp, 29, 29, ExtractBits) \ 164 V_(NEONCmode, 15, 12, ExtractBits) \ 165 \ 166 /* NEON Shift Immediate fields */ \ 167 V_(ImmNEONImmhImmb, 22, 16, ExtractBits) \ 168 V_(ImmNEONImmh, 22, 19, ExtractBits) \ 169 V_(ImmNEONImmb, 18, 16, ExtractBits) 170 // clang-format on 171 172 #define SYSTEM_REGISTER_FIELDS_LIST(V_, M_) \ 173 /* NZCV */ \ 174 V_(Flags, 31, 28, ExtractBits) \ 175 V_(N, 31, 31, ExtractBits) \ 176 V_(Z, 30, 30, ExtractBits) \ 177 V_(C, 29, 29, ExtractBits) \ 178 V_(V, 28, 28, ExtractBits) \ 179 M_(NZCV, Flags_mask) \ 180 /* FPCR */ \ 181 V_(AHP, 26, 26, ExtractBits) \ 182 V_(DN, 25, 25, ExtractBits) \ 183 V_(FZ, 24, 24, ExtractBits) \ 184 V_(RMode, 23, 22, ExtractBits) \ 185 M_(FPCR, AHP_mask | DN_mask | FZ_mask | RMode_mask) 186 187 // Fields offsets. 188 #define DECLARE_FIELDS_OFFSETS(Name, HighBit, LowBit, X) \ 189 const int Name##_offset = LowBit; \ 190 const int Name##_width = HighBit - LowBit + 1; \ 191 const uint32_t Name##_mask = ((1 << Name##_width) - 1) << LowBit; 192 #define NOTHING(A, B) 193 INSTRUCTION_FIELDS_LIST(DECLARE_FIELDS_OFFSETS) 194 SYSTEM_REGISTER_FIELDS_LIST(DECLARE_FIELDS_OFFSETS, NOTHING) 195 #undef NOTHING 196 #undef DECLARE_FIELDS_BITS 197 198 // ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST), formed 199 // from ImmPCRelLo and ImmPCRelHi. 200 const int ImmPCRel_mask = ImmPCRelLo_mask | ImmPCRelHi_mask; 201 202 // Disable `clang-format` for the `enum`s below. We care about the manual 203 // formatting that `clang-format` would destroy. 204 // clang-format off 205 206 // Condition codes. 207 enum Condition { 208 eq = 0, // Z set Equal. 209 ne = 1, // Z clear Not equal. 210 cs = 2, // C set Carry set. 211 cc = 3, // C clear Carry clear. 212 mi = 4, // N set Negative. 213 pl = 5, // N clear Positive or zero. 214 vs = 6, // V set Overflow. 215 vc = 7, // V clear No overflow. 216 hi = 8, // C set, Z clear Unsigned higher. 217 ls = 9, // C clear or Z set Unsigned lower or same. 218 ge = 10, // N == V Greater or equal. 219 lt = 11, // N != V Less than. 220 gt = 12, // Z clear, N == V Greater than. 221 le = 13, // Z set or N != V Less then or equal 222 al = 14, // Always. 223 nv = 15, // Behaves as always/al. 224 225 // Aliases. 226 hs = cs, // C set Unsigned higher or same. 227 lo = cc // C clear Unsigned lower. 228 }; 229 230 inline Condition InvertCondition(Condition cond) { 231 // Conditions al and nv behave identically, as "always true". They can't be 232 // inverted, because there is no "always false" condition. 233 VIXL_ASSERT((cond != al) && (cond != nv)); 234 return static_cast<Condition>(cond ^ 1); 235 } 236 237 enum FPTrapFlags { 238 EnableTrap = 1, 239 DisableTrap = 0 240 }; 241 242 enum FlagsUpdate { 243 SetFlags = 1, 244 LeaveFlags = 0 245 }; 246 247 enum StatusFlags { 248 NoFlag = 0, 249 250 // Derive the flag combinations from the system register bit descriptions. 251 NFlag = N_mask, 252 ZFlag = Z_mask, 253 CFlag = C_mask, 254 VFlag = V_mask, 255 NZFlag = NFlag | ZFlag, 256 NCFlag = NFlag | CFlag, 257 NVFlag = NFlag | VFlag, 258 ZCFlag = ZFlag | CFlag, 259 ZVFlag = ZFlag | VFlag, 260 CVFlag = CFlag | VFlag, 261 NZCFlag = NFlag | ZFlag | CFlag, 262 NZVFlag = NFlag | ZFlag | VFlag, 263 NCVFlag = NFlag | CFlag | VFlag, 264 ZCVFlag = ZFlag | CFlag | VFlag, 265 NZCVFlag = NFlag | ZFlag | CFlag | VFlag, 266 267 // Floating-point comparison results. 268 FPEqualFlag = ZCFlag, 269 FPLessThanFlag = NFlag, 270 FPGreaterThanFlag = CFlag, 271 FPUnorderedFlag = CVFlag 272 }; 273 274 enum Shift { 275 NO_SHIFT = -1, 276 LSL = 0x0, 277 LSR = 0x1, 278 ASR = 0x2, 279 ROR = 0x3, 280 MSL = 0x4 281 }; 282 283 enum Extend { 284 NO_EXTEND = -1, 285 UXTB = 0, 286 UXTH = 1, 287 UXTW = 2, 288 UXTX = 3, 289 SXTB = 4, 290 SXTH = 5, 291 SXTW = 6, 292 SXTX = 7 293 }; 294 295 enum SystemHint { 296 NOP = 0, 297 YIELD = 1, 298 WFE = 2, 299 WFI = 3, 300 SEV = 4, 301 SEVL = 5 302 }; 303 304 enum BarrierDomain { 305 OuterShareable = 0, 306 NonShareable = 1, 307 InnerShareable = 2, 308 FullSystem = 3 309 }; 310 311 enum BarrierType { 312 BarrierOther = 0, 313 BarrierReads = 1, 314 BarrierWrites = 2, 315 BarrierAll = 3 316 }; 317 318 enum PrefetchOperation { 319 PLDL1KEEP = 0x00, 320 PLDL1STRM = 0x01, 321 PLDL2KEEP = 0x02, 322 PLDL2STRM = 0x03, 323 PLDL3KEEP = 0x04, 324 PLDL3STRM = 0x05, 325 326 PLIL1KEEP = 0x08, 327 PLIL1STRM = 0x09, 328 PLIL2KEEP = 0x0a, 329 PLIL2STRM = 0x0b, 330 PLIL3KEEP = 0x0c, 331 PLIL3STRM = 0x0d, 332 333 PSTL1KEEP = 0x10, 334 PSTL1STRM = 0x11, 335 PSTL2KEEP = 0x12, 336 PSTL2STRM = 0x13, 337 PSTL3KEEP = 0x14, 338 PSTL3STRM = 0x15 339 }; 340 341 // System/special register names. 342 // This information is not encoded as one field but as the concatenation of 343 // multiple fields (Op0<0>, Op1, Crn, Crm, Op2). 344 enum SystemRegister { 345 NZCV = ((0x1 << SysO0_offset) | 346 (0x3 << SysOp1_offset) | 347 (0x4 << CRn_offset) | 348 (0x2 << CRm_offset) | 349 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset, 350 FPCR = ((0x1 << SysO0_offset) | 351 (0x3 << SysOp1_offset) | 352 (0x4 << CRn_offset) | 353 (0x4 << CRm_offset) | 354 (0x0 << SysOp2_offset)) >> ImmSystemRegister_offset 355 }; 356 357 enum InstructionCacheOp { 358 IVAU = ((0x3 << SysOp1_offset) | 359 (0x7 << CRn_offset) | 360 (0x5 << CRm_offset) | 361 (0x1 << SysOp2_offset)) >> SysOp_offset 362 }; 363 364 enum DataCacheOp { 365 CVAC = ((0x3 << SysOp1_offset) | 366 (0x7 << CRn_offset) | 367 (0xa << CRm_offset) | 368 (0x1 << SysOp2_offset)) >> SysOp_offset, 369 CVAU = ((0x3 << SysOp1_offset) | 370 (0x7 << CRn_offset) | 371 (0xb << CRm_offset) | 372 (0x1 << SysOp2_offset)) >> SysOp_offset, 373 CIVAC = ((0x3 << SysOp1_offset) | 374 (0x7 << CRn_offset) | 375 (0xe << CRm_offset) | 376 (0x1 << SysOp2_offset)) >> SysOp_offset, 377 ZVA = ((0x3 << SysOp1_offset) | 378 (0x7 << CRn_offset) | 379 (0x4 << CRm_offset) | 380 (0x1 << SysOp2_offset)) >> SysOp_offset 381 }; 382 383 // Instruction enumerations. 384 // 385 // These are the masks that define a class of instructions, and the list of 386 // instructions within each class. Each enumeration has a Fixed, FMask and 387 // Mask value. 388 // 389 // Fixed: The fixed bits in this instruction class. 390 // FMask: The mask used to extract the fixed bits in the class. 391 // Mask: The mask used to identify the instructions within a class. 392 // 393 // The enumerations can be used like this: 394 // 395 // VIXL_ASSERT(instr->Mask(PCRelAddressingFMask) == PCRelAddressingFixed); 396 // switch(instr->Mask(PCRelAddressingMask)) { 397 // case ADR: Format("adr 'Xd, 'AddrPCRelByte"); break; 398 // case ADRP: Format("adrp 'Xd, 'AddrPCRelPage"); break; 399 // default: printf("Unknown instruction\n"); 400 // } 401 402 403 // Generic fields. 404 enum GenericInstrField { 405 SixtyFourBits = 0x80000000, 406 ThirtyTwoBits = 0x00000000, 407 FP32 = 0x00000000, 408 FP64 = 0x00400000 409 }; 410 411 enum NEONFormatField { 412 NEONFormatFieldMask = 0x40C00000, 413 NEON_Q = 0x40000000, 414 NEON_8B = 0x00000000, 415 NEON_16B = NEON_8B | NEON_Q, 416 NEON_4H = 0x00400000, 417 NEON_8H = NEON_4H | NEON_Q, 418 NEON_2S = 0x00800000, 419 NEON_4S = NEON_2S | NEON_Q, 420 NEON_1D = 0x00C00000, 421 NEON_2D = 0x00C00000 | NEON_Q 422 }; 423 424 enum NEONFPFormatField { 425 NEONFPFormatFieldMask = 0x40400000, 426 NEON_FP_2S = FP32, 427 NEON_FP_4S = FP32 | NEON_Q, 428 NEON_FP_2D = FP64 | NEON_Q 429 }; 430 431 enum NEONLSFormatField { 432 NEONLSFormatFieldMask = 0x40000C00, 433 LS_NEON_8B = 0x00000000, 434 LS_NEON_16B = LS_NEON_8B | NEON_Q, 435 LS_NEON_4H = 0x00000400, 436 LS_NEON_8H = LS_NEON_4H | NEON_Q, 437 LS_NEON_2S = 0x00000800, 438 LS_NEON_4S = LS_NEON_2S | NEON_Q, 439 LS_NEON_1D = 0x00000C00, 440 LS_NEON_2D = LS_NEON_1D | NEON_Q 441 }; 442 443 enum NEONScalarFormatField { 444 NEONScalarFormatFieldMask = 0x00C00000, 445 NEONScalar = 0x10000000, 446 NEON_B = 0x00000000, 447 NEON_H = 0x00400000, 448 NEON_S = 0x00800000, 449 NEON_D = 0x00C00000 450 }; 451 452 // PC relative addressing. 453 enum PCRelAddressingOp { 454 PCRelAddressingFixed = 0x10000000, 455 PCRelAddressingFMask = 0x1F000000, 456 PCRelAddressingMask = 0x9F000000, 457 ADR = PCRelAddressingFixed | 0x00000000, 458 ADRP = PCRelAddressingFixed | 0x80000000 459 }; 460 461 // Add/sub (immediate, shifted and extended.) 462 const int kSFOffset = 31; 463 enum AddSubOp { 464 AddSubOpMask = 0x60000000, 465 AddSubSetFlagsBit = 0x20000000, 466 ADD = 0x00000000, 467 ADDS = ADD | AddSubSetFlagsBit, 468 SUB = 0x40000000, 469 SUBS = SUB | AddSubSetFlagsBit 470 }; 471 472 #define ADD_SUB_OP_LIST(V) \ 473 V(ADD), \ 474 V(ADDS), \ 475 V(SUB), \ 476 V(SUBS) 477 478 enum AddSubImmediateOp { 479 AddSubImmediateFixed = 0x11000000, 480 AddSubImmediateFMask = 0x1F000000, 481 AddSubImmediateMask = 0xFF000000, 482 #define ADD_SUB_IMMEDIATE(A) \ 483 A##_w_imm = AddSubImmediateFixed | A, \ 484 A##_x_imm = AddSubImmediateFixed | A | SixtyFourBits 485 ADD_SUB_OP_LIST(ADD_SUB_IMMEDIATE) 486 #undef ADD_SUB_IMMEDIATE 487 }; 488 489 enum AddSubShiftedOp { 490 AddSubShiftedFixed = 0x0B000000, 491 AddSubShiftedFMask = 0x1F200000, 492 AddSubShiftedMask = 0xFF200000, 493 #define ADD_SUB_SHIFTED(A) \ 494 A##_w_shift = AddSubShiftedFixed | A, \ 495 A##_x_shift = AddSubShiftedFixed | A | SixtyFourBits 496 ADD_SUB_OP_LIST(ADD_SUB_SHIFTED) 497 #undef ADD_SUB_SHIFTED 498 }; 499 500 enum AddSubExtendedOp { 501 AddSubExtendedFixed = 0x0B200000, 502 AddSubExtendedFMask = 0x1F200000, 503 AddSubExtendedMask = 0xFFE00000, 504 #define ADD_SUB_EXTENDED(A) \ 505 A##_w_ext = AddSubExtendedFixed | A, \ 506 A##_x_ext = AddSubExtendedFixed | A | SixtyFourBits 507 ADD_SUB_OP_LIST(ADD_SUB_EXTENDED) 508 #undef ADD_SUB_EXTENDED 509 }; 510 511 // Add/sub with carry. 512 enum AddSubWithCarryOp { 513 AddSubWithCarryFixed = 0x1A000000, 514 AddSubWithCarryFMask = 0x1FE00000, 515 AddSubWithCarryMask = 0xFFE0FC00, 516 ADC_w = AddSubWithCarryFixed | ADD, 517 ADC_x = AddSubWithCarryFixed | ADD | SixtyFourBits, 518 ADC = ADC_w, 519 ADCS_w = AddSubWithCarryFixed | ADDS, 520 ADCS_x = AddSubWithCarryFixed | ADDS | SixtyFourBits, 521 SBC_w = AddSubWithCarryFixed | SUB, 522 SBC_x = AddSubWithCarryFixed | SUB | SixtyFourBits, 523 SBC = SBC_w, 524 SBCS_w = AddSubWithCarryFixed | SUBS, 525 SBCS_x = AddSubWithCarryFixed | SUBS | SixtyFourBits 526 }; 527 528 529 // Logical (immediate and shifted register). 530 enum LogicalOp { 531 LogicalOpMask = 0x60200000, 532 NOT = 0x00200000, 533 AND = 0x00000000, 534 BIC = AND | NOT, 535 ORR = 0x20000000, 536 ORN = ORR | NOT, 537 EOR = 0x40000000, 538 EON = EOR | NOT, 539 ANDS = 0x60000000, 540 BICS = ANDS | NOT 541 }; 542 543 // Logical immediate. 544 enum LogicalImmediateOp { 545 LogicalImmediateFixed = 0x12000000, 546 LogicalImmediateFMask = 0x1F800000, 547 LogicalImmediateMask = 0xFF800000, 548 AND_w_imm = LogicalImmediateFixed | AND, 549 AND_x_imm = LogicalImmediateFixed | AND | SixtyFourBits, 550 ORR_w_imm = LogicalImmediateFixed | ORR, 551 ORR_x_imm = LogicalImmediateFixed | ORR | SixtyFourBits, 552 EOR_w_imm = LogicalImmediateFixed | EOR, 553 EOR_x_imm = LogicalImmediateFixed | EOR | SixtyFourBits, 554 ANDS_w_imm = LogicalImmediateFixed | ANDS, 555 ANDS_x_imm = LogicalImmediateFixed | ANDS | SixtyFourBits 556 }; 557 558 // Logical shifted register. 559 enum LogicalShiftedOp { 560 LogicalShiftedFixed = 0x0A000000, 561 LogicalShiftedFMask = 0x1F000000, 562 LogicalShiftedMask = 0xFF200000, 563 AND_w = LogicalShiftedFixed | AND, 564 AND_x = LogicalShiftedFixed | AND | SixtyFourBits, 565 AND_shift = AND_w, 566 BIC_w = LogicalShiftedFixed | BIC, 567 BIC_x = LogicalShiftedFixed | BIC | SixtyFourBits, 568 BIC_shift = BIC_w, 569 ORR_w = LogicalShiftedFixed | ORR, 570 ORR_x = LogicalShiftedFixed | ORR | SixtyFourBits, 571 ORR_shift = ORR_w, 572 ORN_w = LogicalShiftedFixed | ORN, 573 ORN_x = LogicalShiftedFixed | ORN | SixtyFourBits, 574 ORN_shift = ORN_w, 575 EOR_w = LogicalShiftedFixed | EOR, 576 EOR_x = LogicalShiftedFixed | EOR | SixtyFourBits, 577 EOR_shift = EOR_w, 578 EON_w = LogicalShiftedFixed | EON, 579 EON_x = LogicalShiftedFixed | EON | SixtyFourBits, 580 EON_shift = EON_w, 581 ANDS_w = LogicalShiftedFixed | ANDS, 582 ANDS_x = LogicalShiftedFixed | ANDS | SixtyFourBits, 583 ANDS_shift = ANDS_w, 584 BICS_w = LogicalShiftedFixed | BICS, 585 BICS_x = LogicalShiftedFixed | BICS | SixtyFourBits, 586 BICS_shift = BICS_w 587 }; 588 589 // Move wide immediate. 590 enum MoveWideImmediateOp { 591 MoveWideImmediateFixed = 0x12800000, 592 MoveWideImmediateFMask = 0x1F800000, 593 MoveWideImmediateMask = 0xFF800000, 594 MOVN = 0x00000000, 595 MOVZ = 0x40000000, 596 MOVK = 0x60000000, 597 MOVN_w = MoveWideImmediateFixed | MOVN, 598 MOVN_x = MoveWideImmediateFixed | MOVN | SixtyFourBits, 599 MOVZ_w = MoveWideImmediateFixed | MOVZ, 600 MOVZ_x = MoveWideImmediateFixed | MOVZ | SixtyFourBits, 601 MOVK_w = MoveWideImmediateFixed | MOVK, 602 MOVK_x = MoveWideImmediateFixed | MOVK | SixtyFourBits 603 }; 604 605 // Bitfield. 606 const int kBitfieldNOffset = 22; 607 enum BitfieldOp { 608 BitfieldFixed = 0x13000000, 609 BitfieldFMask = 0x1F800000, 610 BitfieldMask = 0xFF800000, 611 SBFM_w = BitfieldFixed | 0x00000000, 612 SBFM_x = BitfieldFixed | 0x80000000, 613 SBFM = SBFM_w, 614 BFM_w = BitfieldFixed | 0x20000000, 615 BFM_x = BitfieldFixed | 0xA0000000, 616 BFM = BFM_w, 617 UBFM_w = BitfieldFixed | 0x40000000, 618 UBFM_x = BitfieldFixed | 0xC0000000, 619 UBFM = UBFM_w 620 // Bitfield N field. 621 }; 622 623 // Extract. 624 enum ExtractOp { 625 ExtractFixed = 0x13800000, 626 ExtractFMask = 0x1F800000, 627 ExtractMask = 0xFFA00000, 628 EXTR_w = ExtractFixed | 0x00000000, 629 EXTR_x = ExtractFixed | 0x80000000, 630 EXTR = EXTR_w 631 }; 632 633 // Unconditional branch. 634 enum UnconditionalBranchOp { 635 UnconditionalBranchFixed = 0x14000000, 636 UnconditionalBranchFMask = 0x7C000000, 637 UnconditionalBranchMask = 0xFC000000, 638 B = UnconditionalBranchFixed | 0x00000000, 639 BL = UnconditionalBranchFixed | 0x80000000 640 }; 641 642 // Unconditional branch to register. 643 enum UnconditionalBranchToRegisterOp { 644 UnconditionalBranchToRegisterFixed = 0xD6000000, 645 UnconditionalBranchToRegisterFMask = 0xFE000000, 646 UnconditionalBranchToRegisterMask = 0xFFFFFC1F, 647 BR = UnconditionalBranchToRegisterFixed | 0x001F0000, 648 BLR = UnconditionalBranchToRegisterFixed | 0x003F0000, 649 RET = UnconditionalBranchToRegisterFixed | 0x005F0000 650 }; 651 652 // Compare and branch. 653 enum CompareBranchOp { 654 CompareBranchFixed = 0x34000000, 655 CompareBranchFMask = 0x7E000000, 656 CompareBranchMask = 0xFF000000, 657 CBZ_w = CompareBranchFixed | 0x00000000, 658 CBZ_x = CompareBranchFixed | 0x80000000, 659 CBZ = CBZ_w, 660 CBNZ_w = CompareBranchFixed | 0x01000000, 661 CBNZ_x = CompareBranchFixed | 0x81000000, 662 CBNZ = CBNZ_w 663 }; 664 665 // Test and branch. 666 enum TestBranchOp { 667 TestBranchFixed = 0x36000000, 668 TestBranchFMask = 0x7E000000, 669 TestBranchMask = 0x7F000000, 670 TBZ = TestBranchFixed | 0x00000000, 671 TBNZ = TestBranchFixed | 0x01000000 672 }; 673 674 // Conditional branch. 675 enum ConditionalBranchOp { 676 ConditionalBranchFixed = 0x54000000, 677 ConditionalBranchFMask = 0xFE000000, 678 ConditionalBranchMask = 0xFF000010, 679 B_cond = ConditionalBranchFixed | 0x00000000 680 }; 681 682 // System. 683 // System instruction encoding is complicated because some instructions use op 684 // and CR fields to encode parameters. To handle this cleanly, the system 685 // instructions are split into more than one enum. 686 687 enum SystemOp { 688 SystemFixed = 0xD5000000, 689 SystemFMask = 0xFFC00000 690 }; 691 692 enum SystemSysRegOp { 693 SystemSysRegFixed = 0xD5100000, 694 SystemSysRegFMask = 0xFFD00000, 695 SystemSysRegMask = 0xFFF00000, 696 MRS = SystemSysRegFixed | 0x00200000, 697 MSR = SystemSysRegFixed | 0x00000000 698 }; 699 700 enum SystemHintOp { 701 SystemHintFixed = 0xD503201F, 702 SystemHintFMask = 0xFFFFF01F, 703 SystemHintMask = 0xFFFFF01F, 704 HINT = SystemHintFixed | 0x00000000 705 }; 706 707 enum SystemSysOp { 708 SystemSysFixed = 0xD5080000, 709 SystemSysFMask = 0xFFF80000, 710 SystemSysMask = 0xFFF80000, 711 SYS = SystemSysFixed | 0x00000000 712 }; 713 714 // Exception. 715 enum ExceptionOp { 716 ExceptionFixed = 0xD4000000, 717 ExceptionFMask = 0xFF000000, 718 ExceptionMask = 0xFFE0001F, 719 HLT = ExceptionFixed | 0x00400000, 720 BRK = ExceptionFixed | 0x00200000, 721 SVC = ExceptionFixed | 0x00000001, 722 HVC = ExceptionFixed | 0x00000002, 723 SMC = ExceptionFixed | 0x00000003, 724 DCPS1 = ExceptionFixed | 0x00A00001, 725 DCPS2 = ExceptionFixed | 0x00A00002, 726 DCPS3 = ExceptionFixed | 0x00A00003 727 }; 728 729 enum MemBarrierOp { 730 MemBarrierFixed = 0xD503309F, 731 MemBarrierFMask = 0xFFFFF09F, 732 MemBarrierMask = 0xFFFFF0FF, 733 DSB = MemBarrierFixed | 0x00000000, 734 DMB = MemBarrierFixed | 0x00000020, 735 ISB = MemBarrierFixed | 0x00000040 736 }; 737 738 enum SystemExclusiveMonitorOp { 739 SystemExclusiveMonitorFixed = 0xD503305F, 740 SystemExclusiveMonitorFMask = 0xFFFFF0FF, 741 SystemExclusiveMonitorMask = 0xFFFFF0FF, 742 CLREX = SystemExclusiveMonitorFixed 743 }; 744 745 // Any load or store. 746 enum LoadStoreAnyOp { 747 LoadStoreAnyFMask = 0x0a000000, 748 LoadStoreAnyFixed = 0x08000000 749 }; 750 751 // Any load pair or store pair. 752 enum LoadStorePairAnyOp { 753 LoadStorePairAnyFMask = 0x3a000000, 754 LoadStorePairAnyFixed = 0x28000000 755 }; 756 757 #define LOAD_STORE_PAIR_OP_LIST(V) \ 758 V(STP, w, 0x00000000), \ 759 V(LDP, w, 0x00400000), \ 760 V(LDPSW, x, 0x40400000), \ 761 V(STP, x, 0x80000000), \ 762 V(LDP, x, 0x80400000), \ 763 V(STP, s, 0x04000000), \ 764 V(LDP, s, 0x04400000), \ 765 V(STP, d, 0x44000000), \ 766 V(LDP, d, 0x44400000), \ 767 V(STP, q, 0x84000000), \ 768 V(LDP, q, 0x84400000) 769 770 // Load/store pair (post, pre and offset.) 771 enum LoadStorePairOp { 772 LoadStorePairMask = 0xC4400000, 773 LoadStorePairLBit = 1 << 22, 774 #define LOAD_STORE_PAIR(A, B, C) \ 775 A##_##B = C 776 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR) 777 #undef LOAD_STORE_PAIR 778 }; 779 780 enum LoadStorePairPostIndexOp { 781 LoadStorePairPostIndexFixed = 0x28800000, 782 LoadStorePairPostIndexFMask = 0x3B800000, 783 LoadStorePairPostIndexMask = 0xFFC00000, 784 #define LOAD_STORE_PAIR_POST_INDEX(A, B, C) \ 785 A##_##B##_post = LoadStorePairPostIndexFixed | A##_##B 786 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_POST_INDEX) 787 #undef LOAD_STORE_PAIR_POST_INDEX 788 }; 789 790 enum LoadStorePairPreIndexOp { 791 LoadStorePairPreIndexFixed = 0x29800000, 792 LoadStorePairPreIndexFMask = 0x3B800000, 793 LoadStorePairPreIndexMask = 0xFFC00000, 794 #define LOAD_STORE_PAIR_PRE_INDEX(A, B, C) \ 795 A##_##B##_pre = LoadStorePairPreIndexFixed | A##_##B 796 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_PRE_INDEX) 797 #undef LOAD_STORE_PAIR_PRE_INDEX 798 }; 799 800 enum LoadStorePairOffsetOp { 801 LoadStorePairOffsetFixed = 0x29000000, 802 LoadStorePairOffsetFMask = 0x3B800000, 803 LoadStorePairOffsetMask = 0xFFC00000, 804 #define LOAD_STORE_PAIR_OFFSET(A, B, C) \ 805 A##_##B##_off = LoadStorePairOffsetFixed | A##_##B 806 LOAD_STORE_PAIR_OP_LIST(LOAD_STORE_PAIR_OFFSET) 807 #undef LOAD_STORE_PAIR_OFFSET 808 }; 809 810 enum LoadStorePairNonTemporalOp { 811 LoadStorePairNonTemporalFixed = 0x28000000, 812 LoadStorePairNonTemporalFMask = 0x3B800000, 813 LoadStorePairNonTemporalMask = 0xFFC00000, 814 LoadStorePairNonTemporalLBit = 1 << 22, 815 STNP_w = LoadStorePairNonTemporalFixed | STP_w, 816 LDNP_w = LoadStorePairNonTemporalFixed | LDP_w, 817 STNP_x = LoadStorePairNonTemporalFixed | STP_x, 818 LDNP_x = LoadStorePairNonTemporalFixed | LDP_x, 819 STNP_s = LoadStorePairNonTemporalFixed | STP_s, 820 LDNP_s = LoadStorePairNonTemporalFixed | LDP_s, 821 STNP_d = LoadStorePairNonTemporalFixed | STP_d, 822 LDNP_d = LoadStorePairNonTemporalFixed | LDP_d, 823 STNP_q = LoadStorePairNonTemporalFixed | STP_q, 824 LDNP_q = LoadStorePairNonTemporalFixed | LDP_q 825 }; 826 827 // Load literal. 828 enum LoadLiteralOp { 829 LoadLiteralFixed = 0x18000000, 830 LoadLiteralFMask = 0x3B000000, 831 LoadLiteralMask = 0xFF000000, 832 LDR_w_lit = LoadLiteralFixed | 0x00000000, 833 LDR_x_lit = LoadLiteralFixed | 0x40000000, 834 LDRSW_x_lit = LoadLiteralFixed | 0x80000000, 835 PRFM_lit = LoadLiteralFixed | 0xC0000000, 836 LDR_s_lit = LoadLiteralFixed | 0x04000000, 837 LDR_d_lit = LoadLiteralFixed | 0x44000000, 838 LDR_q_lit = LoadLiteralFixed | 0x84000000 839 }; 840 841 #define LOAD_STORE_OP_LIST(V) \ 842 V(ST, RB, w, 0x00000000), \ 843 V(ST, RH, w, 0x40000000), \ 844 V(ST, R, w, 0x80000000), \ 845 V(ST, R, x, 0xC0000000), \ 846 V(LD, RB, w, 0x00400000), \ 847 V(LD, RH, w, 0x40400000), \ 848 V(LD, R, w, 0x80400000), \ 849 V(LD, R, x, 0xC0400000), \ 850 V(LD, RSB, x, 0x00800000), \ 851 V(LD, RSH, x, 0x40800000), \ 852 V(LD, RSW, x, 0x80800000), \ 853 V(LD, RSB, w, 0x00C00000), \ 854 V(LD, RSH, w, 0x40C00000), \ 855 V(ST, R, b, 0x04000000), \ 856 V(ST, R, h, 0x44000000), \ 857 V(ST, R, s, 0x84000000), \ 858 V(ST, R, d, 0xC4000000), \ 859 V(ST, R, q, 0x04800000), \ 860 V(LD, R, b, 0x04400000), \ 861 V(LD, R, h, 0x44400000), \ 862 V(LD, R, s, 0x84400000), \ 863 V(LD, R, d, 0xC4400000), \ 864 V(LD, R, q, 0x04C00000) 865 866 // Load/store (post, pre, offset and unsigned.) 867 enum LoadStoreOp { 868 LoadStoreMask = 0xC4C00000, 869 LoadStoreVMask = 0x04000000, 870 #define LOAD_STORE(A, B, C, D) \ 871 A##B##_##C = D 872 LOAD_STORE_OP_LIST(LOAD_STORE), 873 #undef LOAD_STORE 874 PRFM = 0xC0800000 875 }; 876 877 // Load/store unscaled offset. 878 enum LoadStoreUnscaledOffsetOp { 879 LoadStoreUnscaledOffsetFixed = 0x38000000, 880 LoadStoreUnscaledOffsetFMask = 0x3B200C00, 881 LoadStoreUnscaledOffsetMask = 0xFFE00C00, 882 PRFUM = LoadStoreUnscaledOffsetFixed | PRFM, 883 #define LOAD_STORE_UNSCALED(A, B, C, D) \ 884 A##U##B##_##C = LoadStoreUnscaledOffsetFixed | D 885 LOAD_STORE_OP_LIST(LOAD_STORE_UNSCALED) 886 #undef LOAD_STORE_UNSCALED 887 }; 888 889 // Load/store post index. 890 enum LoadStorePostIndex { 891 LoadStorePostIndexFixed = 0x38000400, 892 LoadStorePostIndexFMask = 0x3B200C00, 893 LoadStorePostIndexMask = 0xFFE00C00, 894 #define LOAD_STORE_POST_INDEX(A, B, C, D) \ 895 A##B##_##C##_post = LoadStorePostIndexFixed | D 896 LOAD_STORE_OP_LIST(LOAD_STORE_POST_INDEX) 897 #undef LOAD_STORE_POST_INDEX 898 }; 899 900 // Load/store pre index. 901 enum LoadStorePreIndex { 902 LoadStorePreIndexFixed = 0x38000C00, 903 LoadStorePreIndexFMask = 0x3B200C00, 904 LoadStorePreIndexMask = 0xFFE00C00, 905 #define LOAD_STORE_PRE_INDEX(A, B, C, D) \ 906 A##B##_##C##_pre = LoadStorePreIndexFixed | D 907 LOAD_STORE_OP_LIST(LOAD_STORE_PRE_INDEX) 908 #undef LOAD_STORE_PRE_INDEX 909 }; 910 911 // Load/store unsigned offset. 912 enum LoadStoreUnsignedOffset { 913 LoadStoreUnsignedOffsetFixed = 0x39000000, 914 LoadStoreUnsignedOffsetFMask = 0x3B000000, 915 LoadStoreUnsignedOffsetMask = 0xFFC00000, 916 PRFM_unsigned = LoadStoreUnsignedOffsetFixed | PRFM, 917 #define LOAD_STORE_UNSIGNED_OFFSET(A, B, C, D) \ 918 A##B##_##C##_unsigned = LoadStoreUnsignedOffsetFixed | D 919 LOAD_STORE_OP_LIST(LOAD_STORE_UNSIGNED_OFFSET) 920 #undef LOAD_STORE_UNSIGNED_OFFSET 921 }; 922 923 // Load/store register offset. 924 enum LoadStoreRegisterOffset { 925 LoadStoreRegisterOffsetFixed = 0x38200800, 926 LoadStoreRegisterOffsetFMask = 0x3B200C00, 927 LoadStoreRegisterOffsetMask = 0xFFE00C00, 928 PRFM_reg = LoadStoreRegisterOffsetFixed | PRFM, 929 #define LOAD_STORE_REGISTER_OFFSET(A, B, C, D) \ 930 A##B##_##C##_reg = LoadStoreRegisterOffsetFixed | D 931 LOAD_STORE_OP_LIST(LOAD_STORE_REGISTER_OFFSET) 932 #undef LOAD_STORE_REGISTER_OFFSET 933 }; 934 935 enum LoadStoreExclusive { 936 LoadStoreExclusiveFixed = 0x08000000, 937 LoadStoreExclusiveFMask = 0x3F000000, 938 LoadStoreExclusiveMask = 0xFFE08000, 939 STXRB_w = LoadStoreExclusiveFixed | 0x00000000, 940 STXRH_w = LoadStoreExclusiveFixed | 0x40000000, 941 STXR_w = LoadStoreExclusiveFixed | 0x80000000, 942 STXR_x = LoadStoreExclusiveFixed | 0xC0000000, 943 LDXRB_w = LoadStoreExclusiveFixed | 0x00400000, 944 LDXRH_w = LoadStoreExclusiveFixed | 0x40400000, 945 LDXR_w = LoadStoreExclusiveFixed | 0x80400000, 946 LDXR_x = LoadStoreExclusiveFixed | 0xC0400000, 947 STXP_w = LoadStoreExclusiveFixed | 0x80200000, 948 STXP_x = LoadStoreExclusiveFixed | 0xC0200000, 949 LDXP_w = LoadStoreExclusiveFixed | 0x80600000, 950 LDXP_x = LoadStoreExclusiveFixed | 0xC0600000, 951 STLXRB_w = LoadStoreExclusiveFixed | 0x00008000, 952 STLXRH_w = LoadStoreExclusiveFixed | 0x40008000, 953 STLXR_w = LoadStoreExclusiveFixed | 0x80008000, 954 STLXR_x = LoadStoreExclusiveFixed | 0xC0008000, 955 LDAXRB_w = LoadStoreExclusiveFixed | 0x00408000, 956 LDAXRH_w = LoadStoreExclusiveFixed | 0x40408000, 957 LDAXR_w = LoadStoreExclusiveFixed | 0x80408000, 958 LDAXR_x = LoadStoreExclusiveFixed | 0xC0408000, 959 STLXP_w = LoadStoreExclusiveFixed | 0x80208000, 960 STLXP_x = LoadStoreExclusiveFixed | 0xC0208000, 961 LDAXP_w = LoadStoreExclusiveFixed | 0x80608000, 962 LDAXP_x = LoadStoreExclusiveFixed | 0xC0608000, 963 STLRB_w = LoadStoreExclusiveFixed | 0x00808000, 964 STLRH_w = LoadStoreExclusiveFixed | 0x40808000, 965 STLR_w = LoadStoreExclusiveFixed | 0x80808000, 966 STLR_x = LoadStoreExclusiveFixed | 0xC0808000, 967 LDARB_w = LoadStoreExclusiveFixed | 0x00C08000, 968 LDARH_w = LoadStoreExclusiveFixed | 0x40C08000, 969 LDAR_w = LoadStoreExclusiveFixed | 0x80C08000, 970 LDAR_x = LoadStoreExclusiveFixed | 0xC0C08000 971 }; 972 973 // Conditional compare. 974 enum ConditionalCompareOp { 975 ConditionalCompareMask = 0x60000000, 976 CCMN = 0x20000000, 977 CCMP = 0x60000000 978 }; 979 980 // Conditional compare register. 981 enum ConditionalCompareRegisterOp { 982 ConditionalCompareRegisterFixed = 0x1A400000, 983 ConditionalCompareRegisterFMask = 0x1FE00800, 984 ConditionalCompareRegisterMask = 0xFFE00C10, 985 CCMN_w = ConditionalCompareRegisterFixed | CCMN, 986 CCMN_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMN, 987 CCMP_w = ConditionalCompareRegisterFixed | CCMP, 988 CCMP_x = ConditionalCompareRegisterFixed | SixtyFourBits | CCMP 989 }; 990 991 // Conditional compare immediate. 992 enum ConditionalCompareImmediateOp { 993 ConditionalCompareImmediateFixed = 0x1A400800, 994 ConditionalCompareImmediateFMask = 0x1FE00800, 995 ConditionalCompareImmediateMask = 0xFFE00C10, 996 CCMN_w_imm = ConditionalCompareImmediateFixed | CCMN, 997 CCMN_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMN, 998 CCMP_w_imm = ConditionalCompareImmediateFixed | CCMP, 999 CCMP_x_imm = ConditionalCompareImmediateFixed | SixtyFourBits | CCMP 1000 }; 1001 1002 // Conditional select. 1003 enum ConditionalSelectOp { 1004 ConditionalSelectFixed = 0x1A800000, 1005 ConditionalSelectFMask = 0x1FE00000, 1006 ConditionalSelectMask = 0xFFE00C00, 1007 CSEL_w = ConditionalSelectFixed | 0x00000000, 1008 CSEL_x = ConditionalSelectFixed | 0x80000000, 1009 CSEL = CSEL_w, 1010 CSINC_w = ConditionalSelectFixed | 0x00000400, 1011 CSINC_x = ConditionalSelectFixed | 0x80000400, 1012 CSINC = CSINC_w, 1013 CSINV_w = ConditionalSelectFixed | 0x40000000, 1014 CSINV_x = ConditionalSelectFixed | 0xC0000000, 1015 CSINV = CSINV_w, 1016 CSNEG_w = ConditionalSelectFixed | 0x40000400, 1017 CSNEG_x = ConditionalSelectFixed | 0xC0000400, 1018 CSNEG = CSNEG_w 1019 }; 1020 1021 // Data processing 1 source. 1022 enum DataProcessing1SourceOp { 1023 DataProcessing1SourceFixed = 0x5AC00000, 1024 DataProcessing1SourceFMask = 0x5FE00000, 1025 DataProcessing1SourceMask = 0xFFFFFC00, 1026 RBIT = DataProcessing1SourceFixed | 0x00000000, 1027 RBIT_w = RBIT, 1028 RBIT_x = RBIT | SixtyFourBits, 1029 REV16 = DataProcessing1SourceFixed | 0x00000400, 1030 REV16_w = REV16, 1031 REV16_x = REV16 | SixtyFourBits, 1032 REV = DataProcessing1SourceFixed | 0x00000800, 1033 REV_w = REV, 1034 REV32_x = REV | SixtyFourBits, 1035 REV_x = DataProcessing1SourceFixed | SixtyFourBits | 0x00000C00, 1036 CLZ = DataProcessing1SourceFixed | 0x00001000, 1037 CLZ_w = CLZ, 1038 CLZ_x = CLZ | SixtyFourBits, 1039 CLS = DataProcessing1SourceFixed | 0x00001400, 1040 CLS_w = CLS, 1041 CLS_x = CLS | SixtyFourBits 1042 }; 1043 1044 // Data processing 2 source. 1045 enum DataProcessing2SourceOp { 1046 DataProcessing2SourceFixed = 0x1AC00000, 1047 DataProcessing2SourceFMask = 0x5FE00000, 1048 DataProcessing2SourceMask = 0xFFE0FC00, 1049 UDIV_w = DataProcessing2SourceFixed | 0x00000800, 1050 UDIV_x = DataProcessing2SourceFixed | 0x80000800, 1051 UDIV = UDIV_w, 1052 SDIV_w = DataProcessing2SourceFixed | 0x00000C00, 1053 SDIV_x = DataProcessing2SourceFixed | 0x80000C00, 1054 SDIV = SDIV_w, 1055 LSLV_w = DataProcessing2SourceFixed | 0x00002000, 1056 LSLV_x = DataProcessing2SourceFixed | 0x80002000, 1057 LSLV = LSLV_w, 1058 LSRV_w = DataProcessing2SourceFixed | 0x00002400, 1059 LSRV_x = DataProcessing2SourceFixed | 0x80002400, 1060 LSRV = LSRV_w, 1061 ASRV_w = DataProcessing2SourceFixed | 0x00002800, 1062 ASRV_x = DataProcessing2SourceFixed | 0x80002800, 1063 ASRV = ASRV_w, 1064 RORV_w = DataProcessing2SourceFixed | 0x00002C00, 1065 RORV_x = DataProcessing2SourceFixed | 0x80002C00, 1066 RORV = RORV_w, 1067 CRC32B = DataProcessing2SourceFixed | 0x00004000, 1068 CRC32H = DataProcessing2SourceFixed | 0x00004400, 1069 CRC32W = DataProcessing2SourceFixed | 0x00004800, 1070 CRC32X = DataProcessing2SourceFixed | SixtyFourBits | 0x00004C00, 1071 CRC32CB = DataProcessing2SourceFixed | 0x00005000, 1072 CRC32CH = DataProcessing2SourceFixed | 0x00005400, 1073 CRC32CW = DataProcessing2SourceFixed | 0x00005800, 1074 CRC32CX = DataProcessing2SourceFixed | SixtyFourBits | 0x00005C00 1075 }; 1076 1077 // Data processing 3 source. 1078 enum DataProcessing3SourceOp { 1079 DataProcessing3SourceFixed = 0x1B000000, 1080 DataProcessing3SourceFMask = 0x1F000000, 1081 DataProcessing3SourceMask = 0xFFE08000, 1082 MADD_w = DataProcessing3SourceFixed | 0x00000000, 1083 MADD_x = DataProcessing3SourceFixed | 0x80000000, 1084 MADD = MADD_w, 1085 MSUB_w = DataProcessing3SourceFixed | 0x00008000, 1086 MSUB_x = DataProcessing3SourceFixed | 0x80008000, 1087 MSUB = MSUB_w, 1088 SMADDL_x = DataProcessing3SourceFixed | 0x80200000, 1089 SMSUBL_x = DataProcessing3SourceFixed | 0x80208000, 1090 SMULH_x = DataProcessing3SourceFixed | 0x80400000, 1091 UMADDL_x = DataProcessing3SourceFixed | 0x80A00000, 1092 UMSUBL_x = DataProcessing3SourceFixed | 0x80A08000, 1093 UMULH_x = DataProcessing3SourceFixed | 0x80C00000 1094 }; 1095 1096 // Floating point compare. 1097 enum FPCompareOp { 1098 FPCompareFixed = 0x1E202000, 1099 FPCompareFMask = 0x5F203C00, 1100 FPCompareMask = 0xFFE0FC1F, 1101 FCMP_s = FPCompareFixed | 0x00000000, 1102 FCMP_d = FPCompareFixed | FP64 | 0x00000000, 1103 FCMP = FCMP_s, 1104 FCMP_s_zero = FPCompareFixed | 0x00000008, 1105 FCMP_d_zero = FPCompareFixed | FP64 | 0x00000008, 1106 FCMP_zero = FCMP_s_zero, 1107 FCMPE_s = FPCompareFixed | 0x00000010, 1108 FCMPE_d = FPCompareFixed | FP64 | 0x00000010, 1109 FCMPE = FCMPE_s, 1110 FCMPE_s_zero = FPCompareFixed | 0x00000018, 1111 FCMPE_d_zero = FPCompareFixed | FP64 | 0x00000018, 1112 FCMPE_zero = FCMPE_s_zero 1113 }; 1114 1115 // Floating point conditional compare. 1116 enum FPConditionalCompareOp { 1117 FPConditionalCompareFixed = 0x1E200400, 1118 FPConditionalCompareFMask = 0x5F200C00, 1119 FPConditionalCompareMask = 0xFFE00C10, 1120 FCCMP_s = FPConditionalCompareFixed | 0x00000000, 1121 FCCMP_d = FPConditionalCompareFixed | FP64 | 0x00000000, 1122 FCCMP = FCCMP_s, 1123 FCCMPE_s = FPConditionalCompareFixed | 0x00000010, 1124 FCCMPE_d = FPConditionalCompareFixed | FP64 | 0x00000010, 1125 FCCMPE = FCCMPE_s 1126 }; 1127 1128 // Floating point conditional select. 1129 enum FPConditionalSelectOp { 1130 FPConditionalSelectFixed = 0x1E200C00, 1131 FPConditionalSelectFMask = 0x5F200C00, 1132 FPConditionalSelectMask = 0xFFE00C00, 1133 FCSEL_s = FPConditionalSelectFixed | 0x00000000, 1134 FCSEL_d = FPConditionalSelectFixed | FP64 | 0x00000000, 1135 FCSEL = FCSEL_s 1136 }; 1137 1138 // Floating point immediate. 1139 enum FPImmediateOp { 1140 FPImmediateFixed = 0x1E201000, 1141 FPImmediateFMask = 0x5F201C00, 1142 FPImmediateMask = 0xFFE01C00, 1143 FMOV_s_imm = FPImmediateFixed | 0x00000000, 1144 FMOV_d_imm = FPImmediateFixed | FP64 | 0x00000000 1145 }; 1146 1147 // Floating point data processing 1 source. 1148 enum FPDataProcessing1SourceOp { 1149 FPDataProcessing1SourceFixed = 0x1E204000, 1150 FPDataProcessing1SourceFMask = 0x5F207C00, 1151 FPDataProcessing1SourceMask = 0xFFFFFC00, 1152 FMOV_s = FPDataProcessing1SourceFixed | 0x00000000, 1153 FMOV_d = FPDataProcessing1SourceFixed | FP64 | 0x00000000, 1154 FMOV = FMOV_s, 1155 FABS_s = FPDataProcessing1SourceFixed | 0x00008000, 1156 FABS_d = FPDataProcessing1SourceFixed | FP64 | 0x00008000, 1157 FABS = FABS_s, 1158 FNEG_s = FPDataProcessing1SourceFixed | 0x00010000, 1159 FNEG_d = FPDataProcessing1SourceFixed | FP64 | 0x00010000, 1160 FNEG = FNEG_s, 1161 FSQRT_s = FPDataProcessing1SourceFixed | 0x00018000, 1162 FSQRT_d = FPDataProcessing1SourceFixed | FP64 | 0x00018000, 1163 FSQRT = FSQRT_s, 1164 FCVT_ds = FPDataProcessing1SourceFixed | 0x00028000, 1165 FCVT_sd = FPDataProcessing1SourceFixed | FP64 | 0x00020000, 1166 FCVT_hs = FPDataProcessing1SourceFixed | 0x00038000, 1167 FCVT_hd = FPDataProcessing1SourceFixed | FP64 | 0x00038000, 1168 FCVT_sh = FPDataProcessing1SourceFixed | 0x00C20000, 1169 FCVT_dh = FPDataProcessing1SourceFixed | 0x00C28000, 1170 FRINTN_s = FPDataProcessing1SourceFixed | 0x00040000, 1171 FRINTN_d = FPDataProcessing1SourceFixed | FP64 | 0x00040000, 1172 FRINTN = FRINTN_s, 1173 FRINTP_s = FPDataProcessing1SourceFixed | 0x00048000, 1174 FRINTP_d = FPDataProcessing1SourceFixed | FP64 | 0x00048000, 1175 FRINTP = FRINTP_s, 1176 FRINTM_s = FPDataProcessing1SourceFixed | 0x00050000, 1177 FRINTM_d = FPDataProcessing1SourceFixed | FP64 | 0x00050000, 1178 FRINTM = FRINTM_s, 1179 FRINTZ_s = FPDataProcessing1SourceFixed | 0x00058000, 1180 FRINTZ_d = FPDataProcessing1SourceFixed | FP64 | 0x00058000, 1181 FRINTZ = FRINTZ_s, 1182 FRINTA_s = FPDataProcessing1SourceFixed | 0x00060000, 1183 FRINTA_d = FPDataProcessing1SourceFixed | FP64 | 0x00060000, 1184 FRINTA = FRINTA_s, 1185 FRINTX_s = FPDataProcessing1SourceFixed | 0x00070000, 1186 FRINTX_d = FPDataProcessing1SourceFixed | FP64 | 0x00070000, 1187 FRINTX = FRINTX_s, 1188 FRINTI_s = FPDataProcessing1SourceFixed | 0x00078000, 1189 FRINTI_d = FPDataProcessing1SourceFixed | FP64 | 0x00078000, 1190 FRINTI = FRINTI_s 1191 }; 1192 1193 // Floating point data processing 2 source. 1194 enum FPDataProcessing2SourceOp { 1195 FPDataProcessing2SourceFixed = 0x1E200800, 1196 FPDataProcessing2SourceFMask = 0x5F200C00, 1197 FPDataProcessing2SourceMask = 0xFFE0FC00, 1198 FMUL = FPDataProcessing2SourceFixed | 0x00000000, 1199 FMUL_s = FMUL, 1200 FMUL_d = FMUL | FP64, 1201 FDIV = FPDataProcessing2SourceFixed | 0x00001000, 1202 FDIV_s = FDIV, 1203 FDIV_d = FDIV | FP64, 1204 FADD = FPDataProcessing2SourceFixed | 0x00002000, 1205 FADD_s = FADD, 1206 FADD_d = FADD | FP64, 1207 FSUB = FPDataProcessing2SourceFixed | 0x00003000, 1208 FSUB_s = FSUB, 1209 FSUB_d = FSUB | FP64, 1210 FMAX = FPDataProcessing2SourceFixed | 0x00004000, 1211 FMAX_s = FMAX, 1212 FMAX_d = FMAX | FP64, 1213 FMIN = FPDataProcessing2SourceFixed | 0x00005000, 1214 FMIN_s = FMIN, 1215 FMIN_d = FMIN | FP64, 1216 FMAXNM = FPDataProcessing2SourceFixed | 0x00006000, 1217 FMAXNM_s = FMAXNM, 1218 FMAXNM_d = FMAXNM | FP64, 1219 FMINNM = FPDataProcessing2SourceFixed | 0x00007000, 1220 FMINNM_s = FMINNM, 1221 FMINNM_d = FMINNM | FP64, 1222 FNMUL = FPDataProcessing2SourceFixed | 0x00008000, 1223 FNMUL_s = FNMUL, 1224 FNMUL_d = FNMUL | FP64 1225 }; 1226 1227 // Floating point data processing 3 source. 1228 enum FPDataProcessing3SourceOp { 1229 FPDataProcessing3SourceFixed = 0x1F000000, 1230 FPDataProcessing3SourceFMask = 0x5F000000, 1231 FPDataProcessing3SourceMask = 0xFFE08000, 1232 FMADD_s = FPDataProcessing3SourceFixed | 0x00000000, 1233 FMSUB_s = FPDataProcessing3SourceFixed | 0x00008000, 1234 FNMADD_s = FPDataProcessing3SourceFixed | 0x00200000, 1235 FNMSUB_s = FPDataProcessing3SourceFixed | 0x00208000, 1236 FMADD_d = FPDataProcessing3SourceFixed | 0x00400000, 1237 FMSUB_d = FPDataProcessing3SourceFixed | 0x00408000, 1238 FNMADD_d = FPDataProcessing3SourceFixed | 0x00600000, 1239 FNMSUB_d = FPDataProcessing3SourceFixed | 0x00608000 1240 }; 1241 1242 // Conversion between floating point and integer. 1243 enum FPIntegerConvertOp { 1244 FPIntegerConvertFixed = 0x1E200000, 1245 FPIntegerConvertFMask = 0x5F20FC00, 1246 FPIntegerConvertMask = 0xFFFFFC00, 1247 FCVTNS = FPIntegerConvertFixed | 0x00000000, 1248 FCVTNS_ws = FCVTNS, 1249 FCVTNS_xs = FCVTNS | SixtyFourBits, 1250 FCVTNS_wd = FCVTNS | FP64, 1251 FCVTNS_xd = FCVTNS | SixtyFourBits | FP64, 1252 FCVTNU = FPIntegerConvertFixed | 0x00010000, 1253 FCVTNU_ws = FCVTNU, 1254 FCVTNU_xs = FCVTNU | SixtyFourBits, 1255 FCVTNU_wd = FCVTNU | FP64, 1256 FCVTNU_xd = FCVTNU | SixtyFourBits | FP64, 1257 FCVTPS = FPIntegerConvertFixed | 0x00080000, 1258 FCVTPS_ws = FCVTPS, 1259 FCVTPS_xs = FCVTPS | SixtyFourBits, 1260 FCVTPS_wd = FCVTPS | FP64, 1261 FCVTPS_xd = FCVTPS | SixtyFourBits | FP64, 1262 FCVTPU = FPIntegerConvertFixed | 0x00090000, 1263 FCVTPU_ws = FCVTPU, 1264 FCVTPU_xs = FCVTPU | SixtyFourBits, 1265 FCVTPU_wd = FCVTPU | FP64, 1266 FCVTPU_xd = FCVTPU | SixtyFourBits | FP64, 1267 FCVTMS = FPIntegerConvertFixed | 0x00100000, 1268 FCVTMS_ws = FCVTMS, 1269 FCVTMS_xs = FCVTMS | SixtyFourBits, 1270 FCVTMS_wd = FCVTMS | FP64, 1271 FCVTMS_xd = FCVTMS | SixtyFourBits | FP64, 1272 FCVTMU = FPIntegerConvertFixed | 0x00110000, 1273 FCVTMU_ws = FCVTMU, 1274 FCVTMU_xs = FCVTMU | SixtyFourBits, 1275 FCVTMU_wd = FCVTMU | FP64, 1276 FCVTMU_xd = FCVTMU | SixtyFourBits | FP64, 1277 FCVTZS = FPIntegerConvertFixed | 0x00180000, 1278 FCVTZS_ws = FCVTZS, 1279 FCVTZS_xs = FCVTZS | SixtyFourBits, 1280 FCVTZS_wd = FCVTZS | FP64, 1281 FCVTZS_xd = FCVTZS | SixtyFourBits | FP64, 1282 FCVTZU = FPIntegerConvertFixed | 0x00190000, 1283 FCVTZU_ws = FCVTZU, 1284 FCVTZU_xs = FCVTZU | SixtyFourBits, 1285 FCVTZU_wd = FCVTZU | FP64, 1286 FCVTZU_xd = FCVTZU | SixtyFourBits | FP64, 1287 SCVTF = FPIntegerConvertFixed | 0x00020000, 1288 SCVTF_sw = SCVTF, 1289 SCVTF_sx = SCVTF | SixtyFourBits, 1290 SCVTF_dw = SCVTF | FP64, 1291 SCVTF_dx = SCVTF | SixtyFourBits | FP64, 1292 UCVTF = FPIntegerConvertFixed | 0x00030000, 1293 UCVTF_sw = UCVTF, 1294 UCVTF_sx = UCVTF | SixtyFourBits, 1295 UCVTF_dw = UCVTF | FP64, 1296 UCVTF_dx = UCVTF | SixtyFourBits | FP64, 1297 FCVTAS = FPIntegerConvertFixed | 0x00040000, 1298 FCVTAS_ws = FCVTAS, 1299 FCVTAS_xs = FCVTAS | SixtyFourBits, 1300 FCVTAS_wd = FCVTAS | FP64, 1301 FCVTAS_xd = FCVTAS | SixtyFourBits | FP64, 1302 FCVTAU = FPIntegerConvertFixed | 0x00050000, 1303 FCVTAU_ws = FCVTAU, 1304 FCVTAU_xs = FCVTAU | SixtyFourBits, 1305 FCVTAU_wd = FCVTAU | FP64, 1306 FCVTAU_xd = FCVTAU | SixtyFourBits | FP64, 1307 FMOV_ws = FPIntegerConvertFixed | 0x00060000, 1308 FMOV_sw = FPIntegerConvertFixed | 0x00070000, 1309 FMOV_xd = FMOV_ws | SixtyFourBits | FP64, 1310 FMOV_dx = FMOV_sw | SixtyFourBits | FP64, 1311 FMOV_d1_x = FPIntegerConvertFixed | SixtyFourBits | 0x008F0000, 1312 FMOV_x_d1 = FPIntegerConvertFixed | SixtyFourBits | 0x008E0000 1313 }; 1314 1315 // Conversion between fixed point and floating point. 1316 enum FPFixedPointConvertOp { 1317 FPFixedPointConvertFixed = 0x1E000000, 1318 FPFixedPointConvertFMask = 0x5F200000, 1319 FPFixedPointConvertMask = 0xFFFF0000, 1320 FCVTZS_fixed = FPFixedPointConvertFixed | 0x00180000, 1321 FCVTZS_ws_fixed = FCVTZS_fixed, 1322 FCVTZS_xs_fixed = FCVTZS_fixed | SixtyFourBits, 1323 FCVTZS_wd_fixed = FCVTZS_fixed | FP64, 1324 FCVTZS_xd_fixed = FCVTZS_fixed | SixtyFourBits | FP64, 1325 FCVTZU_fixed = FPFixedPointConvertFixed | 0x00190000, 1326 FCVTZU_ws_fixed = FCVTZU_fixed, 1327 FCVTZU_xs_fixed = FCVTZU_fixed | SixtyFourBits, 1328 FCVTZU_wd_fixed = FCVTZU_fixed | FP64, 1329 FCVTZU_xd_fixed = FCVTZU_fixed | SixtyFourBits | FP64, 1330 SCVTF_fixed = FPFixedPointConvertFixed | 0x00020000, 1331 SCVTF_sw_fixed = SCVTF_fixed, 1332 SCVTF_sx_fixed = SCVTF_fixed | SixtyFourBits, 1333 SCVTF_dw_fixed = SCVTF_fixed | FP64, 1334 SCVTF_dx_fixed = SCVTF_fixed | SixtyFourBits | FP64, 1335 UCVTF_fixed = FPFixedPointConvertFixed | 0x00030000, 1336 UCVTF_sw_fixed = UCVTF_fixed, 1337 UCVTF_sx_fixed = UCVTF_fixed | SixtyFourBits, 1338 UCVTF_dw_fixed = UCVTF_fixed | FP64, 1339 UCVTF_dx_fixed = UCVTF_fixed | SixtyFourBits | FP64 1340 }; 1341 1342 // Crypto - two register SHA. 1343 enum Crypto2RegSHAOp { 1344 Crypto2RegSHAFixed = 0x5E280800, 1345 Crypto2RegSHAFMask = 0xFF3E0C00 1346 }; 1347 1348 // Crypto - three register SHA. 1349 enum Crypto3RegSHAOp { 1350 Crypto3RegSHAFixed = 0x5E000000, 1351 Crypto3RegSHAFMask = 0xFF208C00 1352 }; 1353 1354 // Crypto - AES. 1355 enum CryptoAESOp { 1356 CryptoAESFixed = 0x4E280800, 1357 CryptoAESFMask = 0xFF3E0C00 1358 }; 1359 1360 // NEON instructions with two register operands. 1361 enum NEON2RegMiscOp { 1362 NEON2RegMiscFixed = 0x0E200800, 1363 NEON2RegMiscFMask = 0x9F3E0C00, 1364 NEON2RegMiscMask = 0xBF3FFC00, 1365 NEON2RegMiscUBit = 0x20000000, 1366 NEON_REV64 = NEON2RegMiscFixed | 0x00000000, 1367 NEON_REV32 = NEON2RegMiscFixed | 0x20000000, 1368 NEON_REV16 = NEON2RegMiscFixed | 0x00001000, 1369 NEON_SADDLP = NEON2RegMiscFixed | 0x00002000, 1370 NEON_UADDLP = NEON_SADDLP | NEON2RegMiscUBit, 1371 NEON_SUQADD = NEON2RegMiscFixed | 0x00003000, 1372 NEON_USQADD = NEON_SUQADD | NEON2RegMiscUBit, 1373 NEON_CLS = NEON2RegMiscFixed | 0x00004000, 1374 NEON_CLZ = NEON2RegMiscFixed | 0x20004000, 1375 NEON_CNT = NEON2RegMiscFixed | 0x00005000, 1376 NEON_RBIT_NOT = NEON2RegMiscFixed | 0x20005000, 1377 NEON_SADALP = NEON2RegMiscFixed | 0x00006000, 1378 NEON_UADALP = NEON_SADALP | NEON2RegMiscUBit, 1379 NEON_SQABS = NEON2RegMiscFixed | 0x00007000, 1380 NEON_SQNEG = NEON2RegMiscFixed | 0x20007000, 1381 NEON_CMGT_zero = NEON2RegMiscFixed | 0x00008000, 1382 NEON_CMGE_zero = NEON2RegMiscFixed | 0x20008000, 1383 NEON_CMEQ_zero = NEON2RegMiscFixed | 0x00009000, 1384 NEON_CMLE_zero = NEON2RegMiscFixed | 0x20009000, 1385 NEON_CMLT_zero = NEON2RegMiscFixed | 0x0000A000, 1386 NEON_ABS = NEON2RegMiscFixed | 0x0000B000, 1387 NEON_NEG = NEON2RegMiscFixed | 0x2000B000, 1388 NEON_XTN = NEON2RegMiscFixed | 0x00012000, 1389 NEON_SQXTUN = NEON2RegMiscFixed | 0x20012000, 1390 NEON_SHLL = NEON2RegMiscFixed | 0x20013000, 1391 NEON_SQXTN = NEON2RegMiscFixed | 0x00014000, 1392 NEON_UQXTN = NEON_SQXTN | NEON2RegMiscUBit, 1393 1394 NEON2RegMiscOpcode = 0x0001F000, 1395 NEON_RBIT_NOT_opcode = NEON_RBIT_NOT & NEON2RegMiscOpcode, 1396 NEON_NEG_opcode = NEON_NEG & NEON2RegMiscOpcode, 1397 NEON_XTN_opcode = NEON_XTN & NEON2RegMiscOpcode, 1398 NEON_UQXTN_opcode = NEON_UQXTN & NEON2RegMiscOpcode, 1399 1400 // These instructions use only one bit of the size field. The other bit is 1401 // used to distinguish between instructions. 1402 NEON2RegMiscFPMask = NEON2RegMiscMask | 0x00800000, 1403 NEON_FABS = NEON2RegMiscFixed | 0x0080F000, 1404 NEON_FNEG = NEON2RegMiscFixed | 0x2080F000, 1405 NEON_FCVTN = NEON2RegMiscFixed | 0x00016000, 1406 NEON_FCVTXN = NEON2RegMiscFixed | 0x20016000, 1407 NEON_FCVTL = NEON2RegMiscFixed | 0x00017000, 1408 NEON_FRINTN = NEON2RegMiscFixed | 0x00018000, 1409 NEON_FRINTA = NEON2RegMiscFixed | 0x20018000, 1410 NEON_FRINTP = NEON2RegMiscFixed | 0x00818000, 1411 NEON_FRINTM = NEON2RegMiscFixed | 0x00019000, 1412 NEON_FRINTX = NEON2RegMiscFixed | 0x20019000, 1413 NEON_FRINTZ = NEON2RegMiscFixed | 0x00819000, 1414 NEON_FRINTI = NEON2RegMiscFixed | 0x20819000, 1415 NEON_FCVTNS = NEON2RegMiscFixed | 0x0001A000, 1416 NEON_FCVTNU = NEON_FCVTNS | NEON2RegMiscUBit, 1417 NEON_FCVTPS = NEON2RegMiscFixed | 0x0081A000, 1418 NEON_FCVTPU = NEON_FCVTPS | NEON2RegMiscUBit, 1419 NEON_FCVTMS = NEON2RegMiscFixed | 0x0001B000, 1420 NEON_FCVTMU = NEON_FCVTMS | NEON2RegMiscUBit, 1421 NEON_FCVTZS = NEON2RegMiscFixed | 0x0081B000, 1422 NEON_FCVTZU = NEON_FCVTZS | NEON2RegMiscUBit, 1423 NEON_FCVTAS = NEON2RegMiscFixed | 0x0001C000, 1424 NEON_FCVTAU = NEON_FCVTAS | NEON2RegMiscUBit, 1425 NEON_FSQRT = NEON2RegMiscFixed | 0x2081F000, 1426 NEON_SCVTF = NEON2RegMiscFixed | 0x0001D000, 1427 NEON_UCVTF = NEON_SCVTF | NEON2RegMiscUBit, 1428 NEON_URSQRTE = NEON2RegMiscFixed | 0x2081C000, 1429 NEON_URECPE = NEON2RegMiscFixed | 0x0081C000, 1430 NEON_FRSQRTE = NEON2RegMiscFixed | 0x2081D000, 1431 NEON_FRECPE = NEON2RegMiscFixed | 0x0081D000, 1432 NEON_FCMGT_zero = NEON2RegMiscFixed | 0x0080C000, 1433 NEON_FCMGE_zero = NEON2RegMiscFixed | 0x2080C000, 1434 NEON_FCMEQ_zero = NEON2RegMiscFixed | 0x0080D000, 1435 NEON_FCMLE_zero = NEON2RegMiscFixed | 0x2080D000, 1436 NEON_FCMLT_zero = NEON2RegMiscFixed | 0x0080E000, 1437 1438 NEON_FCVTL_opcode = NEON_FCVTL & NEON2RegMiscOpcode, 1439 NEON_FCVTN_opcode = NEON_FCVTN & NEON2RegMiscOpcode 1440 }; 1441 1442 // NEON instructions with three same-type operands. 1443 enum NEON3SameOp { 1444 NEON3SameFixed = 0x0E200400, 1445 NEON3SameFMask = 0x9F200400, 1446 NEON3SameMask = 0xBF20FC00, 1447 NEON3SameUBit = 0x20000000, 1448 NEON_ADD = NEON3SameFixed | 0x00008000, 1449 NEON_ADDP = NEON3SameFixed | 0x0000B800, 1450 NEON_SHADD = NEON3SameFixed | 0x00000000, 1451 NEON_SHSUB = NEON3SameFixed | 0x00002000, 1452 NEON_SRHADD = NEON3SameFixed | 0x00001000, 1453 NEON_CMEQ = NEON3SameFixed | NEON3SameUBit | 0x00008800, 1454 NEON_CMGE = NEON3SameFixed | 0x00003800, 1455 NEON_CMGT = NEON3SameFixed | 0x00003000, 1456 NEON_CMHI = NEON3SameFixed | NEON3SameUBit | NEON_CMGT, 1457 NEON_CMHS = NEON3SameFixed | NEON3SameUBit | NEON_CMGE, 1458 NEON_CMTST = NEON3SameFixed | 0x00008800, 1459 NEON_MLA = NEON3SameFixed | 0x00009000, 1460 NEON_MLS = NEON3SameFixed | 0x20009000, 1461 NEON_MUL = NEON3SameFixed | 0x00009800, 1462 NEON_PMUL = NEON3SameFixed | 0x20009800, 1463 NEON_SRSHL = NEON3SameFixed | 0x00005000, 1464 NEON_SQSHL = NEON3SameFixed | 0x00004800, 1465 NEON_SQRSHL = NEON3SameFixed | 0x00005800, 1466 NEON_SSHL = NEON3SameFixed | 0x00004000, 1467 NEON_SMAX = NEON3SameFixed | 0x00006000, 1468 NEON_SMAXP = NEON3SameFixed | 0x0000A000, 1469 NEON_SMIN = NEON3SameFixed | 0x00006800, 1470 NEON_SMINP = NEON3SameFixed | 0x0000A800, 1471 NEON_SABD = NEON3SameFixed | 0x00007000, 1472 NEON_SABA = NEON3SameFixed | 0x00007800, 1473 NEON_UABD = NEON3SameFixed | NEON3SameUBit | NEON_SABD, 1474 NEON_UABA = NEON3SameFixed | NEON3SameUBit | NEON_SABA, 1475 NEON_SQADD = NEON3SameFixed | 0x00000800, 1476 NEON_SQSUB = NEON3SameFixed | 0x00002800, 1477 NEON_SUB = NEON3SameFixed | NEON3SameUBit | 0x00008000, 1478 NEON_UHADD = NEON3SameFixed | NEON3SameUBit | NEON_SHADD, 1479 NEON_UHSUB = NEON3SameFixed | NEON3SameUBit | NEON_SHSUB, 1480 NEON_URHADD = NEON3SameFixed | NEON3SameUBit | NEON_SRHADD, 1481 NEON_UMAX = NEON3SameFixed | NEON3SameUBit | NEON_SMAX, 1482 NEON_UMAXP = NEON3SameFixed | NEON3SameUBit | NEON_SMAXP, 1483 NEON_UMIN = NEON3SameFixed | NEON3SameUBit | NEON_SMIN, 1484 NEON_UMINP = NEON3SameFixed | NEON3SameUBit | NEON_SMINP, 1485 NEON_URSHL = NEON3SameFixed | NEON3SameUBit | NEON_SRSHL, 1486 NEON_UQADD = NEON3SameFixed | NEON3SameUBit | NEON_SQADD, 1487 NEON_UQRSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQRSHL, 1488 NEON_UQSHL = NEON3SameFixed | NEON3SameUBit | NEON_SQSHL, 1489 NEON_UQSUB = NEON3SameFixed | NEON3SameUBit | NEON_SQSUB, 1490 NEON_USHL = NEON3SameFixed | NEON3SameUBit | NEON_SSHL, 1491 NEON_SQDMULH = NEON3SameFixed | 0x0000B000, 1492 NEON_SQRDMULH = NEON3SameFixed | 0x2000B000, 1493 1494 // NEON floating point instructions with three same-type operands. 1495 NEON3SameFPFixed = NEON3SameFixed | 0x0000C000, 1496 NEON3SameFPFMask = NEON3SameFMask | 0x0000C000, 1497 NEON3SameFPMask = NEON3SameMask | 0x00800000, 1498 NEON_FADD = NEON3SameFixed | 0x0000D000, 1499 NEON_FSUB = NEON3SameFixed | 0x0080D000, 1500 NEON_FMUL = NEON3SameFixed | 0x2000D800, 1501 NEON_FDIV = NEON3SameFixed | 0x2000F800, 1502 NEON_FMAX = NEON3SameFixed | 0x0000F000, 1503 NEON_FMAXNM = NEON3SameFixed | 0x0000C000, 1504 NEON_FMAXP = NEON3SameFixed | 0x2000F000, 1505 NEON_FMAXNMP = NEON3SameFixed | 0x2000C000, 1506 NEON_FMIN = NEON3SameFixed | 0x0080F000, 1507 NEON_FMINNM = NEON3SameFixed | 0x0080C000, 1508 NEON_FMINP = NEON3SameFixed | 0x2080F000, 1509 NEON_FMINNMP = NEON3SameFixed | 0x2080C000, 1510 NEON_FMLA = NEON3SameFixed | 0x0000C800, 1511 NEON_FMLS = NEON3SameFixed | 0x0080C800, 1512 NEON_FMULX = NEON3SameFixed | 0x0000D800, 1513 NEON_FRECPS = NEON3SameFixed | 0x0000F800, 1514 NEON_FRSQRTS = NEON3SameFixed | 0x0080F800, 1515 NEON_FABD = NEON3SameFixed | 0x2080D000, 1516 NEON_FADDP = NEON3SameFixed | 0x2000D000, 1517 NEON_FCMEQ = NEON3SameFixed | 0x0000E000, 1518 NEON_FCMGE = NEON3SameFixed | 0x2000E000, 1519 NEON_FCMGT = NEON3SameFixed | 0x2080E000, 1520 NEON_FACGE = NEON3SameFixed | 0x2000E800, 1521 NEON_FACGT = NEON3SameFixed | 0x2080E800, 1522 1523 // NEON logical instructions with three same-type operands. 1524 NEON3SameLogicalFixed = NEON3SameFixed | 0x00001800, 1525 NEON3SameLogicalFMask = NEON3SameFMask | 0x0000F800, 1526 NEON3SameLogicalMask = 0xBFE0FC00, 1527 NEON3SameLogicalFormatMask = NEON_Q, 1528 NEON_AND = NEON3SameLogicalFixed | 0x00000000, 1529 NEON_ORR = NEON3SameLogicalFixed | 0x00A00000, 1530 NEON_ORN = NEON3SameLogicalFixed | 0x00C00000, 1531 NEON_EOR = NEON3SameLogicalFixed | 0x20000000, 1532 NEON_BIC = NEON3SameLogicalFixed | 0x00400000, 1533 NEON_BIF = NEON3SameLogicalFixed | 0x20C00000, 1534 NEON_BIT = NEON3SameLogicalFixed | 0x20800000, 1535 NEON_BSL = NEON3SameLogicalFixed | 0x20400000 1536 }; 1537 1538 // NEON instructions with three different-type operands. 1539 enum NEON3DifferentOp { 1540 NEON3DifferentFixed = 0x0E200000, 1541 NEON3DifferentFMask = 0x9F200C00, 1542 NEON3DifferentMask = 0xFF20FC00, 1543 NEON_ADDHN = NEON3DifferentFixed | 0x00004000, 1544 NEON_ADDHN2 = NEON_ADDHN | NEON_Q, 1545 NEON_PMULL = NEON3DifferentFixed | 0x0000E000, 1546 NEON_PMULL2 = NEON_PMULL | NEON_Q, 1547 NEON_RADDHN = NEON3DifferentFixed | 0x20004000, 1548 NEON_RADDHN2 = NEON_RADDHN | NEON_Q, 1549 NEON_RSUBHN = NEON3DifferentFixed | 0x20006000, 1550 NEON_RSUBHN2 = NEON_RSUBHN | NEON_Q, 1551 NEON_SABAL = NEON3DifferentFixed | 0x00005000, 1552 NEON_SABAL2 = NEON_SABAL | NEON_Q, 1553 NEON_SABDL = NEON3DifferentFixed | 0x00007000, 1554 NEON_SABDL2 = NEON_SABDL | NEON_Q, 1555 NEON_SADDL = NEON3DifferentFixed | 0x00000000, 1556 NEON_SADDL2 = NEON_SADDL | NEON_Q, 1557 NEON_SADDW = NEON3DifferentFixed | 0x00001000, 1558 NEON_SADDW2 = NEON_SADDW | NEON_Q, 1559 NEON_SMLAL = NEON3DifferentFixed | 0x00008000, 1560 NEON_SMLAL2 = NEON_SMLAL | NEON_Q, 1561 NEON_SMLSL = NEON3DifferentFixed | 0x0000A000, 1562 NEON_SMLSL2 = NEON_SMLSL | NEON_Q, 1563 NEON_SMULL = NEON3DifferentFixed | 0x0000C000, 1564 NEON_SMULL2 = NEON_SMULL | NEON_Q, 1565 NEON_SSUBL = NEON3DifferentFixed | 0x00002000, 1566 NEON_SSUBL2 = NEON_SSUBL | NEON_Q, 1567 NEON_SSUBW = NEON3DifferentFixed | 0x00003000, 1568 NEON_SSUBW2 = NEON_SSUBW | NEON_Q, 1569 NEON_SQDMLAL = NEON3DifferentFixed | 0x00009000, 1570 NEON_SQDMLAL2 = NEON_SQDMLAL | NEON_Q, 1571 NEON_SQDMLSL = NEON3DifferentFixed | 0x0000B000, 1572 NEON_SQDMLSL2 = NEON_SQDMLSL | NEON_Q, 1573 NEON_SQDMULL = NEON3DifferentFixed | 0x0000D000, 1574 NEON_SQDMULL2 = NEON_SQDMULL | NEON_Q, 1575 NEON_SUBHN = NEON3DifferentFixed | 0x00006000, 1576 NEON_SUBHN2 = NEON_SUBHN | NEON_Q, 1577 NEON_UABAL = NEON_SABAL | NEON3SameUBit, 1578 NEON_UABAL2 = NEON_UABAL | NEON_Q, 1579 NEON_UABDL = NEON_SABDL | NEON3SameUBit, 1580 NEON_UABDL2 = NEON_UABDL | NEON_Q, 1581 NEON_UADDL = NEON_SADDL | NEON3SameUBit, 1582 NEON_UADDL2 = NEON_UADDL | NEON_Q, 1583 NEON_UADDW = NEON_SADDW | NEON3SameUBit, 1584 NEON_UADDW2 = NEON_UADDW | NEON_Q, 1585 NEON_UMLAL = NEON_SMLAL | NEON3SameUBit, 1586 NEON_UMLAL2 = NEON_UMLAL | NEON_Q, 1587 NEON_UMLSL = NEON_SMLSL | NEON3SameUBit, 1588 NEON_UMLSL2 = NEON_UMLSL | NEON_Q, 1589 NEON_UMULL = NEON_SMULL | NEON3SameUBit, 1590 NEON_UMULL2 = NEON_UMULL | NEON_Q, 1591 NEON_USUBL = NEON_SSUBL | NEON3SameUBit, 1592 NEON_USUBL2 = NEON_USUBL | NEON_Q, 1593 NEON_USUBW = NEON_SSUBW | NEON3SameUBit, 1594 NEON_USUBW2 = NEON_USUBW | NEON_Q 1595 }; 1596 1597 // NEON instructions operating across vectors. 1598 enum NEONAcrossLanesOp { 1599 NEONAcrossLanesFixed = 0x0E300800, 1600 NEONAcrossLanesFMask = 0x9F3E0C00, 1601 NEONAcrossLanesMask = 0xBF3FFC00, 1602 NEON_ADDV = NEONAcrossLanesFixed | 0x0001B000, 1603 NEON_SADDLV = NEONAcrossLanesFixed | 0x00003000, 1604 NEON_UADDLV = NEONAcrossLanesFixed | 0x20003000, 1605 NEON_SMAXV = NEONAcrossLanesFixed | 0x0000A000, 1606 NEON_SMINV = NEONAcrossLanesFixed | 0x0001A000, 1607 NEON_UMAXV = NEONAcrossLanesFixed | 0x2000A000, 1608 NEON_UMINV = NEONAcrossLanesFixed | 0x2001A000, 1609 1610 // NEON floating point across instructions. 1611 NEONAcrossLanesFPFixed = NEONAcrossLanesFixed | 0x0000C000, 1612 NEONAcrossLanesFPFMask = NEONAcrossLanesFMask | 0x0000C000, 1613 NEONAcrossLanesFPMask = NEONAcrossLanesMask | 0x00800000, 1614 1615 NEON_FMAXV = NEONAcrossLanesFPFixed | 0x2000F000, 1616 NEON_FMINV = NEONAcrossLanesFPFixed | 0x2080F000, 1617 NEON_FMAXNMV = NEONAcrossLanesFPFixed | 0x2000C000, 1618 NEON_FMINNMV = NEONAcrossLanesFPFixed | 0x2080C000 1619 }; 1620 1621 // NEON instructions with indexed element operand. 1622 enum NEONByIndexedElementOp { 1623 NEONByIndexedElementFixed = 0x0F000000, 1624 NEONByIndexedElementFMask = 0x9F000400, 1625 NEONByIndexedElementMask = 0xBF00F400, 1626 NEON_MUL_byelement = NEONByIndexedElementFixed | 0x00008000, 1627 NEON_MLA_byelement = NEONByIndexedElementFixed | 0x20000000, 1628 NEON_MLS_byelement = NEONByIndexedElementFixed | 0x20004000, 1629 NEON_SMULL_byelement = NEONByIndexedElementFixed | 0x0000A000, 1630 NEON_SMLAL_byelement = NEONByIndexedElementFixed | 0x00002000, 1631 NEON_SMLSL_byelement = NEONByIndexedElementFixed | 0x00006000, 1632 NEON_UMULL_byelement = NEONByIndexedElementFixed | 0x2000A000, 1633 NEON_UMLAL_byelement = NEONByIndexedElementFixed | 0x20002000, 1634 NEON_UMLSL_byelement = NEONByIndexedElementFixed | 0x20006000, 1635 NEON_SQDMULL_byelement = NEONByIndexedElementFixed | 0x0000B000, 1636 NEON_SQDMLAL_byelement = NEONByIndexedElementFixed | 0x00003000, 1637 NEON_SQDMLSL_byelement = NEONByIndexedElementFixed | 0x00007000, 1638 NEON_SQDMULH_byelement = NEONByIndexedElementFixed | 0x0000C000, 1639 NEON_SQRDMULH_byelement = NEONByIndexedElementFixed | 0x0000D000, 1640 1641 // Floating point instructions. 1642 NEONByIndexedElementFPFixed = NEONByIndexedElementFixed | 0x00800000, 1643 NEONByIndexedElementFPMask = NEONByIndexedElementMask | 0x00800000, 1644 NEON_FMLA_byelement = NEONByIndexedElementFPFixed | 0x00001000, 1645 NEON_FMLS_byelement = NEONByIndexedElementFPFixed | 0x00005000, 1646 NEON_FMUL_byelement = NEONByIndexedElementFPFixed | 0x00009000, 1647 NEON_FMULX_byelement = NEONByIndexedElementFPFixed | 0x20009000 1648 }; 1649 1650 // NEON register copy. 1651 enum NEONCopyOp { 1652 NEONCopyFixed = 0x0E000400, 1653 NEONCopyFMask = 0x9FE08400, 1654 NEONCopyMask = 0x3FE08400, 1655 NEONCopyInsElementMask = NEONCopyMask | 0x40000000, 1656 NEONCopyInsGeneralMask = NEONCopyMask | 0x40007800, 1657 NEONCopyDupElementMask = NEONCopyMask | 0x20007800, 1658 NEONCopyDupGeneralMask = NEONCopyDupElementMask, 1659 NEONCopyUmovMask = NEONCopyMask | 0x20007800, 1660 NEONCopySmovMask = NEONCopyMask | 0x20007800, 1661 NEON_INS_ELEMENT = NEONCopyFixed | 0x60000000, 1662 NEON_INS_GENERAL = NEONCopyFixed | 0x40001800, 1663 NEON_DUP_ELEMENT = NEONCopyFixed | 0x00000000, 1664 NEON_DUP_GENERAL = NEONCopyFixed | 0x00000800, 1665 NEON_SMOV = NEONCopyFixed | 0x00002800, 1666 NEON_UMOV = NEONCopyFixed | 0x00003800 1667 }; 1668 1669 // NEON extract. 1670 enum NEONExtractOp { 1671 NEONExtractFixed = 0x2E000000, 1672 NEONExtractFMask = 0xBF208400, 1673 NEONExtractMask = 0xBFE08400, 1674 NEON_EXT = NEONExtractFixed | 0x00000000 1675 }; 1676 1677 enum NEONLoadStoreMultiOp { 1678 NEONLoadStoreMultiL = 0x00400000, 1679 NEONLoadStoreMulti1_1v = 0x00007000, 1680 NEONLoadStoreMulti1_2v = 0x0000A000, 1681 NEONLoadStoreMulti1_3v = 0x00006000, 1682 NEONLoadStoreMulti1_4v = 0x00002000, 1683 NEONLoadStoreMulti2 = 0x00008000, 1684 NEONLoadStoreMulti3 = 0x00004000, 1685 NEONLoadStoreMulti4 = 0x00000000 1686 }; 1687 1688 // NEON load/store multiple structures. 1689 enum NEONLoadStoreMultiStructOp { 1690 NEONLoadStoreMultiStructFixed = 0x0C000000, 1691 NEONLoadStoreMultiStructFMask = 0xBFBF0000, 1692 NEONLoadStoreMultiStructMask = 0xBFFFF000, 1693 NEONLoadStoreMultiStructStore = NEONLoadStoreMultiStructFixed, 1694 NEONLoadStoreMultiStructLoad = NEONLoadStoreMultiStructFixed | 1695 NEONLoadStoreMultiL, 1696 NEON_LD1_1v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_1v, 1697 NEON_LD1_2v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_2v, 1698 NEON_LD1_3v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_3v, 1699 NEON_LD1_4v = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti1_4v, 1700 NEON_LD2 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti2, 1701 NEON_LD3 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti3, 1702 NEON_LD4 = NEONLoadStoreMultiStructLoad | NEONLoadStoreMulti4, 1703 NEON_ST1_1v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_1v, 1704 NEON_ST1_2v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_2v, 1705 NEON_ST1_3v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_3v, 1706 NEON_ST1_4v = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti1_4v, 1707 NEON_ST2 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti2, 1708 NEON_ST3 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti3, 1709 NEON_ST4 = NEONLoadStoreMultiStructStore | NEONLoadStoreMulti4 1710 }; 1711 1712 // NEON load/store multiple structures with post-index addressing. 1713 enum NEONLoadStoreMultiStructPostIndexOp { 1714 NEONLoadStoreMultiStructPostIndexFixed = 0x0C800000, 1715 NEONLoadStoreMultiStructPostIndexFMask = 0xBFA00000, 1716 NEONLoadStoreMultiStructPostIndexMask = 0xBFE0F000, 1717 NEONLoadStoreMultiStructPostIndex = 0x00800000, 1718 NEON_LD1_1v_post = NEON_LD1_1v | NEONLoadStoreMultiStructPostIndex, 1719 NEON_LD1_2v_post = NEON_LD1_2v | NEONLoadStoreMultiStructPostIndex, 1720 NEON_LD1_3v_post = NEON_LD1_3v | NEONLoadStoreMultiStructPostIndex, 1721 NEON_LD1_4v_post = NEON_LD1_4v | NEONLoadStoreMultiStructPostIndex, 1722 NEON_LD2_post = NEON_LD2 | NEONLoadStoreMultiStructPostIndex, 1723 NEON_LD3_post = NEON_LD3 | NEONLoadStoreMultiStructPostIndex, 1724 NEON_LD4_post = NEON_LD4 | NEONLoadStoreMultiStructPostIndex, 1725 NEON_ST1_1v_post = NEON_ST1_1v | NEONLoadStoreMultiStructPostIndex, 1726 NEON_ST1_2v_post = NEON_ST1_2v | NEONLoadStoreMultiStructPostIndex, 1727 NEON_ST1_3v_post = NEON_ST1_3v | NEONLoadStoreMultiStructPostIndex, 1728 NEON_ST1_4v_post = NEON_ST1_4v | NEONLoadStoreMultiStructPostIndex, 1729 NEON_ST2_post = NEON_ST2 | NEONLoadStoreMultiStructPostIndex, 1730 NEON_ST3_post = NEON_ST3 | NEONLoadStoreMultiStructPostIndex, 1731 NEON_ST4_post = NEON_ST4 | NEONLoadStoreMultiStructPostIndex 1732 }; 1733 1734 enum NEONLoadStoreSingleOp { 1735 NEONLoadStoreSingle1 = 0x00000000, 1736 NEONLoadStoreSingle2 = 0x00200000, 1737 NEONLoadStoreSingle3 = 0x00002000, 1738 NEONLoadStoreSingle4 = 0x00202000, 1739 NEONLoadStoreSingleL = 0x00400000, 1740 NEONLoadStoreSingle_b = 0x00000000, 1741 NEONLoadStoreSingle_h = 0x00004000, 1742 NEONLoadStoreSingle_s = 0x00008000, 1743 NEONLoadStoreSingle_d = 0x00008400, 1744 NEONLoadStoreSingleAllLanes = 0x0000C000, 1745 NEONLoadStoreSingleLenMask = 0x00202000 1746 }; 1747 1748 // NEON load/store single structure. 1749 enum NEONLoadStoreSingleStructOp { 1750 NEONLoadStoreSingleStructFixed = 0x0D000000, 1751 NEONLoadStoreSingleStructFMask = 0xBF9F0000, 1752 NEONLoadStoreSingleStructMask = 0xBFFFE000, 1753 NEONLoadStoreSingleStructStore = NEONLoadStoreSingleStructFixed, 1754 NEONLoadStoreSingleStructLoad = NEONLoadStoreSingleStructFixed | 1755 NEONLoadStoreSingleL, 1756 NEONLoadStoreSingleStructLoad1 = NEONLoadStoreSingle1 | 1757 NEONLoadStoreSingleStructLoad, 1758 NEONLoadStoreSingleStructLoad2 = NEONLoadStoreSingle2 | 1759 NEONLoadStoreSingleStructLoad, 1760 NEONLoadStoreSingleStructLoad3 = NEONLoadStoreSingle3 | 1761 NEONLoadStoreSingleStructLoad, 1762 NEONLoadStoreSingleStructLoad4 = NEONLoadStoreSingle4 | 1763 NEONLoadStoreSingleStructLoad, 1764 NEONLoadStoreSingleStructStore1 = NEONLoadStoreSingle1 | 1765 NEONLoadStoreSingleStructFixed, 1766 NEONLoadStoreSingleStructStore2 = NEONLoadStoreSingle2 | 1767 NEONLoadStoreSingleStructFixed, 1768 NEONLoadStoreSingleStructStore3 = NEONLoadStoreSingle3 | 1769 NEONLoadStoreSingleStructFixed, 1770 NEONLoadStoreSingleStructStore4 = NEONLoadStoreSingle4 | 1771 NEONLoadStoreSingleStructFixed, 1772 NEON_LD1_b = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_b, 1773 NEON_LD1_h = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_h, 1774 NEON_LD1_s = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_s, 1775 NEON_LD1_d = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingle_d, 1776 NEON_LD1R = NEONLoadStoreSingleStructLoad1 | NEONLoadStoreSingleAllLanes, 1777 NEON_ST1_b = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_b, 1778 NEON_ST1_h = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_h, 1779 NEON_ST1_s = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_s, 1780 NEON_ST1_d = NEONLoadStoreSingleStructStore1 | NEONLoadStoreSingle_d, 1781 1782 NEON_LD2_b = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_b, 1783 NEON_LD2_h = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_h, 1784 NEON_LD2_s = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_s, 1785 NEON_LD2_d = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingle_d, 1786 NEON_LD2R = NEONLoadStoreSingleStructLoad2 | NEONLoadStoreSingleAllLanes, 1787 NEON_ST2_b = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_b, 1788 NEON_ST2_h = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_h, 1789 NEON_ST2_s = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_s, 1790 NEON_ST2_d = NEONLoadStoreSingleStructStore2 | NEONLoadStoreSingle_d, 1791 1792 NEON_LD3_b = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_b, 1793 NEON_LD3_h = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_h, 1794 NEON_LD3_s = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_s, 1795 NEON_LD3_d = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingle_d, 1796 NEON_LD3R = NEONLoadStoreSingleStructLoad3 | NEONLoadStoreSingleAllLanes, 1797 NEON_ST3_b = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_b, 1798 NEON_ST3_h = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_h, 1799 NEON_ST3_s = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_s, 1800 NEON_ST3_d = NEONLoadStoreSingleStructStore3 | NEONLoadStoreSingle_d, 1801 1802 NEON_LD4_b = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_b, 1803 NEON_LD4_h = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_h, 1804 NEON_LD4_s = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_s, 1805 NEON_LD4_d = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingle_d, 1806 NEON_LD4R = NEONLoadStoreSingleStructLoad4 | NEONLoadStoreSingleAllLanes, 1807 NEON_ST4_b = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_b, 1808 NEON_ST4_h = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_h, 1809 NEON_ST4_s = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_s, 1810 NEON_ST4_d = NEONLoadStoreSingleStructStore4 | NEONLoadStoreSingle_d 1811 }; 1812 1813 // NEON load/store single structure with post-index addressing. 1814 enum NEONLoadStoreSingleStructPostIndexOp { 1815 NEONLoadStoreSingleStructPostIndexFixed = 0x0D800000, 1816 NEONLoadStoreSingleStructPostIndexFMask = 0xBF800000, 1817 NEONLoadStoreSingleStructPostIndexMask = 0xBFE0E000, 1818 NEONLoadStoreSingleStructPostIndex = 0x00800000, 1819 NEON_LD1_b_post = NEON_LD1_b | NEONLoadStoreSingleStructPostIndex, 1820 NEON_LD1_h_post = NEON_LD1_h | NEONLoadStoreSingleStructPostIndex, 1821 NEON_LD1_s_post = NEON_LD1_s | NEONLoadStoreSingleStructPostIndex, 1822 NEON_LD1_d_post = NEON_LD1_d | NEONLoadStoreSingleStructPostIndex, 1823 NEON_LD1R_post = NEON_LD1R | NEONLoadStoreSingleStructPostIndex, 1824 NEON_ST1_b_post = NEON_ST1_b | NEONLoadStoreSingleStructPostIndex, 1825 NEON_ST1_h_post = NEON_ST1_h | NEONLoadStoreSingleStructPostIndex, 1826 NEON_ST1_s_post = NEON_ST1_s | NEONLoadStoreSingleStructPostIndex, 1827 NEON_ST1_d_post = NEON_ST1_d | NEONLoadStoreSingleStructPostIndex, 1828 1829 NEON_LD2_b_post = NEON_LD2_b | NEONLoadStoreSingleStructPostIndex, 1830 NEON_LD2_h_post = NEON_LD2_h | NEONLoadStoreSingleStructPostIndex, 1831 NEON_LD2_s_post = NEON_LD2_s | NEONLoadStoreSingleStructPostIndex, 1832 NEON_LD2_d_post = NEON_LD2_d | NEONLoadStoreSingleStructPostIndex, 1833 NEON_LD2R_post = NEON_LD2R | NEONLoadStoreSingleStructPostIndex, 1834 NEON_ST2_b_post = NEON_ST2_b | NEONLoadStoreSingleStructPostIndex, 1835 NEON_ST2_h_post = NEON_ST2_h | NEONLoadStoreSingleStructPostIndex, 1836 NEON_ST2_s_post = NEON_ST2_s | NEONLoadStoreSingleStructPostIndex, 1837 NEON_ST2_d_post = NEON_ST2_d | NEONLoadStoreSingleStructPostIndex, 1838 1839 NEON_LD3_b_post = NEON_LD3_b | NEONLoadStoreSingleStructPostIndex, 1840 NEON_LD3_h_post = NEON_LD3_h | NEONLoadStoreSingleStructPostIndex, 1841 NEON_LD3_s_post = NEON_LD3_s | NEONLoadStoreSingleStructPostIndex, 1842 NEON_LD3_d_post = NEON_LD3_d | NEONLoadStoreSingleStructPostIndex, 1843 NEON_LD3R_post = NEON_LD3R | NEONLoadStoreSingleStructPostIndex, 1844 NEON_ST3_b_post = NEON_ST3_b | NEONLoadStoreSingleStructPostIndex, 1845 NEON_ST3_h_post = NEON_ST3_h | NEONLoadStoreSingleStructPostIndex, 1846 NEON_ST3_s_post = NEON_ST3_s | NEONLoadStoreSingleStructPostIndex, 1847 NEON_ST3_d_post = NEON_ST3_d | NEONLoadStoreSingleStructPostIndex, 1848 1849 NEON_LD4_b_post = NEON_LD4_b | NEONLoadStoreSingleStructPostIndex, 1850 NEON_LD4_h_post = NEON_LD4_h | NEONLoadStoreSingleStructPostIndex, 1851 NEON_LD4_s_post = NEON_LD4_s | NEONLoadStoreSingleStructPostIndex, 1852 NEON_LD4_d_post = NEON_LD4_d | NEONLoadStoreSingleStructPostIndex, 1853 NEON_LD4R_post = NEON_LD4R | NEONLoadStoreSingleStructPostIndex, 1854 NEON_ST4_b_post = NEON_ST4_b | NEONLoadStoreSingleStructPostIndex, 1855 NEON_ST4_h_post = NEON_ST4_h | NEONLoadStoreSingleStructPostIndex, 1856 NEON_ST4_s_post = NEON_ST4_s | NEONLoadStoreSingleStructPostIndex, 1857 NEON_ST4_d_post = NEON_ST4_d | NEONLoadStoreSingleStructPostIndex 1858 }; 1859 1860 // NEON modified immediate. 1861 enum NEONModifiedImmediateOp { 1862 NEONModifiedImmediateFixed = 0x0F000400, 1863 NEONModifiedImmediateFMask = 0x9FF80400, 1864 NEONModifiedImmediateOpBit = 0x20000000, 1865 NEONModifiedImmediate_MOVI = NEONModifiedImmediateFixed | 0x00000000, 1866 NEONModifiedImmediate_MVNI = NEONModifiedImmediateFixed | 0x20000000, 1867 NEONModifiedImmediate_ORR = NEONModifiedImmediateFixed | 0x00001000, 1868 NEONModifiedImmediate_BIC = NEONModifiedImmediateFixed | 0x20001000 1869 }; 1870 1871 // NEON shift immediate. 1872 enum NEONShiftImmediateOp { 1873 NEONShiftImmediateFixed = 0x0F000400, 1874 NEONShiftImmediateFMask = 0x9F800400, 1875 NEONShiftImmediateMask = 0xBF80FC00, 1876 NEONShiftImmediateUBit = 0x20000000, 1877 NEON_SHL = NEONShiftImmediateFixed | 0x00005000, 1878 NEON_SSHLL = NEONShiftImmediateFixed | 0x0000A000, 1879 NEON_USHLL = NEONShiftImmediateFixed | 0x2000A000, 1880 NEON_SLI = NEONShiftImmediateFixed | 0x20005000, 1881 NEON_SRI = NEONShiftImmediateFixed | 0x20004000, 1882 NEON_SHRN = NEONShiftImmediateFixed | 0x00008000, 1883 NEON_RSHRN = NEONShiftImmediateFixed | 0x00008800, 1884 NEON_UQSHRN = NEONShiftImmediateFixed | 0x20009000, 1885 NEON_UQRSHRN = NEONShiftImmediateFixed | 0x20009800, 1886 NEON_SQSHRN = NEONShiftImmediateFixed | 0x00009000, 1887 NEON_SQRSHRN = NEONShiftImmediateFixed | 0x00009800, 1888 NEON_SQSHRUN = NEONShiftImmediateFixed | 0x20008000, 1889 NEON_SQRSHRUN = NEONShiftImmediateFixed | 0x20008800, 1890 NEON_SSHR = NEONShiftImmediateFixed | 0x00000000, 1891 NEON_SRSHR = NEONShiftImmediateFixed | 0x00002000, 1892 NEON_USHR = NEONShiftImmediateFixed | 0x20000000, 1893 NEON_URSHR = NEONShiftImmediateFixed | 0x20002000, 1894 NEON_SSRA = NEONShiftImmediateFixed | 0x00001000, 1895 NEON_SRSRA = NEONShiftImmediateFixed | 0x00003000, 1896 NEON_USRA = NEONShiftImmediateFixed | 0x20001000, 1897 NEON_URSRA = NEONShiftImmediateFixed | 0x20003000, 1898 NEON_SQSHLU = NEONShiftImmediateFixed | 0x20006000, 1899 NEON_SCVTF_imm = NEONShiftImmediateFixed | 0x0000E000, 1900 NEON_UCVTF_imm = NEONShiftImmediateFixed | 0x2000E000, 1901 NEON_FCVTZS_imm = NEONShiftImmediateFixed | 0x0000F800, 1902 NEON_FCVTZU_imm = NEONShiftImmediateFixed | 0x2000F800, 1903 NEON_SQSHL_imm = NEONShiftImmediateFixed | 0x00007000, 1904 NEON_UQSHL_imm = NEONShiftImmediateFixed | 0x20007000 1905 }; 1906 1907 // NEON table. 1908 enum NEONTableOp { 1909 NEONTableFixed = 0x0E000000, 1910 NEONTableFMask = 0xBF208C00, 1911 NEONTableExt = 0x00001000, 1912 NEONTableMask = 0xBF20FC00, 1913 NEON_TBL_1v = NEONTableFixed | 0x00000000, 1914 NEON_TBL_2v = NEONTableFixed | 0x00002000, 1915 NEON_TBL_3v = NEONTableFixed | 0x00004000, 1916 NEON_TBL_4v = NEONTableFixed | 0x00006000, 1917 NEON_TBX_1v = NEON_TBL_1v | NEONTableExt, 1918 NEON_TBX_2v = NEON_TBL_2v | NEONTableExt, 1919 NEON_TBX_3v = NEON_TBL_3v | NEONTableExt, 1920 NEON_TBX_4v = NEON_TBL_4v | NEONTableExt 1921 }; 1922 1923 // NEON perm. 1924 enum NEONPermOp { 1925 NEONPermFixed = 0x0E000800, 1926 NEONPermFMask = 0xBF208C00, 1927 NEONPermMask = 0x3F20FC00, 1928 NEON_UZP1 = NEONPermFixed | 0x00001000, 1929 NEON_TRN1 = NEONPermFixed | 0x00002000, 1930 NEON_ZIP1 = NEONPermFixed | 0x00003000, 1931 NEON_UZP2 = NEONPermFixed | 0x00005000, 1932 NEON_TRN2 = NEONPermFixed | 0x00006000, 1933 NEON_ZIP2 = NEONPermFixed | 0x00007000 1934 }; 1935 1936 // NEON scalar instructions with two register operands. 1937 enum NEONScalar2RegMiscOp { 1938 NEONScalar2RegMiscFixed = 0x5E200800, 1939 NEONScalar2RegMiscFMask = 0xDF3E0C00, 1940 NEONScalar2RegMiscMask = NEON_Q | NEONScalar | NEON2RegMiscMask, 1941 NEON_CMGT_zero_scalar = NEON_Q | NEONScalar | NEON_CMGT_zero, 1942 NEON_CMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_CMEQ_zero, 1943 NEON_CMLT_zero_scalar = NEON_Q | NEONScalar | NEON_CMLT_zero, 1944 NEON_CMGE_zero_scalar = NEON_Q | NEONScalar | NEON_CMGE_zero, 1945 NEON_CMLE_zero_scalar = NEON_Q | NEONScalar | NEON_CMLE_zero, 1946 NEON_ABS_scalar = NEON_Q | NEONScalar | NEON_ABS, 1947 NEON_SQABS_scalar = NEON_Q | NEONScalar | NEON_SQABS, 1948 NEON_NEG_scalar = NEON_Q | NEONScalar | NEON_NEG, 1949 NEON_SQNEG_scalar = NEON_Q | NEONScalar | NEON_SQNEG, 1950 NEON_SQXTN_scalar = NEON_Q | NEONScalar | NEON_SQXTN, 1951 NEON_UQXTN_scalar = NEON_Q | NEONScalar | NEON_UQXTN, 1952 NEON_SQXTUN_scalar = NEON_Q | NEONScalar | NEON_SQXTUN, 1953 NEON_SUQADD_scalar = NEON_Q | NEONScalar | NEON_SUQADD, 1954 NEON_USQADD_scalar = NEON_Q | NEONScalar | NEON_USQADD, 1955 1956 NEONScalar2RegMiscOpcode = NEON2RegMiscOpcode, 1957 NEON_NEG_scalar_opcode = NEON_NEG_scalar & NEONScalar2RegMiscOpcode, 1958 1959 NEONScalar2RegMiscFPMask = NEONScalar2RegMiscMask | 0x00800000, 1960 NEON_FRSQRTE_scalar = NEON_Q | NEONScalar | NEON_FRSQRTE, 1961 NEON_FRECPE_scalar = NEON_Q | NEONScalar | NEON_FRECPE, 1962 NEON_SCVTF_scalar = NEON_Q | NEONScalar | NEON_SCVTF, 1963 NEON_UCVTF_scalar = NEON_Q | NEONScalar | NEON_UCVTF, 1964 NEON_FCMGT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGT_zero, 1965 NEON_FCMEQ_zero_scalar = NEON_Q | NEONScalar | NEON_FCMEQ_zero, 1966 NEON_FCMLT_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLT_zero, 1967 NEON_FCMGE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMGE_zero, 1968 NEON_FCMLE_zero_scalar = NEON_Q | NEONScalar | NEON_FCMLE_zero, 1969 NEON_FRECPX_scalar = NEONScalar2RegMiscFixed | 0x0081F000, 1970 NEON_FCVTNS_scalar = NEON_Q | NEONScalar | NEON_FCVTNS, 1971 NEON_FCVTNU_scalar = NEON_Q | NEONScalar | NEON_FCVTNU, 1972 NEON_FCVTPS_scalar = NEON_Q | NEONScalar | NEON_FCVTPS, 1973 NEON_FCVTPU_scalar = NEON_Q | NEONScalar | NEON_FCVTPU, 1974 NEON_FCVTMS_scalar = NEON_Q | NEONScalar | NEON_FCVTMS, 1975 NEON_FCVTMU_scalar = NEON_Q | NEONScalar | NEON_FCVTMU, 1976 NEON_FCVTZS_scalar = NEON_Q | NEONScalar | NEON_FCVTZS, 1977 NEON_FCVTZU_scalar = NEON_Q | NEONScalar | NEON_FCVTZU, 1978 NEON_FCVTAS_scalar = NEON_Q | NEONScalar | NEON_FCVTAS, 1979 NEON_FCVTAU_scalar = NEON_Q | NEONScalar | NEON_FCVTAU, 1980 NEON_FCVTXN_scalar = NEON_Q | NEONScalar | NEON_FCVTXN 1981 }; 1982 1983 // NEON scalar instructions with three same-type operands. 1984 enum NEONScalar3SameOp { 1985 NEONScalar3SameFixed = 0x5E200400, 1986 NEONScalar3SameFMask = 0xDF200400, 1987 NEONScalar3SameMask = 0xFF20FC00, 1988 NEON_ADD_scalar = NEON_Q | NEONScalar | NEON_ADD, 1989 NEON_CMEQ_scalar = NEON_Q | NEONScalar | NEON_CMEQ, 1990 NEON_CMGE_scalar = NEON_Q | NEONScalar | NEON_CMGE, 1991 NEON_CMGT_scalar = NEON_Q | NEONScalar | NEON_CMGT, 1992 NEON_CMHI_scalar = NEON_Q | NEONScalar | NEON_CMHI, 1993 NEON_CMHS_scalar = NEON_Q | NEONScalar | NEON_CMHS, 1994 NEON_CMTST_scalar = NEON_Q | NEONScalar | NEON_CMTST, 1995 NEON_SUB_scalar = NEON_Q | NEONScalar | NEON_SUB, 1996 NEON_UQADD_scalar = NEON_Q | NEONScalar | NEON_UQADD, 1997 NEON_SQADD_scalar = NEON_Q | NEONScalar | NEON_SQADD, 1998 NEON_UQSUB_scalar = NEON_Q | NEONScalar | NEON_UQSUB, 1999 NEON_SQSUB_scalar = NEON_Q | NEONScalar | NEON_SQSUB, 2000 NEON_USHL_scalar = NEON_Q | NEONScalar | NEON_USHL, 2001 NEON_SSHL_scalar = NEON_Q | NEONScalar | NEON_SSHL, 2002 NEON_UQSHL_scalar = NEON_Q | NEONScalar | NEON_UQSHL, 2003 NEON_SQSHL_scalar = NEON_Q | NEONScalar | NEON_SQSHL, 2004 NEON_URSHL_scalar = NEON_Q | NEONScalar | NEON_URSHL, 2005 NEON_SRSHL_scalar = NEON_Q | NEONScalar | NEON_SRSHL, 2006 NEON_UQRSHL_scalar = NEON_Q | NEONScalar | NEON_UQRSHL, 2007 NEON_SQRSHL_scalar = NEON_Q | NEONScalar | NEON_SQRSHL, 2008 NEON_SQDMULH_scalar = NEON_Q | NEONScalar | NEON_SQDMULH, 2009 NEON_SQRDMULH_scalar = NEON_Q | NEONScalar | NEON_SQRDMULH, 2010 2011 // NEON floating point scalar instructions with three same-type operands. 2012 NEONScalar3SameFPFixed = NEONScalar3SameFixed | 0x0000C000, 2013 NEONScalar3SameFPFMask = NEONScalar3SameFMask | 0x0000C000, 2014 NEONScalar3SameFPMask = NEONScalar3SameMask | 0x00800000, 2015 NEON_FACGE_scalar = NEON_Q | NEONScalar | NEON_FACGE, 2016 NEON_FACGT_scalar = NEON_Q | NEONScalar | NEON_FACGT, 2017 NEON_FCMEQ_scalar = NEON_Q | NEONScalar | NEON_FCMEQ, 2018 NEON_FCMGE_scalar = NEON_Q | NEONScalar | NEON_FCMGE, 2019 NEON_FCMGT_scalar = NEON_Q | NEONScalar | NEON_FCMGT, 2020 NEON_FMULX_scalar = NEON_Q | NEONScalar | NEON_FMULX, 2021 NEON_FRECPS_scalar = NEON_Q | NEONScalar | NEON_FRECPS, 2022 NEON_FRSQRTS_scalar = NEON_Q | NEONScalar | NEON_FRSQRTS, 2023 NEON_FABD_scalar = NEON_Q | NEONScalar | NEON_FABD 2024 }; 2025 2026 // NEON scalar instructions with three different-type operands. 2027 enum NEONScalar3DiffOp { 2028 NEONScalar3DiffFixed = 0x5E200000, 2029 NEONScalar3DiffFMask = 0xDF200C00, 2030 NEONScalar3DiffMask = NEON_Q | NEONScalar | NEON3DifferentMask, 2031 NEON_SQDMLAL_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL, 2032 NEON_SQDMLSL_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL, 2033 NEON_SQDMULL_scalar = NEON_Q | NEONScalar | NEON_SQDMULL 2034 }; 2035 2036 // NEON scalar instructions with indexed element operand. 2037 enum NEONScalarByIndexedElementOp { 2038 NEONScalarByIndexedElementFixed = 0x5F000000, 2039 NEONScalarByIndexedElementFMask = 0xDF000400, 2040 NEONScalarByIndexedElementMask = 0xFF00F400, 2041 NEON_SQDMLAL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLAL_byelement, 2042 NEON_SQDMLSL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMLSL_byelement, 2043 NEON_SQDMULL_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULL_byelement, 2044 NEON_SQDMULH_byelement_scalar = NEON_Q | NEONScalar | NEON_SQDMULH_byelement, 2045 NEON_SQRDMULH_byelement_scalar 2046 = NEON_Q | NEONScalar | NEON_SQRDMULH_byelement, 2047 2048 // Floating point instructions. 2049 NEONScalarByIndexedElementFPFixed 2050 = NEONScalarByIndexedElementFixed | 0x00800000, 2051 NEONScalarByIndexedElementFPMask 2052 = NEONScalarByIndexedElementMask | 0x00800000, 2053 NEON_FMLA_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLA_byelement, 2054 NEON_FMLS_byelement_scalar = NEON_Q | NEONScalar | NEON_FMLS_byelement, 2055 NEON_FMUL_byelement_scalar = NEON_Q | NEONScalar | NEON_FMUL_byelement, 2056 NEON_FMULX_byelement_scalar = NEON_Q | NEONScalar | NEON_FMULX_byelement 2057 }; 2058 2059 // NEON scalar register copy. 2060 enum NEONScalarCopyOp { 2061 NEONScalarCopyFixed = 0x5E000400, 2062 NEONScalarCopyFMask = 0xDFE08400, 2063 NEONScalarCopyMask = 0xFFE0FC00, 2064 NEON_DUP_ELEMENT_scalar = NEON_Q | NEONScalar | NEON_DUP_ELEMENT 2065 }; 2066 2067 // NEON scalar pairwise instructions. 2068 enum NEONScalarPairwiseOp { 2069 NEONScalarPairwiseFixed = 0x5E300800, 2070 NEONScalarPairwiseFMask = 0xDF3E0C00, 2071 NEONScalarPairwiseMask = 0xFFB1F800, 2072 NEON_ADDP_scalar = NEONScalarPairwiseFixed | 0x0081B000, 2073 NEON_FMAXNMP_scalar = NEONScalarPairwiseFixed | 0x2000C000, 2074 NEON_FMINNMP_scalar = NEONScalarPairwiseFixed | 0x2080C000, 2075 NEON_FADDP_scalar = NEONScalarPairwiseFixed | 0x2000D000, 2076 NEON_FMAXP_scalar = NEONScalarPairwiseFixed | 0x2000F000, 2077 NEON_FMINP_scalar = NEONScalarPairwiseFixed | 0x2080F000 2078 }; 2079 2080 // NEON scalar shift immediate. 2081 enum NEONScalarShiftImmediateOp { 2082 NEONScalarShiftImmediateFixed = 0x5F000400, 2083 NEONScalarShiftImmediateFMask = 0xDF800400, 2084 NEONScalarShiftImmediateMask = 0xFF80FC00, 2085 NEON_SHL_scalar = NEON_Q | NEONScalar | NEON_SHL, 2086 NEON_SLI_scalar = NEON_Q | NEONScalar | NEON_SLI, 2087 NEON_SRI_scalar = NEON_Q | NEONScalar | NEON_SRI, 2088 NEON_SSHR_scalar = NEON_Q | NEONScalar | NEON_SSHR, 2089 NEON_USHR_scalar = NEON_Q | NEONScalar | NEON_USHR, 2090 NEON_SRSHR_scalar = NEON_Q | NEONScalar | NEON_SRSHR, 2091 NEON_URSHR_scalar = NEON_Q | NEONScalar | NEON_URSHR, 2092 NEON_SSRA_scalar = NEON_Q | NEONScalar | NEON_SSRA, 2093 NEON_USRA_scalar = NEON_Q | NEONScalar | NEON_USRA, 2094 NEON_SRSRA_scalar = NEON_Q | NEONScalar | NEON_SRSRA, 2095 NEON_URSRA_scalar = NEON_Q | NEONScalar | NEON_URSRA, 2096 NEON_UQSHRN_scalar = NEON_Q | NEONScalar | NEON_UQSHRN, 2097 NEON_UQRSHRN_scalar = NEON_Q | NEONScalar | NEON_UQRSHRN, 2098 NEON_SQSHRN_scalar = NEON_Q | NEONScalar | NEON_SQSHRN, 2099 NEON_SQRSHRN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRN, 2100 NEON_SQSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQSHRUN, 2101 NEON_SQRSHRUN_scalar = NEON_Q | NEONScalar | NEON_SQRSHRUN, 2102 NEON_SQSHLU_scalar = NEON_Q | NEONScalar | NEON_SQSHLU, 2103 NEON_SQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_SQSHL_imm, 2104 NEON_UQSHL_imm_scalar = NEON_Q | NEONScalar | NEON_UQSHL_imm, 2105 NEON_SCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_SCVTF_imm, 2106 NEON_UCVTF_imm_scalar = NEON_Q | NEONScalar | NEON_UCVTF_imm, 2107 NEON_FCVTZS_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZS_imm, 2108 NEON_FCVTZU_imm_scalar = NEON_Q | NEONScalar | NEON_FCVTZU_imm 2109 }; 2110 2111 // Unimplemented and unallocated instructions. These are defined to make fixed 2112 // bit assertion easier. 2113 enum UnimplementedOp { 2114 UnimplementedFixed = 0x00000000, 2115 UnimplementedFMask = 0x00000000 2116 }; 2117 2118 enum UnallocatedOp { 2119 UnallocatedFixed = 0x00000000, 2120 UnallocatedFMask = 0x00000000 2121 }; 2122 2123 // Re-enable `clang-format` after the `enum`s. 2124 // clang-format on 2125 2126 } // namespace aarch64 2127 } // namespace vixl 2128 2129 #endif // VIXL_AARCH64_CONSTANTS_AARCH64_H_ 2130
