1 //===-- X86ISelLowering.cpp - X86 DAG Lowering Implementation -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file defines the interfaces that X86 uses to lower LLVM code into a 11 // selection DAG. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #define DEBUG_TYPE "x86-isel" 16 #include "X86.h" 17 #include "X86InstrBuilder.h" 18 #include "X86ISelLowering.h" 19 #include "X86TargetMachine.h" 20 #include "X86TargetObjectFile.h" 21 #include "Utils/X86ShuffleDecode.h" 22 #include "llvm/CallingConv.h" 23 #include "llvm/Constants.h" 24 #include "llvm/DerivedTypes.h" 25 #include "llvm/GlobalAlias.h" 26 #include "llvm/GlobalVariable.h" 27 #include "llvm/Function.h" 28 #include "llvm/Instructions.h" 29 #include "llvm/Intrinsics.h" 30 #include "llvm/LLVMContext.h" 31 #include "llvm/CodeGen/IntrinsicLowering.h" 32 #include "llvm/CodeGen/MachineFrameInfo.h" 33 #include "llvm/CodeGen/MachineFunction.h" 34 #include "llvm/CodeGen/MachineInstrBuilder.h" 35 #include "llvm/CodeGen/MachineJumpTableInfo.h" 36 #include "llvm/CodeGen/MachineModuleInfo.h" 37 #include "llvm/CodeGen/MachineRegisterInfo.h" 38 #include "llvm/CodeGen/PseudoSourceValue.h" 39 #include "llvm/MC/MCAsmInfo.h" 40 #include "llvm/MC/MCContext.h" 41 #include "llvm/MC/MCExpr.h" 42 #include "llvm/MC/MCSymbol.h" 43 #include "llvm/ADT/BitVector.h" 44 #include "llvm/ADT/SmallSet.h" 45 #include "llvm/ADT/Statistic.h" 46 #include "llvm/ADT/StringExtras.h" 47 #include "llvm/ADT/VectorExtras.h" 48 #include "llvm/Support/CallSite.h" 49 #include "llvm/Support/Debug.h" 50 #include "llvm/Support/Dwarf.h" 51 #include "llvm/Support/ErrorHandling.h" 52 #include "llvm/Support/MathExtras.h" 53 #include "llvm/Support/raw_ostream.h" 54 #include "llvm/Target/TargetOptions.h" 55 using namespace llvm; 56 using namespace dwarf; 57 58 STATISTIC(NumTailCalls, "Number of tail calls"); 59 60 // Forward declarations. 61 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 62 SDValue V2); 63 64 static SDValue Insert128BitVector(SDValue Result, 65 SDValue Vec, 66 SDValue Idx, 67 SelectionDAG &DAG, 68 DebugLoc dl); 69 70 static SDValue Extract128BitVector(SDValue Vec, 71 SDValue Idx, 72 SelectionDAG &DAG, 73 DebugLoc dl); 74 75 /// Generate a DAG to grab 128-bits from a vector > 128 bits. This 76 /// sets things up to match to an AVX VEXTRACTF128 instruction or a 77 /// simple subregister reference. Idx is an index in the 128 bits we 78 /// want. It need not be aligned to a 128-bit bounday. That makes 79 /// lowering EXTRACT_VECTOR_ELT operations easier. 80 static SDValue Extract128BitVector(SDValue Vec, 81 SDValue Idx, 82 SelectionDAG &DAG, 83 DebugLoc dl) { 84 EVT VT = Vec.getValueType(); 85 assert(VT.getSizeInBits() == 256 && "Unexpected vector size!"); 86 EVT ElVT = VT.getVectorElementType(); 87 int Factor = VT.getSizeInBits()/128; 88 EVT ResultVT = EVT::getVectorVT(*DAG.getContext(), ElVT, 89 VT.getVectorNumElements()/Factor); 90 91 // Extract from UNDEF is UNDEF. 92 if (Vec.getOpcode() == ISD::UNDEF) 93 return DAG.getNode(ISD::UNDEF, dl, ResultVT); 94 95 if (isa<ConstantSDNode>(Idx)) { 96 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 97 98 // Extract the relevant 128 bits. Generate an EXTRACT_SUBVECTOR 99 // we can match to VEXTRACTF128. 100 unsigned ElemsPerChunk = 128 / ElVT.getSizeInBits(); 101 102 // This is the index of the first element of the 128-bit chunk 103 // we want. 104 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits()) / 128) 105 * ElemsPerChunk); 106 107 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 108 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, 109 VecIdx); 110 111 return Result; 112 } 113 114 return SDValue(); 115 } 116 117 /// Generate a DAG to put 128-bits into a vector > 128 bits. This 118 /// sets things up to match to an AVX VINSERTF128 instruction or a 119 /// simple superregister reference. Idx is an index in the 128 bits 120 /// we want. It need not be aligned to a 128-bit bounday. That makes 121 /// lowering INSERT_VECTOR_ELT operations easier. 122 static SDValue Insert128BitVector(SDValue Result, 123 SDValue Vec, 124 SDValue Idx, 125 SelectionDAG &DAG, 126 DebugLoc dl) { 127 if (isa<ConstantSDNode>(Idx)) { 128 EVT VT = Vec.getValueType(); 129 assert(VT.getSizeInBits() == 128 && "Unexpected vector size!"); 130 131 EVT ElVT = VT.getVectorElementType(); 132 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 133 EVT ResultVT = Result.getValueType(); 134 135 // Insert the relevant 128 bits. 136 unsigned ElemsPerChunk = 128/ElVT.getSizeInBits(); 137 138 // This is the index of the first element of the 128-bit chunk 139 // we want. 140 unsigned NormalizedIdxVal = (((IdxVal * ElVT.getSizeInBits())/128) 141 * ElemsPerChunk); 142 143 SDValue VecIdx = DAG.getConstant(NormalizedIdxVal, MVT::i32); 144 Result = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, 145 VecIdx); 146 return Result; 147 } 148 149 return SDValue(); 150 } 151 152 static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) { 153 const X86Subtarget *Subtarget = &TM.getSubtarget<X86Subtarget>(); 154 bool is64Bit = Subtarget->is64Bit(); 155 156 if (Subtarget->isTargetEnvMacho()) { 157 if (is64Bit) 158 return new X8664_MachoTargetObjectFile(); 159 return new TargetLoweringObjectFileMachO(); 160 } 161 162 if (Subtarget->isTargetELF()) 163 return new TargetLoweringObjectFileELF(); 164 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 165 return new TargetLoweringObjectFileCOFF(); 166 llvm_unreachable("unknown subtarget type"); 167 } 168 169 X86TargetLowering::X86TargetLowering(X86TargetMachine &TM) 170 : TargetLowering(TM, createTLOF(TM)) { 171 Subtarget = &TM.getSubtarget<X86Subtarget>(); 172 X86ScalarSSEf64 = Subtarget->hasXMMInt(); 173 X86ScalarSSEf32 = Subtarget->hasXMM(); 174 X86StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP; 175 176 RegInfo = TM.getRegisterInfo(); 177 TD = getTargetData(); 178 179 // Set up the TargetLowering object. 180 static MVT IntVTs[] = { MVT::i8, MVT::i16, MVT::i32, MVT::i64 }; 181 182 // X86 is weird, it always uses i8 for shift amounts and setcc results. 183 setBooleanContents(ZeroOrOneBooleanContent); 184 // X86-SSE is even stranger. It uses -1 or 0 for vector masks. 185 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent); 186 187 // For 64-bit since we have so many registers use the ILP scheduler, for 188 // 32-bit code use the register pressure specific scheduling. 189 if (Subtarget->is64Bit()) 190 setSchedulingPreference(Sched::ILP); 191 else 192 setSchedulingPreference(Sched::RegPressure); 193 setStackPointerRegisterToSaveRestore(X86StackPtr); 194 195 if (Subtarget->isTargetWindows() && !Subtarget->isTargetCygMing()) { 196 // Setup Windows compiler runtime calls. 197 setLibcallName(RTLIB::SDIV_I64, "_alldiv"); 198 setLibcallName(RTLIB::UDIV_I64, "_aulldiv"); 199 setLibcallName(RTLIB::SREM_I64, "_allrem"); 200 setLibcallName(RTLIB::UREM_I64, "_aullrem"); 201 setLibcallName(RTLIB::MUL_I64, "_allmul"); 202 setLibcallName(RTLIB::FPTOUINT_F64_I64, "_ftol2"); 203 setLibcallName(RTLIB::FPTOUINT_F32_I64, "_ftol2"); 204 setLibcallCallingConv(RTLIB::SDIV_I64, CallingConv::X86_StdCall); 205 setLibcallCallingConv(RTLIB::UDIV_I64, CallingConv::X86_StdCall); 206 setLibcallCallingConv(RTLIB::SREM_I64, CallingConv::X86_StdCall); 207 setLibcallCallingConv(RTLIB::UREM_I64, CallingConv::X86_StdCall); 208 setLibcallCallingConv(RTLIB::MUL_I64, CallingConv::X86_StdCall); 209 setLibcallCallingConv(RTLIB::FPTOUINT_F64_I64, CallingConv::C); 210 setLibcallCallingConv(RTLIB::FPTOUINT_F32_I64, CallingConv::C); 211 } 212 213 if (Subtarget->isTargetDarwin()) { 214 // Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 215 setUseUnderscoreSetJmp(false); 216 setUseUnderscoreLongJmp(false); 217 } else if (Subtarget->isTargetMingw()) { 218 // MS runtime is weird: it exports _setjmp, but longjmp! 219 setUseUnderscoreSetJmp(true); 220 setUseUnderscoreLongJmp(false); 221 } else { 222 setUseUnderscoreSetJmp(true); 223 setUseUnderscoreLongJmp(true); 224 } 225 226 // Set up the register classes. 227 addRegisterClass(MVT::i8, X86::GR8RegisterClass); 228 addRegisterClass(MVT::i16, X86::GR16RegisterClass); 229 addRegisterClass(MVT::i32, X86::GR32RegisterClass); 230 if (Subtarget->is64Bit()) 231 addRegisterClass(MVT::i64, X86::GR64RegisterClass); 232 233 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); 234 235 // We don't accept any truncstore of integer registers. 236 setTruncStoreAction(MVT::i64, MVT::i32, Expand); 237 setTruncStoreAction(MVT::i64, MVT::i16, Expand); 238 setTruncStoreAction(MVT::i64, MVT::i8 , Expand); 239 setTruncStoreAction(MVT::i32, MVT::i16, Expand); 240 setTruncStoreAction(MVT::i32, MVT::i8 , Expand); 241 setTruncStoreAction(MVT::i16, MVT::i8, Expand); 242 243 // SETOEQ and SETUNE require checking two conditions. 244 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); 245 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); 246 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); 247 setCondCodeAction(ISD::SETUNE, MVT::f32, Expand); 248 setCondCodeAction(ISD::SETUNE, MVT::f64, Expand); 249 setCondCodeAction(ISD::SETUNE, MVT::f80, Expand); 250 251 // Promote all UINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have this 252 // operation. 253 setOperationAction(ISD::UINT_TO_FP , MVT::i1 , Promote); 254 setOperationAction(ISD::UINT_TO_FP , MVT::i8 , Promote); 255 setOperationAction(ISD::UINT_TO_FP , MVT::i16 , Promote); 256 257 if (Subtarget->is64Bit()) { 258 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Promote); 259 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Expand); 260 } else if (!UseSoftFloat) { 261 // We have an algorithm for SSE2->double, and we turn this into a 262 // 64-bit FILD followed by conditional FADD for other targets. 263 setOperationAction(ISD::UINT_TO_FP , MVT::i64 , Custom); 264 // We have an algorithm for SSE2, and we turn this into a 64-bit 265 // FILD for other targets. 266 setOperationAction(ISD::UINT_TO_FP , MVT::i32 , Custom); 267 } 268 269 // Promote i1/i8 SINT_TO_FP to larger SINT_TO_FP's, as X86 doesn't have 270 // this operation. 271 setOperationAction(ISD::SINT_TO_FP , MVT::i1 , Promote); 272 setOperationAction(ISD::SINT_TO_FP , MVT::i8 , Promote); 273 274 if (!UseSoftFloat) { 275 // SSE has no i16 to fp conversion, only i32 276 if (X86ScalarSSEf32) { 277 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 278 // f32 and f64 cases are Legal, f80 case is not 279 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 280 } else { 281 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Custom); 282 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Custom); 283 } 284 } else { 285 setOperationAction(ISD::SINT_TO_FP , MVT::i16 , Promote); 286 setOperationAction(ISD::SINT_TO_FP , MVT::i32 , Promote); 287 } 288 289 // In 32-bit mode these are custom lowered. In 64-bit mode F32 and F64 290 // are Legal, f80 is custom lowered. 291 setOperationAction(ISD::FP_TO_SINT , MVT::i64 , Custom); 292 setOperationAction(ISD::SINT_TO_FP , MVT::i64 , Custom); 293 294 // Promote i1/i8 FP_TO_SINT to larger FP_TO_SINTS's, as X86 doesn't have 295 // this operation. 296 setOperationAction(ISD::FP_TO_SINT , MVT::i1 , Promote); 297 setOperationAction(ISD::FP_TO_SINT , MVT::i8 , Promote); 298 299 if (X86ScalarSSEf32) { 300 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Promote); 301 // f32 and f64 cases are Legal, f80 case is not 302 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 303 } else { 304 setOperationAction(ISD::FP_TO_SINT , MVT::i16 , Custom); 305 setOperationAction(ISD::FP_TO_SINT , MVT::i32 , Custom); 306 } 307 308 // Handle FP_TO_UINT by promoting the destination to a larger signed 309 // conversion. 310 setOperationAction(ISD::FP_TO_UINT , MVT::i1 , Promote); 311 setOperationAction(ISD::FP_TO_UINT , MVT::i8 , Promote); 312 setOperationAction(ISD::FP_TO_UINT , MVT::i16 , Promote); 313 314 if (Subtarget->is64Bit()) { 315 setOperationAction(ISD::FP_TO_UINT , MVT::i64 , Expand); 316 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Promote); 317 } else if (!UseSoftFloat) { 318 // Since AVX is a superset of SSE3, only check for SSE here. 319 if (Subtarget->hasSSE1() && !Subtarget->hasSSE3()) 320 // Expand FP_TO_UINT into a select. 321 // FIXME: We would like to use a Custom expander here eventually to do 322 // the optimal thing for SSE vs. the default expansion in the legalizer. 323 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Expand); 324 else 325 // With SSE3 we can use fisttpll to convert to a signed i64; without 326 // SSE, we're stuck with a fistpll. 327 setOperationAction(ISD::FP_TO_UINT , MVT::i32 , Custom); 328 } 329 330 // TODO: when we have SSE, these could be more efficient, by using movd/movq. 331 if (!X86ScalarSSEf64) { 332 setOperationAction(ISD::BITCAST , MVT::f32 , Expand); 333 setOperationAction(ISD::BITCAST , MVT::i32 , Expand); 334 if (Subtarget->is64Bit()) { 335 setOperationAction(ISD::BITCAST , MVT::f64 , Expand); 336 // Without SSE, i64->f64 goes through memory. 337 setOperationAction(ISD::BITCAST , MVT::i64 , Expand); 338 } 339 } 340 341 // Scalar integer divide and remainder are lowered to use operations that 342 // produce two results, to match the available instructions. This exposes 343 // the two-result form to trivial CSE, which is able to combine x/y and x%y 344 // into a single instruction. 345 // 346 // Scalar integer multiply-high is also lowered to use two-result 347 // operations, to match the available instructions. However, plain multiply 348 // (low) operations are left as Legal, as there are single-result 349 // instructions for this in x86. Using the two-result multiply instructions 350 // when both high and low results are needed must be arranged by dagcombine. 351 for (unsigned i = 0, e = 4; i != e; ++i) { 352 MVT VT = IntVTs[i]; 353 setOperationAction(ISD::MULHS, VT, Expand); 354 setOperationAction(ISD::MULHU, VT, Expand); 355 setOperationAction(ISD::SDIV, VT, Expand); 356 setOperationAction(ISD::UDIV, VT, Expand); 357 setOperationAction(ISD::SREM, VT, Expand); 358 setOperationAction(ISD::UREM, VT, Expand); 359 360 // Add/Sub overflow ops with MVT::Glues are lowered to EFLAGS dependences. 361 setOperationAction(ISD::ADDC, VT, Custom); 362 setOperationAction(ISD::ADDE, VT, Custom); 363 setOperationAction(ISD::SUBC, VT, Custom); 364 setOperationAction(ISD::SUBE, VT, Custom); 365 } 366 367 setOperationAction(ISD::BR_JT , MVT::Other, Expand); 368 setOperationAction(ISD::BRCOND , MVT::Other, Custom); 369 setOperationAction(ISD::BR_CC , MVT::Other, Expand); 370 setOperationAction(ISD::SELECT_CC , MVT::Other, Expand); 371 if (Subtarget->is64Bit()) 372 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal); 373 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Legal); 374 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal); 375 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1 , Expand); 376 setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); 377 setOperationAction(ISD::FREM , MVT::f32 , Expand); 378 setOperationAction(ISD::FREM , MVT::f64 , Expand); 379 setOperationAction(ISD::FREM , MVT::f80 , Expand); 380 setOperationAction(ISD::FLT_ROUNDS_ , MVT::i32 , Custom); 381 382 if (Subtarget->hasBMI()) { 383 setOperationAction(ISD::CTTZ , MVT::i8 , Promote); 384 } else { 385 setOperationAction(ISD::CTTZ , MVT::i8 , Custom); 386 setOperationAction(ISD::CTTZ , MVT::i16 , Custom); 387 setOperationAction(ISD::CTTZ , MVT::i32 , Custom); 388 if (Subtarget->is64Bit()) 389 setOperationAction(ISD::CTTZ , MVT::i64 , Custom); 390 } 391 392 if (Subtarget->hasLZCNT()) { 393 setOperationAction(ISD::CTLZ , MVT::i8 , Promote); 394 } else { 395 setOperationAction(ISD::CTLZ , MVT::i8 , Custom); 396 setOperationAction(ISD::CTLZ , MVT::i16 , Custom); 397 setOperationAction(ISD::CTLZ , MVT::i32 , Custom); 398 if (Subtarget->is64Bit()) 399 setOperationAction(ISD::CTLZ , MVT::i64 , Custom); 400 } 401 402 if (Subtarget->hasPOPCNT()) { 403 setOperationAction(ISD::CTPOP , MVT::i8 , Promote); 404 } else { 405 setOperationAction(ISD::CTPOP , MVT::i8 , Expand); 406 setOperationAction(ISD::CTPOP , MVT::i16 , Expand); 407 setOperationAction(ISD::CTPOP , MVT::i32 , Expand); 408 if (Subtarget->is64Bit()) 409 setOperationAction(ISD::CTPOP , MVT::i64 , Expand); 410 } 411 412 setOperationAction(ISD::READCYCLECOUNTER , MVT::i64 , Custom); 413 setOperationAction(ISD::BSWAP , MVT::i16 , Expand); 414 415 // These should be promoted to a larger select which is supported. 416 setOperationAction(ISD::SELECT , MVT::i1 , Promote); 417 // X86 wants to expand cmov itself. 418 setOperationAction(ISD::SELECT , MVT::i8 , Custom); 419 setOperationAction(ISD::SELECT , MVT::i16 , Custom); 420 setOperationAction(ISD::SELECT , MVT::i32 , Custom); 421 setOperationAction(ISD::SELECT , MVT::f32 , Custom); 422 setOperationAction(ISD::SELECT , MVT::f64 , Custom); 423 setOperationAction(ISD::SELECT , MVT::f80 , Custom); 424 setOperationAction(ISD::SETCC , MVT::i8 , Custom); 425 setOperationAction(ISD::SETCC , MVT::i16 , Custom); 426 setOperationAction(ISD::SETCC , MVT::i32 , Custom); 427 setOperationAction(ISD::SETCC , MVT::f32 , Custom); 428 setOperationAction(ISD::SETCC , MVT::f64 , Custom); 429 setOperationAction(ISD::SETCC , MVT::f80 , Custom); 430 if (Subtarget->is64Bit()) { 431 setOperationAction(ISD::SELECT , MVT::i64 , Custom); 432 setOperationAction(ISD::SETCC , MVT::i64 , Custom); 433 } 434 setOperationAction(ISD::EH_RETURN , MVT::Other, Custom); 435 436 // Darwin ABI issue. 437 setOperationAction(ISD::ConstantPool , MVT::i32 , Custom); 438 setOperationAction(ISD::JumpTable , MVT::i32 , Custom); 439 setOperationAction(ISD::GlobalAddress , MVT::i32 , Custom); 440 setOperationAction(ISD::GlobalTLSAddress, MVT::i32 , Custom); 441 if (Subtarget->is64Bit()) 442 setOperationAction(ISD::GlobalTLSAddress, MVT::i64, Custom); 443 setOperationAction(ISD::ExternalSymbol , MVT::i32 , Custom); 444 setOperationAction(ISD::BlockAddress , MVT::i32 , Custom); 445 if (Subtarget->is64Bit()) { 446 setOperationAction(ISD::ConstantPool , MVT::i64 , Custom); 447 setOperationAction(ISD::JumpTable , MVT::i64 , Custom); 448 setOperationAction(ISD::GlobalAddress , MVT::i64 , Custom); 449 setOperationAction(ISD::ExternalSymbol, MVT::i64 , Custom); 450 setOperationAction(ISD::BlockAddress , MVT::i64 , Custom); 451 } 452 // 64-bit addm sub, shl, sra, srl (iff 32-bit x86) 453 setOperationAction(ISD::SHL_PARTS , MVT::i32 , Custom); 454 setOperationAction(ISD::SRA_PARTS , MVT::i32 , Custom); 455 setOperationAction(ISD::SRL_PARTS , MVT::i32 , Custom); 456 if (Subtarget->is64Bit()) { 457 setOperationAction(ISD::SHL_PARTS , MVT::i64 , Custom); 458 setOperationAction(ISD::SRA_PARTS , MVT::i64 , Custom); 459 setOperationAction(ISD::SRL_PARTS , MVT::i64 , Custom); 460 } 461 462 if (Subtarget->hasXMM()) 463 setOperationAction(ISD::PREFETCH , MVT::Other, Legal); 464 465 setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom); 466 setOperationAction(ISD::ATOMIC_FENCE , MVT::Other, Custom); 467 468 // On X86 and X86-64, atomic operations are lowered to locked instructions. 469 // Locked instructions, in turn, have implicit fence semantics (all memory 470 // operations are flushed before issuing the locked instruction, and they 471 // are not buffered), so we can fold away the common pattern of 472 // fence-atomic-fence. 473 setShouldFoldAtomicFences(true); 474 475 // Expand certain atomics 476 for (unsigned i = 0, e = 4; i != e; ++i) { 477 MVT VT = IntVTs[i]; 478 setOperationAction(ISD::ATOMIC_CMP_SWAP, VT, Custom); 479 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom); 480 setOperationAction(ISD::ATOMIC_STORE, VT, Custom); 481 } 482 483 if (!Subtarget->is64Bit()) { 484 setOperationAction(ISD::ATOMIC_LOAD, MVT::i64, Custom); 485 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i64, Custom); 486 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i64, Custom); 487 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i64, Custom); 488 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i64, Custom); 489 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i64, Custom); 490 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i64, Custom); 491 setOperationAction(ISD::ATOMIC_SWAP, MVT::i64, Custom); 492 } 493 494 if (Subtarget->hasCmpxchg16b()) { 495 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); 496 } 497 498 // FIXME - use subtarget debug flags 499 if (!Subtarget->isTargetDarwin() && 500 !Subtarget->isTargetELF() && 501 !Subtarget->isTargetCygMing()) { 502 setOperationAction(ISD::EH_LABEL, MVT::Other, Expand); 503 } 504 505 setOperationAction(ISD::EXCEPTIONADDR, MVT::i64, Expand); 506 setOperationAction(ISD::EHSELECTION, MVT::i64, Expand); 507 setOperationAction(ISD::EXCEPTIONADDR, MVT::i32, Expand); 508 setOperationAction(ISD::EHSELECTION, MVT::i32, Expand); 509 if (Subtarget->is64Bit()) { 510 setExceptionPointerRegister(X86::RAX); 511 setExceptionSelectorRegister(X86::RDX); 512 } else { 513 setExceptionPointerRegister(X86::EAX); 514 setExceptionSelectorRegister(X86::EDX); 515 } 516 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i32, Custom); 517 setOperationAction(ISD::FRAME_TO_ARGS_OFFSET, MVT::i64, Custom); 518 519 setOperationAction(ISD::INIT_TRAMPOLINE, MVT::Other, Custom); 520 setOperationAction(ISD::ADJUST_TRAMPOLINE, MVT::Other, Custom); 521 522 setOperationAction(ISD::TRAP, MVT::Other, Legal); 523 524 // VASTART needs to be custom lowered to use the VarArgsFrameIndex 525 setOperationAction(ISD::VASTART , MVT::Other, Custom); 526 setOperationAction(ISD::VAEND , MVT::Other, Expand); 527 if (Subtarget->is64Bit()) { 528 setOperationAction(ISD::VAARG , MVT::Other, Custom); 529 setOperationAction(ISD::VACOPY , MVT::Other, Custom); 530 } else { 531 setOperationAction(ISD::VAARG , MVT::Other, Expand); 532 setOperationAction(ISD::VACOPY , MVT::Other, Expand); 533 } 534 535 setOperationAction(ISD::STACKSAVE, MVT::Other, Expand); 536 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); 537 538 if (Subtarget->isTargetCOFF() && !Subtarget->isTargetEnvMacho()) 539 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 540 MVT::i64 : MVT::i32, Custom); 541 else if (EnableSegmentedStacks) 542 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 543 MVT::i64 : MVT::i32, Custom); 544 else 545 setOperationAction(ISD::DYNAMIC_STACKALLOC, Subtarget->is64Bit() ? 546 MVT::i64 : MVT::i32, Expand); 547 548 if (!UseSoftFloat && X86ScalarSSEf64) { 549 // f32 and f64 use SSE. 550 // Set up the FP register classes. 551 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 552 addRegisterClass(MVT::f64, X86::FR64RegisterClass); 553 554 // Use ANDPD to simulate FABS. 555 setOperationAction(ISD::FABS , MVT::f64, Custom); 556 setOperationAction(ISD::FABS , MVT::f32, Custom); 557 558 // Use XORP to simulate FNEG. 559 setOperationAction(ISD::FNEG , MVT::f64, Custom); 560 setOperationAction(ISD::FNEG , MVT::f32, Custom); 561 562 // Use ANDPD and ORPD to simulate FCOPYSIGN. 563 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); 564 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 565 566 // Lower this to FGETSIGNx86 plus an AND. 567 setOperationAction(ISD::FGETSIGN, MVT::i64, Custom); 568 setOperationAction(ISD::FGETSIGN, MVT::i32, Custom); 569 570 // We don't support sin/cos/fmod 571 setOperationAction(ISD::FSIN , MVT::f64, Expand); 572 setOperationAction(ISD::FCOS , MVT::f64, Expand); 573 setOperationAction(ISD::FSIN , MVT::f32, Expand); 574 setOperationAction(ISD::FCOS , MVT::f32, Expand); 575 576 // Expand FP immediates into loads from the stack, except for the special 577 // cases we handle. 578 addLegalFPImmediate(APFloat(+0.0)); // xorpd 579 addLegalFPImmediate(APFloat(+0.0f)); // xorps 580 } else if (!UseSoftFloat && X86ScalarSSEf32) { 581 // Use SSE for f32, x87 for f64. 582 // Set up the FP register classes. 583 addRegisterClass(MVT::f32, X86::FR32RegisterClass); 584 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 585 586 // Use ANDPS to simulate FABS. 587 setOperationAction(ISD::FABS , MVT::f32, Custom); 588 589 // Use XORP to simulate FNEG. 590 setOperationAction(ISD::FNEG , MVT::f32, Custom); 591 592 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 593 594 // Use ANDPS and ORPS to simulate FCOPYSIGN. 595 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 596 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Custom); 597 598 // We don't support sin/cos/fmod 599 setOperationAction(ISD::FSIN , MVT::f32, Expand); 600 setOperationAction(ISD::FCOS , MVT::f32, Expand); 601 602 // Special cases we handle for FP constants. 603 addLegalFPImmediate(APFloat(+0.0f)); // xorps 604 addLegalFPImmediate(APFloat(+0.0)); // FLD0 605 addLegalFPImmediate(APFloat(+1.0)); // FLD1 606 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 607 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 608 609 if (!UnsafeFPMath) { 610 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 611 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 612 } 613 } else if (!UseSoftFloat) { 614 // f32 and f64 in x87. 615 // Set up the FP register classes. 616 addRegisterClass(MVT::f64, X86::RFP64RegisterClass); 617 addRegisterClass(MVT::f32, X86::RFP32RegisterClass); 618 619 setOperationAction(ISD::UNDEF, MVT::f64, Expand); 620 setOperationAction(ISD::UNDEF, MVT::f32, Expand); 621 setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand); 622 setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand); 623 624 if (!UnsafeFPMath) { 625 setOperationAction(ISD::FSIN , MVT::f64 , Expand); 626 setOperationAction(ISD::FCOS , MVT::f64 , Expand); 627 } 628 addLegalFPImmediate(APFloat(+0.0)); // FLD0 629 addLegalFPImmediate(APFloat(+1.0)); // FLD1 630 addLegalFPImmediate(APFloat(-0.0)); // FLD0/FCHS 631 addLegalFPImmediate(APFloat(-1.0)); // FLD1/FCHS 632 addLegalFPImmediate(APFloat(+0.0f)); // FLD0 633 addLegalFPImmediate(APFloat(+1.0f)); // FLD1 634 addLegalFPImmediate(APFloat(-0.0f)); // FLD0/FCHS 635 addLegalFPImmediate(APFloat(-1.0f)); // FLD1/FCHS 636 } 637 638 // We don't support FMA. 639 setOperationAction(ISD::FMA, MVT::f64, Expand); 640 setOperationAction(ISD::FMA, MVT::f32, Expand); 641 642 // Long double always uses X87. 643 if (!UseSoftFloat) { 644 addRegisterClass(MVT::f80, X86::RFP80RegisterClass); 645 setOperationAction(ISD::UNDEF, MVT::f80, Expand); 646 setOperationAction(ISD::FCOPYSIGN, MVT::f80, Expand); 647 { 648 APFloat TmpFlt = APFloat::getZero(APFloat::x87DoubleExtended); 649 addLegalFPImmediate(TmpFlt); // FLD0 650 TmpFlt.changeSign(); 651 addLegalFPImmediate(TmpFlt); // FLD0/FCHS 652 653 bool ignored; 654 APFloat TmpFlt2(+1.0); 655 TmpFlt2.convert(APFloat::x87DoubleExtended, APFloat::rmNearestTiesToEven, 656 &ignored); 657 addLegalFPImmediate(TmpFlt2); // FLD1 658 TmpFlt2.changeSign(); 659 addLegalFPImmediate(TmpFlt2); // FLD1/FCHS 660 } 661 662 if (!UnsafeFPMath) { 663 setOperationAction(ISD::FSIN , MVT::f80 , Expand); 664 setOperationAction(ISD::FCOS , MVT::f80 , Expand); 665 } 666 667 setOperationAction(ISD::FMA, MVT::f80, Expand); 668 } 669 670 // Always use a library call for pow. 671 setOperationAction(ISD::FPOW , MVT::f32 , Expand); 672 setOperationAction(ISD::FPOW , MVT::f64 , Expand); 673 setOperationAction(ISD::FPOW , MVT::f80 , Expand); 674 675 setOperationAction(ISD::FLOG, MVT::f80, Expand); 676 setOperationAction(ISD::FLOG2, MVT::f80, Expand); 677 setOperationAction(ISD::FLOG10, MVT::f80, Expand); 678 setOperationAction(ISD::FEXP, MVT::f80, Expand); 679 setOperationAction(ISD::FEXP2, MVT::f80, Expand); 680 681 // First set operation action for all vector types to either promote 682 // (for widening) or expand (for scalarization). Then we will selectively 683 // turn on ones that can be effectively codegen'd. 684 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 685 VT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++VT) { 686 setOperationAction(ISD::ADD , (MVT::SimpleValueType)VT, Expand); 687 setOperationAction(ISD::SUB , (MVT::SimpleValueType)VT, Expand); 688 setOperationAction(ISD::FADD, (MVT::SimpleValueType)VT, Expand); 689 setOperationAction(ISD::FNEG, (MVT::SimpleValueType)VT, Expand); 690 setOperationAction(ISD::FSUB, (MVT::SimpleValueType)VT, Expand); 691 setOperationAction(ISD::MUL , (MVT::SimpleValueType)VT, Expand); 692 setOperationAction(ISD::FMUL, (MVT::SimpleValueType)VT, Expand); 693 setOperationAction(ISD::SDIV, (MVT::SimpleValueType)VT, Expand); 694 setOperationAction(ISD::UDIV, (MVT::SimpleValueType)VT, Expand); 695 setOperationAction(ISD::FDIV, (MVT::SimpleValueType)VT, Expand); 696 setOperationAction(ISD::SREM, (MVT::SimpleValueType)VT, Expand); 697 setOperationAction(ISD::UREM, (MVT::SimpleValueType)VT, Expand); 698 setOperationAction(ISD::LOAD, (MVT::SimpleValueType)VT, Expand); 699 setOperationAction(ISD::VECTOR_SHUFFLE, (MVT::SimpleValueType)VT, Expand); 700 setOperationAction(ISD::EXTRACT_VECTOR_ELT,(MVT::SimpleValueType)VT,Expand); 701 setOperationAction(ISD::INSERT_VECTOR_ELT,(MVT::SimpleValueType)VT, Expand); 702 setOperationAction(ISD::EXTRACT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 703 setOperationAction(ISD::INSERT_SUBVECTOR,(MVT::SimpleValueType)VT,Expand); 704 setOperationAction(ISD::FABS, (MVT::SimpleValueType)VT, Expand); 705 setOperationAction(ISD::FSIN, (MVT::SimpleValueType)VT, Expand); 706 setOperationAction(ISD::FCOS, (MVT::SimpleValueType)VT, Expand); 707 setOperationAction(ISD::FREM, (MVT::SimpleValueType)VT, Expand); 708 setOperationAction(ISD::FPOWI, (MVT::SimpleValueType)VT, Expand); 709 setOperationAction(ISD::FSQRT, (MVT::SimpleValueType)VT, Expand); 710 setOperationAction(ISD::FCOPYSIGN, (MVT::SimpleValueType)VT, Expand); 711 setOperationAction(ISD::SMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 712 setOperationAction(ISD::UMUL_LOHI, (MVT::SimpleValueType)VT, Expand); 713 setOperationAction(ISD::SDIVREM, (MVT::SimpleValueType)VT, Expand); 714 setOperationAction(ISD::UDIVREM, (MVT::SimpleValueType)VT, Expand); 715 setOperationAction(ISD::FPOW, (MVT::SimpleValueType)VT, Expand); 716 setOperationAction(ISD::CTPOP, (MVT::SimpleValueType)VT, Expand); 717 setOperationAction(ISD::CTTZ, (MVT::SimpleValueType)VT, Expand); 718 setOperationAction(ISD::CTLZ, (MVT::SimpleValueType)VT, Expand); 719 setOperationAction(ISD::SHL, (MVT::SimpleValueType)VT, Expand); 720 setOperationAction(ISD::SRA, (MVT::SimpleValueType)VT, Expand); 721 setOperationAction(ISD::SRL, (MVT::SimpleValueType)VT, Expand); 722 setOperationAction(ISD::ROTL, (MVT::SimpleValueType)VT, Expand); 723 setOperationAction(ISD::ROTR, (MVT::SimpleValueType)VT, Expand); 724 setOperationAction(ISD::BSWAP, (MVT::SimpleValueType)VT, Expand); 725 setOperationAction(ISD::SETCC, (MVT::SimpleValueType)VT, Expand); 726 setOperationAction(ISD::FLOG, (MVT::SimpleValueType)VT, Expand); 727 setOperationAction(ISD::FLOG2, (MVT::SimpleValueType)VT, Expand); 728 setOperationAction(ISD::FLOG10, (MVT::SimpleValueType)VT, Expand); 729 setOperationAction(ISD::FEXP, (MVT::SimpleValueType)VT, Expand); 730 setOperationAction(ISD::FEXP2, (MVT::SimpleValueType)VT, Expand); 731 setOperationAction(ISD::FP_TO_UINT, (MVT::SimpleValueType)VT, Expand); 732 setOperationAction(ISD::FP_TO_SINT, (MVT::SimpleValueType)VT, Expand); 733 setOperationAction(ISD::UINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 734 setOperationAction(ISD::SINT_TO_FP, (MVT::SimpleValueType)VT, Expand); 735 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT,Expand); 736 setOperationAction(ISD::TRUNCATE, (MVT::SimpleValueType)VT, Expand); 737 setOperationAction(ISD::SIGN_EXTEND, (MVT::SimpleValueType)VT, Expand); 738 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); 739 setOperationAction(ISD::ANY_EXTEND, (MVT::SimpleValueType)VT, Expand); 740 setOperationAction(ISD::VSELECT, (MVT::SimpleValueType)VT, Expand); 741 for (unsigned InnerVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 742 InnerVT <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++InnerVT) 743 setTruncStoreAction((MVT::SimpleValueType)VT, 744 (MVT::SimpleValueType)InnerVT, Expand); 745 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT, Expand); 746 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT, Expand); 747 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT, Expand); 748 } 749 750 // FIXME: In order to prevent SSE instructions being expanded to MMX ones 751 // with -msoft-float, disable use of MMX as well. 752 if (!UseSoftFloat && Subtarget->hasMMX()) { 753 addRegisterClass(MVT::x86mmx, X86::VR64RegisterClass); 754 // No operations on x86mmx supported, everything uses intrinsics. 755 } 756 757 // MMX-sized vectors (other than x86mmx) are expected to be expanded 758 // into smaller operations. 759 setOperationAction(ISD::MULHS, MVT::v8i8, Expand); 760 setOperationAction(ISD::MULHS, MVT::v4i16, Expand); 761 setOperationAction(ISD::MULHS, MVT::v2i32, Expand); 762 setOperationAction(ISD::MULHS, MVT::v1i64, Expand); 763 setOperationAction(ISD::AND, MVT::v8i8, Expand); 764 setOperationAction(ISD::AND, MVT::v4i16, Expand); 765 setOperationAction(ISD::AND, MVT::v2i32, Expand); 766 setOperationAction(ISD::AND, MVT::v1i64, Expand); 767 setOperationAction(ISD::OR, MVT::v8i8, Expand); 768 setOperationAction(ISD::OR, MVT::v4i16, Expand); 769 setOperationAction(ISD::OR, MVT::v2i32, Expand); 770 setOperationAction(ISD::OR, MVT::v1i64, Expand); 771 setOperationAction(ISD::XOR, MVT::v8i8, Expand); 772 setOperationAction(ISD::XOR, MVT::v4i16, Expand); 773 setOperationAction(ISD::XOR, MVT::v2i32, Expand); 774 setOperationAction(ISD::XOR, MVT::v1i64, Expand); 775 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i8, Expand); 776 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4i16, Expand); 777 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2i32, Expand); 778 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v1i64, Expand); 779 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v1i64, Expand); 780 setOperationAction(ISD::SELECT, MVT::v8i8, Expand); 781 setOperationAction(ISD::SELECT, MVT::v4i16, Expand); 782 setOperationAction(ISD::SELECT, MVT::v2i32, Expand); 783 setOperationAction(ISD::SELECT, MVT::v1i64, Expand); 784 setOperationAction(ISD::BITCAST, MVT::v8i8, Expand); 785 setOperationAction(ISD::BITCAST, MVT::v4i16, Expand); 786 setOperationAction(ISD::BITCAST, MVT::v2i32, Expand); 787 setOperationAction(ISD::BITCAST, MVT::v1i64, Expand); 788 789 if (!UseSoftFloat && Subtarget->hasXMM()) { 790 addRegisterClass(MVT::v4f32, X86::VR128RegisterClass); 791 792 setOperationAction(ISD::FADD, MVT::v4f32, Legal); 793 setOperationAction(ISD::FSUB, MVT::v4f32, Legal); 794 setOperationAction(ISD::FMUL, MVT::v4f32, Legal); 795 setOperationAction(ISD::FDIV, MVT::v4f32, Legal); 796 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal); 797 setOperationAction(ISD::FNEG, MVT::v4f32, Custom); 798 setOperationAction(ISD::LOAD, MVT::v4f32, Legal); 799 setOperationAction(ISD::BUILD_VECTOR, MVT::v4f32, Custom); 800 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v4f32, Custom); 801 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 802 setOperationAction(ISD::SELECT, MVT::v4f32, Custom); 803 setOperationAction(ISD::SETCC, MVT::v4f32, Custom); 804 } 805 806 if (!UseSoftFloat && Subtarget->hasXMMInt()) { 807 addRegisterClass(MVT::v2f64, X86::VR128RegisterClass); 808 809 // FIXME: Unfortunately -soft-float and -no-implicit-float means XMM 810 // registers cannot be used even for integer operations. 811 addRegisterClass(MVT::v16i8, X86::VR128RegisterClass); 812 addRegisterClass(MVT::v8i16, X86::VR128RegisterClass); 813 addRegisterClass(MVT::v4i32, X86::VR128RegisterClass); 814 addRegisterClass(MVT::v2i64, X86::VR128RegisterClass); 815 816 setOperationAction(ISD::ADD, MVT::v16i8, Legal); 817 setOperationAction(ISD::ADD, MVT::v8i16, Legal); 818 setOperationAction(ISD::ADD, MVT::v4i32, Legal); 819 setOperationAction(ISD::ADD, MVT::v2i64, Legal); 820 setOperationAction(ISD::MUL, MVT::v2i64, Custom); 821 setOperationAction(ISD::SUB, MVT::v16i8, Legal); 822 setOperationAction(ISD::SUB, MVT::v8i16, Legal); 823 setOperationAction(ISD::SUB, MVT::v4i32, Legal); 824 setOperationAction(ISD::SUB, MVT::v2i64, Legal); 825 setOperationAction(ISD::MUL, MVT::v8i16, Legal); 826 setOperationAction(ISD::FADD, MVT::v2f64, Legal); 827 setOperationAction(ISD::FSUB, MVT::v2f64, Legal); 828 setOperationAction(ISD::FMUL, MVT::v2f64, Legal); 829 setOperationAction(ISD::FDIV, MVT::v2f64, Legal); 830 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal); 831 setOperationAction(ISD::FNEG, MVT::v2f64, Custom); 832 833 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 834 setOperationAction(ISD::SETCC, MVT::v16i8, Custom); 835 setOperationAction(ISD::SETCC, MVT::v8i16, Custom); 836 setOperationAction(ISD::SETCC, MVT::v4i32, Custom); 837 838 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v16i8, Custom); 839 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v8i16, Custom); 840 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 841 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 842 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 843 844 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2f64, Custom); 845 setOperationAction(ISD::CONCAT_VECTORS, MVT::v2i64, Custom); 846 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i8, Custom); 847 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i16, Custom); 848 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i32, Custom); 849 850 // Custom lower build_vector, vector_shuffle, and extract_vector_elt. 851 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; ++i) { 852 EVT VT = (MVT::SimpleValueType)i; 853 // Do not attempt to custom lower non-power-of-2 vectors 854 if (!isPowerOf2_32(VT.getVectorNumElements())) 855 continue; 856 // Do not attempt to custom lower non-128-bit vectors 857 if (!VT.is128BitVector()) 858 continue; 859 setOperationAction(ISD::BUILD_VECTOR, 860 VT.getSimpleVT().SimpleTy, Custom); 861 setOperationAction(ISD::VECTOR_SHUFFLE, 862 VT.getSimpleVT().SimpleTy, Custom); 863 setOperationAction(ISD::EXTRACT_VECTOR_ELT, 864 VT.getSimpleVT().SimpleTy, Custom); 865 } 866 867 setOperationAction(ISD::BUILD_VECTOR, MVT::v2f64, Custom); 868 setOperationAction(ISD::BUILD_VECTOR, MVT::v2i64, Custom); 869 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2f64, Custom); 870 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v2i64, Custom); 871 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom); 872 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom); 873 874 if (Subtarget->is64Bit()) { 875 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Custom); 876 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Custom); 877 } 878 879 // Promote v16i8, v8i16, v4i32 load, select, and, or, xor to v2i64. 880 for (unsigned i = (unsigned)MVT::v16i8; i != (unsigned)MVT::v2i64; i++) { 881 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 882 EVT VT = SVT; 883 884 // Do not attempt to promote non-128-bit vectors 885 if (!VT.is128BitVector()) 886 continue; 887 888 setOperationAction(ISD::AND, SVT, Promote); 889 AddPromotedToType (ISD::AND, SVT, MVT::v2i64); 890 setOperationAction(ISD::OR, SVT, Promote); 891 AddPromotedToType (ISD::OR, SVT, MVT::v2i64); 892 setOperationAction(ISD::XOR, SVT, Promote); 893 AddPromotedToType (ISD::XOR, SVT, MVT::v2i64); 894 setOperationAction(ISD::LOAD, SVT, Promote); 895 AddPromotedToType (ISD::LOAD, SVT, MVT::v2i64); 896 setOperationAction(ISD::SELECT, SVT, Promote); 897 AddPromotedToType (ISD::SELECT, SVT, MVT::v2i64); 898 } 899 900 setTruncStoreAction(MVT::f64, MVT::f32, Expand); 901 902 // Custom lower v2i64 and v2f64 selects. 903 setOperationAction(ISD::LOAD, MVT::v2f64, Legal); 904 setOperationAction(ISD::LOAD, MVT::v2i64, Legal); 905 setOperationAction(ISD::SELECT, MVT::v2f64, Custom); 906 setOperationAction(ISD::SELECT, MVT::v2i64, Custom); 907 908 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Legal); 909 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Legal); 910 } 911 912 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 913 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); 914 setOperationAction(ISD::FCEIL, MVT::f32, Legal); 915 setOperationAction(ISD::FTRUNC, MVT::f32, Legal); 916 setOperationAction(ISD::FRINT, MVT::f32, Legal); 917 setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); 918 setOperationAction(ISD::FFLOOR, MVT::f64, Legal); 919 setOperationAction(ISD::FCEIL, MVT::f64, Legal); 920 setOperationAction(ISD::FTRUNC, MVT::f64, Legal); 921 setOperationAction(ISD::FRINT, MVT::f64, Legal); 922 setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); 923 924 // FIXME: Do we need to handle scalar-to-vector here? 925 setOperationAction(ISD::MUL, MVT::v4i32, Legal); 926 927 // Can turn SHL into an integer multiply. 928 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 929 setOperationAction(ISD::SHL, MVT::v16i8, Custom); 930 931 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal); 932 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal); 933 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal); 934 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal); 935 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal); 936 937 // i8 and i16 vectors are custom , because the source register and source 938 // source memory operand types are not the same width. f32 vectors are 939 // custom since the immediate controlling the insert encodes additional 940 // information. 941 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom); 942 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom); 943 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom); 944 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom); 945 946 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom); 947 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom); 948 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom); 949 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom); 950 951 if (Subtarget->is64Bit()) { 952 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2i64, Legal); 953 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2i64, Legal); 954 } 955 } 956 957 if (Subtarget->hasXMMInt()) { 958 setOperationAction(ISD::SRL, MVT::v2i64, Custom); 959 setOperationAction(ISD::SRL, MVT::v4i32, Custom); 960 setOperationAction(ISD::SRL, MVT::v16i8, Custom); 961 setOperationAction(ISD::SRL, MVT::v8i16, Custom); 962 963 setOperationAction(ISD::SHL, MVT::v2i64, Custom); 964 setOperationAction(ISD::SHL, MVT::v4i32, Custom); 965 setOperationAction(ISD::SHL, MVT::v8i16, Custom); 966 967 setOperationAction(ISD::SRA, MVT::v4i32, Custom); 968 setOperationAction(ISD::SRA, MVT::v8i16, Custom); 969 } 970 971 if (Subtarget->hasSSE42() || Subtarget->hasAVX()) 972 setOperationAction(ISD::SETCC, MVT::v2i64, Custom); 973 974 if (!UseSoftFloat && Subtarget->hasAVX()) { 975 addRegisterClass(MVT::v32i8, X86::VR256RegisterClass); 976 addRegisterClass(MVT::v16i16, X86::VR256RegisterClass); 977 addRegisterClass(MVT::v8i32, X86::VR256RegisterClass); 978 addRegisterClass(MVT::v8f32, X86::VR256RegisterClass); 979 addRegisterClass(MVT::v4i64, X86::VR256RegisterClass); 980 addRegisterClass(MVT::v4f64, X86::VR256RegisterClass); 981 982 setOperationAction(ISD::LOAD, MVT::v8f32, Legal); 983 setOperationAction(ISD::LOAD, MVT::v4f64, Legal); 984 setOperationAction(ISD::LOAD, MVT::v4i64, Legal); 985 986 setOperationAction(ISD::FADD, MVT::v8f32, Legal); 987 setOperationAction(ISD::FSUB, MVT::v8f32, Legal); 988 setOperationAction(ISD::FMUL, MVT::v8f32, Legal); 989 setOperationAction(ISD::FDIV, MVT::v8f32, Legal); 990 setOperationAction(ISD::FSQRT, MVT::v8f32, Legal); 991 setOperationAction(ISD::FNEG, MVT::v8f32, Custom); 992 993 setOperationAction(ISD::FADD, MVT::v4f64, Legal); 994 setOperationAction(ISD::FSUB, MVT::v4f64, Legal); 995 setOperationAction(ISD::FMUL, MVT::v4f64, Legal); 996 setOperationAction(ISD::FDIV, MVT::v4f64, Legal); 997 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal); 998 setOperationAction(ISD::FNEG, MVT::v4f64, Custom); 999 1000 setOperationAction(ISD::FP_TO_SINT, MVT::v8i32, Legal); 1001 setOperationAction(ISD::SINT_TO_FP, MVT::v8i32, Legal); 1002 setOperationAction(ISD::FP_ROUND, MVT::v4f32, Legal); 1003 1004 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f64, Custom); 1005 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4i64, Custom); 1006 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8f32, Custom); 1007 setOperationAction(ISD::CONCAT_VECTORS, MVT::v8i32, Custom); 1008 setOperationAction(ISD::CONCAT_VECTORS, MVT::v32i8, Custom); 1009 setOperationAction(ISD::CONCAT_VECTORS, MVT::v16i16, Custom); 1010 1011 setOperationAction(ISD::SRL, MVT::v4i64, Custom); 1012 setOperationAction(ISD::SRL, MVT::v8i32, Custom); 1013 setOperationAction(ISD::SRL, MVT::v16i16, Custom); 1014 setOperationAction(ISD::SRL, MVT::v32i8, Custom); 1015 1016 setOperationAction(ISD::SHL, MVT::v4i64, Custom); 1017 setOperationAction(ISD::SHL, MVT::v8i32, Custom); 1018 setOperationAction(ISD::SHL, MVT::v16i16, Custom); 1019 setOperationAction(ISD::SHL, MVT::v32i8, Custom); 1020 1021 setOperationAction(ISD::SRA, MVT::v8i32, Custom); 1022 setOperationAction(ISD::SRA, MVT::v16i16, Custom); 1023 1024 setOperationAction(ISD::SETCC, MVT::v32i8, Custom); 1025 setOperationAction(ISD::SETCC, MVT::v16i16, Custom); 1026 setOperationAction(ISD::SETCC, MVT::v8i32, Custom); 1027 setOperationAction(ISD::SETCC, MVT::v4i64, Custom); 1028 1029 setOperationAction(ISD::SELECT, MVT::v4f64, Custom); 1030 setOperationAction(ISD::SELECT, MVT::v4i64, Custom); 1031 setOperationAction(ISD::SELECT, MVT::v8f32, Custom); 1032 1033 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal); 1034 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal); 1035 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal); 1036 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal); 1037 1038 setOperationAction(ISD::ADD, MVT::v4i64, Custom); 1039 setOperationAction(ISD::ADD, MVT::v8i32, Custom); 1040 setOperationAction(ISD::ADD, MVT::v16i16, Custom); 1041 setOperationAction(ISD::ADD, MVT::v32i8, Custom); 1042 1043 setOperationAction(ISD::SUB, MVT::v4i64, Custom); 1044 setOperationAction(ISD::SUB, MVT::v8i32, Custom); 1045 setOperationAction(ISD::SUB, MVT::v16i16, Custom); 1046 setOperationAction(ISD::SUB, MVT::v32i8, Custom); 1047 1048 setOperationAction(ISD::MUL, MVT::v4i64, Custom); 1049 setOperationAction(ISD::MUL, MVT::v8i32, Custom); 1050 setOperationAction(ISD::MUL, MVT::v16i16, Custom); 1051 // Don't lower v32i8 because there is no 128-bit byte mul 1052 1053 // Custom lower several nodes for 256-bit types. 1054 for (unsigned i = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1055 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) { 1056 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1057 EVT VT = SVT; 1058 1059 // Extract subvector is special because the value type 1060 // (result) is 128-bit but the source is 256-bit wide. 1061 if (VT.is128BitVector()) 1062 setOperationAction(ISD::EXTRACT_SUBVECTOR, SVT, Custom); 1063 1064 // Do not attempt to custom lower other non-256-bit vectors 1065 if (!VT.is256BitVector()) 1066 continue; 1067 1068 setOperationAction(ISD::BUILD_VECTOR, SVT, Custom); 1069 setOperationAction(ISD::VECTOR_SHUFFLE, SVT, Custom); 1070 setOperationAction(ISD::INSERT_VECTOR_ELT, SVT, Custom); 1071 setOperationAction(ISD::EXTRACT_VECTOR_ELT, SVT, Custom); 1072 setOperationAction(ISD::SCALAR_TO_VECTOR, SVT, Custom); 1073 setOperationAction(ISD::INSERT_SUBVECTOR, SVT, Custom); 1074 } 1075 1076 // Promote v32i8, v16i16, v8i32 select, and, or, xor to v4i64. 1077 for (unsigned i = (unsigned)MVT::v32i8; i != (unsigned)MVT::v4i64; ++i) { 1078 MVT::SimpleValueType SVT = (MVT::SimpleValueType)i; 1079 EVT VT = SVT; 1080 1081 // Do not attempt to promote non-256-bit vectors 1082 if (!VT.is256BitVector()) 1083 continue; 1084 1085 setOperationAction(ISD::AND, SVT, Promote); 1086 AddPromotedToType (ISD::AND, SVT, MVT::v4i64); 1087 setOperationAction(ISD::OR, SVT, Promote); 1088 AddPromotedToType (ISD::OR, SVT, MVT::v4i64); 1089 setOperationAction(ISD::XOR, SVT, Promote); 1090 AddPromotedToType (ISD::XOR, SVT, MVT::v4i64); 1091 setOperationAction(ISD::LOAD, SVT, Promote); 1092 AddPromotedToType (ISD::LOAD, SVT, MVT::v4i64); 1093 setOperationAction(ISD::SELECT, SVT, Promote); 1094 AddPromotedToType (ISD::SELECT, SVT, MVT::v4i64); 1095 } 1096 } 1097 1098 // SIGN_EXTEND_INREGs are evaluated by the extend type. Handle the expansion 1099 // of this type with custom code. 1100 for (unsigned VT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 1101 VT != (unsigned)MVT::LAST_VECTOR_VALUETYPE; VT++) { 1102 setOperationAction(ISD::SIGN_EXTEND_INREG, (MVT::SimpleValueType)VT, Custom); 1103 } 1104 1105 // We want to custom lower some of our intrinsics. 1106 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 1107 1108 1109 // Only custom-lower 64-bit SADDO and friends on 64-bit because we don't 1110 // handle type legalization for these operations here. 1111 // 1112 // FIXME: We really should do custom legalization for addition and 1113 // subtraction on x86-32 once PR3203 is fixed. We really can't do much better 1114 // than generic legalization for 64-bit multiplication-with-overflow, though. 1115 for (unsigned i = 0, e = 3+Subtarget->is64Bit(); i != e; ++i) { 1116 // Add/Sub/Mul with overflow operations are custom lowered. 1117 MVT VT = IntVTs[i]; 1118 setOperationAction(ISD::SADDO, VT, Custom); 1119 setOperationAction(ISD::UADDO, VT, Custom); 1120 setOperationAction(ISD::SSUBO, VT, Custom); 1121 setOperationAction(ISD::USUBO, VT, Custom); 1122 setOperationAction(ISD::SMULO, VT, Custom); 1123 setOperationAction(ISD::UMULO, VT, Custom); 1124 } 1125 1126 // There are no 8-bit 3-address imul/mul instructions 1127 setOperationAction(ISD::SMULO, MVT::i8, Expand); 1128 setOperationAction(ISD::UMULO, MVT::i8, Expand); 1129 1130 if (!Subtarget->is64Bit()) { 1131 // These libcalls are not available in 32-bit. 1132 setLibcallName(RTLIB::SHL_I128, 0); 1133 setLibcallName(RTLIB::SRL_I128, 0); 1134 setLibcallName(RTLIB::SRA_I128, 0); 1135 } 1136 1137 // We have target-specific dag combine patterns for the following nodes: 1138 setTargetDAGCombine(ISD::VECTOR_SHUFFLE); 1139 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT); 1140 setTargetDAGCombine(ISD::BUILD_VECTOR); 1141 setTargetDAGCombine(ISD::VSELECT); 1142 setTargetDAGCombine(ISD::SELECT); 1143 setTargetDAGCombine(ISD::SHL); 1144 setTargetDAGCombine(ISD::SRA); 1145 setTargetDAGCombine(ISD::SRL); 1146 setTargetDAGCombine(ISD::OR); 1147 setTargetDAGCombine(ISD::AND); 1148 setTargetDAGCombine(ISD::ADD); 1149 setTargetDAGCombine(ISD::FADD); 1150 setTargetDAGCombine(ISD::FSUB); 1151 setTargetDAGCombine(ISD::SUB); 1152 setTargetDAGCombine(ISD::LOAD); 1153 setTargetDAGCombine(ISD::STORE); 1154 setTargetDAGCombine(ISD::ZERO_EXTEND); 1155 setTargetDAGCombine(ISD::SINT_TO_FP); 1156 if (Subtarget->is64Bit()) 1157 setTargetDAGCombine(ISD::MUL); 1158 1159 computeRegisterProperties(); 1160 1161 // On Darwin, -Os means optimize for size without hurting performance, 1162 // do not reduce the limit. 1163 maxStoresPerMemset = 16; // For @llvm.memset -> sequence of stores 1164 maxStoresPerMemsetOptSize = Subtarget->isTargetDarwin() ? 16 : 8; 1165 maxStoresPerMemcpy = 8; // For @llvm.memcpy -> sequence of stores 1166 maxStoresPerMemcpyOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1167 maxStoresPerMemmove = 8; // For @llvm.memmove -> sequence of stores 1168 maxStoresPerMemmoveOptSize = Subtarget->isTargetDarwin() ? 8 : 4; 1169 setPrefLoopAlignment(16); 1170 benefitFromCodePlacementOpt = true; 1171 1172 setPrefFunctionAlignment(4); 1173 } 1174 1175 1176 EVT X86TargetLowering::getSetCCResultType(EVT VT) const { 1177 if (!VT.isVector()) return MVT::i8; 1178 return VT.changeVectorElementTypeToInteger(); 1179 } 1180 1181 1182 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine 1183 /// the desired ByVal argument alignment. 1184 static void getMaxByValAlign(Type *Ty, unsigned &MaxAlign) { 1185 if (MaxAlign == 16) 1186 return; 1187 if (VectorType *VTy = dyn_cast<VectorType>(Ty)) { 1188 if (VTy->getBitWidth() == 128) 1189 MaxAlign = 16; 1190 } else if (ArrayType *ATy = dyn_cast<ArrayType>(Ty)) { 1191 unsigned EltAlign = 0; 1192 getMaxByValAlign(ATy->getElementType(), EltAlign); 1193 if (EltAlign > MaxAlign) 1194 MaxAlign = EltAlign; 1195 } else if (StructType *STy = dyn_cast<StructType>(Ty)) { 1196 for (unsigned i = 0, e = STy->getNumElements(); i != e; ++i) { 1197 unsigned EltAlign = 0; 1198 getMaxByValAlign(STy->getElementType(i), EltAlign); 1199 if (EltAlign > MaxAlign) 1200 MaxAlign = EltAlign; 1201 if (MaxAlign == 16) 1202 break; 1203 } 1204 } 1205 return; 1206 } 1207 1208 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate 1209 /// function arguments in the caller parameter area. For X86, aggregates 1210 /// that contain SSE vectors are placed at 16-byte boundaries while the rest 1211 /// are at 4-byte boundaries. 1212 unsigned X86TargetLowering::getByValTypeAlignment(Type *Ty) const { 1213 if (Subtarget->is64Bit()) { 1214 // Max of 8 and alignment of type. 1215 unsigned TyAlign = TD->getABITypeAlignment(Ty); 1216 if (TyAlign > 8) 1217 return TyAlign; 1218 return 8; 1219 } 1220 1221 unsigned Align = 4; 1222 if (Subtarget->hasXMM()) 1223 getMaxByValAlign(Ty, Align); 1224 return Align; 1225 } 1226 1227 /// getOptimalMemOpType - Returns the target specific optimal type for load 1228 /// and store operations as a result of memset, memcpy, and memmove 1229 /// lowering. If DstAlign is zero that means it's safe to destination 1230 /// alignment can satisfy any constraint. Similarly if SrcAlign is zero it 1231 /// means there isn't a need to check it against alignment requirement, 1232 /// probably because the source does not need to be loaded. If 1233 /// 'NonScalarIntSafe' is true, that means it's safe to return a 1234 /// non-scalar-integer type, e.g. empty string source, constant, or loaded 1235 /// from memory. 'MemcpyStrSrc' indicates whether the memcpy source is 1236 /// constant so it does not need to be loaded. 1237 /// It returns EVT::Other if the type should be determined using generic 1238 /// target-independent logic. 1239 EVT 1240 X86TargetLowering::getOptimalMemOpType(uint64_t Size, 1241 unsigned DstAlign, unsigned SrcAlign, 1242 bool NonScalarIntSafe, 1243 bool MemcpyStrSrc, 1244 MachineFunction &MF) const { 1245 // FIXME: This turns off use of xmm stores for memset/memcpy on targets like 1246 // linux. This is because the stack realignment code can't handle certain 1247 // cases like PR2962. This should be removed when PR2962 is fixed. 1248 const Function *F = MF.getFunction(); 1249 if (NonScalarIntSafe && 1250 !F->hasFnAttr(Attribute::NoImplicitFloat)) { 1251 if (Size >= 16 && 1252 (Subtarget->isUnalignedMemAccessFast() || 1253 ((DstAlign == 0 || DstAlign >= 16) && 1254 (SrcAlign == 0 || SrcAlign >= 16))) && 1255 Subtarget->getStackAlignment() >= 16) { 1256 if (Subtarget->hasAVX() && 1257 Subtarget->getStackAlignment() >= 32) 1258 return MVT::v8f32; 1259 if (Subtarget->hasXMMInt()) 1260 return MVT::v4i32; 1261 if (Subtarget->hasXMM()) 1262 return MVT::v4f32; 1263 } else if (!MemcpyStrSrc && Size >= 8 && 1264 !Subtarget->is64Bit() && 1265 Subtarget->getStackAlignment() >= 8 && 1266 Subtarget->hasXMMInt()) { 1267 // Do not use f64 to lower memcpy if source is string constant. It's 1268 // better to use i32 to avoid the loads. 1269 return MVT::f64; 1270 } 1271 } 1272 if (Subtarget->is64Bit() && Size >= 8) 1273 return MVT::i64; 1274 return MVT::i32; 1275 } 1276 1277 /// getJumpTableEncoding - Return the entry encoding for a jump table in the 1278 /// current function. The returned value is a member of the 1279 /// MachineJumpTableInfo::JTEntryKind enum. 1280 unsigned X86TargetLowering::getJumpTableEncoding() const { 1281 // In GOT pic mode, each entry in the jump table is emitted as a @GOTOFF 1282 // symbol. 1283 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1284 Subtarget->isPICStyleGOT()) 1285 return MachineJumpTableInfo::EK_Custom32; 1286 1287 // Otherwise, use the normal jump table encoding heuristics. 1288 return TargetLowering::getJumpTableEncoding(); 1289 } 1290 1291 const MCExpr * 1292 X86TargetLowering::LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, 1293 const MachineBasicBlock *MBB, 1294 unsigned uid,MCContext &Ctx) const{ 1295 assert(getTargetMachine().getRelocationModel() == Reloc::PIC_ && 1296 Subtarget->isPICStyleGOT()); 1297 // In 32-bit ELF systems, our jump table entries are formed with @GOTOFF 1298 // entries. 1299 return MCSymbolRefExpr::Create(MBB->getSymbol(), 1300 MCSymbolRefExpr::VK_GOTOFF, Ctx); 1301 } 1302 1303 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC 1304 /// jumptable. 1305 SDValue X86TargetLowering::getPICJumpTableRelocBase(SDValue Table, 1306 SelectionDAG &DAG) const { 1307 if (!Subtarget->is64Bit()) 1308 // This doesn't have DebugLoc associated with it, but is not really the 1309 // same as a Register. 1310 return DAG.getNode(X86ISD::GlobalBaseReg, DebugLoc(), getPointerTy()); 1311 return Table; 1312 } 1313 1314 /// getPICJumpTableRelocBaseExpr - This returns the relocation base for the 1315 /// given PIC jumptable, the same as getPICJumpTableRelocBase, but as an 1316 /// MCExpr. 1317 const MCExpr *X86TargetLowering:: 1318 getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, 1319 MCContext &Ctx) const { 1320 // X86-64 uses RIP relative addressing based on the jump table label. 1321 if (Subtarget->isPICStyleRIPRel()) 1322 return TargetLowering::getPICJumpTableRelocBaseExpr(MF, JTI, Ctx); 1323 1324 // Otherwise, the reference is relative to the PIC base. 1325 return MCSymbolRefExpr::Create(MF->getPICBaseSymbol(), Ctx); 1326 } 1327 1328 // FIXME: Why this routine is here? Move to RegInfo! 1329 std::pair<const TargetRegisterClass*, uint8_t> 1330 X86TargetLowering::findRepresentativeClass(EVT VT) const{ 1331 const TargetRegisterClass *RRC = 0; 1332 uint8_t Cost = 1; 1333 switch (VT.getSimpleVT().SimpleTy) { 1334 default: 1335 return TargetLowering::findRepresentativeClass(VT); 1336 case MVT::i8: case MVT::i16: case MVT::i32: case MVT::i64: 1337 RRC = (Subtarget->is64Bit() 1338 ? X86::GR64RegisterClass : X86::GR32RegisterClass); 1339 break; 1340 case MVT::x86mmx: 1341 RRC = X86::VR64RegisterClass; 1342 break; 1343 case MVT::f32: case MVT::f64: 1344 case MVT::v16i8: case MVT::v8i16: case MVT::v4i32: case MVT::v2i64: 1345 case MVT::v4f32: case MVT::v2f64: 1346 case MVT::v32i8: case MVT::v8i32: case MVT::v4i64: case MVT::v8f32: 1347 case MVT::v4f64: 1348 RRC = X86::VR128RegisterClass; 1349 break; 1350 } 1351 return std::make_pair(RRC, Cost); 1352 } 1353 1354 bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace, 1355 unsigned &Offset) const { 1356 if (!Subtarget->isTargetLinux()) 1357 return false; 1358 1359 if (Subtarget->is64Bit()) { 1360 // %fs:0x28, unless we're using a Kernel code model, in which case it's %gs: 1361 Offset = 0x28; 1362 if (getTargetMachine().getCodeModel() == CodeModel::Kernel) 1363 AddressSpace = 256; 1364 else 1365 AddressSpace = 257; 1366 } else { 1367 // %gs:0x14 on i386 1368 Offset = 0x14; 1369 AddressSpace = 256; 1370 } 1371 return true; 1372 } 1373 1374 1375 //===----------------------------------------------------------------------===// 1376 // Return Value Calling Convention Implementation 1377 //===----------------------------------------------------------------------===// 1378 1379 #include "X86GenCallingConv.inc" 1380 1381 bool 1382 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, 1383 MachineFunction &MF, bool isVarArg, 1384 const SmallVectorImpl<ISD::OutputArg> &Outs, 1385 LLVMContext &Context) const { 1386 SmallVector<CCValAssign, 16> RVLocs; 1387 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1388 RVLocs, Context); 1389 return CCInfo.CheckReturn(Outs, RetCC_X86); 1390 } 1391 1392 SDValue 1393 X86TargetLowering::LowerReturn(SDValue Chain, 1394 CallingConv::ID CallConv, bool isVarArg, 1395 const SmallVectorImpl<ISD::OutputArg> &Outs, 1396 const SmallVectorImpl<SDValue> &OutVals, 1397 DebugLoc dl, SelectionDAG &DAG) const { 1398 MachineFunction &MF = DAG.getMachineFunction(); 1399 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1400 1401 SmallVector<CCValAssign, 16> RVLocs; 1402 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1403 RVLocs, *DAG.getContext()); 1404 CCInfo.AnalyzeReturn(Outs, RetCC_X86); 1405 1406 // Add the regs to the liveout set for the function. 1407 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 1408 for (unsigned i = 0; i != RVLocs.size(); ++i) 1409 if (RVLocs[i].isRegLoc() && !MRI.isLiveOut(RVLocs[i].getLocReg())) 1410 MRI.addLiveOut(RVLocs[i].getLocReg()); 1411 1412 SDValue Flag; 1413 1414 SmallVector<SDValue, 6> RetOps; 1415 RetOps.push_back(Chain); // Operand #0 = Chain (updated below) 1416 // Operand #1 = Bytes To Pop 1417 RetOps.push_back(DAG.getTargetConstant(FuncInfo->getBytesToPopOnReturn(), 1418 MVT::i16)); 1419 1420 // Copy the result values into the output registers. 1421 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1422 CCValAssign &VA = RVLocs[i]; 1423 assert(VA.isRegLoc() && "Can only return in registers!"); 1424 SDValue ValToCopy = OutVals[i]; 1425 EVT ValVT = ValToCopy.getValueType(); 1426 1427 // If this is x86-64, and we disabled SSE, we can't return FP values, 1428 // or SSE or MMX vectors. 1429 if ((ValVT == MVT::f32 || ValVT == MVT::f64 || 1430 VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) && 1431 (Subtarget->is64Bit() && !Subtarget->hasXMM())) { 1432 report_fatal_error("SSE register return with SSE disabled"); 1433 } 1434 // Likewise we can't return F64 values with SSE1 only. gcc does so, but 1435 // llvm-gcc has never done it right and no one has noticed, so this 1436 // should be OK for now. 1437 if (ValVT == MVT::f64 && 1438 (Subtarget->is64Bit() && !Subtarget->hasXMMInt())) 1439 report_fatal_error("SSE2 register return with SSE2 disabled"); 1440 1441 // Returns in ST0/ST1 are handled specially: these are pushed as operands to 1442 // the RET instruction and handled by the FP Stackifier. 1443 if (VA.getLocReg() == X86::ST0 || 1444 VA.getLocReg() == X86::ST1) { 1445 // If this is a copy from an xmm register to ST(0), use an FPExtend to 1446 // change the value to the FP stack register class. 1447 if (isScalarFPTypeInSSEReg(VA.getValVT())) 1448 ValToCopy = DAG.getNode(ISD::FP_EXTEND, dl, MVT::f80, ValToCopy); 1449 RetOps.push_back(ValToCopy); 1450 // Don't emit a copytoreg. 1451 continue; 1452 } 1453 1454 // 64-bit vector (MMX) values are returned in XMM0 / XMM1 except for v1i64 1455 // which is returned in RAX / RDX. 1456 if (Subtarget->is64Bit()) { 1457 if (ValVT == MVT::x86mmx) { 1458 if (VA.getLocReg() == X86::XMM0 || VA.getLocReg() == X86::XMM1) { 1459 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::i64, ValToCopy); 1460 ValToCopy = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, 1461 ValToCopy); 1462 // If we don't have SSE2 available, convert to v4f32 so the generated 1463 // register is legal. 1464 if (!Subtarget->hasXMMInt()) 1465 ValToCopy = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32,ValToCopy); 1466 } 1467 } 1468 } 1469 1470 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag); 1471 Flag = Chain.getValue(1); 1472 } 1473 1474 // The x86-64 ABI for returning structs by value requires that we copy 1475 // the sret argument into %rax for the return. We saved the argument into 1476 // a virtual register in the entry block, so now we copy the value out 1477 // and into %rax. 1478 if (Subtarget->is64Bit() && 1479 DAG.getMachineFunction().getFunction()->hasStructRetAttr()) { 1480 MachineFunction &MF = DAG.getMachineFunction(); 1481 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1482 unsigned Reg = FuncInfo->getSRetReturnReg(); 1483 assert(Reg && 1484 "SRetReturnReg should have been set in LowerFormalArguments()."); 1485 SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy()); 1486 1487 Chain = DAG.getCopyToReg(Chain, dl, X86::RAX, Val, Flag); 1488 Flag = Chain.getValue(1); 1489 1490 // RAX now acts like a return value. 1491 MRI.addLiveOut(X86::RAX); 1492 } 1493 1494 RetOps[0] = Chain; // Update chain. 1495 1496 // Add the flag if we have it. 1497 if (Flag.getNode()) 1498 RetOps.push_back(Flag); 1499 1500 return DAG.getNode(X86ISD::RET_FLAG, dl, 1501 MVT::Other, &RetOps[0], RetOps.size()); 1502 } 1503 1504 bool X86TargetLowering::isUsedByReturnOnly(SDNode *N) const { 1505 if (N->getNumValues() != 1) 1506 return false; 1507 if (!N->hasNUsesOfValue(1, 0)) 1508 return false; 1509 1510 SDNode *Copy = *N->use_begin(); 1511 if (Copy->getOpcode() != ISD::CopyToReg && 1512 Copy->getOpcode() != ISD::FP_EXTEND) 1513 return false; 1514 1515 bool HasRet = false; 1516 for (SDNode::use_iterator UI = Copy->use_begin(), UE = Copy->use_end(); 1517 UI != UE; ++UI) { 1518 if (UI->getOpcode() != X86ISD::RET_FLAG) 1519 return false; 1520 HasRet = true; 1521 } 1522 1523 return HasRet; 1524 } 1525 1526 EVT 1527 X86TargetLowering::getTypeForExtArgOrReturn(LLVMContext &Context, EVT VT, 1528 ISD::NodeType ExtendKind) const { 1529 MVT ReturnMVT; 1530 // TODO: Is this also valid on 32-bit? 1531 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) 1532 ReturnMVT = MVT::i8; 1533 else 1534 ReturnMVT = MVT::i32; 1535 1536 EVT MinVT = getRegisterType(Context, ReturnMVT); 1537 return VT.bitsLT(MinVT) ? MinVT : VT; 1538 } 1539 1540 /// LowerCallResult - Lower the result values of a call into the 1541 /// appropriate copies out of appropriate physical registers. 1542 /// 1543 SDValue 1544 X86TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag, 1545 CallingConv::ID CallConv, bool isVarArg, 1546 const SmallVectorImpl<ISD::InputArg> &Ins, 1547 DebugLoc dl, SelectionDAG &DAG, 1548 SmallVectorImpl<SDValue> &InVals) const { 1549 1550 // Assign locations to each value returned by this call. 1551 SmallVector<CCValAssign, 16> RVLocs; 1552 bool Is64Bit = Subtarget->is64Bit(); 1553 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), 1554 getTargetMachine(), RVLocs, *DAG.getContext()); 1555 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 1556 1557 // Copy all of the result registers out of their specified physreg. 1558 for (unsigned i = 0; i != RVLocs.size(); ++i) { 1559 CCValAssign &VA = RVLocs[i]; 1560 EVT CopyVT = VA.getValVT(); 1561 1562 // If this is x86-64, and we disabled SSE, we can't return FP values 1563 if ((CopyVT == MVT::f32 || CopyVT == MVT::f64) && 1564 ((Is64Bit || Ins[i].Flags.isInReg()) && !Subtarget->hasXMM())) { 1565 report_fatal_error("SSE register return with SSE disabled"); 1566 } 1567 1568 SDValue Val; 1569 1570 // If this is a call to a function that returns an fp value on the floating 1571 // point stack, we must guarantee the the value is popped from the stack, so 1572 // a CopyFromReg is not good enough - the copy instruction may be eliminated 1573 // if the return value is not used. We use the FpPOP_RETVAL instruction 1574 // instead. 1575 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) { 1576 // If we prefer to use the value in xmm registers, copy it out as f80 and 1577 // use a truncate to move it from fp stack reg to xmm reg. 1578 if (isScalarFPTypeInSSEReg(VA.getValVT())) CopyVT = MVT::f80; 1579 SDValue Ops[] = { Chain, InFlag }; 1580 Chain = SDValue(DAG.getMachineNode(X86::FpPOP_RETVAL, dl, CopyVT, 1581 MVT::Other, MVT::Glue, Ops, 2), 1); 1582 Val = Chain.getValue(0); 1583 1584 // Round the f80 to the right size, which also moves it to the appropriate 1585 // xmm register. 1586 if (CopyVT != VA.getValVT()) 1587 Val = DAG.getNode(ISD::FP_ROUND, dl, VA.getValVT(), Val, 1588 // This truncation won't change the value. 1589 DAG.getIntPtrConstant(1)); 1590 } else { 1591 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(), 1592 CopyVT, InFlag).getValue(1); 1593 Val = Chain.getValue(0); 1594 } 1595 InFlag = Chain.getValue(2); 1596 InVals.push_back(Val); 1597 } 1598 1599 return Chain; 1600 } 1601 1602 1603 //===----------------------------------------------------------------------===// 1604 // C & StdCall & Fast Calling Convention implementation 1605 //===----------------------------------------------------------------------===// 1606 // StdCall calling convention seems to be standard for many Windows' API 1607 // routines and around. It differs from C calling convention just a little: 1608 // callee should clean up the stack, not caller. Symbols should be also 1609 // decorated in some fancy way :) It doesn't support any vector arguments. 1610 // For info on fast calling convention see Fast Calling Convention (tail call) 1611 // implementation LowerX86_32FastCCCallTo. 1612 1613 /// CallIsStructReturn - Determines whether a call uses struct return 1614 /// semantics. 1615 static bool CallIsStructReturn(const SmallVectorImpl<ISD::OutputArg> &Outs) { 1616 if (Outs.empty()) 1617 return false; 1618 1619 return Outs[0].Flags.isSRet(); 1620 } 1621 1622 /// ArgsAreStructReturn - Determines whether a function uses struct 1623 /// return semantics. 1624 static bool 1625 ArgsAreStructReturn(const SmallVectorImpl<ISD::InputArg> &Ins) { 1626 if (Ins.empty()) 1627 return false; 1628 1629 return Ins[0].Flags.isSRet(); 1630 } 1631 1632 /// CreateCopyOfByValArgument - Make a copy of an aggregate at address specified 1633 /// by "Src" to address "Dst" with size and alignment information specified by 1634 /// the specific parameter attribute. The copy will be passed as a byval 1635 /// function parameter. 1636 static SDValue 1637 CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain, 1638 ISD::ArgFlagsTy Flags, SelectionDAG &DAG, 1639 DebugLoc dl) { 1640 SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32); 1641 1642 return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(), 1643 /*isVolatile*/false, /*AlwaysInline=*/true, 1644 MachinePointerInfo(), MachinePointerInfo()); 1645 } 1646 1647 /// IsTailCallConvention - Return true if the calling convention is one that 1648 /// supports tail call optimization. 1649 static bool IsTailCallConvention(CallingConv::ID CC) { 1650 return (CC == CallingConv::Fast || CC == CallingConv::GHC); 1651 } 1652 1653 bool X86TargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const { 1654 if (!CI->isTailCall()) 1655 return false; 1656 1657 CallSite CS(CI); 1658 CallingConv::ID CalleeCC = CS.getCallingConv(); 1659 if (!IsTailCallConvention(CalleeCC) && CalleeCC != CallingConv::C) 1660 return false; 1661 1662 return true; 1663 } 1664 1665 /// FuncIsMadeTailCallSafe - Return true if the function is being made into 1666 /// a tailcall target by changing its ABI. 1667 static bool FuncIsMadeTailCallSafe(CallingConv::ID CC) { 1668 return GuaranteedTailCallOpt && IsTailCallConvention(CC); 1669 } 1670 1671 SDValue 1672 X86TargetLowering::LowerMemArgument(SDValue Chain, 1673 CallingConv::ID CallConv, 1674 const SmallVectorImpl<ISD::InputArg> &Ins, 1675 DebugLoc dl, SelectionDAG &DAG, 1676 const CCValAssign &VA, 1677 MachineFrameInfo *MFI, 1678 unsigned i) const { 1679 // Create the nodes corresponding to a load from this parameter slot. 1680 ISD::ArgFlagsTy Flags = Ins[i].Flags; 1681 bool AlwaysUseMutable = FuncIsMadeTailCallSafe(CallConv); 1682 bool isImmutable = !AlwaysUseMutable && !Flags.isByVal(); 1683 EVT ValVT; 1684 1685 // If value is passed by pointer we have address passed instead of the value 1686 // itself. 1687 if (VA.getLocInfo() == CCValAssign::Indirect) 1688 ValVT = VA.getLocVT(); 1689 else 1690 ValVT = VA.getValVT(); 1691 1692 // FIXME: For now, all byval parameter objects are marked mutable. This can be 1693 // changed with more analysis. 1694 // In case of tail call optimization mark all arguments mutable. Since they 1695 // could be overwritten by lowering of arguments in case of a tail call. 1696 if (Flags.isByVal()) { 1697 unsigned Bytes = Flags.getByValSize(); 1698 if (Bytes == 0) Bytes = 1; // Don't create zero-sized stack objects. 1699 int FI = MFI->CreateFixedObject(Bytes, VA.getLocMemOffset(), isImmutable); 1700 return DAG.getFrameIndex(FI, getPointerTy()); 1701 } else { 1702 int FI = MFI->CreateFixedObject(ValVT.getSizeInBits()/8, 1703 VA.getLocMemOffset(), isImmutable); 1704 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy()); 1705 return DAG.getLoad(ValVT, dl, Chain, FIN, 1706 MachinePointerInfo::getFixedStack(FI), 1707 false, false, 0); 1708 } 1709 } 1710 1711 SDValue 1712 X86TargetLowering::LowerFormalArguments(SDValue Chain, 1713 CallingConv::ID CallConv, 1714 bool isVarArg, 1715 const SmallVectorImpl<ISD::InputArg> &Ins, 1716 DebugLoc dl, 1717 SelectionDAG &DAG, 1718 SmallVectorImpl<SDValue> &InVals) 1719 const { 1720 MachineFunction &MF = DAG.getMachineFunction(); 1721 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1722 1723 const Function* Fn = MF.getFunction(); 1724 if (Fn->hasExternalLinkage() && 1725 Subtarget->isTargetCygMing() && 1726 Fn->getName() == "main") 1727 FuncInfo->setForceFramePointer(true); 1728 1729 MachineFrameInfo *MFI = MF.getFrameInfo(); 1730 bool Is64Bit = Subtarget->is64Bit(); 1731 bool IsWin64 = Subtarget->isTargetWin64(); 1732 1733 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 1734 "Var args not supported with calling convention fastcc or ghc"); 1735 1736 // Assign locations to all of the incoming arguments. 1737 SmallVector<CCValAssign, 16> ArgLocs; 1738 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 1739 ArgLocs, *DAG.getContext()); 1740 1741 // Allocate shadow area for Win64 1742 if (IsWin64) { 1743 CCInfo.AllocateStack(32, 8); 1744 } 1745 1746 CCInfo.AnalyzeFormalArguments(Ins, CC_X86); 1747 1748 unsigned LastVal = ~0U; 1749 SDValue ArgValue; 1750 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 1751 CCValAssign &VA = ArgLocs[i]; 1752 // TODO: If an arg is passed in two places (e.g. reg and stack), skip later 1753 // places. 1754 assert(VA.getValNo() != LastVal && 1755 "Don't support value assigned to multiple locs yet"); 1756 (void)LastVal; 1757 LastVal = VA.getValNo(); 1758 1759 if (VA.isRegLoc()) { 1760 EVT RegVT = VA.getLocVT(); 1761 TargetRegisterClass *RC = NULL; 1762 if (RegVT == MVT::i32) 1763 RC = X86::GR32RegisterClass; 1764 else if (Is64Bit && RegVT == MVT::i64) 1765 RC = X86::GR64RegisterClass; 1766 else if (RegVT == MVT::f32) 1767 RC = X86::FR32RegisterClass; 1768 else if (RegVT == MVT::f64) 1769 RC = X86::FR64RegisterClass; 1770 else if (RegVT.isVector() && RegVT.getSizeInBits() == 256) 1771 RC = X86::VR256RegisterClass; 1772 else if (RegVT.isVector() && RegVT.getSizeInBits() == 128) 1773 RC = X86::VR128RegisterClass; 1774 else if (RegVT == MVT::x86mmx) 1775 RC = X86::VR64RegisterClass; 1776 else 1777 llvm_unreachable("Unknown argument type!"); 1778 1779 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); 1780 ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT); 1781 1782 // If this is an 8 or 16-bit value, it is really passed promoted to 32 1783 // bits. Insert an assert[sz]ext to capture this, then truncate to the 1784 // right size. 1785 if (VA.getLocInfo() == CCValAssign::SExt) 1786 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue, 1787 DAG.getValueType(VA.getValVT())); 1788 else if (VA.getLocInfo() == CCValAssign::ZExt) 1789 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue, 1790 DAG.getValueType(VA.getValVT())); 1791 else if (VA.getLocInfo() == CCValAssign::BCvt) 1792 ArgValue = DAG.getNode(ISD::BITCAST, dl, VA.getValVT(), ArgValue); 1793 1794 if (VA.isExtInLoc()) { 1795 // Handle MMX values passed in XMM regs. 1796 if (RegVT.isVector()) { 1797 ArgValue = DAG.getNode(X86ISD::MOVDQ2Q, dl, VA.getValVT(), 1798 ArgValue); 1799 } else 1800 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue); 1801 } 1802 } else { 1803 assert(VA.isMemLoc()); 1804 ArgValue = LowerMemArgument(Chain, CallConv, Ins, dl, DAG, VA, MFI, i); 1805 } 1806 1807 // If value is passed via pointer - do a load. 1808 if (VA.getLocInfo() == CCValAssign::Indirect) 1809 ArgValue = DAG.getLoad(VA.getValVT(), dl, Chain, ArgValue, 1810 MachinePointerInfo(), false, false, 0); 1811 1812 InVals.push_back(ArgValue); 1813 } 1814 1815 // The x86-64 ABI for returning structs by value requires that we copy 1816 // the sret argument into %rax for the return. Save the argument into 1817 // a virtual register so that we can access it from the return points. 1818 if (Is64Bit && MF.getFunction()->hasStructRetAttr()) { 1819 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 1820 unsigned Reg = FuncInfo->getSRetReturnReg(); 1821 if (!Reg) { 1822 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); 1823 FuncInfo->setSRetReturnReg(Reg); 1824 } 1825 SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]); 1826 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain); 1827 } 1828 1829 unsigned StackSize = CCInfo.getNextStackOffset(); 1830 // Align stack specially for tail calls. 1831 if (FuncIsMadeTailCallSafe(CallConv)) 1832 StackSize = GetAlignedArgumentStackSize(StackSize, DAG); 1833 1834 // If the function takes variable number of arguments, make a frame index for 1835 // the start of the first vararg value... for expansion of llvm.va_start. 1836 if (isVarArg) { 1837 if (Is64Bit || (CallConv != CallingConv::X86_FastCall && 1838 CallConv != CallingConv::X86_ThisCall)) { 1839 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize,true)); 1840 } 1841 if (Is64Bit) { 1842 unsigned TotalNumIntRegs = 0, TotalNumXMMRegs = 0; 1843 1844 // FIXME: We should really autogenerate these arrays 1845 static const unsigned GPR64ArgRegsWin64[] = { 1846 X86::RCX, X86::RDX, X86::R8, X86::R9 1847 }; 1848 static const unsigned GPR64ArgRegs64Bit[] = { 1849 X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9 1850 }; 1851 static const unsigned XMMArgRegs64Bit[] = { 1852 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 1853 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 1854 }; 1855 const unsigned *GPR64ArgRegs; 1856 unsigned NumXMMRegs = 0; 1857 1858 if (IsWin64) { 1859 // The XMM registers which might contain var arg parameters are shadowed 1860 // in their paired GPR. So we only need to save the GPR to their home 1861 // slots. 1862 TotalNumIntRegs = 4; 1863 GPR64ArgRegs = GPR64ArgRegsWin64; 1864 } else { 1865 TotalNumIntRegs = 6; TotalNumXMMRegs = 8; 1866 GPR64ArgRegs = GPR64ArgRegs64Bit; 1867 1868 NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs64Bit, TotalNumXMMRegs); 1869 } 1870 unsigned NumIntRegs = CCInfo.getFirstUnallocated(GPR64ArgRegs, 1871 TotalNumIntRegs); 1872 1873 bool NoImplicitFloatOps = Fn->hasFnAttr(Attribute::NoImplicitFloat); 1874 assert(!(NumXMMRegs && !Subtarget->hasXMM()) && 1875 "SSE register cannot be used when SSE is disabled!"); 1876 assert(!(NumXMMRegs && UseSoftFloat && NoImplicitFloatOps) && 1877 "SSE register cannot be used when SSE is disabled!"); 1878 if (UseSoftFloat || NoImplicitFloatOps || !Subtarget->hasXMM()) 1879 // Kernel mode asks for SSE to be disabled, so don't push them 1880 // on the stack. 1881 TotalNumXMMRegs = 0; 1882 1883 if (IsWin64) { 1884 const TargetFrameLowering &TFI = *getTargetMachine().getFrameLowering(); 1885 // Get to the caller-allocated home save location. Add 8 to account 1886 // for the return address. 1887 int HomeOffset = TFI.getOffsetOfLocalArea() + 8; 1888 FuncInfo->setRegSaveFrameIndex( 1889 MFI->CreateFixedObject(1, NumIntRegs * 8 + HomeOffset, false)); 1890 // Fixup to set vararg frame on shadow area (4 x i64). 1891 if (NumIntRegs < 4) 1892 FuncInfo->setVarArgsFrameIndex(FuncInfo->getRegSaveFrameIndex()); 1893 } else { 1894 // For X86-64, if there are vararg parameters that are passed via 1895 // registers, then we must store them to their spots on the stack so they 1896 // may be loaded by deferencing the result of va_next. 1897 FuncInfo->setVarArgsGPOffset(NumIntRegs * 8); 1898 FuncInfo->setVarArgsFPOffset(TotalNumIntRegs * 8 + NumXMMRegs * 16); 1899 FuncInfo->setRegSaveFrameIndex( 1900 MFI->CreateStackObject(TotalNumIntRegs * 8 + TotalNumXMMRegs * 16, 16, 1901 false)); 1902 } 1903 1904 // Store the integer parameter registers. 1905 SmallVector<SDValue, 8> MemOps; 1906 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 1907 getPointerTy()); 1908 unsigned Offset = FuncInfo->getVarArgsGPOffset(); 1909 for (; NumIntRegs != TotalNumIntRegs; ++NumIntRegs) { 1910 SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN, 1911 DAG.getIntPtrConstant(Offset)); 1912 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], 1913 X86::GR64RegisterClass); 1914 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64); 1915 SDValue Store = 1916 DAG.getStore(Val.getValue(1), dl, Val, FIN, 1917 MachinePointerInfo::getFixedStack( 1918 FuncInfo->getRegSaveFrameIndex(), Offset), 1919 false, false, 0); 1920 MemOps.push_back(Store); 1921 Offset += 8; 1922 } 1923 1924 if (TotalNumXMMRegs != 0 && NumXMMRegs != TotalNumXMMRegs) { 1925 // Now store the XMM (fp + vector) parameter registers. 1926 SmallVector<SDValue, 11> SaveXMMOps; 1927 SaveXMMOps.push_back(Chain); 1928 1929 unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass); 1930 SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8); 1931 SaveXMMOps.push_back(ALVal); 1932 1933 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1934 FuncInfo->getRegSaveFrameIndex())); 1935 SaveXMMOps.push_back(DAG.getIntPtrConstant( 1936 FuncInfo->getVarArgsFPOffset())); 1937 1938 for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) { 1939 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], 1940 X86::VR128RegisterClass); 1941 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32); 1942 SaveXMMOps.push_back(Val); 1943 } 1944 MemOps.push_back(DAG.getNode(X86ISD::VASTART_SAVE_XMM_REGS, dl, 1945 MVT::Other, 1946 &SaveXMMOps[0], SaveXMMOps.size())); 1947 } 1948 1949 if (!MemOps.empty()) 1950 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1951 &MemOps[0], MemOps.size()); 1952 } 1953 } 1954 1955 // Some CCs need callee pop. 1956 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) { 1957 FuncInfo->setBytesToPopOnReturn(StackSize); // Callee pops everything. 1958 } else { 1959 FuncInfo->setBytesToPopOnReturn(0); // Callee pops nothing. 1960 // If this is an sret function, the return should pop the hidden pointer. 1961 if (!Is64Bit && !IsTailCallConvention(CallConv) && ArgsAreStructReturn(Ins)) 1962 FuncInfo->setBytesToPopOnReturn(4); 1963 } 1964 1965 if (!Is64Bit) { 1966 // RegSaveFrameIndex is X86-64 only. 1967 FuncInfo->setRegSaveFrameIndex(0xAAAAAAA); 1968 if (CallConv == CallingConv::X86_FastCall || 1969 CallConv == CallingConv::X86_ThisCall) 1970 // fastcc functions can't have varargs. 1971 FuncInfo->setVarArgsFrameIndex(0xAAAAAAA); 1972 } 1973 1974 FuncInfo->setArgumentStackSize(StackSize); 1975 1976 return Chain; 1977 } 1978 1979 SDValue 1980 X86TargetLowering::LowerMemOpCallTo(SDValue Chain, 1981 SDValue StackPtr, SDValue Arg, 1982 DebugLoc dl, SelectionDAG &DAG, 1983 const CCValAssign &VA, 1984 ISD::ArgFlagsTy Flags) const { 1985 unsigned LocMemOffset = VA.getLocMemOffset(); 1986 SDValue PtrOff = DAG.getIntPtrConstant(LocMemOffset); 1987 PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, PtrOff); 1988 if (Flags.isByVal()) 1989 return CreateCopyOfByValArgument(Arg, PtrOff, Chain, Flags, DAG, dl); 1990 1991 return DAG.getStore(Chain, dl, Arg, PtrOff, 1992 MachinePointerInfo::getStack(LocMemOffset), 1993 false, false, 0); 1994 } 1995 1996 /// EmitTailCallLoadRetAddr - Emit a load of return address if tail call 1997 /// optimization is performed and it is required. 1998 SDValue 1999 X86TargetLowering::EmitTailCallLoadRetAddr(SelectionDAG &DAG, 2000 SDValue &OutRetAddr, SDValue Chain, 2001 bool IsTailCall, bool Is64Bit, 2002 int FPDiff, DebugLoc dl) const { 2003 // Adjust the Return address stack slot. 2004 EVT VT = getPointerTy(); 2005 OutRetAddr = getReturnAddressFrameIndex(DAG); 2006 2007 // Load the "old" Return address. 2008 OutRetAddr = DAG.getLoad(VT, dl, Chain, OutRetAddr, MachinePointerInfo(), 2009 false, false, 0); 2010 return SDValue(OutRetAddr.getNode(), 1); 2011 } 2012 2013 /// EmitTailCallStoreRetAddr - Emit a store of the return address if tail call 2014 /// optimization is performed and it is required (FPDiff!=0). 2015 static SDValue 2016 EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF, 2017 SDValue Chain, SDValue RetAddrFrIdx, 2018 bool Is64Bit, int FPDiff, DebugLoc dl) { 2019 // Store the return address to the appropriate stack slot. 2020 if (!FPDiff) return Chain; 2021 // Calculate the new stack slot for the return address. 2022 int SlotSize = Is64Bit ? 8 : 4; 2023 int NewReturnAddrFI = 2024 MF.getFrameInfo()->CreateFixedObject(SlotSize, FPDiff-SlotSize, false); 2025 EVT VT = Is64Bit ? MVT::i64 : MVT::i32; 2026 SDValue NewRetAddrFrIdx = DAG.getFrameIndex(NewReturnAddrFI, VT); 2027 Chain = DAG.getStore(Chain, dl, RetAddrFrIdx, NewRetAddrFrIdx, 2028 MachinePointerInfo::getFixedStack(NewReturnAddrFI), 2029 false, false, 0); 2030 return Chain; 2031 } 2032 2033 SDValue 2034 X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee, 2035 CallingConv::ID CallConv, bool isVarArg, 2036 bool &isTailCall, 2037 const SmallVectorImpl<ISD::OutputArg> &Outs, 2038 const SmallVectorImpl<SDValue> &OutVals, 2039 const SmallVectorImpl<ISD::InputArg> &Ins, 2040 DebugLoc dl, SelectionDAG &DAG, 2041 SmallVectorImpl<SDValue> &InVals) const { 2042 MachineFunction &MF = DAG.getMachineFunction(); 2043 bool Is64Bit = Subtarget->is64Bit(); 2044 bool IsWin64 = Subtarget->isTargetWin64(); 2045 bool IsStructRet = CallIsStructReturn(Outs); 2046 bool IsSibcall = false; 2047 2048 if (isTailCall) { 2049 // Check if it's really possible to do a tail call. 2050 isTailCall = IsEligibleForTailCallOptimization(Callee, CallConv, 2051 isVarArg, IsStructRet, MF.getFunction()->hasStructRetAttr(), 2052 Outs, OutVals, Ins, DAG); 2053 2054 // Sibcalls are automatically detected tailcalls which do not require 2055 // ABI changes. 2056 if (!GuaranteedTailCallOpt && isTailCall) 2057 IsSibcall = true; 2058 2059 if (isTailCall) 2060 ++NumTailCalls; 2061 } 2062 2063 assert(!(isVarArg && IsTailCallConvention(CallConv)) && 2064 "Var args not supported with calling convention fastcc or ghc"); 2065 2066 // Analyze operands of the call, assigning locations to each operand. 2067 SmallVector<CCValAssign, 16> ArgLocs; 2068 CCState CCInfo(CallConv, isVarArg, MF, getTargetMachine(), 2069 ArgLocs, *DAG.getContext()); 2070 2071 // Allocate shadow area for Win64 2072 if (IsWin64) { 2073 CCInfo.AllocateStack(32, 8); 2074 } 2075 2076 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2077 2078 // Get a count of how many bytes are to be pushed on the stack. 2079 unsigned NumBytes = CCInfo.getNextStackOffset(); 2080 if (IsSibcall) 2081 // This is a sibcall. The memory operands are available in caller's 2082 // own caller's stack. 2083 NumBytes = 0; 2084 else if (GuaranteedTailCallOpt && IsTailCallConvention(CallConv)) 2085 NumBytes = GetAlignedArgumentStackSize(NumBytes, DAG); 2086 2087 int FPDiff = 0; 2088 if (isTailCall && !IsSibcall) { 2089 // Lower arguments at fp - stackoffset + fpdiff. 2090 unsigned NumBytesCallerPushed = 2091 MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn(); 2092 FPDiff = NumBytesCallerPushed - NumBytes; 2093 2094 // Set the delta of movement of the returnaddr stackslot. 2095 // But only set if delta is greater than previous delta. 2096 if (FPDiff < (MF.getInfo<X86MachineFunctionInfo>()->getTCReturnAddrDelta())) 2097 MF.getInfo<X86MachineFunctionInfo>()->setTCReturnAddrDelta(FPDiff); 2098 } 2099 2100 if (!IsSibcall) 2101 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true)); 2102 2103 SDValue RetAddrFrIdx; 2104 // Load return address for tail calls. 2105 if (isTailCall && FPDiff) 2106 Chain = EmitTailCallLoadRetAddr(DAG, RetAddrFrIdx, Chain, isTailCall, 2107 Is64Bit, FPDiff, dl); 2108 2109 SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass; 2110 SmallVector<SDValue, 8> MemOpChains; 2111 SDValue StackPtr; 2112 2113 // Walk the register/memloc assignments, inserting copies/loads. In the case 2114 // of tail call optimization arguments are handle later. 2115 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2116 CCValAssign &VA = ArgLocs[i]; 2117 EVT RegVT = VA.getLocVT(); 2118 SDValue Arg = OutVals[i]; 2119 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2120 bool isByVal = Flags.isByVal(); 2121 2122 // Promote the value if needed. 2123 switch (VA.getLocInfo()) { 2124 default: llvm_unreachable("Unknown loc info!"); 2125 case CCValAssign::Full: break; 2126 case CCValAssign::SExt: 2127 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, RegVT, Arg); 2128 break; 2129 case CCValAssign::ZExt: 2130 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); 2131 break; 2132 case CCValAssign::AExt: 2133 if (RegVT.isVector() && RegVT.getSizeInBits() == 128) { 2134 // Special case: passing MMX values in XMM registers. 2135 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg); 2136 Arg = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2i64, Arg); 2137 Arg = getMOVL(DAG, dl, MVT::v2i64, DAG.getUNDEF(MVT::v2i64), Arg); 2138 } else 2139 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, RegVT, Arg); 2140 break; 2141 case CCValAssign::BCvt: 2142 Arg = DAG.getNode(ISD::BITCAST, dl, RegVT, Arg); 2143 break; 2144 case CCValAssign::Indirect: { 2145 // Store the argument. 2146 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT()); 2147 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex(); 2148 Chain = DAG.getStore(Chain, dl, Arg, SpillSlot, 2149 MachinePointerInfo::getFixedStack(FI), 2150 false, false, 0); 2151 Arg = SpillSlot; 2152 break; 2153 } 2154 } 2155 2156 if (VA.isRegLoc()) { 2157 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg)); 2158 if (isVarArg && IsWin64) { 2159 // Win64 ABI requires argument XMM reg to be copied to the corresponding 2160 // shadow reg if callee is a varargs function. 2161 unsigned ShadowReg = 0; 2162 switch (VA.getLocReg()) { 2163 case X86::XMM0: ShadowReg = X86::RCX; break; 2164 case X86::XMM1: ShadowReg = X86::RDX; break; 2165 case X86::XMM2: ShadowReg = X86::R8; break; 2166 case X86::XMM3: ShadowReg = X86::R9; break; 2167 } 2168 if (ShadowReg) 2169 RegsToPass.push_back(std::make_pair(ShadowReg, Arg)); 2170 } 2171 } else if (!IsSibcall && (!isTailCall || isByVal)) { 2172 assert(VA.isMemLoc()); 2173 if (StackPtr.getNode() == 0) 2174 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, getPointerTy()); 2175 MemOpChains.push_back(LowerMemOpCallTo(Chain, StackPtr, Arg, 2176 dl, DAG, VA, Flags)); 2177 } 2178 } 2179 2180 if (!MemOpChains.empty()) 2181 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2182 &MemOpChains[0], MemOpChains.size()); 2183 2184 // Build a sequence of copy-to-reg nodes chained together with token chain 2185 // and flag operands which copy the outgoing args into registers. 2186 SDValue InFlag; 2187 // Tail call byval lowering might overwrite argument registers so in case of 2188 // tail call optimization the copies to registers are lowered later. 2189 if (!isTailCall) 2190 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2191 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2192 RegsToPass[i].second, InFlag); 2193 InFlag = Chain.getValue(1); 2194 } 2195 2196 if (Subtarget->isPICStyleGOT()) { 2197 // ELF / PIC requires GOT in the EBX register before function calls via PLT 2198 // GOT pointer. 2199 if (!isTailCall) { 2200 Chain = DAG.getCopyToReg(Chain, dl, X86::EBX, 2201 DAG.getNode(X86ISD::GlobalBaseReg, 2202 DebugLoc(), getPointerTy()), 2203 InFlag); 2204 InFlag = Chain.getValue(1); 2205 } else { 2206 // If we are tail calling and generating PIC/GOT style code load the 2207 // address of the callee into ECX. The value in ecx is used as target of 2208 // the tail jump. This is done to circumvent the ebx/callee-saved problem 2209 // for tail calls on PIC/GOT architectures. Normally we would just put the 2210 // address of GOT into ebx and then call target@PLT. But for tail calls 2211 // ebx would be restored (since ebx is callee saved) before jumping to the 2212 // target@PLT. 2213 2214 // Note: The actual moving to ECX is done further down. 2215 GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee); 2216 if (G && !G->getGlobal()->hasHiddenVisibility() && 2217 !G->getGlobal()->hasProtectedVisibility()) 2218 Callee = LowerGlobalAddress(Callee, DAG); 2219 else if (isa<ExternalSymbolSDNode>(Callee)) 2220 Callee = LowerExternalSymbol(Callee, DAG); 2221 } 2222 } 2223 2224 if (Is64Bit && isVarArg && !IsWin64) { 2225 // From AMD64 ABI document: 2226 // For calls that may call functions that use varargs or stdargs 2227 // (prototype-less calls or calls to functions containing ellipsis (...) in 2228 // the declaration) %al is used as hidden argument to specify the number 2229 // of SSE registers used. The contents of %al do not need to match exactly 2230 // the number of registers, but must be an ubound on the number of SSE 2231 // registers used and is in the range 0 - 8 inclusive. 2232 2233 // Count the number of XMM registers allocated. 2234 static const unsigned XMMArgRegs[] = { 2235 X86::XMM0, X86::XMM1, X86::XMM2, X86::XMM3, 2236 X86::XMM4, X86::XMM5, X86::XMM6, X86::XMM7 2237 }; 2238 unsigned NumXMMRegs = CCInfo.getFirstUnallocated(XMMArgRegs, 8); 2239 assert((Subtarget->hasXMM() || !NumXMMRegs) 2240 && "SSE registers cannot be used when SSE is disabled"); 2241 2242 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, 2243 DAG.getConstant(NumXMMRegs, MVT::i8), InFlag); 2244 InFlag = Chain.getValue(1); 2245 } 2246 2247 2248 // For tail calls lower the arguments to the 'real' stack slot. 2249 if (isTailCall) { 2250 // Force all the incoming stack arguments to be loaded from the stack 2251 // before any new outgoing arguments are stored to the stack, because the 2252 // outgoing stack slots may alias the incoming argument stack slots, and 2253 // the alias isn't otherwise explicit. This is slightly more conservative 2254 // than necessary, because it means that each store effectively depends 2255 // on every argument instead of just those arguments it would clobber. 2256 SDValue ArgChain = DAG.getStackArgumentTokenFactor(Chain); 2257 2258 SmallVector<SDValue, 8> MemOpChains2; 2259 SDValue FIN; 2260 int FI = 0; 2261 // Do not flag preceding copytoreg stuff together with the following stuff. 2262 InFlag = SDValue(); 2263 if (GuaranteedTailCallOpt) { 2264 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2265 CCValAssign &VA = ArgLocs[i]; 2266 if (VA.isRegLoc()) 2267 continue; 2268 assert(VA.isMemLoc()); 2269 SDValue Arg = OutVals[i]; 2270 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2271 // Create frame index. 2272 int32_t Offset = VA.getLocMemOffset()+FPDiff; 2273 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; 2274 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); 2275 FIN = DAG.getFrameIndex(FI, getPointerTy()); 2276 2277 if (Flags.isByVal()) { 2278 // Copy relative to framepointer. 2279 SDValue Source = DAG.getIntPtrConstant(VA.getLocMemOffset()); 2280 if (StackPtr.getNode() == 0) 2281 StackPtr = DAG.getCopyFromReg(Chain, dl, X86StackPtr, 2282 getPointerTy()); 2283 Source = DAG.getNode(ISD::ADD, dl, getPointerTy(), StackPtr, Source); 2284 2285 MemOpChains2.push_back(CreateCopyOfByValArgument(Source, FIN, 2286 ArgChain, 2287 Flags, DAG, dl)); 2288 } else { 2289 // Store relative to framepointer. 2290 MemOpChains2.push_back( 2291 DAG.getStore(ArgChain, dl, Arg, FIN, 2292 MachinePointerInfo::getFixedStack(FI), 2293 false, false, 0)); 2294 } 2295 } 2296 } 2297 2298 if (!MemOpChains2.empty()) 2299 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 2300 &MemOpChains2[0], MemOpChains2.size()); 2301 2302 // Copy arguments to their registers. 2303 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { 2304 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, 2305 RegsToPass[i].second, InFlag); 2306 InFlag = Chain.getValue(1); 2307 } 2308 InFlag =SDValue(); 2309 2310 // Store the return address to the appropriate stack slot. 2311 Chain = EmitTailCallStoreRetAddr(DAG, MF, Chain, RetAddrFrIdx, Is64Bit, 2312 FPDiff, dl); 2313 } 2314 2315 if (getTargetMachine().getCodeModel() == CodeModel::Large) { 2316 assert(Is64Bit && "Large code model is only legal in 64-bit mode."); 2317 // In the 64-bit large code model, we have to make all calls 2318 // through a register, since the call instruction's 32-bit 2319 // pc-relative offset may not be large enough to hold the whole 2320 // address. 2321 } else if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) { 2322 // If the callee is a GlobalAddress node (quite common, every direct call 2323 // is) turn it into a TargetGlobalAddress node so that legalize doesn't hack 2324 // it. 2325 2326 // We should use extra load for direct calls to dllimported functions in 2327 // non-JIT mode. 2328 const GlobalValue *GV = G->getGlobal(); 2329 if (!GV->hasDLLImportLinkage()) { 2330 unsigned char OpFlags = 0; 2331 bool ExtraLoad = false; 2332 unsigned WrapperKind = ISD::DELETED_NODE; 2333 2334 // On ELF targets, in both X86-64 and X86-32 mode, direct calls to 2335 // external symbols most go through the PLT in PIC mode. If the symbol 2336 // has hidden or protected visibility, or if it is static or local, then 2337 // we don't need to use the PLT - we can directly call it. 2338 if (Subtarget->isTargetELF() && 2339 getTargetMachine().getRelocationModel() == Reloc::PIC_ && 2340 GV->hasDefaultVisibility() && !GV->hasLocalLinkage()) { 2341 OpFlags = X86II::MO_PLT; 2342 } else if (Subtarget->isPICStyleStubAny() && 2343 (GV->isDeclaration() || GV->isWeakForLinker()) && 2344 (!Subtarget->getTargetTriple().isMacOSX() || 2345 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2346 // PC-relative references to external symbols should go through $stub, 2347 // unless we're building with the leopard linker or later, which 2348 // automatically synthesizes these stubs. 2349 OpFlags = X86II::MO_DARWIN_STUB; 2350 } else if (Subtarget->isPICStyleRIPRel() && 2351 isa<Function>(GV) && 2352 cast<Function>(GV)->hasFnAttr(Attribute::NonLazyBind)) { 2353 // If the function is marked as non-lazy, generate an indirect call 2354 // which loads from the GOT directly. This avoids runtime overhead 2355 // at the cost of eager binding (and one extra byte of encoding). 2356 OpFlags = X86II::MO_GOTPCREL; 2357 WrapperKind = X86ISD::WrapperRIP; 2358 ExtraLoad = true; 2359 } 2360 2361 Callee = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 2362 G->getOffset(), OpFlags); 2363 2364 // Add a wrapper if needed. 2365 if (WrapperKind != ISD::DELETED_NODE) 2366 Callee = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Callee); 2367 // Add extra indirection if needed. 2368 if (ExtraLoad) 2369 Callee = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Callee, 2370 MachinePointerInfo::getGOT(), 2371 false, false, 0); 2372 } 2373 } else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee)) { 2374 unsigned char OpFlags = 0; 2375 2376 // On ELF targets, in either X86-64 or X86-32 mode, direct calls to 2377 // external symbols should go through the PLT. 2378 if (Subtarget->isTargetELF() && 2379 getTargetMachine().getRelocationModel() == Reloc::PIC_) { 2380 OpFlags = X86II::MO_PLT; 2381 } else if (Subtarget->isPICStyleStubAny() && 2382 (!Subtarget->getTargetTriple().isMacOSX() || 2383 Subtarget->getTargetTriple().isMacOSXVersionLT(10, 5))) { 2384 // PC-relative references to external symbols should go through $stub, 2385 // unless we're building with the leopard linker or later, which 2386 // automatically synthesizes these stubs. 2387 OpFlags = X86II::MO_DARWIN_STUB; 2388 } 2389 2390 Callee = DAG.getTargetExternalSymbol(S->getSymbol(), getPointerTy(), 2391 OpFlags); 2392 } 2393 2394 // Returns a chain & a flag for retval copy to use. 2395 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 2396 SmallVector<SDValue, 8> Ops; 2397 2398 if (!IsSibcall && isTailCall) { 2399 Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true), 2400 DAG.getIntPtrConstant(0, true), InFlag); 2401 InFlag = Chain.getValue(1); 2402 } 2403 2404 Ops.push_back(Chain); 2405 Ops.push_back(Callee); 2406 2407 if (isTailCall) 2408 Ops.push_back(DAG.getConstant(FPDiff, MVT::i32)); 2409 2410 // Add argument registers to the end of the list so that they are known live 2411 // into the call. 2412 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) 2413 Ops.push_back(DAG.getRegister(RegsToPass[i].first, 2414 RegsToPass[i].second.getValueType())); 2415 2416 // Add an implicit use GOT pointer in EBX. 2417 if (!isTailCall && Subtarget->isPICStyleGOT()) 2418 Ops.push_back(DAG.getRegister(X86::EBX, getPointerTy())); 2419 2420 // Add an implicit use of AL for non-Windows x86 64-bit vararg functions. 2421 if (Is64Bit && isVarArg && !IsWin64) 2422 Ops.push_back(DAG.getRegister(X86::AL, MVT::i8)); 2423 2424 if (InFlag.getNode()) 2425 Ops.push_back(InFlag); 2426 2427 if (isTailCall) { 2428 // We used to do: 2429 //// If this is the first return lowered for this function, add the regs 2430 //// to the liveout set for the function. 2431 // This isn't right, although it's probably harmless on x86; liveouts 2432 // should be computed from returns not tail calls. Consider a void 2433 // function making a tail call to a function returning int. 2434 return DAG.getNode(X86ISD::TC_RETURN, dl, 2435 NodeTys, &Ops[0], Ops.size()); 2436 } 2437 2438 Chain = DAG.getNode(X86ISD::CALL, dl, NodeTys, &Ops[0], Ops.size()); 2439 InFlag = Chain.getValue(1); 2440 2441 // Create the CALLSEQ_END node. 2442 unsigned NumBytesForCalleeToPush; 2443 if (X86::isCalleePop(CallConv, Is64Bit, isVarArg, GuaranteedTailCallOpt)) 2444 NumBytesForCalleeToPush = NumBytes; // Callee pops everything 2445 else if (!Is64Bit && !IsTailCallConvention(CallConv) && IsStructRet) 2446 // If this is a call to a struct-return function, the callee 2447 // pops the hidden struct pointer, so we have to push it back. 2448 // This is common for Darwin/X86, Linux & Mingw32 targets. 2449 NumBytesForCalleeToPush = 4; 2450 else 2451 NumBytesForCalleeToPush = 0; // Callee pops nothing. 2452 2453 // Returns a flag for retval copy to use. 2454 if (!IsSibcall) { 2455 Chain = DAG.getCALLSEQ_END(Chain, 2456 DAG.getIntPtrConstant(NumBytes, true), 2457 DAG.getIntPtrConstant(NumBytesForCalleeToPush, 2458 true), 2459 InFlag); 2460 InFlag = Chain.getValue(1); 2461 } 2462 2463 // Handle result values, copying them out of physregs into vregs that we 2464 // return. 2465 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, 2466 Ins, dl, DAG, InVals); 2467 } 2468 2469 2470 //===----------------------------------------------------------------------===// 2471 // Fast Calling Convention (tail call) implementation 2472 //===----------------------------------------------------------------------===// 2473 2474 // Like std call, callee cleans arguments, convention except that ECX is 2475 // reserved for storing the tail called function address. Only 2 registers are 2476 // free for argument passing (inreg). Tail call optimization is performed 2477 // provided: 2478 // * tailcallopt is enabled 2479 // * caller/callee are fastcc 2480 // On X86_64 architecture with GOT-style position independent code only local 2481 // (within module) calls are supported at the moment. 2482 // To keep the stack aligned according to platform abi the function 2483 // GetAlignedArgumentStackSize ensures that argument delta is always multiples 2484 // of stack alignment. (Dynamic linkers need this - darwin's dyld for example) 2485 // If a tail called function callee has more arguments than the caller the 2486 // caller needs to make sure that there is room to move the RETADDR to. This is 2487 // achieved by reserving an area the size of the argument delta right after the 2488 // original REtADDR, but before the saved framepointer or the spilled registers 2489 // e.g. caller(arg1, arg2) calls callee(arg1, arg2,arg3,arg4) 2490 // stack layout: 2491 // arg1 2492 // arg2 2493 // RETADDR 2494 // [ new RETADDR 2495 // move area ] 2496 // (possible EBP) 2497 // ESI 2498 // EDI 2499 // local1 .. 2500 2501 /// GetAlignedArgumentStackSize - Make the stack size align e.g 16n + 12 aligned 2502 /// for a 16 byte align requirement. 2503 unsigned 2504 X86TargetLowering::GetAlignedArgumentStackSize(unsigned StackSize, 2505 SelectionDAG& DAG) const { 2506 MachineFunction &MF = DAG.getMachineFunction(); 2507 const TargetMachine &TM = MF.getTarget(); 2508 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 2509 unsigned StackAlignment = TFI.getStackAlignment(); 2510 uint64_t AlignMask = StackAlignment - 1; 2511 int64_t Offset = StackSize; 2512 uint64_t SlotSize = TD->getPointerSize(); 2513 if ( (Offset & AlignMask) <= (StackAlignment - SlotSize) ) { 2514 // Number smaller than 12 so just add the difference. 2515 Offset += ((StackAlignment - SlotSize) - (Offset & AlignMask)); 2516 } else { 2517 // Mask out lower bits, add stackalignment once plus the 12 bytes. 2518 Offset = ((~AlignMask) & Offset) + StackAlignment + 2519 (StackAlignment-SlotSize); 2520 } 2521 return Offset; 2522 } 2523 2524 /// MatchingStackOffset - Return true if the given stack call argument is 2525 /// already available in the same position (relatively) of the caller's 2526 /// incoming argument stack. 2527 static 2528 bool MatchingStackOffset(SDValue Arg, unsigned Offset, ISD::ArgFlagsTy Flags, 2529 MachineFrameInfo *MFI, const MachineRegisterInfo *MRI, 2530 const X86InstrInfo *TII) { 2531 unsigned Bytes = Arg.getValueType().getSizeInBits() / 8; 2532 int FI = INT_MAX; 2533 if (Arg.getOpcode() == ISD::CopyFromReg) { 2534 unsigned VR = cast<RegisterSDNode>(Arg.getOperand(1))->getReg(); 2535 if (!TargetRegisterInfo::isVirtualRegister(VR)) 2536 return false; 2537 MachineInstr *Def = MRI->getVRegDef(VR); 2538 if (!Def) 2539 return false; 2540 if (!Flags.isByVal()) { 2541 if (!TII->isLoadFromStackSlot(Def, FI)) 2542 return false; 2543 } else { 2544 unsigned Opcode = Def->getOpcode(); 2545 if ((Opcode == X86::LEA32r || Opcode == X86::LEA64r) && 2546 Def->getOperand(1).isFI()) { 2547 FI = Def->getOperand(1).getIndex(); 2548 Bytes = Flags.getByValSize(); 2549 } else 2550 return false; 2551 } 2552 } else if (LoadSDNode *Ld = dyn_cast<LoadSDNode>(Arg)) { 2553 if (Flags.isByVal()) 2554 // ByVal argument is passed in as a pointer but it's now being 2555 // dereferenced. e.g. 2556 // define @foo(%struct.X* %A) { 2557 // tail call @bar(%struct.X* byval %A) 2558 // } 2559 return false; 2560 SDValue Ptr = Ld->getBasePtr(); 2561 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr); 2562 if (!FINode) 2563 return false; 2564 FI = FINode->getIndex(); 2565 } else if (Arg.getOpcode() == ISD::FrameIndex && Flags.isByVal()) { 2566 FrameIndexSDNode *FINode = cast<FrameIndexSDNode>(Arg); 2567 FI = FINode->getIndex(); 2568 Bytes = Flags.getByValSize(); 2569 } else 2570 return false; 2571 2572 assert(FI != INT_MAX); 2573 if (!MFI->isFixedObjectIndex(FI)) 2574 return false; 2575 return Offset == MFI->getObjectOffset(FI) && Bytes == MFI->getObjectSize(FI); 2576 } 2577 2578 /// IsEligibleForTailCallOptimization - Check whether the call is eligible 2579 /// for tail call optimization. Targets which want to do tail call 2580 /// optimization should implement this function. 2581 bool 2582 X86TargetLowering::IsEligibleForTailCallOptimization(SDValue Callee, 2583 CallingConv::ID CalleeCC, 2584 bool isVarArg, 2585 bool isCalleeStructRet, 2586 bool isCallerStructRet, 2587 const SmallVectorImpl<ISD::OutputArg> &Outs, 2588 const SmallVectorImpl<SDValue> &OutVals, 2589 const SmallVectorImpl<ISD::InputArg> &Ins, 2590 SelectionDAG& DAG) const { 2591 if (!IsTailCallConvention(CalleeCC) && 2592 CalleeCC != CallingConv::C) 2593 return false; 2594 2595 // If -tailcallopt is specified, make fastcc functions tail-callable. 2596 const MachineFunction &MF = DAG.getMachineFunction(); 2597 const Function *CallerF = DAG.getMachineFunction().getFunction(); 2598 CallingConv::ID CallerCC = CallerF->getCallingConv(); 2599 bool CCMatch = CallerCC == CalleeCC; 2600 2601 if (GuaranteedTailCallOpt) { 2602 if (IsTailCallConvention(CalleeCC) && CCMatch) 2603 return true; 2604 return false; 2605 } 2606 2607 // Look for obvious safe cases to perform tail call optimization that do not 2608 // require ABI changes. This is what gcc calls sibcall. 2609 2610 // Can't do sibcall if stack needs to be dynamically re-aligned. PEI needs to 2611 // emit a special epilogue. 2612 if (RegInfo->needsStackRealignment(MF)) 2613 return false; 2614 2615 // Also avoid sibcall optimization if either caller or callee uses struct 2616 // return semantics. 2617 if (isCalleeStructRet || isCallerStructRet) 2618 return false; 2619 2620 // An stdcall caller is expected to clean up its arguments; the callee 2621 // isn't going to do that. 2622 if (!CCMatch && CallerCC==CallingConv::X86_StdCall) 2623 return false; 2624 2625 // Do not sibcall optimize vararg calls unless all arguments are passed via 2626 // registers. 2627 if (isVarArg && !Outs.empty()) { 2628 2629 // Optimizing for varargs on Win64 is unlikely to be safe without 2630 // additional testing. 2631 if (Subtarget->isTargetWin64()) 2632 return false; 2633 2634 SmallVector<CCValAssign, 16> ArgLocs; 2635 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2636 getTargetMachine(), ArgLocs, *DAG.getContext()); 2637 2638 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2639 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) 2640 if (!ArgLocs[i].isRegLoc()) 2641 return false; 2642 } 2643 2644 // If the call result is in ST0 / ST1, it needs to be popped off the x87 stack. 2645 // Therefore if it's not used by the call it is not safe to optimize this into 2646 // a sibcall. 2647 bool Unused = false; 2648 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 2649 if (!Ins[i].Used) { 2650 Unused = true; 2651 break; 2652 } 2653 } 2654 if (Unused) { 2655 SmallVector<CCValAssign, 16> RVLocs; 2656 CCState CCInfo(CalleeCC, false, DAG.getMachineFunction(), 2657 getTargetMachine(), RVLocs, *DAG.getContext()); 2658 CCInfo.AnalyzeCallResult(Ins, RetCC_X86); 2659 for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) { 2660 CCValAssign &VA = RVLocs[i]; 2661 if (VA.getLocReg() == X86::ST0 || VA.getLocReg() == X86::ST1) 2662 return false; 2663 } 2664 } 2665 2666 // If the calling conventions do not match, then we'd better make sure the 2667 // results are returned in the same way as what the caller expects. 2668 if (!CCMatch) { 2669 SmallVector<CCValAssign, 16> RVLocs1; 2670 CCState CCInfo1(CalleeCC, false, DAG.getMachineFunction(), 2671 getTargetMachine(), RVLocs1, *DAG.getContext()); 2672 CCInfo1.AnalyzeCallResult(Ins, RetCC_X86); 2673 2674 SmallVector<CCValAssign, 16> RVLocs2; 2675 CCState CCInfo2(CallerCC, false, DAG.getMachineFunction(), 2676 getTargetMachine(), RVLocs2, *DAG.getContext()); 2677 CCInfo2.AnalyzeCallResult(Ins, RetCC_X86); 2678 2679 if (RVLocs1.size() != RVLocs2.size()) 2680 return false; 2681 for (unsigned i = 0, e = RVLocs1.size(); i != e; ++i) { 2682 if (RVLocs1[i].isRegLoc() != RVLocs2[i].isRegLoc()) 2683 return false; 2684 if (RVLocs1[i].getLocInfo() != RVLocs2[i].getLocInfo()) 2685 return false; 2686 if (RVLocs1[i].isRegLoc()) { 2687 if (RVLocs1[i].getLocReg() != RVLocs2[i].getLocReg()) 2688 return false; 2689 } else { 2690 if (RVLocs1[i].getLocMemOffset() != RVLocs2[i].getLocMemOffset()) 2691 return false; 2692 } 2693 } 2694 } 2695 2696 // If the callee takes no arguments then go on to check the results of the 2697 // call. 2698 if (!Outs.empty()) { 2699 // Check if stack adjustment is needed. For now, do not do this if any 2700 // argument is passed on the stack. 2701 SmallVector<CCValAssign, 16> ArgLocs; 2702 CCState CCInfo(CalleeCC, isVarArg, DAG.getMachineFunction(), 2703 getTargetMachine(), ArgLocs, *DAG.getContext()); 2704 2705 // Allocate shadow area for Win64 2706 if (Subtarget->isTargetWin64()) { 2707 CCInfo.AllocateStack(32, 8); 2708 } 2709 2710 CCInfo.AnalyzeCallOperands(Outs, CC_X86); 2711 if (CCInfo.getNextStackOffset()) { 2712 MachineFunction &MF = DAG.getMachineFunction(); 2713 if (MF.getInfo<X86MachineFunctionInfo>()->getBytesToPopOnReturn()) 2714 return false; 2715 2716 // Check if the arguments are already laid out in the right way as 2717 // the caller's fixed stack objects. 2718 MachineFrameInfo *MFI = MF.getFrameInfo(); 2719 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 2720 const X86InstrInfo *TII = 2721 ((X86TargetMachine&)getTargetMachine()).getInstrInfo(); 2722 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2723 CCValAssign &VA = ArgLocs[i]; 2724 SDValue Arg = OutVals[i]; 2725 ISD::ArgFlagsTy Flags = Outs[i].Flags; 2726 if (VA.getLocInfo() == CCValAssign::Indirect) 2727 return false; 2728 if (!VA.isRegLoc()) { 2729 if (!MatchingStackOffset(Arg, VA.getLocMemOffset(), Flags, 2730 MFI, MRI, TII)) 2731 return false; 2732 } 2733 } 2734 } 2735 2736 // If the tailcall address may be in a register, then make sure it's 2737 // possible to register allocate for it. In 32-bit, the call address can 2738 // only target EAX, EDX, or ECX since the tail call must be scheduled after 2739 // callee-saved registers are restored. These happen to be the same 2740 // registers used to pass 'inreg' arguments so watch out for those. 2741 if (!Subtarget->is64Bit() && 2742 !isa<GlobalAddressSDNode>(Callee) && 2743 !isa<ExternalSymbolSDNode>(Callee)) { 2744 unsigned NumInRegs = 0; 2745 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { 2746 CCValAssign &VA = ArgLocs[i]; 2747 if (!VA.isRegLoc()) 2748 continue; 2749 unsigned Reg = VA.getLocReg(); 2750 switch (Reg) { 2751 default: break; 2752 case X86::EAX: case X86::EDX: case X86::ECX: 2753 if (++NumInRegs == 3) 2754 return false; 2755 break; 2756 } 2757 } 2758 } 2759 } 2760 2761 return true; 2762 } 2763 2764 FastISel * 2765 X86TargetLowering::createFastISel(FunctionLoweringInfo &funcInfo) const { 2766 return X86::createFastISel(funcInfo); 2767 } 2768 2769 2770 //===----------------------------------------------------------------------===// 2771 // Other Lowering Hooks 2772 //===----------------------------------------------------------------------===// 2773 2774 static bool MayFoldLoad(SDValue Op) { 2775 return Op.hasOneUse() && ISD::isNormalLoad(Op.getNode()); 2776 } 2777 2778 static bool MayFoldIntoStore(SDValue Op) { 2779 return Op.hasOneUse() && ISD::isNormalStore(*Op.getNode()->use_begin()); 2780 } 2781 2782 static bool isTargetShuffle(unsigned Opcode) { 2783 switch(Opcode) { 2784 default: return false; 2785 case X86ISD::PSHUFD: 2786 case X86ISD::PSHUFHW: 2787 case X86ISD::PSHUFLW: 2788 case X86ISD::SHUFPD: 2789 case X86ISD::PALIGN: 2790 case X86ISD::SHUFPS: 2791 case X86ISD::MOVLHPS: 2792 case X86ISD::MOVLHPD: 2793 case X86ISD::MOVHLPS: 2794 case X86ISD::MOVLPS: 2795 case X86ISD::MOVLPD: 2796 case X86ISD::MOVSHDUP: 2797 case X86ISD::MOVSLDUP: 2798 case X86ISD::MOVDDUP: 2799 case X86ISD::MOVSS: 2800 case X86ISD::MOVSD: 2801 case X86ISD::UNPCKLPS: 2802 case X86ISD::UNPCKLPD: 2803 case X86ISD::VUNPCKLPSY: 2804 case X86ISD::VUNPCKLPDY: 2805 case X86ISD::PUNPCKLWD: 2806 case X86ISD::PUNPCKLBW: 2807 case X86ISD::PUNPCKLDQ: 2808 case X86ISD::PUNPCKLQDQ: 2809 case X86ISD::UNPCKHPS: 2810 case X86ISD::UNPCKHPD: 2811 case X86ISD::VUNPCKHPSY: 2812 case X86ISD::VUNPCKHPDY: 2813 case X86ISD::PUNPCKHWD: 2814 case X86ISD::PUNPCKHBW: 2815 case X86ISD::PUNPCKHDQ: 2816 case X86ISD::PUNPCKHQDQ: 2817 case X86ISD::VPERMILPS: 2818 case X86ISD::VPERMILPSY: 2819 case X86ISD::VPERMILPD: 2820 case X86ISD::VPERMILPDY: 2821 case X86ISD::VPERM2F128: 2822 return true; 2823 } 2824 return false; 2825 } 2826 2827 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2828 SDValue V1, SelectionDAG &DAG) { 2829 switch(Opc) { 2830 default: llvm_unreachable("Unknown x86 shuffle node"); 2831 case X86ISD::MOVSHDUP: 2832 case X86ISD::MOVSLDUP: 2833 case X86ISD::MOVDDUP: 2834 return DAG.getNode(Opc, dl, VT, V1); 2835 } 2836 2837 return SDValue(); 2838 } 2839 2840 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2841 SDValue V1, unsigned TargetMask, SelectionDAG &DAG) { 2842 switch(Opc) { 2843 default: llvm_unreachable("Unknown x86 shuffle node"); 2844 case X86ISD::PSHUFD: 2845 case X86ISD::PSHUFHW: 2846 case X86ISD::PSHUFLW: 2847 case X86ISD::VPERMILPS: 2848 case X86ISD::VPERMILPSY: 2849 case X86ISD::VPERMILPD: 2850 case X86ISD::VPERMILPDY: 2851 return DAG.getNode(Opc, dl, VT, V1, DAG.getConstant(TargetMask, MVT::i8)); 2852 } 2853 2854 return SDValue(); 2855 } 2856 2857 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2858 SDValue V1, SDValue V2, unsigned TargetMask, SelectionDAG &DAG) { 2859 switch(Opc) { 2860 default: llvm_unreachable("Unknown x86 shuffle node"); 2861 case X86ISD::PALIGN: 2862 case X86ISD::SHUFPD: 2863 case X86ISD::SHUFPS: 2864 case X86ISD::VPERM2F128: 2865 return DAG.getNode(Opc, dl, VT, V1, V2, 2866 DAG.getConstant(TargetMask, MVT::i8)); 2867 } 2868 return SDValue(); 2869 } 2870 2871 static SDValue getTargetShuffleNode(unsigned Opc, DebugLoc dl, EVT VT, 2872 SDValue V1, SDValue V2, SelectionDAG &DAG) { 2873 switch(Opc) { 2874 default: llvm_unreachable("Unknown x86 shuffle node"); 2875 case X86ISD::MOVLHPS: 2876 case X86ISD::MOVLHPD: 2877 case X86ISD::MOVHLPS: 2878 case X86ISD::MOVLPS: 2879 case X86ISD::MOVLPD: 2880 case X86ISD::MOVSS: 2881 case X86ISD::MOVSD: 2882 case X86ISD::UNPCKLPS: 2883 case X86ISD::UNPCKLPD: 2884 case X86ISD::VUNPCKLPSY: 2885 case X86ISD::VUNPCKLPDY: 2886 case X86ISD::PUNPCKLWD: 2887 case X86ISD::PUNPCKLBW: 2888 case X86ISD::PUNPCKLDQ: 2889 case X86ISD::PUNPCKLQDQ: 2890 case X86ISD::UNPCKHPS: 2891 case X86ISD::UNPCKHPD: 2892 case X86ISD::VUNPCKHPSY: 2893 case X86ISD::VUNPCKHPDY: 2894 case X86ISD::PUNPCKHWD: 2895 case X86ISD::PUNPCKHBW: 2896 case X86ISD::PUNPCKHDQ: 2897 case X86ISD::PUNPCKHQDQ: 2898 return DAG.getNode(Opc, dl, VT, V1, V2); 2899 } 2900 return SDValue(); 2901 } 2902 2903 SDValue X86TargetLowering::getReturnAddressFrameIndex(SelectionDAG &DAG) const { 2904 MachineFunction &MF = DAG.getMachineFunction(); 2905 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 2906 int ReturnAddrIndex = FuncInfo->getRAIndex(); 2907 2908 if (ReturnAddrIndex == 0) { 2909 // Set up a frame object for the return address. 2910 uint64_t SlotSize = TD->getPointerSize(); 2911 ReturnAddrIndex = MF.getFrameInfo()->CreateFixedObject(SlotSize, -SlotSize, 2912 false); 2913 FuncInfo->setRAIndex(ReturnAddrIndex); 2914 } 2915 2916 return DAG.getFrameIndex(ReturnAddrIndex, getPointerTy()); 2917 } 2918 2919 2920 bool X86::isOffsetSuitableForCodeModel(int64_t Offset, CodeModel::Model M, 2921 bool hasSymbolicDisplacement) { 2922 // Offset should fit into 32 bit immediate field. 2923 if (!isInt<32>(Offset)) 2924 return false; 2925 2926 // If we don't have a symbolic displacement - we don't have any extra 2927 // restrictions. 2928 if (!hasSymbolicDisplacement) 2929 return true; 2930 2931 // FIXME: Some tweaks might be needed for medium code model. 2932 if (M != CodeModel::Small && M != CodeModel::Kernel) 2933 return false; 2934 2935 // For small code model we assume that latest object is 16MB before end of 31 2936 // bits boundary. We may also accept pretty large negative constants knowing 2937 // that all objects are in the positive half of address space. 2938 if (M == CodeModel::Small && Offset < 16*1024*1024) 2939 return true; 2940 2941 // For kernel code model we know that all object resist in the negative half 2942 // of 32bits address space. We may not accept negative offsets, since they may 2943 // be just off and we may accept pretty large positive ones. 2944 if (M == CodeModel::Kernel && Offset > 0) 2945 return true; 2946 2947 return false; 2948 } 2949 2950 /// isCalleePop - Determines whether the callee is required to pop its 2951 /// own arguments. Callee pop is necessary to support tail calls. 2952 bool X86::isCalleePop(CallingConv::ID CallingConv, 2953 bool is64Bit, bool IsVarArg, bool TailCallOpt) { 2954 if (IsVarArg) 2955 return false; 2956 2957 switch (CallingConv) { 2958 default: 2959 return false; 2960 case CallingConv::X86_StdCall: 2961 return !is64Bit; 2962 case CallingConv::X86_FastCall: 2963 return !is64Bit; 2964 case CallingConv::X86_ThisCall: 2965 return !is64Bit; 2966 case CallingConv::Fast: 2967 return TailCallOpt; 2968 case CallingConv::GHC: 2969 return TailCallOpt; 2970 } 2971 } 2972 2973 /// TranslateX86CC - do a one to one translation of a ISD::CondCode to the X86 2974 /// specific condition code, returning the condition code and the LHS/RHS of the 2975 /// comparison to make. 2976 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, 2977 SDValue &LHS, SDValue &RHS, SelectionDAG &DAG) { 2978 if (!isFP) { 2979 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 2980 if (SetCCOpcode == ISD::SETGT && RHSC->isAllOnesValue()) { 2981 // X > -1 -> X == 0, jump !sign. 2982 RHS = DAG.getConstant(0, RHS.getValueType()); 2983 return X86::COND_NS; 2984 } else if (SetCCOpcode == ISD::SETLT && RHSC->isNullValue()) { 2985 // X < 0 -> X == 0, jump on sign. 2986 return X86::COND_S; 2987 } else if (SetCCOpcode == ISD::SETLT && RHSC->getZExtValue() == 1) { 2988 // X < 1 -> X <= 0 2989 RHS = DAG.getConstant(0, RHS.getValueType()); 2990 return X86::COND_LE; 2991 } 2992 } 2993 2994 switch (SetCCOpcode) { 2995 default: llvm_unreachable("Invalid integer condition!"); 2996 case ISD::SETEQ: return X86::COND_E; 2997 case ISD::SETGT: return X86::COND_G; 2998 case ISD::SETGE: return X86::COND_GE; 2999 case ISD::SETLT: return X86::COND_L; 3000 case ISD::SETLE: return X86::COND_LE; 3001 case ISD::SETNE: return X86::COND_NE; 3002 case ISD::SETULT: return X86::COND_B; 3003 case ISD::SETUGT: return X86::COND_A; 3004 case ISD::SETULE: return X86::COND_BE; 3005 case ISD::SETUGE: return X86::COND_AE; 3006 } 3007 } 3008 3009 // First determine if it is required or is profitable to flip the operands. 3010 3011 // If LHS is a foldable load, but RHS is not, flip the condition. 3012 if (ISD::isNON_EXTLoad(LHS.getNode()) && 3013 !ISD::isNON_EXTLoad(RHS.getNode())) { 3014 SetCCOpcode = getSetCCSwappedOperands(SetCCOpcode); 3015 std::swap(LHS, RHS); 3016 } 3017 3018 switch (SetCCOpcode) { 3019 default: break; 3020 case ISD::SETOLT: 3021 case ISD::SETOLE: 3022 case ISD::SETUGT: 3023 case ISD::SETUGE: 3024 std::swap(LHS, RHS); 3025 break; 3026 } 3027 3028 // On a floating point condition, the flags are set as follows: 3029 // ZF PF CF op 3030 // 0 | 0 | 0 | X > Y 3031 // 0 | 0 | 1 | X < Y 3032 // 1 | 0 | 0 | X == Y 3033 // 1 | 1 | 1 | unordered 3034 switch (SetCCOpcode) { 3035 default: llvm_unreachable("Condcode should be pre-legalized away"); 3036 case ISD::SETUEQ: 3037 case ISD::SETEQ: return X86::COND_E; 3038 case ISD::SETOLT: // flipped 3039 case ISD::SETOGT: 3040 case ISD::SETGT: return X86::COND_A; 3041 case ISD::SETOLE: // flipped 3042 case ISD::SETOGE: 3043 case ISD::SETGE: return X86::COND_AE; 3044 case ISD::SETUGT: // flipped 3045 case ISD::SETULT: 3046 case ISD::SETLT: return X86::COND_B; 3047 case ISD::SETUGE: // flipped 3048 case ISD::SETULE: 3049 case ISD::SETLE: return X86::COND_BE; 3050 case ISD::SETONE: 3051 case ISD::SETNE: return X86::COND_NE; 3052 case ISD::SETUO: return X86::COND_P; 3053 case ISD::SETO: return X86::COND_NP; 3054 case ISD::SETOEQ: 3055 case ISD::SETUNE: return X86::COND_INVALID; 3056 } 3057 } 3058 3059 /// hasFPCMov - is there a floating point cmov for the specific X86 condition 3060 /// code. Current x86 isa includes the following FP cmov instructions: 3061 /// fcmovb, fcomvbe, fcomve, fcmovu, fcmovae, fcmova, fcmovne, fcmovnu. 3062 static bool hasFPCMov(unsigned X86CC) { 3063 switch (X86CC) { 3064 default: 3065 return false; 3066 case X86::COND_B: 3067 case X86::COND_BE: 3068 case X86::COND_E: 3069 case X86::COND_P: 3070 case X86::COND_A: 3071 case X86::COND_AE: 3072 case X86::COND_NE: 3073 case X86::COND_NP: 3074 return true; 3075 } 3076 } 3077 3078 /// isFPImmLegal - Returns true if the target can instruction select the 3079 /// specified FP immediate natively. If false, the legalizer will 3080 /// materialize the FP immediate as a load from a constant pool. 3081 bool X86TargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { 3082 for (unsigned i = 0, e = LegalFPImmediates.size(); i != e; ++i) { 3083 if (Imm.bitwiseIsEqual(LegalFPImmediates[i])) 3084 return true; 3085 } 3086 return false; 3087 } 3088 3089 /// isUndefOrInRange - Return true if Val is undef or if its value falls within 3090 /// the specified range (L, H]. 3091 static bool isUndefOrInRange(int Val, int Low, int Hi) { 3092 return (Val < 0) || (Val >= Low && Val < Hi); 3093 } 3094 3095 /// isUndefOrInRange - Return true if every element in Mask, begining 3096 /// from position Pos and ending in Pos+Size, falls within the specified 3097 /// range (L, L+Pos]. or is undef. 3098 static bool isUndefOrInRange(const SmallVectorImpl<int> &Mask, 3099 int Pos, int Size, int Low, int Hi) { 3100 for (int i = Pos, e = Pos+Size; i != e; ++i) 3101 if (!isUndefOrInRange(Mask[i], Low, Hi)) 3102 return false; 3103 return true; 3104 } 3105 3106 /// isUndefOrEqual - Val is either less than zero (undef) or equal to the 3107 /// specified value. 3108 static bool isUndefOrEqual(int Val, int CmpVal) { 3109 if (Val < 0 || Val == CmpVal) 3110 return true; 3111 return false; 3112 } 3113 3114 /// isSequentialOrUndefInRange - Return true if every element in Mask, begining 3115 /// from position Pos and ending in Pos+Size, falls within the specified 3116 /// sequential range (L, L+Pos]. or is undef. 3117 static bool isSequentialOrUndefInRange(const SmallVectorImpl<int> &Mask, 3118 int Pos, int Size, int Low) { 3119 for (int i = Pos, e = Pos+Size; i != e; ++i, ++Low) 3120 if (!isUndefOrEqual(Mask[i], Low)) 3121 return false; 3122 return true; 3123 } 3124 3125 /// isPSHUFDMask - Return true if the node specifies a shuffle of elements that 3126 /// is suitable for input to PSHUFD or PSHUFW. That is, it doesn't reference 3127 /// the second operand. 3128 static bool isPSHUFDMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3129 if (VT == MVT::v4f32 || VT == MVT::v4i32 ) 3130 return (Mask[0] < 4 && Mask[1] < 4 && Mask[2] < 4 && Mask[3] < 4); 3131 if (VT == MVT::v2f64 || VT == MVT::v2i64) 3132 return (Mask[0] < 2 && Mask[1] < 2); 3133 return false; 3134 } 3135 3136 bool X86::isPSHUFDMask(ShuffleVectorSDNode *N) { 3137 SmallVector<int, 8> M; 3138 N->getMask(M); 3139 return ::isPSHUFDMask(M, N->getValueType(0)); 3140 } 3141 3142 /// isPSHUFHWMask - Return true if the node specifies a shuffle of elements that 3143 /// is suitable for input to PSHUFHW. 3144 static bool isPSHUFHWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3145 if (VT != MVT::v8i16) 3146 return false; 3147 3148 // Lower quadword copied in order or undef. 3149 for (int i = 0; i != 4; ++i) 3150 if (Mask[i] >= 0 && Mask[i] != i) 3151 return false; 3152 3153 // Upper quadword shuffled. 3154 for (int i = 4; i != 8; ++i) 3155 if (Mask[i] >= 0 && (Mask[i] < 4 || Mask[i] > 7)) 3156 return false; 3157 3158 return true; 3159 } 3160 3161 bool X86::isPSHUFHWMask(ShuffleVectorSDNode *N) { 3162 SmallVector<int, 8> M; 3163 N->getMask(M); 3164 return ::isPSHUFHWMask(M, N->getValueType(0)); 3165 } 3166 3167 /// isPSHUFLWMask - Return true if the node specifies a shuffle of elements that 3168 /// is suitable for input to PSHUFLW. 3169 static bool isPSHUFLWMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3170 if (VT != MVT::v8i16) 3171 return false; 3172 3173 // Upper quadword copied in order. 3174 for (int i = 4; i != 8; ++i) 3175 if (Mask[i] >= 0 && Mask[i] != i) 3176 return false; 3177 3178 // Lower quadword shuffled. 3179 for (int i = 0; i != 4; ++i) 3180 if (Mask[i] >= 4) 3181 return false; 3182 3183 return true; 3184 } 3185 3186 bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) { 3187 SmallVector<int, 8> M; 3188 N->getMask(M); 3189 return ::isPSHUFLWMask(M, N->getValueType(0)); 3190 } 3191 3192 /// isPALIGNRMask - Return true if the node specifies a shuffle of elements that 3193 /// is suitable for input to PALIGNR. 3194 static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT, 3195 bool hasSSSE3OrAVX) { 3196 int i, e = VT.getVectorNumElements(); 3197 if (VT.getSizeInBits() != 128 && VT.getSizeInBits() != 64) 3198 return false; 3199 3200 // Do not handle v2i64 / v2f64 shuffles with palignr. 3201 if (e < 4 || !hasSSSE3OrAVX) 3202 return false; 3203 3204 for (i = 0; i != e; ++i) 3205 if (Mask[i] >= 0) 3206 break; 3207 3208 // All undef, not a palignr. 3209 if (i == e) 3210 return false; 3211 3212 // Make sure we're shifting in the right direction. 3213 if (Mask[i] <= i) 3214 return false; 3215 3216 int s = Mask[i] - i; 3217 3218 // Check the rest of the elements to see if they are consecutive. 3219 for (++i; i != e; ++i) { 3220 int m = Mask[i]; 3221 if (m >= 0 && m != s+i) 3222 return false; 3223 } 3224 return true; 3225 } 3226 3227 /// isVSHUFPSYMask - Return true if the specified VECTOR_SHUFFLE operand 3228 /// specifies a shuffle of elements that is suitable for input to 256-bit 3229 /// VSHUFPSY. 3230 static bool isVSHUFPSYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3231 const X86Subtarget *Subtarget) { 3232 int NumElems = VT.getVectorNumElements(); 3233 3234 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3235 return false; 3236 3237 if (NumElems != 8) 3238 return false; 3239 3240 // VSHUFPSY divides the resulting vector into 4 chunks. 3241 // The sources are also splitted into 4 chunks, and each destination 3242 // chunk must come from a different source chunk. 3243 // 3244 // SRC1 => X7 X6 X5 X4 X3 X2 X1 X0 3245 // SRC2 => Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y9 3246 // 3247 // DST => Y7..Y4, Y7..Y4, X7..X4, X7..X4, 3248 // Y3..Y0, Y3..Y0, X3..X0, X3..X0 3249 // 3250 int QuarterSize = NumElems/4; 3251 int HalfSize = QuarterSize*2; 3252 for (int i = 0; i < QuarterSize; ++i) 3253 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3254 return false; 3255 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3256 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3257 return false; 3258 3259 // The mask of the second half must be the same as the first but with 3260 // the appropriate offsets. This works in the same way as VPERMILPS 3261 // works with masks. 3262 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) { 3263 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3264 return false; 3265 int FstHalfIdx = i-HalfSize; 3266 if (Mask[FstHalfIdx] < 0) 3267 continue; 3268 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3269 return false; 3270 } 3271 for (int i = QuarterSize*3; i < NumElems; ++i) { 3272 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3273 return false; 3274 int FstHalfIdx = i-HalfSize; 3275 if (Mask[FstHalfIdx] < 0) 3276 continue; 3277 if (!isUndefOrEqual(Mask[i], Mask[FstHalfIdx]+HalfSize)) 3278 return false; 3279 3280 } 3281 3282 return true; 3283 } 3284 3285 /// getShuffleVSHUFPSYImmediate - Return the appropriate immediate to shuffle 3286 /// the specified VECTOR_MASK mask with VSHUFPSY instruction. 3287 static unsigned getShuffleVSHUFPSYImmediate(SDNode *N) { 3288 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3289 EVT VT = SVOp->getValueType(0); 3290 int NumElems = VT.getVectorNumElements(); 3291 3292 assert(NumElems == 8 && VT.getSizeInBits() == 256 && 3293 "Only supports v8i32 and v8f32 types"); 3294 3295 int HalfSize = NumElems/2; 3296 unsigned Mask = 0; 3297 for (int i = 0; i != NumElems ; ++i) { 3298 if (SVOp->getMaskElt(i) < 0) 3299 continue; 3300 // The mask of the first half must be equal to the second one. 3301 unsigned Shamt = (i%HalfSize)*2; 3302 unsigned Elt = SVOp->getMaskElt(i) % HalfSize; 3303 Mask |= Elt << Shamt; 3304 } 3305 3306 return Mask; 3307 } 3308 3309 /// isVSHUFPDYMask - Return true if the specified VECTOR_SHUFFLE operand 3310 /// specifies a shuffle of elements that is suitable for input to 256-bit 3311 /// VSHUFPDY. This shuffle doesn't have the same restriction as the PS 3312 /// version and the mask of the second half isn't binded with the first 3313 /// one. 3314 static bool isVSHUFPDYMask(const SmallVectorImpl<int> &Mask, EVT VT, 3315 const X86Subtarget *Subtarget) { 3316 int NumElems = VT.getVectorNumElements(); 3317 3318 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3319 return false; 3320 3321 if (NumElems != 4) 3322 return false; 3323 3324 // VSHUFPSY divides the resulting vector into 4 chunks. 3325 // The sources are also splitted into 4 chunks, and each destination 3326 // chunk must come from a different source chunk. 3327 // 3328 // SRC1 => X3 X2 X1 X0 3329 // SRC2 => Y3 Y2 Y1 Y0 3330 // 3331 // DST => Y2..Y3, X2..X3, Y1..Y0, X1..X0 3332 // 3333 int QuarterSize = NumElems/4; 3334 int HalfSize = QuarterSize*2; 3335 for (int i = 0; i < QuarterSize; ++i) 3336 if (!isUndefOrInRange(Mask[i], 0, HalfSize)) 3337 return false; 3338 for (int i = QuarterSize; i < QuarterSize*2; ++i) 3339 if (!isUndefOrInRange(Mask[i], NumElems, NumElems+HalfSize)) 3340 return false; 3341 for (int i = QuarterSize*2; i < QuarterSize*3; ++i) 3342 if (!isUndefOrInRange(Mask[i], HalfSize, NumElems)) 3343 return false; 3344 for (int i = QuarterSize*3; i < NumElems; ++i) 3345 if (!isUndefOrInRange(Mask[i], NumElems+HalfSize, NumElems*2)) 3346 return false; 3347 3348 return true; 3349 } 3350 3351 /// getShuffleVSHUFPDYImmediate - Return the appropriate immediate to shuffle 3352 /// the specified VECTOR_MASK mask with VSHUFPDY instruction. 3353 static unsigned getShuffleVSHUFPDYImmediate(SDNode *N) { 3354 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3355 EVT VT = SVOp->getValueType(0); 3356 int NumElems = VT.getVectorNumElements(); 3357 3358 assert(NumElems == 4 && VT.getSizeInBits() == 256 && 3359 "Only supports v4i64 and v4f64 types"); 3360 3361 int HalfSize = NumElems/2; 3362 unsigned Mask = 0; 3363 for (int i = 0; i != NumElems ; ++i) { 3364 if (SVOp->getMaskElt(i) < 0) 3365 continue; 3366 int Elt = SVOp->getMaskElt(i) % HalfSize; 3367 Mask |= Elt << i; 3368 } 3369 3370 return Mask; 3371 } 3372 3373 /// isSHUFPMask - Return true if the specified VECTOR_SHUFFLE operand 3374 /// specifies a shuffle of elements that is suitable for input to 128-bit 3375 /// SHUFPS and SHUFPD. 3376 static bool isSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3377 int NumElems = VT.getVectorNumElements(); 3378 3379 if (VT.getSizeInBits() != 128) 3380 return false; 3381 3382 if (NumElems != 2 && NumElems != 4) 3383 return false; 3384 3385 int Half = NumElems / 2; 3386 for (int i = 0; i < Half; ++i) 3387 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3388 return false; 3389 for (int i = Half; i < NumElems; ++i) 3390 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3391 return false; 3392 3393 return true; 3394 } 3395 3396 bool X86::isSHUFPMask(ShuffleVectorSDNode *N) { 3397 SmallVector<int, 8> M; 3398 N->getMask(M); 3399 return ::isSHUFPMask(M, N->getValueType(0)); 3400 } 3401 3402 /// isCommutedSHUFP - Returns true if the shuffle mask is exactly 3403 /// the reverse of what x86 shuffles want. x86 shuffles requires the lower 3404 /// half elements to come from vector 1 (which would equal the dest.) and 3405 /// the upper half to come from vector 2. 3406 static bool isCommutedSHUFPMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3407 int NumElems = VT.getVectorNumElements(); 3408 3409 if (NumElems != 2 && NumElems != 4) 3410 return false; 3411 3412 int Half = NumElems / 2; 3413 for (int i = 0; i < Half; ++i) 3414 if (!isUndefOrInRange(Mask[i], NumElems, NumElems*2)) 3415 return false; 3416 for (int i = Half; i < NumElems; ++i) 3417 if (!isUndefOrInRange(Mask[i], 0, NumElems)) 3418 return false; 3419 return true; 3420 } 3421 3422 static bool isCommutedSHUFP(ShuffleVectorSDNode *N) { 3423 SmallVector<int, 8> M; 3424 N->getMask(M); 3425 return isCommutedSHUFPMask(M, N->getValueType(0)); 3426 } 3427 3428 /// isMOVHLPSMask - Return true if the specified VECTOR_SHUFFLE operand 3429 /// specifies a shuffle of elements that is suitable for input to MOVHLPS. 3430 bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) { 3431 EVT VT = N->getValueType(0); 3432 unsigned NumElems = VT.getVectorNumElements(); 3433 3434 if (VT.getSizeInBits() != 128) 3435 return false; 3436 3437 if (NumElems != 4) 3438 return false; 3439 3440 // Expect bit0 == 6, bit1 == 7, bit2 == 2, bit3 == 3 3441 return isUndefOrEqual(N->getMaskElt(0), 6) && 3442 isUndefOrEqual(N->getMaskElt(1), 7) && 3443 isUndefOrEqual(N->getMaskElt(2), 2) && 3444 isUndefOrEqual(N->getMaskElt(3), 3); 3445 } 3446 3447 /// isMOVHLPS_v_undef_Mask - Special case of isMOVHLPSMask for canonical form 3448 /// of vector_shuffle v, v, <2, 3, 2, 3>, i.e. vector_shuffle v, undef, 3449 /// <2, 3, 2, 3> 3450 bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) { 3451 EVT VT = N->getValueType(0); 3452 unsigned NumElems = VT.getVectorNumElements(); 3453 3454 if (VT.getSizeInBits() != 128) 3455 return false; 3456 3457 if (NumElems != 4) 3458 return false; 3459 3460 return isUndefOrEqual(N->getMaskElt(0), 2) && 3461 isUndefOrEqual(N->getMaskElt(1), 3) && 3462 isUndefOrEqual(N->getMaskElt(2), 2) && 3463 isUndefOrEqual(N->getMaskElt(3), 3); 3464 } 3465 3466 /// isMOVLPMask - Return true if the specified VECTOR_SHUFFLE operand 3467 /// specifies a shuffle of elements that is suitable for input to MOVLP{S|D}. 3468 bool X86::isMOVLPMask(ShuffleVectorSDNode *N) { 3469 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3470 3471 if (NumElems != 2 && NumElems != 4) 3472 return false; 3473 3474 for (unsigned i = 0; i < NumElems/2; ++i) 3475 if (!isUndefOrEqual(N->getMaskElt(i), i + NumElems)) 3476 return false; 3477 3478 for (unsigned i = NumElems/2; i < NumElems; ++i) 3479 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3480 return false; 3481 3482 return true; 3483 } 3484 3485 /// isMOVLHPSMask - Return true if the specified VECTOR_SHUFFLE operand 3486 /// specifies a shuffle of elements that is suitable for input to MOVLHPS. 3487 bool X86::isMOVLHPSMask(ShuffleVectorSDNode *N) { 3488 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 3489 3490 if ((NumElems != 2 && NumElems != 4) 3491 || N->getValueType(0).getSizeInBits() > 128) 3492 return false; 3493 3494 for (unsigned i = 0; i < NumElems/2; ++i) 3495 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3496 return false; 3497 3498 for (unsigned i = 0; i < NumElems/2; ++i) 3499 if (!isUndefOrEqual(N->getMaskElt(i + NumElems/2), i + NumElems)) 3500 return false; 3501 3502 return true; 3503 } 3504 3505 /// isUNPCKLMask - Return true if the specified VECTOR_SHUFFLE operand 3506 /// specifies a shuffle of elements that is suitable for input to UNPCKL. 3507 static bool isUNPCKLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3508 bool V2IsSplat = false) { 3509 int NumElts = VT.getVectorNumElements(); 3510 3511 assert((VT.is128BitVector() || VT.is256BitVector()) && 3512 "Unsupported vector type for unpckh"); 3513 3514 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3515 return false; 3516 3517 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3518 // independently on 128-bit lanes. 3519 unsigned NumLanes = VT.getSizeInBits()/128; 3520 unsigned NumLaneElts = NumElts/NumLanes; 3521 3522 unsigned Start = 0; 3523 unsigned End = NumLaneElts; 3524 for (unsigned s = 0; s < NumLanes; ++s) { 3525 for (unsigned i = Start, j = s * NumLaneElts; 3526 i != End; 3527 i += 2, ++j) { 3528 int BitI = Mask[i]; 3529 int BitI1 = Mask[i+1]; 3530 if (!isUndefOrEqual(BitI, j)) 3531 return false; 3532 if (V2IsSplat) { 3533 if (!isUndefOrEqual(BitI1, NumElts)) 3534 return false; 3535 } else { 3536 if (!isUndefOrEqual(BitI1, j + NumElts)) 3537 return false; 3538 } 3539 } 3540 // Process the next 128 bits. 3541 Start += NumLaneElts; 3542 End += NumLaneElts; 3543 } 3544 3545 return true; 3546 } 3547 3548 bool X86::isUNPCKLMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3549 SmallVector<int, 8> M; 3550 N->getMask(M); 3551 return ::isUNPCKLMask(M, N->getValueType(0), V2IsSplat); 3552 } 3553 3554 /// isUNPCKHMask - Return true if the specified VECTOR_SHUFFLE operand 3555 /// specifies a shuffle of elements that is suitable for input to UNPCKH. 3556 static bool isUNPCKHMask(const SmallVectorImpl<int> &Mask, EVT VT, 3557 bool V2IsSplat = false) { 3558 int NumElts = VT.getVectorNumElements(); 3559 3560 assert((VT.is128BitVector() || VT.is256BitVector()) && 3561 "Unsupported vector type for unpckh"); 3562 3563 if (VT.getSizeInBits() == 256 && NumElts != 4 && NumElts != 8) 3564 return false; 3565 3566 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3567 // independently on 128-bit lanes. 3568 unsigned NumLanes = VT.getSizeInBits()/128; 3569 unsigned NumLaneElts = NumElts/NumLanes; 3570 3571 unsigned Start = 0; 3572 unsigned End = NumLaneElts; 3573 for (unsigned l = 0; l != NumLanes; ++l) { 3574 for (unsigned i = Start, j = (l*NumLaneElts)+NumLaneElts/2; 3575 i != End; i += 2, ++j) { 3576 int BitI = Mask[i]; 3577 int BitI1 = Mask[i+1]; 3578 if (!isUndefOrEqual(BitI, j)) 3579 return false; 3580 if (V2IsSplat) { 3581 if (isUndefOrEqual(BitI1, NumElts)) 3582 return false; 3583 } else { 3584 if (!isUndefOrEqual(BitI1, j+NumElts)) 3585 return false; 3586 } 3587 } 3588 // Process the next 128 bits. 3589 Start += NumLaneElts; 3590 End += NumLaneElts; 3591 } 3592 return true; 3593 } 3594 3595 bool X86::isUNPCKHMask(ShuffleVectorSDNode *N, bool V2IsSplat) { 3596 SmallVector<int, 8> M; 3597 N->getMask(M); 3598 return ::isUNPCKHMask(M, N->getValueType(0), V2IsSplat); 3599 } 3600 3601 /// isUNPCKL_v_undef_Mask - Special case of isUNPCKLMask for canonical form 3602 /// of vector_shuffle v, v, <0, 4, 1, 5>, i.e. vector_shuffle v, undef, 3603 /// <0, 0, 1, 1> 3604 static bool isUNPCKL_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3605 int NumElems = VT.getVectorNumElements(); 3606 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3607 return false; 3608 3609 // For 256-bit i64/f64, use MOVDDUPY instead, so reject the matching pattern 3610 // FIXME: Need a better way to get rid of this, there's no latency difference 3611 // between UNPCKLPD and MOVDDUP, the later should always be checked first and 3612 // the former later. We should also remove the "_undef" special mask. 3613 if (NumElems == 4 && VT.getSizeInBits() == 256) 3614 return false; 3615 3616 // Handle 128 and 256-bit vector lengths. AVX defines UNPCK* to operate 3617 // independently on 128-bit lanes. 3618 unsigned NumLanes = VT.getSizeInBits() / 128; 3619 unsigned NumLaneElts = NumElems / NumLanes; 3620 3621 for (unsigned s = 0; s < NumLanes; ++s) { 3622 for (unsigned i = s * NumLaneElts, j = s * NumLaneElts; 3623 i != NumLaneElts * (s + 1); 3624 i += 2, ++j) { 3625 int BitI = Mask[i]; 3626 int BitI1 = Mask[i+1]; 3627 3628 if (!isUndefOrEqual(BitI, j)) 3629 return false; 3630 if (!isUndefOrEqual(BitI1, j)) 3631 return false; 3632 } 3633 } 3634 3635 return true; 3636 } 3637 3638 bool X86::isUNPCKL_v_undef_Mask(ShuffleVectorSDNode *N) { 3639 SmallVector<int, 8> M; 3640 N->getMask(M); 3641 return ::isUNPCKL_v_undef_Mask(M, N->getValueType(0)); 3642 } 3643 3644 /// isUNPCKH_v_undef_Mask - Special case of isUNPCKHMask for canonical form 3645 /// of vector_shuffle v, v, <2, 6, 3, 7>, i.e. vector_shuffle v, undef, 3646 /// <2, 2, 3, 3> 3647 static bool isUNPCKH_v_undef_Mask(const SmallVectorImpl<int> &Mask, EVT VT) { 3648 int NumElems = VT.getVectorNumElements(); 3649 if (NumElems != 2 && NumElems != 4 && NumElems != 8 && NumElems != 16) 3650 return false; 3651 3652 for (int i = 0, j = NumElems / 2; i != NumElems; i += 2, ++j) { 3653 int BitI = Mask[i]; 3654 int BitI1 = Mask[i+1]; 3655 if (!isUndefOrEqual(BitI, j)) 3656 return false; 3657 if (!isUndefOrEqual(BitI1, j)) 3658 return false; 3659 } 3660 return true; 3661 } 3662 3663 bool X86::isUNPCKH_v_undef_Mask(ShuffleVectorSDNode *N) { 3664 SmallVector<int, 8> M; 3665 N->getMask(M); 3666 return ::isUNPCKH_v_undef_Mask(M, N->getValueType(0)); 3667 } 3668 3669 /// isMOVLMask - Return true if the specified VECTOR_SHUFFLE operand 3670 /// specifies a shuffle of elements that is suitable for input to MOVSS, 3671 /// MOVSD, and MOVD, i.e. setting the lowest element. 3672 static bool isMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT) { 3673 if (VT.getVectorElementType().getSizeInBits() < 32) 3674 return false; 3675 3676 int NumElts = VT.getVectorNumElements(); 3677 3678 if (!isUndefOrEqual(Mask[0], NumElts)) 3679 return false; 3680 3681 for (int i = 1; i < NumElts; ++i) 3682 if (!isUndefOrEqual(Mask[i], i)) 3683 return false; 3684 3685 return true; 3686 } 3687 3688 bool X86::isMOVLMask(ShuffleVectorSDNode *N) { 3689 SmallVector<int, 8> M; 3690 N->getMask(M); 3691 return ::isMOVLMask(M, N->getValueType(0)); 3692 } 3693 3694 /// isVPERM2F128Mask - Match 256-bit shuffles where the elements are considered 3695 /// as permutations between 128-bit chunks or halves. As an example: this 3696 /// shuffle bellow: 3697 /// vector_shuffle <4, 5, 6, 7, 12, 13, 14, 15> 3698 /// The first half comes from the second half of V1 and the second half from the 3699 /// the second half of V2. 3700 static bool isVPERM2F128Mask(const SmallVectorImpl<int> &Mask, EVT VT, 3701 const X86Subtarget *Subtarget) { 3702 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256) 3703 return false; 3704 3705 // The shuffle result is divided into half A and half B. In total the two 3706 // sources have 4 halves, namely: C, D, E, F. The final values of A and 3707 // B must come from C, D, E or F. 3708 int HalfSize = VT.getVectorNumElements()/2; 3709 bool MatchA = false, MatchB = false; 3710 3711 // Check if A comes from one of C, D, E, F. 3712 for (int Half = 0; Half < 4; ++Half) { 3713 if (isSequentialOrUndefInRange(Mask, 0, HalfSize, Half*HalfSize)) { 3714 MatchA = true; 3715 break; 3716 } 3717 } 3718 3719 // Check if B comes from one of C, D, E, F. 3720 for (int Half = 0; Half < 4; ++Half) { 3721 if (isSequentialOrUndefInRange(Mask, HalfSize, HalfSize, Half*HalfSize)) { 3722 MatchB = true; 3723 break; 3724 } 3725 } 3726 3727 return MatchA && MatchB; 3728 } 3729 3730 /// getShuffleVPERM2F128Immediate - Return the appropriate immediate to shuffle 3731 /// the specified VECTOR_MASK mask with VPERM2F128 instructions. 3732 static unsigned getShuffleVPERM2F128Immediate(SDNode *N) { 3733 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3734 EVT VT = SVOp->getValueType(0); 3735 3736 int HalfSize = VT.getVectorNumElements()/2; 3737 3738 int FstHalf = 0, SndHalf = 0; 3739 for (int i = 0; i < HalfSize; ++i) { 3740 if (SVOp->getMaskElt(i) > 0) { 3741 FstHalf = SVOp->getMaskElt(i)/HalfSize; 3742 break; 3743 } 3744 } 3745 for (int i = HalfSize; i < HalfSize*2; ++i) { 3746 if (SVOp->getMaskElt(i) > 0) { 3747 SndHalf = SVOp->getMaskElt(i)/HalfSize; 3748 break; 3749 } 3750 } 3751 3752 return (FstHalf | (SndHalf << 4)); 3753 } 3754 3755 /// isVPERMILPDMask - Return true if the specified VECTOR_SHUFFLE operand 3756 /// specifies a shuffle of elements that is suitable for input to VPERMILPD*. 3757 /// Note that VPERMIL mask matching is different depending whether theunderlying 3758 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3759 /// to the same elements of the low, but to the higher half of the source. 3760 /// In VPERMILPD the two lanes could be shuffled independently of each other 3761 /// with the same restriction that lanes can't be crossed. 3762 static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, 3763 const X86Subtarget *Subtarget) { 3764 int NumElts = VT.getVectorNumElements(); 3765 int NumLanes = VT.getSizeInBits()/128; 3766 3767 if (!Subtarget->hasAVX()) 3768 return false; 3769 3770 // Only match 256-bit with 64-bit types 3771 if (VT.getSizeInBits() != 256 || NumElts != 4) 3772 return false; 3773 3774 // The mask on the high lane is independent of the low. Both can match 3775 // any element in inside its own lane, but can't cross. 3776 int LaneSize = NumElts/NumLanes; 3777 for (int l = 0; l < NumLanes; ++l) 3778 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3779 int LaneStart = l*LaneSize; 3780 if (!isUndefOrInRange(Mask[i], LaneStart, LaneStart+LaneSize)) 3781 return false; 3782 } 3783 3784 return true; 3785 } 3786 3787 /// isVPERMILPSMask - Return true if the specified VECTOR_SHUFFLE operand 3788 /// specifies a shuffle of elements that is suitable for input to VPERMILPS*. 3789 /// Note that VPERMIL mask matching is different depending whether theunderlying 3790 /// type is 32 or 64. In the VPERMILPS the high half of the mask should point 3791 /// to the same elements of the low, but to the higher half of the source. 3792 /// In VPERMILPD the two lanes could be shuffled independently of each other 3793 /// with the same restriction that lanes can't be crossed. 3794 static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, 3795 const X86Subtarget *Subtarget) { 3796 unsigned NumElts = VT.getVectorNumElements(); 3797 unsigned NumLanes = VT.getSizeInBits()/128; 3798 3799 if (!Subtarget->hasAVX()) 3800 return false; 3801 3802 // Only match 256-bit with 32-bit types 3803 if (VT.getSizeInBits() != 256 || NumElts != 8) 3804 return false; 3805 3806 // The mask on the high lane should be the same as the low. Actually, 3807 // they can differ if any of the corresponding index in a lane is undef 3808 // and the other stays in range. 3809 int LaneSize = NumElts/NumLanes; 3810 for (int i = 0; i < LaneSize; ++i) { 3811 int HighElt = i+LaneSize; 3812 bool HighValid = isUndefOrInRange(Mask[HighElt], LaneSize, NumElts); 3813 bool LowValid = isUndefOrInRange(Mask[i], 0, LaneSize); 3814 3815 if (!HighValid || !LowValid) 3816 return false; 3817 if (Mask[i] < 0 || Mask[HighElt] < 0) 3818 continue; 3819 if (Mask[HighElt]-Mask[i] != LaneSize) 3820 return false; 3821 } 3822 3823 return true; 3824 } 3825 3826 /// getShuffleVPERMILPSImmediate - Return the appropriate immediate to shuffle 3827 /// the specified VECTOR_MASK mask with VPERMILPS* instructions. 3828 static unsigned getShuffleVPERMILPSImmediate(SDNode *N) { 3829 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3830 EVT VT = SVOp->getValueType(0); 3831 3832 int NumElts = VT.getVectorNumElements(); 3833 int NumLanes = VT.getSizeInBits()/128; 3834 int LaneSize = NumElts/NumLanes; 3835 3836 // Although the mask is equal for both lanes do it twice to get the cases 3837 // where a mask will match because the same mask element is undef on the 3838 // first half but valid on the second. This would get pathological cases 3839 // such as: shuffle <u, 0, 1, 2, 4, 4, 5, 6>, which is completely valid. 3840 unsigned Mask = 0; 3841 for (int l = 0; l < NumLanes; ++l) { 3842 for (int i = 0; i < LaneSize; ++i) { 3843 int MaskElt = SVOp->getMaskElt(i+(l*LaneSize)); 3844 if (MaskElt < 0) 3845 continue; 3846 if (MaskElt >= LaneSize) 3847 MaskElt -= LaneSize; 3848 Mask |= MaskElt << (i*2); 3849 } 3850 } 3851 3852 return Mask; 3853 } 3854 3855 /// getShuffleVPERMILPDImmediate - Return the appropriate immediate to shuffle 3856 /// the specified VECTOR_MASK mask with VPERMILPD* instructions. 3857 static unsigned getShuffleVPERMILPDImmediate(SDNode *N) { 3858 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 3859 EVT VT = SVOp->getValueType(0); 3860 3861 int NumElts = VT.getVectorNumElements(); 3862 int NumLanes = VT.getSizeInBits()/128; 3863 3864 unsigned Mask = 0; 3865 int LaneSize = NumElts/NumLanes; 3866 for (int l = 0; l < NumLanes; ++l) 3867 for (int i = l*LaneSize; i < LaneSize*(l+1); ++i) { 3868 int MaskElt = SVOp->getMaskElt(i); 3869 if (MaskElt < 0) 3870 continue; 3871 Mask |= (MaskElt-l*LaneSize) << i; 3872 } 3873 3874 return Mask; 3875 } 3876 3877 /// isCommutedMOVL - Returns true if the shuffle mask is except the reverse 3878 /// of what x86 movss want. X86 movs requires the lowest element to be lowest 3879 /// element of vector 2 and the other elements to come from vector 1 in order. 3880 static bool isCommutedMOVLMask(const SmallVectorImpl<int> &Mask, EVT VT, 3881 bool V2IsSplat = false, bool V2IsUndef = false) { 3882 int NumOps = VT.getVectorNumElements(); 3883 if (NumOps != 2 && NumOps != 4 && NumOps != 8 && NumOps != 16) 3884 return false; 3885 3886 if (!isUndefOrEqual(Mask[0], 0)) 3887 return false; 3888 3889 for (int i = 1; i < NumOps; ++i) 3890 if (!(isUndefOrEqual(Mask[i], i+NumOps) || 3891 (V2IsUndef && isUndefOrInRange(Mask[i], NumOps, NumOps*2)) || 3892 (V2IsSplat && isUndefOrEqual(Mask[i], NumOps)))) 3893 return false; 3894 3895 return true; 3896 } 3897 3898 static bool isCommutedMOVL(ShuffleVectorSDNode *N, bool V2IsSplat = false, 3899 bool V2IsUndef = false) { 3900 SmallVector<int, 8> M; 3901 N->getMask(M); 3902 return isCommutedMOVLMask(M, N->getValueType(0), V2IsSplat, V2IsUndef); 3903 } 3904 3905 /// isMOVSHDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3906 /// specifies a shuffle of elements that is suitable for input to MOVSHDUP. 3907 /// Masks to match: <1, 1, 3, 3> or <1, 1, 3, 3, 5, 5, 7, 7> 3908 bool X86::isMOVSHDUPMask(ShuffleVectorSDNode *N, 3909 const X86Subtarget *Subtarget) { 3910 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3911 return false; 3912 3913 // The second vector must be undef 3914 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3915 return false; 3916 3917 EVT VT = N->getValueType(0); 3918 unsigned NumElems = VT.getVectorNumElements(); 3919 3920 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3921 (VT.getSizeInBits() == 256 && NumElems != 8)) 3922 return false; 3923 3924 // "i+1" is the value the indexed mask element must have 3925 for (unsigned i = 0; i < NumElems; i += 2) 3926 if (!isUndefOrEqual(N->getMaskElt(i), i+1) || 3927 !isUndefOrEqual(N->getMaskElt(i+1), i+1)) 3928 return false; 3929 3930 return true; 3931 } 3932 3933 /// isMOVSLDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3934 /// specifies a shuffle of elements that is suitable for input to MOVSLDUP. 3935 /// Masks to match: <0, 0, 2, 2> or <0, 0, 2, 2, 4, 4, 6, 6> 3936 bool X86::isMOVSLDUPMask(ShuffleVectorSDNode *N, 3937 const X86Subtarget *Subtarget) { 3938 if (!Subtarget->hasSSE3() && !Subtarget->hasAVX()) 3939 return false; 3940 3941 // The second vector must be undef 3942 if (N->getOperand(1).getOpcode() != ISD::UNDEF) 3943 return false; 3944 3945 EVT VT = N->getValueType(0); 3946 unsigned NumElems = VT.getVectorNumElements(); 3947 3948 if ((VT.getSizeInBits() == 128 && NumElems != 4) || 3949 (VT.getSizeInBits() == 256 && NumElems != 8)) 3950 return false; 3951 3952 // "i" is the value the indexed mask element must have 3953 for (unsigned i = 0; i < NumElems; i += 2) 3954 if (!isUndefOrEqual(N->getMaskElt(i), i) || 3955 !isUndefOrEqual(N->getMaskElt(i+1), i)) 3956 return false; 3957 3958 return true; 3959 } 3960 3961 /// isMOVDDUPYMask - Return true if the specified VECTOR_SHUFFLE operand 3962 /// specifies a shuffle of elements that is suitable for input to 256-bit 3963 /// version of MOVDDUP. 3964 static bool isMOVDDUPYMask(ShuffleVectorSDNode *N, 3965 const X86Subtarget *Subtarget) { 3966 EVT VT = N->getValueType(0); 3967 int NumElts = VT.getVectorNumElements(); 3968 bool V2IsUndef = N->getOperand(1).getOpcode() == ISD::UNDEF; 3969 3970 if (!Subtarget->hasAVX() || VT.getSizeInBits() != 256 || 3971 !V2IsUndef || NumElts != 4) 3972 return false; 3973 3974 for (int i = 0; i != NumElts/2; ++i) 3975 if (!isUndefOrEqual(N->getMaskElt(i), 0)) 3976 return false; 3977 for (int i = NumElts/2; i != NumElts; ++i) 3978 if (!isUndefOrEqual(N->getMaskElt(i), NumElts/2)) 3979 return false; 3980 return true; 3981 } 3982 3983 /// isMOVDDUPMask - Return true if the specified VECTOR_SHUFFLE operand 3984 /// specifies a shuffle of elements that is suitable for input to 128-bit 3985 /// version of MOVDDUP. 3986 bool X86::isMOVDDUPMask(ShuffleVectorSDNode *N) { 3987 EVT VT = N->getValueType(0); 3988 3989 if (VT.getSizeInBits() != 128) 3990 return false; 3991 3992 int e = VT.getVectorNumElements() / 2; 3993 for (int i = 0; i < e; ++i) 3994 if (!isUndefOrEqual(N->getMaskElt(i), i)) 3995 return false; 3996 for (int i = 0; i < e; ++i) 3997 if (!isUndefOrEqual(N->getMaskElt(e+i), i)) 3998 return false; 3999 return true; 4000 } 4001 4002 /// isVEXTRACTF128Index - Return true if the specified 4003 /// EXTRACT_SUBVECTOR operand specifies a vector extract that is 4004 /// suitable for input to VEXTRACTF128. 4005 bool X86::isVEXTRACTF128Index(SDNode *N) { 4006 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4007 return false; 4008 4009 // The index should be aligned on a 128-bit boundary. 4010 uint64_t Index = 4011 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4012 4013 unsigned VL = N->getValueType(0).getVectorNumElements(); 4014 unsigned VBits = N->getValueType(0).getSizeInBits(); 4015 unsigned ElSize = VBits / VL; 4016 bool Result = (Index * ElSize) % 128 == 0; 4017 4018 return Result; 4019 } 4020 4021 /// isVINSERTF128Index - Return true if the specified INSERT_SUBVECTOR 4022 /// operand specifies a subvector insert that is suitable for input to 4023 /// VINSERTF128. 4024 bool X86::isVINSERTF128Index(SDNode *N) { 4025 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4026 return false; 4027 4028 // The index should be aligned on a 128-bit boundary. 4029 uint64_t Index = 4030 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4031 4032 unsigned VL = N->getValueType(0).getVectorNumElements(); 4033 unsigned VBits = N->getValueType(0).getSizeInBits(); 4034 unsigned ElSize = VBits / VL; 4035 bool Result = (Index * ElSize) % 128 == 0; 4036 4037 return Result; 4038 } 4039 4040 /// getShuffleSHUFImmediate - Return the appropriate immediate to shuffle 4041 /// the specified VECTOR_SHUFFLE mask with PSHUF* and SHUFP* instructions. 4042 unsigned X86::getShuffleSHUFImmediate(SDNode *N) { 4043 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4044 int NumOperands = SVOp->getValueType(0).getVectorNumElements(); 4045 4046 unsigned Shift = (NumOperands == 4) ? 2 : 1; 4047 unsigned Mask = 0; 4048 for (int i = 0; i < NumOperands; ++i) { 4049 int Val = SVOp->getMaskElt(NumOperands-i-1); 4050 if (Val < 0) Val = 0; 4051 if (Val >= NumOperands) Val -= NumOperands; 4052 Mask |= Val; 4053 if (i != NumOperands - 1) 4054 Mask <<= Shift; 4055 } 4056 return Mask; 4057 } 4058 4059 /// getShufflePSHUFHWImmediate - Return the appropriate immediate to shuffle 4060 /// the specified VECTOR_SHUFFLE mask with the PSHUFHW instruction. 4061 unsigned X86::getShufflePSHUFHWImmediate(SDNode *N) { 4062 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4063 unsigned Mask = 0; 4064 // 8 nodes, but we only care about the last 4. 4065 for (unsigned i = 7; i >= 4; --i) { 4066 int Val = SVOp->getMaskElt(i); 4067 if (Val >= 0) 4068 Mask |= (Val - 4); 4069 if (i != 4) 4070 Mask <<= 2; 4071 } 4072 return Mask; 4073 } 4074 4075 /// getShufflePSHUFLWImmediate - Return the appropriate immediate to shuffle 4076 /// the specified VECTOR_SHUFFLE mask with the PSHUFLW instruction. 4077 unsigned X86::getShufflePSHUFLWImmediate(SDNode *N) { 4078 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4079 unsigned Mask = 0; 4080 // 8 nodes, but we only care about the first 4. 4081 for (int i = 3; i >= 0; --i) { 4082 int Val = SVOp->getMaskElt(i); 4083 if (Val >= 0) 4084 Mask |= Val; 4085 if (i != 0) 4086 Mask <<= 2; 4087 } 4088 return Mask; 4089 } 4090 4091 /// getShufflePALIGNRImmediate - Return the appropriate immediate to shuffle 4092 /// the specified VECTOR_SHUFFLE mask with the PALIGNR instruction. 4093 unsigned X86::getShufflePALIGNRImmediate(SDNode *N) { 4094 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 4095 EVT VVT = N->getValueType(0); 4096 unsigned EltSize = VVT.getVectorElementType().getSizeInBits() >> 3; 4097 int Val = 0; 4098 4099 unsigned i, e; 4100 for (i = 0, e = VVT.getVectorNumElements(); i != e; ++i) { 4101 Val = SVOp->getMaskElt(i); 4102 if (Val >= 0) 4103 break; 4104 } 4105 assert(Val - i > 0 && "PALIGNR imm should be positive"); 4106 return (Val - i) * EltSize; 4107 } 4108 4109 /// getExtractVEXTRACTF128Immediate - Return the appropriate immediate 4110 /// to extract the specified EXTRACT_SUBVECTOR index with VEXTRACTF128 4111 /// instructions. 4112 unsigned X86::getExtractVEXTRACTF128Immediate(SDNode *N) { 4113 if (!isa<ConstantSDNode>(N->getOperand(1).getNode())) 4114 llvm_unreachable("Illegal extract subvector for VEXTRACTF128"); 4115 4116 uint64_t Index = 4117 cast<ConstantSDNode>(N->getOperand(1).getNode())->getZExtValue(); 4118 4119 EVT VecVT = N->getOperand(0).getValueType(); 4120 EVT ElVT = VecVT.getVectorElementType(); 4121 4122 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4123 return Index / NumElemsPerChunk; 4124 } 4125 4126 /// getInsertVINSERTF128Immediate - Return the appropriate immediate 4127 /// to insert at the specified INSERT_SUBVECTOR index with VINSERTF128 4128 /// instructions. 4129 unsigned X86::getInsertVINSERTF128Immediate(SDNode *N) { 4130 if (!isa<ConstantSDNode>(N->getOperand(2).getNode())) 4131 llvm_unreachable("Illegal insert subvector for VINSERTF128"); 4132 4133 uint64_t Index = 4134 cast<ConstantSDNode>(N->getOperand(2).getNode())->getZExtValue(); 4135 4136 EVT VecVT = N->getValueType(0); 4137 EVT ElVT = VecVT.getVectorElementType(); 4138 4139 unsigned NumElemsPerChunk = 128 / ElVT.getSizeInBits(); 4140 return Index / NumElemsPerChunk; 4141 } 4142 4143 /// isZeroNode - Returns true if Elt is a constant zero or a floating point 4144 /// constant +0.0. 4145 bool X86::isZeroNode(SDValue Elt) { 4146 return ((isa<ConstantSDNode>(Elt) && 4147 cast<ConstantSDNode>(Elt)->isNullValue()) || 4148 (isa<ConstantFPSDNode>(Elt) && 4149 cast<ConstantFPSDNode>(Elt)->getValueAPF().isPosZero())); 4150 } 4151 4152 /// CommuteVectorShuffle - Swap vector_shuffle operands as well as values in 4153 /// their permute mask. 4154 static SDValue CommuteVectorShuffle(ShuffleVectorSDNode *SVOp, 4155 SelectionDAG &DAG) { 4156 EVT VT = SVOp->getValueType(0); 4157 unsigned NumElems = VT.getVectorNumElements(); 4158 SmallVector<int, 8> MaskVec; 4159 4160 for (unsigned i = 0; i != NumElems; ++i) { 4161 int idx = SVOp->getMaskElt(i); 4162 if (idx < 0) 4163 MaskVec.push_back(idx); 4164 else if (idx < (int)NumElems) 4165 MaskVec.push_back(idx + NumElems); 4166 else 4167 MaskVec.push_back(idx - NumElems); 4168 } 4169 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(1), 4170 SVOp->getOperand(0), &MaskVec[0]); 4171 } 4172 4173 /// CommuteVectorShuffleMask - Change values in a shuffle permute mask assuming 4174 /// the two vector operands have swapped position. 4175 static void CommuteVectorShuffleMask(SmallVectorImpl<int> &Mask, EVT VT) { 4176 unsigned NumElems = VT.getVectorNumElements(); 4177 for (unsigned i = 0; i != NumElems; ++i) { 4178 int idx = Mask[i]; 4179 if (idx < 0) 4180 continue; 4181 else if (idx < (int)NumElems) 4182 Mask[i] = idx + NumElems; 4183 else 4184 Mask[i] = idx - NumElems; 4185 } 4186 } 4187 4188 /// ShouldXformToMOVHLPS - Return true if the node should be transformed to 4189 /// match movhlps. The lower half elements should come from upper half of 4190 /// V1 (and in order), and the upper half elements should come from the upper 4191 /// half of V2 (and in order). 4192 static bool ShouldXformToMOVHLPS(ShuffleVectorSDNode *Op) { 4193 EVT VT = Op->getValueType(0); 4194 if (VT.getSizeInBits() != 128) 4195 return false; 4196 if (VT.getVectorNumElements() != 4) 4197 return false; 4198 for (unsigned i = 0, e = 2; i != e; ++i) 4199 if (!isUndefOrEqual(Op->getMaskElt(i), i+2)) 4200 return false; 4201 for (unsigned i = 2; i != 4; ++i) 4202 if (!isUndefOrEqual(Op->getMaskElt(i), i+4)) 4203 return false; 4204 return true; 4205 } 4206 4207 /// isScalarLoadToVector - Returns true if the node is a scalar load that 4208 /// is promoted to a vector. It also returns the LoadSDNode by reference if 4209 /// required. 4210 static bool isScalarLoadToVector(SDNode *N, LoadSDNode **LD = NULL) { 4211 if (N->getOpcode() != ISD::SCALAR_TO_VECTOR) 4212 return false; 4213 N = N->getOperand(0).getNode(); 4214 if (!ISD::isNON_EXTLoad(N)) 4215 return false; 4216 if (LD) 4217 *LD = cast<LoadSDNode>(N); 4218 return true; 4219 } 4220 4221 /// ShouldXformToMOVLP{S|D} - Return true if the node should be transformed to 4222 /// match movlp{s|d}. The lower half elements should come from lower half of 4223 /// V1 (and in order), and the upper half elements should come from the upper 4224 /// half of V2 (and in order). And since V1 will become the source of the 4225 /// MOVLP, it must be either a vector load or a scalar load to vector. 4226 static bool ShouldXformToMOVLP(SDNode *V1, SDNode *V2, 4227 ShuffleVectorSDNode *Op) { 4228 EVT VT = Op->getValueType(0); 4229 if (VT.getSizeInBits() != 128) 4230 return false; 4231 4232 if (!ISD::isNON_EXTLoad(V1) && !isScalarLoadToVector(V1)) 4233 return false; 4234 // Is V2 is a vector load, don't do this transformation. We will try to use 4235 // load folding shufps op. 4236 if (ISD::isNON_EXTLoad(V2)) 4237 return false; 4238 4239 unsigned NumElems = VT.getVectorNumElements(); 4240 4241 if (NumElems != 2 && NumElems != 4) 4242 return false; 4243 for (unsigned i = 0, e = NumElems/2; i != e; ++i) 4244 if (!isUndefOrEqual(Op->getMaskElt(i), i)) 4245 return false; 4246 for (unsigned i = NumElems/2; i != NumElems; ++i) 4247 if (!isUndefOrEqual(Op->getMaskElt(i), i+NumElems)) 4248 return false; 4249 return true; 4250 } 4251 4252 /// isSplatVector - Returns true if N is a BUILD_VECTOR node whose elements are 4253 /// all the same. 4254 static bool isSplatVector(SDNode *N) { 4255 if (N->getOpcode() != ISD::BUILD_VECTOR) 4256 return false; 4257 4258 SDValue SplatValue = N->getOperand(0); 4259 for (unsigned i = 1, e = N->getNumOperands(); i != e; ++i) 4260 if (N->getOperand(i) != SplatValue) 4261 return false; 4262 return true; 4263 } 4264 4265 /// isZeroShuffle - Returns true if N is a VECTOR_SHUFFLE that can be resolved 4266 /// to an zero vector. 4267 /// FIXME: move to dag combiner / method on ShuffleVectorSDNode 4268 static bool isZeroShuffle(ShuffleVectorSDNode *N) { 4269 SDValue V1 = N->getOperand(0); 4270 SDValue V2 = N->getOperand(1); 4271 unsigned NumElems = N->getValueType(0).getVectorNumElements(); 4272 for (unsigned i = 0; i != NumElems; ++i) { 4273 int Idx = N->getMaskElt(i); 4274 if (Idx >= (int)NumElems) { 4275 unsigned Opc = V2.getOpcode(); 4276 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V2.getNode())) 4277 continue; 4278 if (Opc != ISD::BUILD_VECTOR || 4279 !X86::isZeroNode(V2.getOperand(Idx-NumElems))) 4280 return false; 4281 } else if (Idx >= 0) { 4282 unsigned Opc = V1.getOpcode(); 4283 if (Opc == ISD::UNDEF || ISD::isBuildVectorAllZeros(V1.getNode())) 4284 continue; 4285 if (Opc != ISD::BUILD_VECTOR || 4286 !X86::isZeroNode(V1.getOperand(Idx))) 4287 return false; 4288 } 4289 } 4290 return true; 4291 } 4292 4293 /// getZeroVector - Returns a vector of specified type with all zero elements. 4294 /// 4295 static SDValue getZeroVector(EVT VT, bool HasXMMInt, SelectionDAG &DAG, 4296 DebugLoc dl) { 4297 assert(VT.isVector() && "Expected a vector type"); 4298 4299 // Always build SSE zero vectors as <4 x i32> bitcasted 4300 // to their dest type. This ensures they get CSE'd. 4301 SDValue Vec; 4302 if (VT.getSizeInBits() == 128) { // SSE 4303 if (HasXMMInt) { // SSE2 4304 SDValue Cst = DAG.getTargetConstant(0, MVT::i32); 4305 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst); 4306 } else { // SSE1 4307 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4308 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst); 4309 } 4310 } else if (VT.getSizeInBits() == 256) { // AVX 4311 // 256-bit logic and arithmetic instructions in AVX are 4312 // all floating-point, no support for integer ops. Default 4313 // to emitting fp zeroed vectors then. 4314 SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32); 4315 SDValue Ops[] = { Cst, Cst, Cst, Cst, Cst, Cst, Cst, Cst }; 4316 Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8f32, Ops, 8); 4317 } 4318 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4319 } 4320 4321 /// getOnesVector - Returns a vector of specified type with all bits set. 4322 /// Always build ones vectors as <4 x i32>. For 256-bit types, use two 4323 /// <4 x i32> inserted in a <8 x i32> appropriately. Then bitcast to their 4324 /// original type, ensuring they get CSE'd. 4325 static SDValue getOnesVector(EVT VT, SelectionDAG &DAG, DebugLoc dl) { 4326 assert(VT.isVector() && "Expected a vector type"); 4327 assert((VT.is128BitVector() || VT.is256BitVector()) 4328 && "Expected a 128-bit or 256-bit vector type"); 4329 4330 SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32); 4331 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, 4332 Cst, Cst, Cst, Cst); 4333 4334 if (VT.is256BitVector()) { 4335 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, MVT::v8i32), 4336 Vec, DAG.getConstant(0, MVT::i32), DAG, dl); 4337 Vec = Insert128BitVector(InsV, Vec, 4338 DAG.getConstant(4 /* NumElems/2 */, MVT::i32), DAG, dl); 4339 } 4340 4341 return DAG.getNode(ISD::BITCAST, dl, VT, Vec); 4342 } 4343 4344 /// NormalizeMask - V2 is a splat, modify the mask (if needed) so all elements 4345 /// that point to V2 points to its first element. 4346 static SDValue NormalizeMask(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 4347 EVT VT = SVOp->getValueType(0); 4348 unsigned NumElems = VT.getVectorNumElements(); 4349 4350 bool Changed = false; 4351 SmallVector<int, 8> MaskVec; 4352 SVOp->getMask(MaskVec); 4353 4354 for (unsigned i = 0; i != NumElems; ++i) { 4355 if (MaskVec[i] > (int)NumElems) { 4356 MaskVec[i] = NumElems; 4357 Changed = true; 4358 } 4359 } 4360 if (Changed) 4361 return DAG.getVectorShuffle(VT, SVOp->getDebugLoc(), SVOp->getOperand(0), 4362 SVOp->getOperand(1), &MaskVec[0]); 4363 return SDValue(SVOp, 0); 4364 } 4365 4366 /// getMOVLMask - Returns a vector_shuffle mask for an movs{s|d}, movd 4367 /// operation of specified width. 4368 static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4369 SDValue V2) { 4370 unsigned NumElems = VT.getVectorNumElements(); 4371 SmallVector<int, 8> Mask; 4372 Mask.push_back(NumElems); 4373 for (unsigned i = 1; i != NumElems; ++i) 4374 Mask.push_back(i); 4375 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4376 } 4377 4378 /// getUnpackl - Returns a vector_shuffle node for an unpackl operation. 4379 static SDValue getUnpackl(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4380 SDValue V2) { 4381 unsigned NumElems = VT.getVectorNumElements(); 4382 SmallVector<int, 8> Mask; 4383 for (unsigned i = 0, e = NumElems/2; i != e; ++i) { 4384 Mask.push_back(i); 4385 Mask.push_back(i + NumElems); 4386 } 4387 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4388 } 4389 4390 /// getUnpackh - Returns a vector_shuffle node for an unpackh operation. 4391 static SDValue getUnpackh(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1, 4392 SDValue V2) { 4393 unsigned NumElems = VT.getVectorNumElements(); 4394 unsigned Half = NumElems/2; 4395 SmallVector<int, 8> Mask; 4396 for (unsigned i = 0; i != Half; ++i) { 4397 Mask.push_back(i + Half); 4398 Mask.push_back(i + NumElems + Half); 4399 } 4400 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask[0]); 4401 } 4402 4403 // PromoteSplati8i16 - All i16 and i8 vector types can't be used directly by 4404 // a generic shuffle instruction because the target has no such instructions. 4405 // Generate shuffles which repeat i16 and i8 several times until they can be 4406 // represented by v4f32 and then be manipulated by target suported shuffles. 4407 static SDValue PromoteSplati8i16(SDValue V, SelectionDAG &DAG, int &EltNo) { 4408 EVT VT = V.getValueType(); 4409 int NumElems = VT.getVectorNumElements(); 4410 DebugLoc dl = V.getDebugLoc(); 4411 4412 while (NumElems > 4) { 4413 if (EltNo < NumElems/2) { 4414 V = getUnpackl(DAG, dl, VT, V, V); 4415 } else { 4416 V = getUnpackh(DAG, dl, VT, V, V); 4417 EltNo -= NumElems/2; 4418 } 4419 NumElems >>= 1; 4420 } 4421 return V; 4422 } 4423 4424 /// getLegalSplat - Generate a legal splat with supported x86 shuffles 4425 static SDValue getLegalSplat(SelectionDAG &DAG, SDValue V, int EltNo) { 4426 EVT VT = V.getValueType(); 4427 DebugLoc dl = V.getDebugLoc(); 4428 assert((VT.getSizeInBits() == 128 || VT.getSizeInBits() == 256) 4429 && "Vector size not supported"); 4430 4431 if (VT.getSizeInBits() == 128) { 4432 V = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V); 4433 int SplatMask[4] = { EltNo, EltNo, EltNo, EltNo }; 4434 V = DAG.getVectorShuffle(MVT::v4f32, dl, V, DAG.getUNDEF(MVT::v4f32), 4435 &SplatMask[0]); 4436 } else { 4437 // To use VPERMILPS to splat scalars, the second half of indicies must 4438 // refer to the higher part, which is a duplication of the lower one, 4439 // because VPERMILPS can only handle in-lane permutations. 4440 int SplatMask[8] = { EltNo, EltNo, EltNo, EltNo, 4441 EltNo+4, EltNo+4, EltNo+4, EltNo+4 }; 4442 4443 V = DAG.getNode(ISD::BITCAST, dl, MVT::v8f32, V); 4444 V = DAG.getVectorShuffle(MVT::v8f32, dl, V, DAG.getUNDEF(MVT::v8f32), 4445 &SplatMask[0]); 4446 } 4447 4448 return DAG.getNode(ISD::BITCAST, dl, VT, V); 4449 } 4450 4451 /// PromoteSplat - Splat is promoted to target supported vector shuffles. 4452 static SDValue PromoteSplat(ShuffleVectorSDNode *SV, SelectionDAG &DAG) { 4453 EVT SrcVT = SV->getValueType(0); 4454 SDValue V1 = SV->getOperand(0); 4455 DebugLoc dl = SV->getDebugLoc(); 4456 4457 int EltNo = SV->getSplatIndex(); 4458 int NumElems = SrcVT.getVectorNumElements(); 4459 unsigned Size = SrcVT.getSizeInBits(); 4460 4461 assert(((Size == 128 && NumElems > 4) || Size == 256) && 4462 "Unknown how to promote splat for type"); 4463 4464 // Extract the 128-bit part containing the splat element and update 4465 // the splat element index when it refers to the higher register. 4466 if (Size == 256) { 4467 unsigned Idx = (EltNo > NumElems/2) ? NumElems/2 : 0; 4468 V1 = Extract128BitVector(V1, DAG.getConstant(Idx, MVT::i32), DAG, dl); 4469 if (Idx > 0) 4470 EltNo -= NumElems/2; 4471 } 4472 4473 // All i16 and i8 vector types can't be used directly by a generic shuffle 4474 // instruction because the target has no such instruction. Generate shuffles 4475 // which repeat i16 and i8 several times until they fit in i32, and then can 4476 // be manipulated by target suported shuffles. 4477 EVT EltVT = SrcVT.getVectorElementType(); 4478 if (EltVT == MVT::i8 || EltVT == MVT::i16) 4479 V1 = PromoteSplati8i16(V1, DAG, EltNo); 4480 4481 // Recreate the 256-bit vector and place the same 128-bit vector 4482 // into the low and high part. This is necessary because we want 4483 // to use VPERM* to shuffle the vectors 4484 if (Size == 256) { 4485 SDValue InsV = Insert128BitVector(DAG.getUNDEF(SrcVT), V1, 4486 DAG.getConstant(0, MVT::i32), DAG, dl); 4487 V1 = Insert128BitVector(InsV, V1, 4488 DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 4489 } 4490 4491 return getLegalSplat(DAG, V1, EltNo); 4492 } 4493 4494 /// getShuffleVectorZeroOrUndef - Return a vector_shuffle of the specified 4495 /// vector of zero or undef vector. This produces a shuffle where the low 4496 /// element of V2 is swizzled into the zero/undef vector, landing at element 4497 /// Idx. This produces a shuffle mask like 4,1,2,3 (idx=0) or 0,1,2,4 (idx=3). 4498 static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx, 4499 bool isZero, bool HasXMMInt, 4500 SelectionDAG &DAG) { 4501 EVT VT = V2.getValueType(); 4502 SDValue V1 = isZero 4503 ? getZeroVector(VT, HasXMMInt, DAG, V2.getDebugLoc()) : DAG.getUNDEF(VT); 4504 unsigned NumElems = VT.getVectorNumElements(); 4505 SmallVector<int, 16> MaskVec; 4506 for (unsigned i = 0; i != NumElems; ++i) 4507 // If this is the insertion idx, put the low elt of V2 here. 4508 MaskVec.push_back(i == Idx ? NumElems : i); 4509 return DAG.getVectorShuffle(VT, V2.getDebugLoc(), V1, V2, &MaskVec[0]); 4510 } 4511 4512 /// getShuffleScalarElt - Returns the scalar element that will make up the ith 4513 /// element of the result of the vector shuffle. 4514 static SDValue getShuffleScalarElt(SDNode *N, int Index, SelectionDAG &DAG, 4515 unsigned Depth) { 4516 if (Depth == 6) 4517 return SDValue(); // Limit search depth. 4518 4519 SDValue V = SDValue(N, 0); 4520 EVT VT = V.getValueType(); 4521 unsigned Opcode = V.getOpcode(); 4522 4523 // Recurse into ISD::VECTOR_SHUFFLE node to find scalars. 4524 if (const ShuffleVectorSDNode *SV = dyn_cast<ShuffleVectorSDNode>(N)) { 4525 Index = SV->getMaskElt(Index); 4526 4527 if (Index < 0) 4528 return DAG.getUNDEF(VT.getVectorElementType()); 4529 4530 int NumElems = VT.getVectorNumElements(); 4531 SDValue NewV = (Index < NumElems) ? SV->getOperand(0) : SV->getOperand(1); 4532 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, Depth+1); 4533 } 4534 4535 // Recurse into target specific vector shuffles to find scalars. 4536 if (isTargetShuffle(Opcode)) { 4537 int NumElems = VT.getVectorNumElements(); 4538 SmallVector<unsigned, 16> ShuffleMask; 4539 SDValue ImmN; 4540 4541 switch(Opcode) { 4542 case X86ISD::SHUFPS: 4543 case X86ISD::SHUFPD: 4544 ImmN = N->getOperand(N->getNumOperands()-1); 4545 DecodeSHUFPSMask(NumElems, 4546 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4547 ShuffleMask); 4548 break; 4549 case X86ISD::PUNPCKHBW: 4550 case X86ISD::PUNPCKHWD: 4551 case X86ISD::PUNPCKHDQ: 4552 case X86ISD::PUNPCKHQDQ: 4553 DecodePUNPCKHMask(NumElems, ShuffleMask); 4554 break; 4555 case X86ISD::UNPCKHPS: 4556 case X86ISD::UNPCKHPD: 4557 case X86ISD::VUNPCKHPSY: 4558 case X86ISD::VUNPCKHPDY: 4559 DecodeUNPCKHPMask(NumElems, ShuffleMask); 4560 break; 4561 case X86ISD::PUNPCKLBW: 4562 case X86ISD::PUNPCKLWD: 4563 case X86ISD::PUNPCKLDQ: 4564 case X86ISD::PUNPCKLQDQ: 4565 DecodePUNPCKLMask(VT, ShuffleMask); 4566 break; 4567 case X86ISD::UNPCKLPS: 4568 case X86ISD::UNPCKLPD: 4569 case X86ISD::VUNPCKLPSY: 4570 case X86ISD::VUNPCKLPDY: 4571 DecodeUNPCKLPMask(VT, ShuffleMask); 4572 break; 4573 case X86ISD::MOVHLPS: 4574 DecodeMOVHLPSMask(NumElems, ShuffleMask); 4575 break; 4576 case X86ISD::MOVLHPS: 4577 DecodeMOVLHPSMask(NumElems, ShuffleMask); 4578 break; 4579 case X86ISD::PSHUFD: 4580 ImmN = N->getOperand(N->getNumOperands()-1); 4581 DecodePSHUFMask(NumElems, 4582 cast<ConstantSDNode>(ImmN)->getZExtValue(), 4583 ShuffleMask); 4584 break; 4585 case X86ISD::PSHUFHW: 4586 ImmN = N->getOperand(N->getNumOperands()-1); 4587 DecodePSHUFHWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4588 ShuffleMask); 4589 break; 4590 case X86ISD::PSHUFLW: 4591 ImmN = N->getOperand(N->getNumOperands()-1); 4592 DecodePSHUFLWMask(cast<ConstantSDNode>(ImmN)->getZExtValue(), 4593 ShuffleMask); 4594 break; 4595 case X86ISD::MOVSS: 4596 case X86ISD::MOVSD: { 4597 // The index 0 always comes from the first element of the second source, 4598 // this is why MOVSS and MOVSD are used in the first place. The other 4599 // elements come from the other positions of the first source vector. 4600 unsigned OpNum = (Index == 0) ? 1 : 0; 4601 return getShuffleScalarElt(V.getOperand(OpNum).getNode(), Index, DAG, 4602 Depth+1); 4603 } 4604 case X86ISD::VPERMILPS: 4605 ImmN = N->getOperand(N->getNumOperands()-1); 4606 DecodeVPERMILPSMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4607 ShuffleMask); 4608 break; 4609 case X86ISD::VPERMILPSY: 4610 ImmN = N->getOperand(N->getNumOperands()-1); 4611 DecodeVPERMILPSMask(8, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4612 ShuffleMask); 4613 break; 4614 case X86ISD::VPERMILPD: 4615 ImmN = N->getOperand(N->getNumOperands()-1); 4616 DecodeVPERMILPDMask(2, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4617 ShuffleMask); 4618 break; 4619 case X86ISD::VPERMILPDY: 4620 ImmN = N->getOperand(N->getNumOperands()-1); 4621 DecodeVPERMILPDMask(4, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4622 ShuffleMask); 4623 break; 4624 case X86ISD::VPERM2F128: 4625 ImmN = N->getOperand(N->getNumOperands()-1); 4626 DecodeVPERM2F128Mask(VT, cast<ConstantSDNode>(ImmN)->getZExtValue(), 4627 ShuffleMask); 4628 break; 4629 case X86ISD::MOVDDUP: 4630 case X86ISD::MOVLHPD: 4631 case X86ISD::MOVLPD: 4632 case X86ISD::MOVLPS: 4633 case X86ISD::MOVSHDUP: 4634 case X86ISD::MOVSLDUP: 4635 case X86ISD::PALIGN: 4636 return SDValue(); // Not yet implemented. 4637 default: 4638 assert(0 && "unknown target shuffle node"); 4639 return SDValue(); 4640 } 4641 4642 Index = ShuffleMask[Index]; 4643 if (Index < 0) 4644 return DAG.getUNDEF(VT.getVectorElementType()); 4645 4646 SDValue NewV = (Index < NumElems) ? N->getOperand(0) : N->getOperand(1); 4647 return getShuffleScalarElt(NewV.getNode(), Index % NumElems, DAG, 4648 Depth+1); 4649 } 4650 4651 // Actual nodes that may contain scalar elements 4652 if (Opcode == ISD::BITCAST) { 4653 V = V.getOperand(0); 4654 EVT SrcVT = V.getValueType(); 4655 unsigned NumElems = VT.getVectorNumElements(); 4656 4657 if (!SrcVT.isVector() || SrcVT.getVectorNumElements() != NumElems) 4658 return SDValue(); 4659 } 4660 4661 if (V.getOpcode() == ISD::SCALAR_TO_VECTOR) 4662 return (Index == 0) ? V.getOperand(0) 4663 : DAG.getUNDEF(VT.getVectorElementType()); 4664 4665 if (V.getOpcode() == ISD::BUILD_VECTOR) 4666 return V.getOperand(Index); 4667 4668 return SDValue(); 4669 } 4670 4671 /// getNumOfConsecutiveZeros - Return the number of elements of a vector 4672 /// shuffle operation which come from a consecutively from a zero. The 4673 /// search can start in two different directions, from left or right. 4674 static 4675 unsigned getNumOfConsecutiveZeros(SDNode *N, int NumElems, 4676 bool ZerosFromLeft, SelectionDAG &DAG) { 4677 int i = 0; 4678 4679 while (i < NumElems) { 4680 unsigned Index = ZerosFromLeft ? i : NumElems-i-1; 4681 SDValue Elt = getShuffleScalarElt(N, Index, DAG, 0); 4682 if (!(Elt.getNode() && 4683 (Elt.getOpcode() == ISD::UNDEF || X86::isZeroNode(Elt)))) 4684 break; 4685 ++i; 4686 } 4687 4688 return i; 4689 } 4690 4691 /// isShuffleMaskConsecutive - Check if the shuffle mask indicies from MaskI to 4692 /// MaskE correspond consecutively to elements from one of the vector operands, 4693 /// starting from its index OpIdx. Also tell OpNum which source vector operand. 4694 static 4695 bool isShuffleMaskConsecutive(ShuffleVectorSDNode *SVOp, int MaskI, int MaskE, 4696 int OpIdx, int NumElems, unsigned &OpNum) { 4697 bool SeenV1 = false; 4698 bool SeenV2 = false; 4699 4700 for (int i = MaskI; i <= MaskE; ++i, ++OpIdx) { 4701 int Idx = SVOp->getMaskElt(i); 4702 // Ignore undef indicies 4703 if (Idx < 0) 4704 continue; 4705 4706 if (Idx < NumElems) 4707 SeenV1 = true; 4708 else 4709 SeenV2 = true; 4710 4711 // Only accept consecutive elements from the same vector 4712 if ((Idx % NumElems != OpIdx) || (SeenV1 && SeenV2)) 4713 return false; 4714 } 4715 4716 OpNum = SeenV1 ? 0 : 1; 4717 return true; 4718 } 4719 4720 /// isVectorShiftRight - Returns true if the shuffle can be implemented as a 4721 /// logical left shift of a vector. 4722 static bool isVectorShiftRight(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4723 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4724 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4725 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4726 false /* check zeros from right */, DAG); 4727 unsigned OpSrc; 4728 4729 if (!NumZeros) 4730 return false; 4731 4732 // Considering the elements in the mask that are not consecutive zeros, 4733 // check if they consecutively come from only one of the source vectors. 4734 // 4735 // V1 = {X, A, B, C} 0 4736 // \ \ \ / 4737 // vector_shuffle V1, V2 <1, 2, 3, X> 4738 // 4739 if (!isShuffleMaskConsecutive(SVOp, 4740 0, // Mask Start Index 4741 NumElems-NumZeros-1, // Mask End Index 4742 NumZeros, // Where to start looking in the src vector 4743 NumElems, // Number of elements in vector 4744 OpSrc)) // Which source operand ? 4745 return false; 4746 4747 isLeft = false; 4748 ShAmt = NumZeros; 4749 ShVal = SVOp->getOperand(OpSrc); 4750 return true; 4751 } 4752 4753 /// isVectorShiftLeft - Returns true if the shuffle can be implemented as a 4754 /// logical left shift of a vector. 4755 static bool isVectorShiftLeft(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4756 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4757 unsigned NumElems = SVOp->getValueType(0).getVectorNumElements(); 4758 unsigned NumZeros = getNumOfConsecutiveZeros(SVOp, NumElems, 4759 true /* check zeros from left */, DAG); 4760 unsigned OpSrc; 4761 4762 if (!NumZeros) 4763 return false; 4764 4765 // Considering the elements in the mask that are not consecutive zeros, 4766 // check if they consecutively come from only one of the source vectors. 4767 // 4768 // 0 { A, B, X, X } = V2 4769 // / \ / / 4770 // vector_shuffle V1, V2 <X, X, 4, 5> 4771 // 4772 if (!isShuffleMaskConsecutive(SVOp, 4773 NumZeros, // Mask Start Index 4774 NumElems-1, // Mask End Index 4775 0, // Where to start looking in the src vector 4776 NumElems, // Number of elements in vector 4777 OpSrc)) // Which source operand ? 4778 return false; 4779 4780 isLeft = true; 4781 ShAmt = NumZeros; 4782 ShVal = SVOp->getOperand(OpSrc); 4783 return true; 4784 } 4785 4786 /// isVectorShift - Returns true if the shuffle can be implemented as a 4787 /// logical left or right shift of a vector. 4788 static bool isVectorShift(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG, 4789 bool &isLeft, SDValue &ShVal, unsigned &ShAmt) { 4790 // Although the logic below support any bitwidth size, there are no 4791 // shift instructions which handle more than 128-bit vectors. 4792 if (SVOp->getValueType(0).getSizeInBits() > 128) 4793 return false; 4794 4795 if (isVectorShiftLeft(SVOp, DAG, isLeft, ShVal, ShAmt) || 4796 isVectorShiftRight(SVOp, DAG, isLeft, ShVal, ShAmt)) 4797 return true; 4798 4799 return false; 4800 } 4801 4802 /// LowerBuildVectorv16i8 - Custom lower build_vector of v16i8. 4803 /// 4804 static SDValue LowerBuildVectorv16i8(SDValue Op, unsigned NonZeros, 4805 unsigned NumNonZero, unsigned NumZero, 4806 SelectionDAG &DAG, 4807 const TargetLowering &TLI) { 4808 if (NumNonZero > 8) 4809 return SDValue(); 4810 4811 DebugLoc dl = Op.getDebugLoc(); 4812 SDValue V(0, 0); 4813 bool First = true; 4814 for (unsigned i = 0; i < 16; ++i) { 4815 bool ThisIsNonZero = (NonZeros & (1 << i)) != 0; 4816 if (ThisIsNonZero && First) { 4817 if (NumZero) 4818 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4819 else 4820 V = DAG.getUNDEF(MVT::v8i16); 4821 First = false; 4822 } 4823 4824 if ((i & 1) != 0) { 4825 SDValue ThisElt(0, 0), LastElt(0, 0); 4826 bool LastIsNonZero = (NonZeros & (1 << (i-1))) != 0; 4827 if (LastIsNonZero) { 4828 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, 4829 MVT::i16, Op.getOperand(i-1)); 4830 } 4831 if (ThisIsNonZero) { 4832 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); 4833 ThisElt = DAG.getNode(ISD::SHL, dl, MVT::i16, 4834 ThisElt, DAG.getConstant(8, MVT::i8)); 4835 if (LastIsNonZero) 4836 ThisElt = DAG.getNode(ISD::OR, dl, MVT::i16, ThisElt, LastElt); 4837 } else 4838 ThisElt = LastElt; 4839 4840 if (ThisElt.getNode()) 4841 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, V, ThisElt, 4842 DAG.getIntPtrConstant(i/2)); 4843 } 4844 } 4845 4846 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V); 4847 } 4848 4849 /// LowerBuildVectorv8i16 - Custom lower build_vector of v8i16. 4850 /// 4851 static SDValue LowerBuildVectorv8i16(SDValue Op, unsigned NonZeros, 4852 unsigned NumNonZero, unsigned NumZero, 4853 SelectionDAG &DAG, 4854 const TargetLowering &TLI) { 4855 if (NumNonZero > 4) 4856 return SDValue(); 4857 4858 DebugLoc dl = Op.getDebugLoc(); 4859 SDValue V(0, 0); 4860 bool First = true; 4861 for (unsigned i = 0; i < 8; ++i) { 4862 bool isNonZero = (NonZeros & (1 << i)) != 0; 4863 if (isNonZero) { 4864 if (First) { 4865 if (NumZero) 4866 V = getZeroVector(MVT::v8i16, true, DAG, dl); 4867 else 4868 V = DAG.getUNDEF(MVT::v8i16); 4869 First = false; 4870 } 4871 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, 4872 MVT::v8i16, V, Op.getOperand(i), 4873 DAG.getIntPtrConstant(i)); 4874 } 4875 } 4876 4877 return V; 4878 } 4879 4880 /// getVShift - Return a vector logical shift node. 4881 /// 4882 static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp, 4883 unsigned NumBits, SelectionDAG &DAG, 4884 const TargetLowering &TLI, DebugLoc dl) { 4885 assert(VT.getSizeInBits() == 128 && "Unknown type for VShift"); 4886 EVT ShVT = MVT::v2i64; 4887 unsigned Opc = isLeft ? X86ISD::VSHL : X86ISD::VSRL; 4888 SrcOp = DAG.getNode(ISD::BITCAST, dl, ShVT, SrcOp); 4889 return DAG.getNode(ISD::BITCAST, dl, VT, 4890 DAG.getNode(Opc, dl, ShVT, SrcOp, 4891 DAG.getConstant(NumBits, 4892 TLI.getShiftAmountTy(SrcOp.getValueType())))); 4893 } 4894 4895 SDValue 4896 X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl, 4897 SelectionDAG &DAG) const { 4898 4899 // Check if the scalar load can be widened into a vector load. And if 4900 // the address is "base + cst" see if the cst can be "absorbed" into 4901 // the shuffle mask. 4902 if (LoadSDNode *LD = dyn_cast<LoadSDNode>(SrcOp)) { 4903 SDValue Ptr = LD->getBasePtr(); 4904 if (!ISD::isNormalLoad(LD) || LD->isVolatile()) 4905 return SDValue(); 4906 EVT PVT = LD->getValueType(0); 4907 if (PVT != MVT::i32 && PVT != MVT::f32) 4908 return SDValue(); 4909 4910 int FI = -1; 4911 int64_t Offset = 0; 4912 if (FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(Ptr)) { 4913 FI = FINode->getIndex(); 4914 Offset = 0; 4915 } else if (DAG.isBaseWithConstantOffset(Ptr) && 4916 isa<FrameIndexSDNode>(Ptr.getOperand(0))) { 4917 FI = cast<FrameIndexSDNode>(Ptr.getOperand(0))->getIndex(); 4918 Offset = Ptr.getConstantOperandVal(1); 4919 Ptr = Ptr.getOperand(0); 4920 } else { 4921 return SDValue(); 4922 } 4923 4924 // FIXME: 256-bit vector instructions don't require a strict alignment, 4925 // improve this code to support it better. 4926 unsigned RequiredAlign = VT.getSizeInBits()/8; 4927 SDValue Chain = LD->getChain(); 4928 // Make sure the stack object alignment is at least 16 or 32. 4929 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4930 if (DAG.InferPtrAlignment(Ptr) < RequiredAlign) { 4931 if (MFI->isFixedObjectIndex(FI)) { 4932 // Can't change the alignment. FIXME: It's possible to compute 4933 // the exact stack offset and reference FI + adjust offset instead. 4934 // If someone *really* cares about this. That's the way to implement it. 4935 return SDValue(); 4936 } else { 4937 MFI->setObjectAlignment(FI, RequiredAlign); 4938 } 4939 } 4940 4941 // (Offset % 16 or 32) must be multiple of 4. Then address is then 4942 // Ptr + (Offset & ~15). 4943 if (Offset < 0) 4944 return SDValue(); 4945 if ((Offset % RequiredAlign) & 3) 4946 return SDValue(); 4947 int64_t StartOffset = Offset & ~(RequiredAlign-1); 4948 if (StartOffset) 4949 Ptr = DAG.getNode(ISD::ADD, Ptr.getDebugLoc(), Ptr.getValueType(), 4950 Ptr,DAG.getConstant(StartOffset, Ptr.getValueType())); 4951 4952 int EltNo = (Offset - StartOffset) >> 2; 4953 int NumElems = VT.getVectorNumElements(); 4954 4955 EVT CanonVT = VT.getSizeInBits() == 128 ? MVT::v4i32 : MVT::v8i32; 4956 EVT NVT = EVT::getVectorVT(*DAG.getContext(), PVT, NumElems); 4957 SDValue V1 = DAG.getLoad(NVT, dl, Chain, Ptr, 4958 LD->getPointerInfo().getWithOffset(StartOffset), 4959 false, false, 0); 4960 4961 // Canonicalize it to a v4i32 or v8i32 shuffle. 4962 SmallVector<int, 8> Mask; 4963 for (int i = 0; i < NumElems; ++i) 4964 Mask.push_back(EltNo); 4965 4966 V1 = DAG.getNode(ISD::BITCAST, dl, CanonVT, V1); 4967 return DAG.getNode(ISD::BITCAST, dl, NVT, 4968 DAG.getVectorShuffle(CanonVT, dl, V1, 4969 DAG.getUNDEF(CanonVT),&Mask[0])); 4970 } 4971 4972 return SDValue(); 4973 } 4974 4975 /// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a 4976 /// vector of type 'VT', see if the elements can be replaced by a single large 4977 /// load which has the same value as a build_vector whose operands are 'elts'. 4978 /// 4979 /// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a 4980 /// 4981 /// FIXME: we'd also like to handle the case where the last elements are zero 4982 /// rather than undef via VZEXT_LOAD, but we do not detect that case today. 4983 /// There's even a handy isZeroNode for that purpose. 4984 static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts, 4985 DebugLoc &DL, SelectionDAG &DAG) { 4986 EVT EltVT = VT.getVectorElementType(); 4987 unsigned NumElems = Elts.size(); 4988 4989 LoadSDNode *LDBase = NULL; 4990 unsigned LastLoadedElt = -1U; 4991 4992 // For each element in the initializer, see if we've found a load or an undef. 4993 // If we don't find an initial load element, or later load elements are 4994 // non-consecutive, bail out. 4995 for (unsigned i = 0; i < NumElems; ++i) { 4996 SDValue Elt = Elts[i]; 4997 4998 if (!Elt.getNode() || 4999 (Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode()))) 5000 return SDValue(); 5001 if (!LDBase) { 5002 if (Elt.getNode()->getOpcode() == ISD::UNDEF) 5003 return SDValue(); 5004 LDBase = cast<LoadSDNode>(Elt.getNode()); 5005 LastLoadedElt = i; 5006 continue; 5007 } 5008 if (Elt.getOpcode() == ISD::UNDEF) 5009 continue; 5010 5011 LoadSDNode *LD = cast<LoadSDNode>(Elt); 5012 if (!DAG.isConsecutiveLoad(LD, LDBase, EltVT.getSizeInBits()/8, i)) 5013 return SDValue(); 5014 LastLoadedElt = i; 5015 } 5016 5017 // If we have found an entire vector of loads and undefs, then return a large 5018 // load of the entire vector width starting at the base pointer. If we found 5019 // consecutive loads for the low half, generate a vzext_load node. 5020 if (LastLoadedElt == NumElems - 1) { 5021 if (DAG.InferPtrAlignment(LDBase->getBasePtr()) >= 16) 5022 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5023 LDBase->getPointerInfo(), 5024 LDBase->isVolatile(), LDBase->isNonTemporal(), 0); 5025 return DAG.getLoad(VT, DL, LDBase->getChain(), LDBase->getBasePtr(), 5026 LDBase->getPointerInfo(), 5027 LDBase->isVolatile(), LDBase->isNonTemporal(), 5028 LDBase->getAlignment()); 5029 } else if (NumElems == 4 && LastLoadedElt == 1 && 5030 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { 5031 SDVTList Tys = DAG.getVTList(MVT::v2i64, MVT::Other); 5032 SDValue Ops[] = { LDBase->getChain(), LDBase->getBasePtr() }; 5033 SDValue ResNode = 5034 DAG.getMemIntrinsicNode(X86ISD::VZEXT_LOAD, DL, Tys, Ops, 2, MVT::i64, 5035 LDBase->getPointerInfo(), 5036 LDBase->getAlignment(), 5037 false/*isVolatile*/, true/*ReadMem*/, 5038 false/*WriteMem*/); 5039 return DAG.getNode(ISD::BITCAST, DL, VT, ResNode); 5040 } 5041 return SDValue(); 5042 } 5043 5044 SDValue 5045 X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const { 5046 DebugLoc dl = Op.getDebugLoc(); 5047 5048 EVT VT = Op.getValueType(); 5049 EVT ExtVT = VT.getVectorElementType(); 5050 unsigned NumElems = Op.getNumOperands(); 5051 5052 // Vectors containing all zeros can be matched by pxor and xorps later 5053 if (ISD::isBuildVectorAllZeros(Op.getNode())) { 5054 // Canonicalize this to <4 x i32> to 1) ensure the zero vectors are CSE'd 5055 // and 2) ensure that i64 scalars are eliminated on x86-32 hosts. 5056 if (Op.getValueType() == MVT::v4i32 || 5057 Op.getValueType() == MVT::v8i32) 5058 return Op; 5059 5060 return getZeroVector(Op.getValueType(), Subtarget->hasXMMInt(), DAG, dl); 5061 } 5062 5063 // Vectors containing all ones can be matched by pcmpeqd on 128-bit width 5064 // vectors or broken into v4i32 operations on 256-bit vectors. 5065 if (ISD::isBuildVectorAllOnes(Op.getNode())) { 5066 if (Op.getValueType() == MVT::v4i32) 5067 return Op; 5068 5069 return getOnesVector(Op.getValueType(), DAG, dl); 5070 } 5071 5072 unsigned EVTBits = ExtVT.getSizeInBits(); 5073 5074 unsigned NumZero = 0; 5075 unsigned NumNonZero = 0; 5076 unsigned NonZeros = 0; 5077 bool IsAllConstants = true; 5078 SmallSet<SDValue, 8> Values; 5079 for (unsigned i = 0; i < NumElems; ++i) { 5080 SDValue Elt = Op.getOperand(i); 5081 if (Elt.getOpcode() == ISD::UNDEF) 5082 continue; 5083 Values.insert(Elt); 5084 if (Elt.getOpcode() != ISD::Constant && 5085 Elt.getOpcode() != ISD::ConstantFP) 5086 IsAllConstants = false; 5087 if (X86::isZeroNode(Elt)) 5088 NumZero++; 5089 else { 5090 NonZeros |= (1 << i); 5091 NumNonZero++; 5092 } 5093 } 5094 5095 // All undef vector. Return an UNDEF. All zero vectors were handled above. 5096 if (NumNonZero == 0) 5097 return DAG.getUNDEF(VT); 5098 5099 // Special case for single non-zero, non-undef, element. 5100 if (NumNonZero == 1) { 5101 unsigned Idx = CountTrailingZeros_32(NonZeros); 5102 SDValue Item = Op.getOperand(Idx); 5103 5104 // If this is an insertion of an i64 value on x86-32, and if the top bits of 5105 // the value are obviously zero, truncate the value to i32 and do the 5106 // insertion that way. Only do this if the value is non-constant or if the 5107 // value is a constant being inserted into element 0. It is cheaper to do 5108 // a constant pool load than it is to do a movd + shuffle. 5109 if (ExtVT == MVT::i64 && !Subtarget->is64Bit() && 5110 (!IsAllConstants || Idx == 0)) { 5111 if (DAG.MaskedValueIsZero(Item, APInt::getBitsSet(64, 32, 64))) { 5112 // Handle SSE only. 5113 assert(VT == MVT::v2i64 && "Expected an SSE value type!"); 5114 EVT VecVT = MVT::v4i32; 5115 unsigned VecElts = 4; 5116 5117 // Truncate the value (which may itself be a constant) to i32, and 5118 // convert it to a vector with movd (S2V+shuffle to zero extend). 5119 Item = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Item); 5120 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VecVT, Item); 5121 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5122 Subtarget->hasXMMInt(), DAG); 5123 5124 // Now we have our 32-bit value zero extended in the low element of 5125 // a vector. If Idx != 0, swizzle it into place. 5126 if (Idx != 0) { 5127 SmallVector<int, 4> Mask; 5128 Mask.push_back(Idx); 5129 for (unsigned i = 1; i != VecElts; ++i) 5130 Mask.push_back(i); 5131 Item = DAG.getVectorShuffle(VecVT, dl, Item, 5132 DAG.getUNDEF(Item.getValueType()), 5133 &Mask[0]); 5134 } 5135 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), Item); 5136 } 5137 } 5138 5139 // If we have a constant or non-constant insertion into the low element of 5140 // a vector, we can do this with SCALAR_TO_VECTOR + shuffle of zero into 5141 // the rest of the elements. This will be matched as movd/movq/movss/movsd 5142 // depending on what the source datatype is. 5143 if (Idx == 0) { 5144 if (NumZero == 0) { 5145 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5146 } else if (ExtVT == MVT::i32 || ExtVT == MVT::f32 || ExtVT == MVT::f64 || 5147 (ExtVT == MVT::i64 && Subtarget->is64Bit())) { 5148 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5149 // Turn it into a MOVL (i.e. movss, movsd, or movd) to a zero vector. 5150 return getShuffleVectorZeroOrUndef(Item, 0, true,Subtarget->hasXMMInt(), 5151 DAG); 5152 } else if (ExtVT == MVT::i16 || ExtVT == MVT::i8) { 5153 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); 5154 assert(VT.getSizeInBits() == 128 && "Expected an SSE value type!"); 5155 EVT MiddleVT = MVT::v4i32; 5156 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MiddleVT, Item); 5157 Item = getShuffleVectorZeroOrUndef(Item, 0, true, 5158 Subtarget->hasXMMInt(), DAG); 5159 return DAG.getNode(ISD::BITCAST, dl, VT, Item); 5160 } 5161 } 5162 5163 // Is it a vector logical left shift? 5164 if (NumElems == 2 && Idx == 1 && 5165 X86::isZeroNode(Op.getOperand(0)) && 5166 !X86::isZeroNode(Op.getOperand(1))) { 5167 unsigned NumBits = VT.getSizeInBits(); 5168 return getVShift(true, VT, 5169 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5170 VT, Op.getOperand(1)), 5171 NumBits/2, DAG, *this, dl); 5172 } 5173 5174 if (IsAllConstants) // Otherwise, it's better to do a constpool load. 5175 return SDValue(); 5176 5177 // Otherwise, if this is a vector with i32 or f32 elements, and the element 5178 // is a non-constant being inserted into an element other than the low one, 5179 // we can't use a constant pool load. Instead, use SCALAR_TO_VECTOR (aka 5180 // movd/movss) to move this into the low element, then shuffle it into 5181 // place. 5182 if (EVTBits == 32) { 5183 Item = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Item); 5184 5185 // Turn it into a shuffle of zero and zero-extended scalar to vector. 5186 Item = getShuffleVectorZeroOrUndef(Item, 0, NumZero > 0, 5187 Subtarget->hasXMMInt(), DAG); 5188 SmallVector<int, 8> MaskVec; 5189 for (unsigned i = 0; i < NumElems; i++) 5190 MaskVec.push_back(i == Idx ? 0 : 1); 5191 return DAG.getVectorShuffle(VT, dl, Item, DAG.getUNDEF(VT), &MaskVec[0]); 5192 } 5193 } 5194 5195 // Splat is obviously ok. Let legalizer expand it to a shuffle. 5196 if (Values.size() == 1) { 5197 if (EVTBits == 32) { 5198 // Instead of a shuffle like this: 5199 // shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0> 5200 // Check if it's possible to issue this instead. 5201 // shuffle (vload ptr)), undef, <1, 1, 1, 1> 5202 unsigned Idx = CountTrailingZeros_32(NonZeros); 5203 SDValue Item = Op.getOperand(Idx); 5204 if (Op.getNode()->isOnlyUserOf(Item.getNode())) 5205 return LowerAsSplatVectorLoad(Item, VT, dl, DAG); 5206 } 5207 return SDValue(); 5208 } 5209 5210 // A vector full of immediates; various special cases are already 5211 // handled, so this is best done with a single constant-pool load. 5212 if (IsAllConstants) 5213 return SDValue(); 5214 5215 // For AVX-length vectors, build the individual 128-bit pieces and use 5216 // shuffles to put them in place. 5217 if (VT.getSizeInBits() == 256 && !ISD::isBuildVectorAllZeros(Op.getNode())) { 5218 SmallVector<SDValue, 32> V; 5219 for (unsigned i = 0; i < NumElems; ++i) 5220 V.push_back(Op.getOperand(i)); 5221 5222 EVT HVT = EVT::getVectorVT(*DAG.getContext(), ExtVT, NumElems/2); 5223 5224 // Build both the lower and upper subvector. 5225 SDValue Lower = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[0], NumElems/2); 5226 SDValue Upper = DAG.getNode(ISD::BUILD_VECTOR, dl, HVT, &V[NumElems / 2], 5227 NumElems/2); 5228 5229 // Recreate the wider vector with the lower and upper part. 5230 SDValue Vec = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), Lower, 5231 DAG.getConstant(0, MVT::i32), DAG, dl); 5232 return Insert128BitVector(Vec, Upper, DAG.getConstant(NumElems/2, MVT::i32), 5233 DAG, dl); 5234 } 5235 5236 // Let legalizer expand 2-wide build_vectors. 5237 if (EVTBits == 64) { 5238 if (NumNonZero == 1) { 5239 // One half is zero or undef. 5240 unsigned Idx = CountTrailingZeros_32(NonZeros); 5241 SDValue V2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, 5242 Op.getOperand(Idx)); 5243 return getShuffleVectorZeroOrUndef(V2, Idx, true, 5244 Subtarget->hasXMMInt(), DAG); 5245 } 5246 return SDValue(); 5247 } 5248 5249 // If element VT is < 32 bits, convert it to inserts into a zero vector. 5250 if (EVTBits == 8 && NumElems == 16) { 5251 SDValue V = LowerBuildVectorv16i8(Op, NonZeros,NumNonZero,NumZero, DAG, 5252 *this); 5253 if (V.getNode()) return V; 5254 } 5255 5256 if (EVTBits == 16 && NumElems == 8) { 5257 SDValue V = LowerBuildVectorv8i16(Op, NonZeros,NumNonZero,NumZero, DAG, 5258 *this); 5259 if (V.getNode()) return V; 5260 } 5261 5262 // If element VT is == 32 bits, turn it into a number of shuffles. 5263 SmallVector<SDValue, 8> V; 5264 V.resize(NumElems); 5265 if (NumElems == 4 && NumZero > 0) { 5266 for (unsigned i = 0; i < 4; ++i) { 5267 bool isZero = !(NonZeros & (1 << i)); 5268 if (isZero) 5269 V[i] = getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 5270 else 5271 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5272 } 5273 5274 for (unsigned i = 0; i < 2; ++i) { 5275 switch ((NonZeros & (0x3 << i*2)) >> (i*2)) { 5276 default: break; 5277 case 0: 5278 V[i] = V[i*2]; // Must be a zero vector. 5279 break; 5280 case 1: 5281 V[i] = getMOVL(DAG, dl, VT, V[i*2+1], V[i*2]); 5282 break; 5283 case 2: 5284 V[i] = getMOVL(DAG, dl, VT, V[i*2], V[i*2+1]); 5285 break; 5286 case 3: 5287 V[i] = getUnpackl(DAG, dl, VT, V[i*2], V[i*2+1]); 5288 break; 5289 } 5290 } 5291 5292 SmallVector<int, 8> MaskVec; 5293 bool Reverse = (NonZeros & 0x3) == 2; 5294 for (unsigned i = 0; i < 2; ++i) 5295 MaskVec.push_back(Reverse ? 1-i : i); 5296 Reverse = ((NonZeros & (0x3 << 2)) >> 2) == 2; 5297 for (unsigned i = 0; i < 2; ++i) 5298 MaskVec.push_back(Reverse ? 1-i+NumElems : i+NumElems); 5299 return DAG.getVectorShuffle(VT, dl, V[0], V[1], &MaskVec[0]); 5300 } 5301 5302 if (Values.size() > 1 && VT.getSizeInBits() == 128) { 5303 // Check for a build vector of consecutive loads. 5304 for (unsigned i = 0; i < NumElems; ++i) 5305 V[i] = Op.getOperand(i); 5306 5307 // Check for elements which are consecutive loads. 5308 SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG); 5309 if (LD.getNode()) 5310 return LD; 5311 5312 // For SSE 4.1, use insertps to put the high elements into the low element. 5313 if (getSubtarget()->hasSSE41() || getSubtarget()->hasAVX()) { 5314 SDValue Result; 5315 if (Op.getOperand(0).getOpcode() != ISD::UNDEF) 5316 Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0)); 5317 else 5318 Result = DAG.getUNDEF(VT); 5319 5320 for (unsigned i = 1; i < NumElems; ++i) { 5321 if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue; 5322 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result, 5323 Op.getOperand(i), DAG.getIntPtrConstant(i)); 5324 } 5325 return Result; 5326 } 5327 5328 // Otherwise, expand into a number of unpckl*, start by extending each of 5329 // our (non-undef) elements to the full vector width with the element in the 5330 // bottom slot of the vector (which generates no code for SSE). 5331 for (unsigned i = 0; i < NumElems; ++i) { 5332 if (Op.getOperand(i).getOpcode() != ISD::UNDEF) 5333 V[i] = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(i)); 5334 else 5335 V[i] = DAG.getUNDEF(VT); 5336 } 5337 5338 // Next, we iteratively mix elements, e.g. for v4f32: 5339 // Step 1: unpcklps 0, 2 ==> X: <?, ?, 2, 0> 5340 // : unpcklps 1, 3 ==> Y: <?, ?, 3, 1> 5341 // Step 2: unpcklps X, Y ==> <3, 2, 1, 0> 5342 unsigned EltStride = NumElems >> 1; 5343 while (EltStride != 0) { 5344 for (unsigned i = 0; i < EltStride; ++i) { 5345 // If V[i+EltStride] is undef and this is the first round of mixing, 5346 // then it is safe to just drop this shuffle: V[i] is already in the 5347 // right place, the one element (since it's the first round) being 5348 // inserted as undef can be dropped. This isn't safe for successive 5349 // rounds because they will permute elements within both vectors. 5350 if (V[i+EltStride].getOpcode() == ISD::UNDEF && 5351 EltStride == NumElems/2) 5352 continue; 5353 5354 V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]); 5355 } 5356 EltStride >>= 1; 5357 } 5358 return V[0]; 5359 } 5360 return SDValue(); 5361 } 5362 5363 // LowerMMXCONCAT_VECTORS - We support concatenate two MMX registers and place 5364 // them in a MMX register. This is better than doing a stack convert. 5365 static SDValue LowerMMXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5366 DebugLoc dl = Op.getDebugLoc(); 5367 EVT ResVT = Op.getValueType(); 5368 5369 assert(ResVT == MVT::v2i64 || ResVT == MVT::v4i32 || 5370 ResVT == MVT::v8i16 || ResVT == MVT::v16i8); 5371 int Mask[2]; 5372 SDValue InVec = DAG.getNode(ISD::BITCAST,dl, MVT::v1i64, Op.getOperand(0)); 5373 SDValue VecOp = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5374 InVec = Op.getOperand(1); 5375 if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) { 5376 unsigned NumElts = ResVT.getVectorNumElements(); 5377 VecOp = DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5378 VecOp = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, ResVT, VecOp, 5379 InVec.getOperand(0), DAG.getIntPtrConstant(NumElts/2+1)); 5380 } else { 5381 InVec = DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, InVec); 5382 SDValue VecOp2 = DAG.getNode(X86ISD::MOVQ2DQ, dl, MVT::v2i64, InVec); 5383 Mask[0] = 0; Mask[1] = 2; 5384 VecOp = DAG.getVectorShuffle(MVT::v2i64, dl, VecOp, VecOp2, Mask); 5385 } 5386 return DAG.getNode(ISD::BITCAST, dl, ResVT, VecOp); 5387 } 5388 5389 // LowerAVXCONCAT_VECTORS - 256-bit AVX can use the vinsertf128 instruction 5390 // to create 256-bit vectors from two other 128-bit ones. 5391 static SDValue LowerAVXCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) { 5392 DebugLoc dl = Op.getDebugLoc(); 5393 EVT ResVT = Op.getValueType(); 5394 5395 assert(ResVT.getSizeInBits() == 256 && "Value type must be 256-bit wide"); 5396 5397 SDValue V1 = Op.getOperand(0); 5398 SDValue V2 = Op.getOperand(1); 5399 unsigned NumElems = ResVT.getVectorNumElements(); 5400 5401 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, ResVT), V1, 5402 DAG.getConstant(0, MVT::i32), DAG, dl); 5403 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 5404 DAG, dl); 5405 } 5406 5407 SDValue 5408 X86TargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const { 5409 EVT ResVT = Op.getValueType(); 5410 5411 assert(Op.getNumOperands() == 2); 5412 assert((ResVT.getSizeInBits() == 128 || ResVT.getSizeInBits() == 256) && 5413 "Unsupported CONCAT_VECTORS for value type"); 5414 5415 // We support concatenate two MMX registers and place them in a MMX register. 5416 // This is better than doing a stack convert. 5417 if (ResVT.is128BitVector()) 5418 return LowerMMXCONCAT_VECTORS(Op, DAG); 5419 5420 // 256-bit AVX can use the vinsertf128 instruction to create 256-bit vectors 5421 // from two other 128-bit ones. 5422 return LowerAVXCONCAT_VECTORS(Op, DAG); 5423 } 5424 5425 // v8i16 shuffles - Prefer shuffles in the following order: 5426 // 1. [all] pshuflw, pshufhw, optional move 5427 // 2. [ssse3] 1 x pshufb 5428 // 3. [ssse3] 2 x pshufb + 1 x por 5429 // 4. [all] mov + pshuflw + pshufhw + N x (pextrw + pinsrw) 5430 SDValue 5431 X86TargetLowering::LowerVECTOR_SHUFFLEv8i16(SDValue Op, 5432 SelectionDAG &DAG) const { 5433 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 5434 SDValue V1 = SVOp->getOperand(0); 5435 SDValue V2 = SVOp->getOperand(1); 5436 DebugLoc dl = SVOp->getDebugLoc(); 5437 SmallVector<int, 8> MaskVals; 5438 5439 // Determine if more than 1 of the words in each of the low and high quadwords 5440 // of the result come from the same quadword of one of the two inputs. Undef 5441 // mask values count as coming from any quadword, for better codegen. 5442 unsigned LoQuad[] = { 0, 0, 0, 0 }; 5443 unsigned HiQuad[] = { 0, 0, 0, 0 }; 5444 BitVector InputQuads(4); 5445 for (unsigned i = 0; i < 8; ++i) { 5446 unsigned *Quad = i < 4 ? LoQuad : HiQuad; 5447 int EltIdx = SVOp->getMaskElt(i); 5448 MaskVals.push_back(EltIdx); 5449 if (EltIdx < 0) { 5450 ++Quad[0]; 5451 ++Quad[1]; 5452 ++Quad[2]; 5453 ++Quad[3]; 5454 continue; 5455 } 5456 ++Quad[EltIdx / 4]; 5457 InputQuads.set(EltIdx / 4); 5458 } 5459 5460 int BestLoQuad = -1; 5461 unsigned MaxQuad = 1; 5462 for (unsigned i = 0; i < 4; ++i) { 5463 if (LoQuad[i] > MaxQuad) { 5464 BestLoQuad = i; 5465 MaxQuad = LoQuad[i]; 5466 } 5467 } 5468 5469 int BestHiQuad = -1; 5470 MaxQuad = 1; 5471 for (unsigned i = 0; i < 4; ++i) { 5472 if (HiQuad[i] > MaxQuad) { 5473 BestHiQuad = i; 5474 MaxQuad = HiQuad[i]; 5475 } 5476 } 5477 5478 // For SSSE3, If all 8 words of the result come from only 1 quadword of each 5479 // of the two input vectors, shuffle them into one input vector so only a 5480 // single pshufb instruction is necessary. If There are more than 2 input 5481 // quads, disable the next transformation since it does not help SSSE3. 5482 bool V1Used = InputQuads[0] || InputQuads[1]; 5483 bool V2Used = InputQuads[2] || InputQuads[3]; 5484 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5485 if (InputQuads.count() == 2 && V1Used && V2Used) { 5486 BestLoQuad = InputQuads.find_first(); 5487 BestHiQuad = InputQuads.find_next(BestLoQuad); 5488 } 5489 if (InputQuads.count() > 2) { 5490 BestLoQuad = -1; 5491 BestHiQuad = -1; 5492 } 5493 } 5494 5495 // If BestLoQuad or BestHiQuad are set, shuffle the quads together and update 5496 // the shuffle mask. If a quad is scored as -1, that means that it contains 5497 // words from all 4 input quadwords. 5498 SDValue NewV; 5499 if (BestLoQuad >= 0 || BestHiQuad >= 0) { 5500 SmallVector<int, 8> MaskV; 5501 MaskV.push_back(BestLoQuad < 0 ? 0 : BestLoQuad); 5502 MaskV.push_back(BestHiQuad < 0 ? 1 : BestHiQuad); 5503 NewV = DAG.getVectorShuffle(MVT::v2i64, dl, 5504 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V1), 5505 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, V2), &MaskV[0]); 5506 NewV = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, NewV); 5507 5508 // Rewrite the MaskVals and assign NewV to V1 if NewV now contains all the 5509 // source words for the shuffle, to aid later transformations. 5510 bool AllWordsInNewV = true; 5511 bool InOrder[2] = { true, true }; 5512 for (unsigned i = 0; i != 8; ++i) { 5513 int idx = MaskVals[i]; 5514 if (idx != (int)i) 5515 InOrder[i/4] = false; 5516 if (idx < 0 || (idx/4) == BestLoQuad || (idx/4) == BestHiQuad) 5517 continue; 5518 AllWordsInNewV = false; 5519 break; 5520 } 5521 5522 bool pshuflw = AllWordsInNewV, pshufhw = AllWordsInNewV; 5523 if (AllWordsInNewV) { 5524 for (int i = 0; i != 8; ++i) { 5525 int idx = MaskVals[i]; 5526 if (idx < 0) 5527 continue; 5528 idx = MaskVals[i] = (idx / 4) == BestLoQuad ? (idx & 3) : (idx & 3) + 4; 5529 if ((idx != i) && idx < 4) 5530 pshufhw = false; 5531 if ((idx != i) && idx > 3) 5532 pshuflw = false; 5533 } 5534 V1 = NewV; 5535 V2Used = false; 5536 BestLoQuad = 0; 5537 BestHiQuad = 1; 5538 } 5539 5540 // If we've eliminated the use of V2, and the new mask is a pshuflw or 5541 // pshufhw, that's as cheap as it gets. Return the new shuffle. 5542 if ((pshufhw && InOrder[0]) || (pshuflw && InOrder[1])) { 5543 unsigned Opc = pshufhw ? X86ISD::PSHUFHW : X86ISD::PSHUFLW; 5544 unsigned TargetMask = 0; 5545 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, 5546 DAG.getUNDEF(MVT::v8i16), &MaskVals[0]); 5547 TargetMask = pshufhw ? X86::getShufflePSHUFHWImmediate(NewV.getNode()): 5548 X86::getShufflePSHUFLWImmediate(NewV.getNode()); 5549 V1 = NewV.getOperand(0); 5550 return getTargetShuffleNode(Opc, dl, MVT::v8i16, V1, TargetMask, DAG); 5551 } 5552 } 5553 5554 // If we have SSSE3, and all words of the result are from 1 input vector, 5555 // case 2 is generated, otherwise case 3 is generated. If no SSSE3 5556 // is present, fall back to case 4. 5557 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 5558 SmallVector<SDValue,16> pshufbMask; 5559 5560 // If we have elements from both input vectors, set the high bit of the 5561 // shuffle mask element to zero out elements that come from V2 in the V1 5562 // mask, and elements that come from V1 in the V2 mask, so that the two 5563 // results can be OR'd together. 5564 bool TwoInputs = V1Used && V2Used; 5565 for (unsigned i = 0; i != 8; ++i) { 5566 int EltIdx = MaskVals[i] * 2; 5567 if (TwoInputs && (EltIdx >= 16)) { 5568 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5569 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5570 continue; 5571 } 5572 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5573 pshufbMask.push_back(DAG.getConstant(EltIdx+1, MVT::i8)); 5574 } 5575 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V1); 5576 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5577 DAG.getNode(ISD::BUILD_VECTOR, dl, 5578 MVT::v16i8, &pshufbMask[0], 16)); 5579 if (!TwoInputs) 5580 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5581 5582 // Calculate the shuffle mask for the second input, shuffle it, and 5583 // OR it with the first shuffled input. 5584 pshufbMask.clear(); 5585 for (unsigned i = 0; i != 8; ++i) { 5586 int EltIdx = MaskVals[i] * 2; 5587 if (EltIdx < 16) { 5588 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5589 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5590 continue; 5591 } 5592 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5593 pshufbMask.push_back(DAG.getConstant(EltIdx - 15, MVT::i8)); 5594 } 5595 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, V2); 5596 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5597 DAG.getNode(ISD::BUILD_VECTOR, dl, 5598 MVT::v16i8, &pshufbMask[0], 16)); 5599 V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5600 return DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5601 } 5602 5603 // If BestLoQuad >= 0, generate a pshuflw to put the low elements in order, 5604 // and update MaskVals with new element order. 5605 BitVector InOrder(8); 5606 if (BestLoQuad >= 0) { 5607 SmallVector<int, 8> MaskV; 5608 for (int i = 0; i != 4; ++i) { 5609 int idx = MaskVals[i]; 5610 if (idx < 0) { 5611 MaskV.push_back(-1); 5612 InOrder.set(i); 5613 } else if ((idx / 4) == BestLoQuad) { 5614 MaskV.push_back(idx & 3); 5615 InOrder.set(i); 5616 } else { 5617 MaskV.push_back(-1); 5618 } 5619 } 5620 for (unsigned i = 4; i != 8; ++i) 5621 MaskV.push_back(i); 5622 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5623 &MaskV[0]); 5624 5625 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5626 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5627 NewV = getTargetShuffleNode(X86ISD::PSHUFLW, dl, MVT::v8i16, 5628 NewV.getOperand(0), 5629 X86::getShufflePSHUFLWImmediate(NewV.getNode()), 5630 DAG); 5631 } 5632 5633 // If BestHi >= 0, generate a pshufhw to put the high elements in order, 5634 // and update MaskVals with the new element order. 5635 if (BestHiQuad >= 0) { 5636 SmallVector<int, 8> MaskV; 5637 for (unsigned i = 0; i != 4; ++i) 5638 MaskV.push_back(i); 5639 for (unsigned i = 4; i != 8; ++i) { 5640 int idx = MaskVals[i]; 5641 if (idx < 0) { 5642 MaskV.push_back(-1); 5643 InOrder.set(i); 5644 } else if ((idx / 4) == BestHiQuad) { 5645 MaskV.push_back((idx & 3) + 4); 5646 InOrder.set(i); 5647 } else { 5648 MaskV.push_back(-1); 5649 } 5650 } 5651 NewV = DAG.getVectorShuffle(MVT::v8i16, dl, NewV, DAG.getUNDEF(MVT::v8i16), 5652 &MaskV[0]); 5653 5654 if (NewV.getOpcode() == ISD::VECTOR_SHUFFLE && 5655 (Subtarget->hasSSSE3() || Subtarget->hasAVX())) 5656 NewV = getTargetShuffleNode(X86ISD::PSHUFHW, dl, MVT::v8i16, 5657 NewV.getOperand(0), 5658 X86::getShufflePSHUFHWImmediate(NewV.getNode()), 5659 DAG); 5660 } 5661 5662 // In case BestHi & BestLo were both -1, which means each quadword has a word 5663 // from each of the four input quadwords, calculate the InOrder bitvector now 5664 // before falling through to the insert/extract cleanup. 5665 if (BestLoQuad == -1 && BestHiQuad == -1) { 5666 NewV = V1; 5667 for (int i = 0; i != 8; ++i) 5668 if (MaskVals[i] < 0 || MaskVals[i] == i) 5669 InOrder.set(i); 5670 } 5671 5672 // The other elements are put in the right place using pextrw and pinsrw. 5673 for (unsigned i = 0; i != 8; ++i) { 5674 if (InOrder[i]) 5675 continue; 5676 int EltIdx = MaskVals[i]; 5677 if (EltIdx < 0) 5678 continue; 5679 SDValue ExtOp = (EltIdx < 8) 5680 ? DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V1, 5681 DAG.getIntPtrConstant(EltIdx)) 5682 : DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, V2, 5683 DAG.getIntPtrConstant(EltIdx - 8)); 5684 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, ExtOp, 5685 DAG.getIntPtrConstant(i)); 5686 } 5687 return NewV; 5688 } 5689 5690 // v16i8 shuffles - Prefer shuffles in the following order: 5691 // 1. [ssse3] 1 x pshufb 5692 // 2. [ssse3] 2 x pshufb + 1 x por 5693 // 3. [all] v8i16 shuffle + N x pextrw + rotate + pinsrw 5694 static 5695 SDValue LowerVECTOR_SHUFFLEv16i8(ShuffleVectorSDNode *SVOp, 5696 SelectionDAG &DAG, 5697 const X86TargetLowering &TLI) { 5698 SDValue V1 = SVOp->getOperand(0); 5699 SDValue V2 = SVOp->getOperand(1); 5700 DebugLoc dl = SVOp->getDebugLoc(); 5701 SmallVector<int, 16> MaskVals; 5702 SVOp->getMask(MaskVals); 5703 5704 // If we have SSSE3, case 1 is generated when all result bytes come from 5705 // one of the inputs. Otherwise, case 2 is generated. If no SSSE3 is 5706 // present, fall back to case 3. 5707 // FIXME: kill V2Only once shuffles are canonizalized by getNode. 5708 bool V1Only = true; 5709 bool V2Only = true; 5710 for (unsigned i = 0; i < 16; ++i) { 5711 int EltIdx = MaskVals[i]; 5712 if (EltIdx < 0) 5713 continue; 5714 if (EltIdx < 16) 5715 V2Only = false; 5716 else 5717 V1Only = false; 5718 } 5719 5720 // If SSSE3, use 1 pshufb instruction per vector with elements in the result. 5721 if (TLI.getSubtarget()->hasSSSE3() || TLI.getSubtarget()->hasAVX()) { 5722 SmallVector<SDValue,16> pshufbMask; 5723 5724 // If all result elements are from one input vector, then only translate 5725 // undef mask values to 0x80 (zero out result) in the pshufb mask. 5726 // 5727 // Otherwise, we have elements from both input vectors, and must zero out 5728 // elements that come from V2 in the first mask, and V1 in the second mask 5729 // so that we can OR them together. 5730 bool TwoInputs = !(V1Only || V2Only); 5731 for (unsigned i = 0; i != 16; ++i) { 5732 int EltIdx = MaskVals[i]; 5733 if (EltIdx < 0 || (TwoInputs && EltIdx >= 16)) { 5734 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5735 continue; 5736 } 5737 pshufbMask.push_back(DAG.getConstant(EltIdx, MVT::i8)); 5738 } 5739 // If all the elements are from V2, assign it to V1 and return after 5740 // building the first pshufb. 5741 if (V2Only) 5742 V1 = V2; 5743 V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1, 5744 DAG.getNode(ISD::BUILD_VECTOR, dl, 5745 MVT::v16i8, &pshufbMask[0], 16)); 5746 if (!TwoInputs) 5747 return V1; 5748 5749 // Calculate the shuffle mask for the second input, shuffle it, and 5750 // OR it with the first shuffled input. 5751 pshufbMask.clear(); 5752 for (unsigned i = 0; i != 16; ++i) { 5753 int EltIdx = MaskVals[i]; 5754 if (EltIdx < 16) { 5755 pshufbMask.push_back(DAG.getConstant(0x80, MVT::i8)); 5756 continue; 5757 } 5758 pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8)); 5759 } 5760 V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2, 5761 DAG.getNode(ISD::BUILD_VECTOR, dl, 5762 MVT::v16i8, &pshufbMask[0], 16)); 5763 return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2); 5764 } 5765 5766 // No SSSE3 - Calculate in place words and then fix all out of place words 5767 // With 0-16 extracts & inserts. Worst case is 16 bytes out of order from 5768 // the 16 different words that comprise the two doublequadword input vectors. 5769 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V1); 5770 V2 = DAG.getNode(ISD::BITCAST, dl, MVT::v8i16, V2); 5771 SDValue NewV = V2Only ? V2 : V1; 5772 for (int i = 0; i != 8; ++i) { 5773 int Elt0 = MaskVals[i*2]; 5774 int Elt1 = MaskVals[i*2+1]; 5775 5776 // This word of the result is all undef, skip it. 5777 if (Elt0 < 0 && Elt1 < 0) 5778 continue; 5779 5780 // This word of the result is already in the correct place, skip it. 5781 if (V1Only && (Elt0 == i*2) && (Elt1 == i*2+1)) 5782 continue; 5783 if (V2Only && (Elt0 == i*2+16) && (Elt1 == i*2+17)) 5784 continue; 5785 5786 SDValue Elt0Src = Elt0 < 16 ? V1 : V2; 5787 SDValue Elt1Src = Elt1 < 16 ? V1 : V2; 5788 SDValue InsElt; 5789 5790 // If Elt0 and Elt1 are defined, are consecutive, and can be load 5791 // using a single extract together, load it and store it. 5792 if ((Elt0 >= 0) && ((Elt0 + 1) == Elt1) && ((Elt0 & 1) == 0)) { 5793 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5794 DAG.getIntPtrConstant(Elt1 / 2)); 5795 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5796 DAG.getIntPtrConstant(i)); 5797 continue; 5798 } 5799 5800 // If Elt1 is defined, extract it from the appropriate source. If the 5801 // source byte is not also odd, shift the extracted word left 8 bits 5802 // otherwise clear the bottom 8 bits if we need to do an or. 5803 if (Elt1 >= 0) { 5804 InsElt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, Elt1Src, 5805 DAG.getIntPtrConstant(Elt1 / 2)); 5806 if ((Elt1 & 1) == 0) 5807 InsElt = DAG.getNode(ISD::SHL, dl, MVT::i16, InsElt, 5808 DAG.getConstant(8, 5809 TLI.getShiftAmountTy(InsElt.getValueType()))); 5810 else if (Elt0 >= 0) 5811 InsElt = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt, 5812 DAG.getConstant(0xFF00, MVT::i16)); 5813 } 5814 // If Elt0 is defined, extract it from the appropriate source. If the 5815 // source byte is not also even, shift the extracted word right 8 bits. If 5816 // Elt1 was also defined, OR the extracted values together before 5817 // inserting them in the result. 5818 if (Elt0 >= 0) { 5819 SDValue InsElt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i16, 5820 Elt0Src, DAG.getIntPtrConstant(Elt0 / 2)); 5821 if ((Elt0 & 1) != 0) 5822 InsElt0 = DAG.getNode(ISD::SRL, dl, MVT::i16, InsElt0, 5823 DAG.getConstant(8, 5824 TLI.getShiftAmountTy(InsElt0.getValueType()))); 5825 else if (Elt1 >= 0) 5826 InsElt0 = DAG.getNode(ISD::AND, dl, MVT::i16, InsElt0, 5827 DAG.getConstant(0x00FF, MVT::i16)); 5828 InsElt = Elt1 >= 0 ? DAG.getNode(ISD::OR, dl, MVT::i16, InsElt, InsElt0) 5829 : InsElt0; 5830 } 5831 NewV = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, MVT::v8i16, NewV, InsElt, 5832 DAG.getIntPtrConstant(i)); 5833 } 5834 return DAG.getNode(ISD::BITCAST, dl, MVT::v16i8, NewV); 5835 } 5836 5837 /// RewriteAsNarrowerShuffle - Try rewriting v8i16 and v16i8 shuffles as 4 wide 5838 /// ones, or rewriting v4i32 / v4f32 as 2 wide ones if possible. This can be 5839 /// done when every pair / quad of shuffle mask elements point to elements in 5840 /// the right sequence. e.g. 5841 /// vector_shuffle X, Y, <2, 3, | 10, 11, | 0, 1, | 14, 15> 5842 static 5843 SDValue RewriteAsNarrowerShuffle(ShuffleVectorSDNode *SVOp, 5844 SelectionDAG &DAG, DebugLoc dl) { 5845 EVT VT = SVOp->getValueType(0); 5846 SDValue V1 = SVOp->getOperand(0); 5847 SDValue V2 = SVOp->getOperand(1); 5848 unsigned NumElems = VT.getVectorNumElements(); 5849 unsigned NewWidth = (NumElems == 4) ? 2 : 4; 5850 EVT NewVT; 5851 switch (VT.getSimpleVT().SimpleTy) { 5852 default: assert(false && "Unexpected!"); 5853 case MVT::v4f32: NewVT = MVT::v2f64; break; 5854 case MVT::v4i32: NewVT = MVT::v2i64; break; 5855 case MVT::v8i16: NewVT = MVT::v4i32; break; 5856 case MVT::v16i8: NewVT = MVT::v4i32; break; 5857 } 5858 5859 int Scale = NumElems / NewWidth; 5860 SmallVector<int, 8> MaskVec; 5861 for (unsigned i = 0; i < NumElems; i += Scale) { 5862 int StartIdx = -1; 5863 for (int j = 0; j < Scale; ++j) { 5864 int EltIdx = SVOp->getMaskElt(i+j); 5865 if (EltIdx < 0) 5866 continue; 5867 if (StartIdx == -1) 5868 StartIdx = EltIdx - (EltIdx % Scale); 5869 if (EltIdx != StartIdx + j) 5870 return SDValue(); 5871 } 5872 if (StartIdx == -1) 5873 MaskVec.push_back(-1); 5874 else 5875 MaskVec.push_back(StartIdx / Scale); 5876 } 5877 5878 V1 = DAG.getNode(ISD::BITCAST, dl, NewVT, V1); 5879 V2 = DAG.getNode(ISD::BITCAST, dl, NewVT, V2); 5880 return DAG.getVectorShuffle(NewVT, dl, V1, V2, &MaskVec[0]); 5881 } 5882 5883 /// getVZextMovL - Return a zero-extending vector move low node. 5884 /// 5885 static SDValue getVZextMovL(EVT VT, EVT OpVT, 5886 SDValue SrcOp, SelectionDAG &DAG, 5887 const X86Subtarget *Subtarget, DebugLoc dl) { 5888 if (VT == MVT::v2f64 || VT == MVT::v4f32) { 5889 LoadSDNode *LD = NULL; 5890 if (!isScalarLoadToVector(SrcOp.getNode(), &LD)) 5891 LD = dyn_cast<LoadSDNode>(SrcOp); 5892 if (!LD) { 5893 // movssrr and movsdrr do not clear top bits. Try to use movd, movq 5894 // instead. 5895 MVT ExtVT = (OpVT == MVT::v2f64) ? MVT::i64 : MVT::i32; 5896 if ((ExtVT != MVT::i64 || Subtarget->is64Bit()) && 5897 SrcOp.getOpcode() == ISD::SCALAR_TO_VECTOR && 5898 SrcOp.getOperand(0).getOpcode() == ISD::BITCAST && 5899 SrcOp.getOperand(0).getOperand(0).getValueType() == ExtVT) { 5900 // PR2108 5901 OpVT = (OpVT == MVT::v2f64) ? MVT::v2i64 : MVT::v4i32; 5902 return DAG.getNode(ISD::BITCAST, dl, VT, 5903 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5904 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 5905 OpVT, 5906 SrcOp.getOperand(0) 5907 .getOperand(0)))); 5908 } 5909 } 5910 } 5911 5912 return DAG.getNode(ISD::BITCAST, dl, VT, 5913 DAG.getNode(X86ISD::VZEXT_MOVL, dl, OpVT, 5914 DAG.getNode(ISD::BITCAST, dl, 5915 OpVT, SrcOp))); 5916 } 5917 5918 /// areShuffleHalvesWithinDisjointLanes - Check whether each half of a vector 5919 /// shuffle node referes to only one lane in the sources. 5920 static bool areShuffleHalvesWithinDisjointLanes(ShuffleVectorSDNode *SVOp) { 5921 EVT VT = SVOp->getValueType(0); 5922 int NumElems = VT.getVectorNumElements(); 5923 int HalfSize = NumElems/2; 5924 SmallVector<int, 16> M; 5925 SVOp->getMask(M); 5926 bool MatchA = false, MatchB = false; 5927 5928 for (int l = 0; l < NumElems*2; l += HalfSize) { 5929 if (isUndefOrInRange(M, 0, HalfSize, l, l+HalfSize)) { 5930 MatchA = true; 5931 break; 5932 } 5933 } 5934 5935 for (int l = 0; l < NumElems*2; l += HalfSize) { 5936 if (isUndefOrInRange(M, HalfSize, HalfSize, l, l+HalfSize)) { 5937 MatchB = true; 5938 break; 5939 } 5940 } 5941 5942 return MatchA && MatchB; 5943 } 5944 5945 /// LowerVECTOR_SHUFFLE_256 - Handle all 256-bit wide vectors shuffles 5946 /// which could not be matched by any known target speficic shuffle 5947 static SDValue 5948 LowerVECTOR_SHUFFLE_256(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 5949 if (areShuffleHalvesWithinDisjointLanes(SVOp)) { 5950 // If each half of a vector shuffle node referes to only one lane in the 5951 // source vectors, extract each used 128-bit lane and shuffle them using 5952 // 128-bit shuffles. Then, concatenate the results. Otherwise leave 5953 // the work to the legalizer. 5954 DebugLoc dl = SVOp->getDebugLoc(); 5955 EVT VT = SVOp->getValueType(0); 5956 int NumElems = VT.getVectorNumElements(); 5957 int HalfSize = NumElems/2; 5958 5959 // Extract the reference for each half 5960 int FstVecExtractIdx = 0, SndVecExtractIdx = 0; 5961 int FstVecOpNum = 0, SndVecOpNum = 0; 5962 for (int i = 0; i < HalfSize; ++i) { 5963 int Elt = SVOp->getMaskElt(i); 5964 if (SVOp->getMaskElt(i) < 0) 5965 continue; 5966 FstVecOpNum = Elt/NumElems; 5967 FstVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5968 break; 5969 } 5970 for (int i = HalfSize; i < NumElems; ++i) { 5971 int Elt = SVOp->getMaskElt(i); 5972 if (SVOp->getMaskElt(i) < 0) 5973 continue; 5974 SndVecOpNum = Elt/NumElems; 5975 SndVecExtractIdx = Elt % NumElems < HalfSize ? 0 : HalfSize; 5976 break; 5977 } 5978 5979 // Extract the subvectors 5980 SDValue V1 = Extract128BitVector(SVOp->getOperand(FstVecOpNum), 5981 DAG.getConstant(FstVecExtractIdx, MVT::i32), DAG, dl); 5982 SDValue V2 = Extract128BitVector(SVOp->getOperand(SndVecOpNum), 5983 DAG.getConstant(SndVecExtractIdx, MVT::i32), DAG, dl); 5984 5985 // Generate 128-bit shuffles 5986 SmallVector<int, 16> MaskV1, MaskV2; 5987 for (int i = 0; i < HalfSize; ++i) { 5988 int Elt = SVOp->getMaskElt(i); 5989 MaskV1.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5990 } 5991 for (int i = HalfSize; i < NumElems; ++i) { 5992 int Elt = SVOp->getMaskElt(i); 5993 MaskV2.push_back(Elt < 0 ? Elt : Elt % HalfSize); 5994 } 5995 5996 EVT NVT = V1.getValueType(); 5997 V1 = DAG.getVectorShuffle(NVT, dl, V1, DAG.getUNDEF(NVT), &MaskV1[0]); 5998 V2 = DAG.getVectorShuffle(NVT, dl, V2, DAG.getUNDEF(NVT), &MaskV2[0]); 5999 6000 // Concatenate the result back 6001 SDValue V = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), V1, 6002 DAG.getConstant(0, MVT::i32), DAG, dl); 6003 return Insert128BitVector(V, V2, DAG.getConstant(NumElems/2, MVT::i32), 6004 DAG, dl); 6005 } 6006 6007 return SDValue(); 6008 } 6009 6010 /// LowerVECTOR_SHUFFLE_128v4 - Handle all 128-bit wide vectors with 6011 /// 4 elements, and match them with several different shuffle types. 6012 static SDValue 6013 LowerVECTOR_SHUFFLE_128v4(ShuffleVectorSDNode *SVOp, SelectionDAG &DAG) { 6014 SDValue V1 = SVOp->getOperand(0); 6015 SDValue V2 = SVOp->getOperand(1); 6016 DebugLoc dl = SVOp->getDebugLoc(); 6017 EVT VT = SVOp->getValueType(0); 6018 6019 assert(VT.getSizeInBits() == 128 && "Unsupported vector size"); 6020 6021 SmallVector<std::pair<int, int>, 8> Locs; 6022 Locs.resize(4); 6023 SmallVector<int, 8> Mask1(4U, -1); 6024 SmallVector<int, 8> PermMask; 6025 SVOp->getMask(PermMask); 6026 6027 unsigned NumHi = 0; 6028 unsigned NumLo = 0; 6029 for (unsigned i = 0; i != 4; ++i) { 6030 int Idx = PermMask[i]; 6031 if (Idx < 0) { 6032 Locs[i] = std::make_pair(-1, -1); 6033 } else { 6034 assert(Idx < 8 && "Invalid VECTOR_SHUFFLE index!"); 6035 if (Idx < 4) { 6036 Locs[i] = std::make_pair(0, NumLo); 6037 Mask1[NumLo] = Idx; 6038 NumLo++; 6039 } else { 6040 Locs[i] = std::make_pair(1, NumHi); 6041 if (2+NumHi < 4) 6042 Mask1[2+NumHi] = Idx; 6043 NumHi++; 6044 } 6045 } 6046 } 6047 6048 if (NumLo <= 2 && NumHi <= 2) { 6049 // If no more than two elements come from either vector. This can be 6050 // implemented with two shuffles. First shuffle gather the elements. 6051 // The second shuffle, which takes the first shuffle as both of its 6052 // vector operands, put the elements into the right order. 6053 V1 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6054 6055 SmallVector<int, 8> Mask2(4U, -1); 6056 6057 for (unsigned i = 0; i != 4; ++i) { 6058 if (Locs[i].first == -1) 6059 continue; 6060 else { 6061 unsigned Idx = (i < 2) ? 0 : 4; 6062 Idx += Locs[i].first * 2 + Locs[i].second; 6063 Mask2[i] = Idx; 6064 } 6065 } 6066 6067 return DAG.getVectorShuffle(VT, dl, V1, V1, &Mask2[0]); 6068 } else if (NumLo == 3 || NumHi == 3) { 6069 // Otherwise, we must have three elements from one vector, call it X, and 6070 // one element from the other, call it Y. First, use a shufps to build an 6071 // intermediate vector with the one element from Y and the element from X 6072 // that will be in the same half in the final destination (the indexes don't 6073 // matter). Then, use a shufps to build the final vector, taking the half 6074 // containing the element from Y from the intermediate, and the other half 6075 // from X. 6076 if (NumHi == 3) { 6077 // Normalize it so the 3 elements come from V1. 6078 CommuteVectorShuffleMask(PermMask, VT); 6079 std::swap(V1, V2); 6080 } 6081 6082 // Find the element from V2. 6083 unsigned HiIndex; 6084 for (HiIndex = 0; HiIndex < 3; ++HiIndex) { 6085 int Val = PermMask[HiIndex]; 6086 if (Val < 0) 6087 continue; 6088 if (Val >= 4) 6089 break; 6090 } 6091 6092 Mask1[0] = PermMask[HiIndex]; 6093 Mask1[1] = -1; 6094 Mask1[2] = PermMask[HiIndex^1]; 6095 Mask1[3] = -1; 6096 V2 = DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6097 6098 if (HiIndex >= 2) { 6099 Mask1[0] = PermMask[0]; 6100 Mask1[1] = PermMask[1]; 6101 Mask1[2] = HiIndex & 1 ? 6 : 4; 6102 Mask1[3] = HiIndex & 1 ? 4 : 6; 6103 return DAG.getVectorShuffle(VT, dl, V1, V2, &Mask1[0]); 6104 } else { 6105 Mask1[0] = HiIndex & 1 ? 2 : 0; 6106 Mask1[1] = HiIndex & 1 ? 0 : 2; 6107 Mask1[2] = PermMask[2]; 6108 Mask1[3] = PermMask[3]; 6109 if (Mask1[2] >= 0) 6110 Mask1[2] += 4; 6111 if (Mask1[3] >= 0) 6112 Mask1[3] += 4; 6113 return DAG.getVectorShuffle(VT, dl, V2, V1, &Mask1[0]); 6114 } 6115 } 6116 6117 // Break it into (shuffle shuffle_hi, shuffle_lo). 6118 Locs.clear(); 6119 Locs.resize(4); 6120 SmallVector<int,8> LoMask(4U, -1); 6121 SmallVector<int,8> HiMask(4U, -1); 6122 6123 SmallVector<int,8> *MaskPtr = &LoMask; 6124 unsigned MaskIdx = 0; 6125 unsigned LoIdx = 0; 6126 unsigned HiIdx = 2; 6127 for (unsigned i = 0; i != 4; ++i) { 6128 if (i == 2) { 6129 MaskPtr = &HiMask; 6130 MaskIdx = 1; 6131 LoIdx = 0; 6132 HiIdx = 2; 6133 } 6134 int Idx = PermMask[i]; 6135 if (Idx < 0) { 6136 Locs[i] = std::make_pair(-1, -1); 6137 } else if (Idx < 4) { 6138 Locs[i] = std::make_pair(MaskIdx, LoIdx); 6139 (*MaskPtr)[LoIdx] = Idx; 6140 LoIdx++; 6141 } else { 6142 Locs[i] = std::make_pair(MaskIdx, HiIdx); 6143 (*MaskPtr)[HiIdx] = Idx; 6144 HiIdx++; 6145 } 6146 } 6147 6148 SDValue LoShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &LoMask[0]); 6149 SDValue HiShuffle = DAG.getVectorShuffle(VT, dl, V1, V2, &HiMask[0]); 6150 SmallVector<int, 8> MaskOps; 6151 for (unsigned i = 0; i != 4; ++i) { 6152 if (Locs[i].first == -1) { 6153 MaskOps.push_back(-1); 6154 } else { 6155 unsigned Idx = Locs[i].first * 4 + Locs[i].second; 6156 MaskOps.push_back(Idx); 6157 } 6158 } 6159 return DAG.getVectorShuffle(VT, dl, LoShuffle, HiShuffle, &MaskOps[0]); 6160 } 6161 6162 static bool MayFoldVectorLoad(SDValue V) { 6163 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6164 V = V.getOperand(0); 6165 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6166 V = V.getOperand(0); 6167 if (MayFoldLoad(V)) 6168 return true; 6169 return false; 6170 } 6171 6172 // FIXME: the version above should always be used. Since there's 6173 // a bug where several vector shuffles can't be folded because the 6174 // DAG is not updated during lowering and a node claims to have two 6175 // uses while it only has one, use this version, and let isel match 6176 // another instruction if the load really happens to have more than 6177 // one use. Remove this version after this bug get fixed. 6178 // rdar://8434668, PR8156 6179 static bool RelaxedMayFoldVectorLoad(SDValue V) { 6180 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6181 V = V.getOperand(0); 6182 if (V.hasOneUse() && V.getOpcode() == ISD::SCALAR_TO_VECTOR) 6183 V = V.getOperand(0); 6184 if (ISD::isNormalLoad(V.getNode())) 6185 return true; 6186 return false; 6187 } 6188 6189 /// CanFoldShuffleIntoVExtract - Check if the current shuffle is used by 6190 /// a vector extract, and if both can be later optimized into a single load. 6191 /// This is done in visitEXTRACT_VECTOR_ELT and the conditions are checked 6192 /// here because otherwise a target specific shuffle node is going to be 6193 /// emitted for this shuffle, and the optimization not done. 6194 /// FIXME: This is probably not the best approach, but fix the problem 6195 /// until the right path is decided. 6196 static 6197 bool CanXFormVExtractWithShuffleIntoLoad(SDValue V, SelectionDAG &DAG, 6198 const TargetLowering &TLI) { 6199 EVT VT = V.getValueType(); 6200 ShuffleVectorSDNode *SVOp = dyn_cast<ShuffleVectorSDNode>(V); 6201 6202 // Be sure that the vector shuffle is present in a pattern like this: 6203 // (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), c) -> (f32 load $addr) 6204 if (!V.hasOneUse()) 6205 return false; 6206 6207 SDNode *N = *V.getNode()->use_begin(); 6208 if (N->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 6209 return false; 6210 6211 SDValue EltNo = N->getOperand(1); 6212 if (!isa<ConstantSDNode>(EltNo)) 6213 return false; 6214 6215 // If the bit convert changed the number of elements, it is unsafe 6216 // to examine the mask. 6217 bool HasShuffleIntoBitcast = false; 6218 if (V.getOpcode() == ISD::BITCAST) { 6219 EVT SrcVT = V.getOperand(0).getValueType(); 6220 if (SrcVT.getVectorNumElements() != VT.getVectorNumElements()) 6221 return false; 6222 V = V.getOperand(0); 6223 HasShuffleIntoBitcast = true; 6224 } 6225 6226 // Select the input vector, guarding against out of range extract vector. 6227 unsigned NumElems = VT.getVectorNumElements(); 6228 unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue(); 6229 int Idx = (Elt > NumElems) ? -1 : SVOp->getMaskElt(Elt); 6230 V = (Idx < (int)NumElems) ? V.getOperand(0) : V.getOperand(1); 6231 6232 // Skip one more bit_convert if necessary 6233 if (V.getOpcode() == ISD::BITCAST) 6234 V = V.getOperand(0); 6235 6236 if (ISD::isNormalLoad(V.getNode())) { 6237 // Is the original load suitable? 6238 LoadSDNode *LN0 = cast<LoadSDNode>(V); 6239 6240 // FIXME: avoid the multi-use bug that is preventing lots of 6241 // of foldings to be detected, this is still wrong of course, but 6242 // give the temporary desired behavior, and if it happens that 6243 // the load has real more uses, during isel it will not fold, and 6244 // will generate poor code. 6245 if (!LN0 || LN0->isVolatile()) // || !LN0->hasOneUse() 6246 return false; 6247 6248 if (!HasShuffleIntoBitcast) 6249 return true; 6250 6251 // If there's a bitcast before the shuffle, check if the load type and 6252 // alignment is valid. 6253 unsigned Align = LN0->getAlignment(); 6254 unsigned NewAlign = 6255 TLI.getTargetData()->getABITypeAlignment( 6256 VT.getTypeForEVT(*DAG.getContext())); 6257 6258 if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, VT)) 6259 return false; 6260 } 6261 6262 return true; 6263 } 6264 6265 static 6266 SDValue getMOVDDup(SDValue &Op, DebugLoc &dl, SDValue V1, SelectionDAG &DAG) { 6267 EVT VT = Op.getValueType(); 6268 6269 // Canonizalize to v2f64. 6270 V1 = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, V1); 6271 return DAG.getNode(ISD::BITCAST, dl, VT, 6272 getTargetShuffleNode(X86ISD::MOVDDUP, dl, MVT::v2f64, 6273 V1, DAG)); 6274 } 6275 6276 static 6277 SDValue getMOVLowToHigh(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, 6278 bool HasXMMInt) { 6279 SDValue V1 = Op.getOperand(0); 6280 SDValue V2 = Op.getOperand(1); 6281 EVT VT = Op.getValueType(); 6282 6283 assert(VT != MVT::v2i64 && "unsupported shuffle type"); 6284 6285 if (HasXMMInt && VT == MVT::v2f64) 6286 return getTargetShuffleNode(X86ISD::MOVLHPD, dl, VT, V1, V2, DAG); 6287 6288 // v4f32 or v4i32: canonizalized to v4f32 (which is legal for SSE1) 6289 return DAG.getNode(ISD::BITCAST, dl, VT, 6290 getTargetShuffleNode(X86ISD::MOVLHPS, dl, MVT::v4f32, 6291 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V1), 6292 DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, V2), DAG)); 6293 } 6294 6295 static 6296 SDValue getMOVHighToLow(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG) { 6297 SDValue V1 = Op.getOperand(0); 6298 SDValue V2 = Op.getOperand(1); 6299 EVT VT = Op.getValueType(); 6300 6301 assert((VT == MVT::v4i32 || VT == MVT::v4f32) && 6302 "unsupported shuffle type"); 6303 6304 if (V2.getOpcode() == ISD::UNDEF) 6305 V2 = V1; 6306 6307 // v4i32 or v4f32 6308 return getTargetShuffleNode(X86ISD::MOVHLPS, dl, VT, V1, V2, DAG); 6309 } 6310 6311 static inline unsigned getSHUFPOpcode(EVT VT) { 6312 switch(VT.getSimpleVT().SimpleTy) { 6313 case MVT::v8i32: // Use fp unit for int unpack. 6314 case MVT::v8f32: 6315 case MVT::v4i32: // Use fp unit for int unpack. 6316 case MVT::v4f32: return X86ISD::SHUFPS; 6317 case MVT::v4i64: // Use fp unit for int unpack. 6318 case MVT::v4f64: 6319 case MVT::v2i64: // Use fp unit for int unpack. 6320 case MVT::v2f64: return X86ISD::SHUFPD; 6321 default: 6322 llvm_unreachable("Unknown type for shufp*"); 6323 } 6324 return 0; 6325 } 6326 6327 static 6328 SDValue getMOVLP(SDValue &Op, DebugLoc &dl, SelectionDAG &DAG, bool HasXMMInt) { 6329 SDValue V1 = Op.getOperand(0); 6330 SDValue V2 = Op.getOperand(1); 6331 EVT VT = Op.getValueType(); 6332 unsigned NumElems = VT.getVectorNumElements(); 6333 6334 // Use MOVLPS and MOVLPD in case V1 or V2 are loads. During isel, the second 6335 // operand of these instructions is only memory, so check if there's a 6336 // potencial load folding here, otherwise use SHUFPS or MOVSD to match the 6337 // same masks. 6338 bool CanFoldLoad = false; 6339 6340 // Trivial case, when V2 comes from a load. 6341 if (MayFoldVectorLoad(V2)) 6342 CanFoldLoad = true; 6343 6344 // When V1 is a load, it can be folded later into a store in isel, example: 6345 // (store (v4f32 (X86Movlps (load addr:$src1), VR128:$src2)), addr:$src1) 6346 // turns into: 6347 // (MOVLPSmr addr:$src1, VR128:$src2) 6348 // So, recognize this potential and also use MOVLPS or MOVLPD 6349 if (MayFoldVectorLoad(V1) && MayFoldIntoStore(Op)) 6350 CanFoldLoad = true; 6351 6352 // Both of them can't be memory operations though. 6353 if (MayFoldVectorLoad(V1) && MayFoldVectorLoad(V2)) 6354 CanFoldLoad = false; 6355 6356 if (CanFoldLoad) { 6357 if (HasXMMInt && NumElems == 2) 6358 return getTargetShuffleNode(X86ISD::MOVLPD, dl, VT, V1, V2, DAG); 6359 6360 if (NumElems == 4) 6361 return getTargetShuffleNode(X86ISD::MOVLPS, dl, VT, V1, V2, DAG); 6362 } 6363 6364 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6365 // movl and movlp will both match v2i64, but v2i64 is never matched by 6366 // movl earlier because we make it strict to avoid messing with the movlp load 6367 // folding logic (see the code above getMOVLP call). Match it here then, 6368 // this is horrible, but will stay like this until we move all shuffle 6369 // matching to x86 specific nodes. Note that for the 1st condition all 6370 // types are matched with movsd. 6371 if (HasXMMInt) { 6372 // FIXME: isMOVLMask should be checked and matched before getMOVLP, 6373 // as to remove this logic from here, as much as possible 6374 if (NumElems == 2 || !X86::isMOVLMask(SVOp)) 6375 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6376 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6377 } 6378 6379 assert(VT != MVT::v4i32 && "unsupported shuffle type"); 6380 6381 // Invert the operand order and use SHUFPS to match it. 6382 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V2, V1, 6383 X86::getShuffleSHUFImmediate(SVOp), DAG); 6384 } 6385 6386 static inline unsigned getUNPCKLOpcode(EVT VT) { 6387 switch(VT.getSimpleVT().SimpleTy) { 6388 case MVT::v4i32: return X86ISD::PUNPCKLDQ; 6389 case MVT::v2i64: return X86ISD::PUNPCKLQDQ; 6390 case MVT::v4f32: return X86ISD::UNPCKLPS; 6391 case MVT::v2f64: return X86ISD::UNPCKLPD; 6392 case MVT::v8i32: // Use fp unit for int unpack. 6393 case MVT::v8f32: return X86ISD::VUNPCKLPSY; 6394 case MVT::v4i64: // Use fp unit for int unpack. 6395 case MVT::v4f64: return X86ISD::VUNPCKLPDY; 6396 case MVT::v16i8: return X86ISD::PUNPCKLBW; 6397 case MVT::v8i16: return X86ISD::PUNPCKLWD; 6398 default: 6399 llvm_unreachable("Unknown type for unpckl"); 6400 } 6401 return 0; 6402 } 6403 6404 static inline unsigned getUNPCKHOpcode(EVT VT) { 6405 switch(VT.getSimpleVT().SimpleTy) { 6406 case MVT::v4i32: return X86ISD::PUNPCKHDQ; 6407 case MVT::v2i64: return X86ISD::PUNPCKHQDQ; 6408 case MVT::v4f32: return X86ISD::UNPCKHPS; 6409 case MVT::v2f64: return X86ISD::UNPCKHPD; 6410 case MVT::v8i32: // Use fp unit for int unpack. 6411 case MVT::v8f32: return X86ISD::VUNPCKHPSY; 6412 case MVT::v4i64: // Use fp unit for int unpack. 6413 case MVT::v4f64: return X86ISD::VUNPCKHPDY; 6414 case MVT::v16i8: return X86ISD::PUNPCKHBW; 6415 case MVT::v8i16: return X86ISD::PUNPCKHWD; 6416 default: 6417 llvm_unreachable("Unknown type for unpckh"); 6418 } 6419 return 0; 6420 } 6421 6422 static inline unsigned getVPERMILOpcode(EVT VT) { 6423 switch(VT.getSimpleVT().SimpleTy) { 6424 case MVT::v4i32: 6425 case MVT::v4f32: return X86ISD::VPERMILPS; 6426 case MVT::v2i64: 6427 case MVT::v2f64: return X86ISD::VPERMILPD; 6428 case MVT::v8i32: 6429 case MVT::v8f32: return X86ISD::VPERMILPSY; 6430 case MVT::v4i64: 6431 case MVT::v4f64: return X86ISD::VPERMILPDY; 6432 default: 6433 llvm_unreachable("Unknown type for vpermil"); 6434 } 6435 return 0; 6436 } 6437 6438 /// isVectorBroadcast - Check if the node chain is suitable to be xformed to 6439 /// a vbroadcast node. The nodes are suitable whenever we can fold a load coming 6440 /// from a 32 or 64 bit scalar. Update Op to the desired load to be folded. 6441 static bool isVectorBroadcast(SDValue &Op) { 6442 EVT VT = Op.getValueType(); 6443 bool Is256 = VT.getSizeInBits() == 256; 6444 6445 assert((VT.getSizeInBits() == 128 || Is256) && 6446 "Unsupported type for vbroadcast node"); 6447 6448 SDValue V = Op; 6449 if (V.hasOneUse() && V.getOpcode() == ISD::BITCAST) 6450 V = V.getOperand(0); 6451 6452 if (Is256 && !(V.hasOneUse() && 6453 V.getOpcode() == ISD::INSERT_SUBVECTOR && 6454 V.getOperand(0).getOpcode() == ISD::UNDEF)) 6455 return false; 6456 6457 if (Is256) 6458 V = V.getOperand(1); 6459 6460 if (!V.hasOneUse()) 6461 return false; 6462 6463 // Check the source scalar_to_vector type. 256-bit broadcasts are 6464 // supported for 32/64-bit sizes, while 128-bit ones are only supported 6465 // for 32-bit scalars. 6466 if (V.getOpcode() != ISD::SCALAR_TO_VECTOR) 6467 return false; 6468 6469 unsigned ScalarSize = V.getOperand(0).getValueType().getSizeInBits(); 6470 if (ScalarSize != 32 && ScalarSize != 64) 6471 return false; 6472 if (!Is256 && ScalarSize == 64) 6473 return false; 6474 6475 V = V.getOperand(0); 6476 if (!MayFoldLoad(V)) 6477 return false; 6478 6479 // Return the load node 6480 Op = V; 6481 return true; 6482 } 6483 6484 static 6485 SDValue NormalizeVectorShuffle(SDValue Op, SelectionDAG &DAG, 6486 const TargetLowering &TLI, 6487 const X86Subtarget *Subtarget) { 6488 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6489 EVT VT = Op.getValueType(); 6490 DebugLoc dl = Op.getDebugLoc(); 6491 SDValue V1 = Op.getOperand(0); 6492 SDValue V2 = Op.getOperand(1); 6493 6494 if (isZeroShuffle(SVOp)) 6495 return getZeroVector(VT, Subtarget->hasXMMInt(), DAG, dl); 6496 6497 // Handle splat operations 6498 if (SVOp->isSplat()) { 6499 unsigned NumElem = VT.getVectorNumElements(); 6500 int Size = VT.getSizeInBits(); 6501 // Special case, this is the only place now where it's allowed to return 6502 // a vector_shuffle operation without using a target specific node, because 6503 // *hopefully* it will be optimized away by the dag combiner. FIXME: should 6504 // this be moved to DAGCombine instead? 6505 if (NumElem <= 4 && CanXFormVExtractWithShuffleIntoLoad(Op, DAG, TLI)) 6506 return Op; 6507 6508 // Use vbroadcast whenever the splat comes from a foldable load 6509 if (Subtarget->hasAVX() && isVectorBroadcast(V1)) 6510 return DAG.getNode(X86ISD::VBROADCAST, dl, VT, V1); 6511 6512 // Handle splats by matching through known shuffle masks 6513 if ((Size == 128 && NumElem <= 4) || 6514 (Size == 256 && NumElem < 8)) 6515 return SDValue(); 6516 6517 // All remaning splats are promoted to target supported vector shuffles. 6518 return PromoteSplat(SVOp, DAG); 6519 } 6520 6521 // If the shuffle can be profitably rewritten as a narrower shuffle, then 6522 // do it! 6523 if (VT == MVT::v8i16 || VT == MVT::v16i8) { 6524 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6525 if (NewOp.getNode()) 6526 return DAG.getNode(ISD::BITCAST, dl, VT, NewOp); 6527 } else if ((VT == MVT::v4i32 || 6528 (VT == MVT::v4f32 && Subtarget->hasXMMInt()))) { 6529 // FIXME: Figure out a cleaner way to do this. 6530 // Try to make use of movq to zero out the top part. 6531 if (ISD::isBuildVectorAllZeros(V2.getNode())) { 6532 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6533 if (NewOp.getNode()) { 6534 if (isCommutedMOVL(cast<ShuffleVectorSDNode>(NewOp), true, false)) 6535 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(0), 6536 DAG, Subtarget, dl); 6537 } 6538 } else if (ISD::isBuildVectorAllZeros(V1.getNode())) { 6539 SDValue NewOp = RewriteAsNarrowerShuffle(SVOp, DAG, dl); 6540 if (NewOp.getNode() && X86::isMOVLMask(cast<ShuffleVectorSDNode>(NewOp))) 6541 return getVZextMovL(VT, NewOp.getValueType(), NewOp.getOperand(1), 6542 DAG, Subtarget, dl); 6543 } 6544 } 6545 return SDValue(); 6546 } 6547 6548 SDValue 6549 X86TargetLowering::LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const { 6550 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(Op); 6551 SDValue V1 = Op.getOperand(0); 6552 SDValue V2 = Op.getOperand(1); 6553 EVT VT = Op.getValueType(); 6554 DebugLoc dl = Op.getDebugLoc(); 6555 unsigned NumElems = VT.getVectorNumElements(); 6556 bool isMMX = VT.getSizeInBits() == 64; 6557 bool V1IsUndef = V1.getOpcode() == ISD::UNDEF; 6558 bool V2IsUndef = V2.getOpcode() == ISD::UNDEF; 6559 bool V1IsSplat = false; 6560 bool V2IsSplat = false; 6561 bool HasXMMInt = Subtarget->hasXMMInt(); 6562 MachineFunction &MF = DAG.getMachineFunction(); 6563 bool OptForSize = MF.getFunction()->hasFnAttr(Attribute::OptimizeForSize); 6564 6565 // Shuffle operations on MMX not supported. 6566 if (isMMX) 6567 return Op; 6568 6569 // Vector shuffle lowering takes 3 steps: 6570 // 6571 // 1) Normalize the input vectors. Here splats, zeroed vectors, profitable 6572 // narrowing and commutation of operands should be handled. 6573 // 2) Matching of shuffles with known shuffle masks to x86 target specific 6574 // shuffle nodes. 6575 // 3) Rewriting of unmatched masks into new generic shuffle operations, 6576 // so the shuffle can be broken into other shuffles and the legalizer can 6577 // try the lowering again. 6578 // 6579 // The general ideia is that no vector_shuffle operation should be left to 6580 // be matched during isel, all of them must be converted to a target specific 6581 // node here. 6582 6583 // Normalize the input vectors. Here splats, zeroed vectors, profitable 6584 // narrowing and commutation of operands should be handled. The actual code 6585 // doesn't include all of those, work in progress... 6586 SDValue NewOp = NormalizeVectorShuffle(Op, DAG, *this, Subtarget); 6587 if (NewOp.getNode()) 6588 return NewOp; 6589 6590 // NOTE: isPSHUFDMask can also match both masks below (unpckl_undef and 6591 // unpckh_undef). Only use pshufd if speed is more important than size. 6592 if (OptForSize && X86::isUNPCKL_v_undef_Mask(SVOp)) 6593 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6594 if (OptForSize && X86::isUNPCKH_v_undef_Mask(SVOp)) 6595 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6596 6597 if (X86::isMOVDDUPMask(SVOp) && 6598 (Subtarget->hasSSE3() || Subtarget->hasAVX()) && 6599 V2IsUndef && RelaxedMayFoldVectorLoad(V1)) 6600 return getMOVDDup(Op, dl, V1, DAG); 6601 6602 if (X86::isMOVHLPS_v_undef_Mask(SVOp)) 6603 return getMOVHighToLow(Op, dl, DAG); 6604 6605 // Use to match splats 6606 if (HasXMMInt && X86::isUNPCKHMask(SVOp) && V2IsUndef && 6607 (VT == MVT::v2f64 || VT == MVT::v2i64)) 6608 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6609 6610 if (X86::isPSHUFDMask(SVOp)) { 6611 // The actual implementation will match the mask in the if above and then 6612 // during isel it can match several different instructions, not only pshufd 6613 // as its name says, sad but true, emulate the behavior for now... 6614 if (X86::isMOVDDUPMask(SVOp) && ((VT == MVT::v4f32 || VT == MVT::v2i64))) 6615 return getTargetShuffleNode(X86ISD::MOVLHPS, dl, VT, V1, V1, DAG); 6616 6617 unsigned TargetMask = X86::getShuffleSHUFImmediate(SVOp); 6618 6619 if (HasXMMInt && (VT == MVT::v4f32 || VT == MVT::v4i32)) 6620 return getTargetShuffleNode(X86ISD::PSHUFD, dl, VT, V1, TargetMask, DAG); 6621 6622 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V1, 6623 TargetMask, DAG); 6624 } 6625 6626 // Check if this can be converted into a logical shift. 6627 bool isLeft = false; 6628 unsigned ShAmt = 0; 6629 SDValue ShVal; 6630 bool isShift = getSubtarget()->hasXMMInt() && 6631 isVectorShift(SVOp, DAG, isLeft, ShVal, ShAmt); 6632 if (isShift && ShVal.hasOneUse()) { 6633 // If the shifted value has multiple uses, it may be cheaper to use 6634 // v_set0 + movlhps or movhlps, etc. 6635 EVT EltVT = VT.getVectorElementType(); 6636 ShAmt *= EltVT.getSizeInBits(); 6637 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6638 } 6639 6640 if (X86::isMOVLMask(SVOp)) { 6641 if (V1IsUndef) 6642 return V2; 6643 if (ISD::isBuildVectorAllZeros(V1.getNode())) 6644 return getVZextMovL(VT, VT, V2, DAG, Subtarget, dl); 6645 if (!X86::isMOVLPMask(SVOp)) { 6646 if (HasXMMInt && (VT == MVT::v2i64 || VT == MVT::v2f64)) 6647 return getTargetShuffleNode(X86ISD::MOVSD, dl, VT, V1, V2, DAG); 6648 6649 if (VT == MVT::v4i32 || VT == MVT::v4f32) 6650 return getTargetShuffleNode(X86ISD::MOVSS, dl, VT, V1, V2, DAG); 6651 } 6652 } 6653 6654 // FIXME: fold these into legal mask. 6655 if (X86::isMOVLHPSMask(SVOp) && !X86::isUNPCKLMask(SVOp)) 6656 return getMOVLowToHigh(Op, dl, DAG, HasXMMInt); 6657 6658 if (X86::isMOVHLPSMask(SVOp)) 6659 return getMOVHighToLow(Op, dl, DAG); 6660 6661 if (X86::isMOVSHDUPMask(SVOp, Subtarget)) 6662 return getTargetShuffleNode(X86ISD::MOVSHDUP, dl, VT, V1, DAG); 6663 6664 if (X86::isMOVSLDUPMask(SVOp, Subtarget)) 6665 return getTargetShuffleNode(X86ISD::MOVSLDUP, dl, VT, V1, DAG); 6666 6667 if (X86::isMOVLPMask(SVOp)) 6668 return getMOVLP(Op, dl, DAG, HasXMMInt); 6669 6670 if (ShouldXformToMOVHLPS(SVOp) || 6671 ShouldXformToMOVLP(V1.getNode(), V2.getNode(), SVOp)) 6672 return CommuteVectorShuffle(SVOp, DAG); 6673 6674 if (isShift) { 6675 // No better options. Use a vshl / vsrl. 6676 EVT EltVT = VT.getVectorElementType(); 6677 ShAmt *= EltVT.getSizeInBits(); 6678 return getVShift(isLeft, VT, ShVal, ShAmt, DAG, *this, dl); 6679 } 6680 6681 bool Commuted = false; 6682 // FIXME: This should also accept a bitcast of a splat? Be careful, not 6683 // 1,1,1,1 -> v8i16 though. 6684 V1IsSplat = isSplatVector(V1.getNode()); 6685 V2IsSplat = isSplatVector(V2.getNode()); 6686 6687 // Canonicalize the splat or undef, if present, to be on the RHS. 6688 if ((V1IsSplat || V1IsUndef) && !(V2IsSplat || V2IsUndef)) { 6689 Op = CommuteVectorShuffle(SVOp, DAG); 6690 SVOp = cast<ShuffleVectorSDNode>(Op); 6691 V1 = SVOp->getOperand(0); 6692 V2 = SVOp->getOperand(1); 6693 std::swap(V1IsSplat, V2IsSplat); 6694 std::swap(V1IsUndef, V2IsUndef); 6695 Commuted = true; 6696 } 6697 6698 if (isCommutedMOVL(SVOp, V2IsSplat, V2IsUndef)) { 6699 // Shuffling low element of v1 into undef, just return v1. 6700 if (V2IsUndef) 6701 return V1; 6702 // If V2 is a splat, the mask may be malformed such as <4,3,3,3>, which 6703 // the instruction selector will not match, so get a canonical MOVL with 6704 // swapped operands to undo the commute. 6705 return getMOVL(DAG, dl, VT, V2, V1); 6706 } 6707 6708 if (X86::isUNPCKLMask(SVOp)) 6709 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V2, DAG); 6710 6711 if (X86::isUNPCKHMask(SVOp)) 6712 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V2, DAG); 6713 6714 if (V2IsSplat) { 6715 // Normalize mask so all entries that point to V2 points to its first 6716 // element then try to match unpck{h|l} again. If match, return a 6717 // new vector_shuffle with the corrected mask. 6718 SDValue NewMask = NormalizeMask(SVOp, DAG); 6719 ShuffleVectorSDNode *NSVOp = cast<ShuffleVectorSDNode>(NewMask); 6720 if (NSVOp != SVOp) { 6721 if (X86::isUNPCKLMask(NSVOp, true)) { 6722 return NewMask; 6723 } else if (X86::isUNPCKHMask(NSVOp, true)) { 6724 return NewMask; 6725 } 6726 } 6727 } 6728 6729 if (Commuted) { 6730 // Commute is back and try unpck* again. 6731 // FIXME: this seems wrong. 6732 SDValue NewOp = CommuteVectorShuffle(SVOp, DAG); 6733 ShuffleVectorSDNode *NewSVOp = cast<ShuffleVectorSDNode>(NewOp); 6734 6735 if (X86::isUNPCKLMask(NewSVOp)) 6736 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V2, V1, DAG); 6737 6738 if (X86::isUNPCKHMask(NewSVOp)) 6739 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V2, V1, DAG); 6740 } 6741 6742 // Normalize the node to match x86 shuffle ops if needed 6743 if (V2.getOpcode() != ISD::UNDEF && isCommutedSHUFP(SVOp)) 6744 return CommuteVectorShuffle(SVOp, DAG); 6745 6746 // The checks below are all present in isShuffleMaskLegal, but they are 6747 // inlined here right now to enable us to directly emit target specific 6748 // nodes, and remove one by one until they don't return Op anymore. 6749 SmallVector<int, 16> M; 6750 SVOp->getMask(M); 6751 6752 if (isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX())) 6753 return getTargetShuffleNode(X86ISD::PALIGN, dl, VT, V1, V2, 6754 X86::getShufflePALIGNRImmediate(SVOp), 6755 DAG); 6756 6757 if (ShuffleVectorSDNode::isSplatMask(&M[0], VT) && 6758 SVOp->getSplatIndex() == 0 && V2IsUndef) { 6759 if (VT == MVT::v2f64) 6760 return getTargetShuffleNode(X86ISD::UNPCKLPD, dl, VT, V1, V1, DAG); 6761 if (VT == MVT::v2i64) 6762 return getTargetShuffleNode(X86ISD::PUNPCKLQDQ, dl, VT, V1, V1, DAG); 6763 } 6764 6765 if (isPSHUFHWMask(M, VT)) 6766 return getTargetShuffleNode(X86ISD::PSHUFHW, dl, VT, V1, 6767 X86::getShufflePSHUFHWImmediate(SVOp), 6768 DAG); 6769 6770 if (isPSHUFLWMask(M, VT)) 6771 return getTargetShuffleNode(X86ISD::PSHUFLW, dl, VT, V1, 6772 X86::getShufflePSHUFLWImmediate(SVOp), 6773 DAG); 6774 6775 if (isSHUFPMask(M, VT)) 6776 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6777 X86::getShuffleSHUFImmediate(SVOp), DAG); 6778 6779 if (X86::isUNPCKL_v_undef_Mask(SVOp)) 6780 return getTargetShuffleNode(getUNPCKLOpcode(VT), dl, VT, V1, V1, DAG); 6781 if (X86::isUNPCKH_v_undef_Mask(SVOp)) 6782 return getTargetShuffleNode(getUNPCKHOpcode(VT), dl, VT, V1, V1, DAG); 6783 6784 //===--------------------------------------------------------------------===// 6785 // Generate target specific nodes for 128 or 256-bit shuffles only 6786 // supported in the AVX instruction set. 6787 // 6788 6789 // Handle VMOVDDUPY permutations 6790 if (isMOVDDUPYMask(SVOp, Subtarget)) 6791 return getTargetShuffleNode(X86ISD::MOVDDUP, dl, VT, V1, DAG); 6792 6793 // Handle VPERMILPS* permutations 6794 if (isVPERMILPSMask(M, VT, Subtarget)) 6795 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6796 getShuffleVPERMILPSImmediate(SVOp), DAG); 6797 6798 // Handle VPERMILPD* permutations 6799 if (isVPERMILPDMask(M, VT, Subtarget)) 6800 return getTargetShuffleNode(getVPERMILOpcode(VT), dl, VT, V1, 6801 getShuffleVPERMILPDImmediate(SVOp), DAG); 6802 6803 // Handle VPERM2F128 permutations 6804 if (isVPERM2F128Mask(M, VT, Subtarget)) 6805 return getTargetShuffleNode(X86ISD::VPERM2F128, dl, VT, V1, V2, 6806 getShuffleVPERM2F128Immediate(SVOp), DAG); 6807 6808 // Handle VSHUFPSY permutations 6809 if (isVSHUFPSYMask(M, VT, Subtarget)) 6810 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6811 getShuffleVSHUFPSYImmediate(SVOp), DAG); 6812 6813 // Handle VSHUFPDY permutations 6814 if (isVSHUFPDYMask(M, VT, Subtarget)) 6815 return getTargetShuffleNode(getSHUFPOpcode(VT), dl, VT, V1, V2, 6816 getShuffleVSHUFPDYImmediate(SVOp), DAG); 6817 6818 //===--------------------------------------------------------------------===// 6819 // Since no target specific shuffle was selected for this generic one, 6820 // lower it into other known shuffles. FIXME: this isn't true yet, but 6821 // this is the plan. 6822 // 6823 6824 // Handle v8i16 specifically since SSE can do byte extraction and insertion. 6825 if (VT == MVT::v8i16) { 6826 SDValue NewOp = LowerVECTOR_SHUFFLEv8i16(Op, DAG); 6827 if (NewOp.getNode()) 6828 return NewOp; 6829 } 6830 6831 if (VT == MVT::v16i8) { 6832 SDValue NewOp = LowerVECTOR_SHUFFLEv16i8(SVOp, DAG, *this); 6833 if (NewOp.getNode()) 6834 return NewOp; 6835 } 6836 6837 // Handle all 128-bit wide vectors with 4 elements, and match them with 6838 // several different shuffle types. 6839 if (NumElems == 4 && VT.getSizeInBits() == 128) 6840 return LowerVECTOR_SHUFFLE_128v4(SVOp, DAG); 6841 6842 // Handle general 256-bit shuffles 6843 if (VT.is256BitVector()) 6844 return LowerVECTOR_SHUFFLE_256(SVOp, DAG); 6845 6846 return SDValue(); 6847 } 6848 6849 SDValue 6850 X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op, 6851 SelectionDAG &DAG) const { 6852 EVT VT = Op.getValueType(); 6853 DebugLoc dl = Op.getDebugLoc(); 6854 6855 if (Op.getOperand(0).getValueType().getSizeInBits() != 128) 6856 return SDValue(); 6857 6858 if (VT.getSizeInBits() == 8) { 6859 SDValue Extract = DAG.getNode(X86ISD::PEXTRB, dl, MVT::i32, 6860 Op.getOperand(0), Op.getOperand(1)); 6861 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6862 DAG.getValueType(VT)); 6863 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6864 } else if (VT.getSizeInBits() == 16) { 6865 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6866 // If Idx is 0, it's cheaper to do a move instead of a pextrw. 6867 if (Idx == 0) 6868 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6869 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6870 DAG.getNode(ISD::BITCAST, dl, 6871 MVT::v4i32, 6872 Op.getOperand(0)), 6873 Op.getOperand(1))); 6874 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, MVT::i32, 6875 Op.getOperand(0), Op.getOperand(1)); 6876 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, MVT::i32, Extract, 6877 DAG.getValueType(VT)); 6878 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6879 } else if (VT == MVT::f32) { 6880 // EXTRACTPS outputs to a GPR32 register which will require a movd to copy 6881 // the result back to FR32 register. It's only worth matching if the 6882 // result has a single use which is a store or a bitcast to i32. And in 6883 // the case of a store, it's not worth it if the index is a constant 0, 6884 // because a MOVSSmr can be used instead, which is smaller and faster. 6885 if (!Op.hasOneUse()) 6886 return SDValue(); 6887 SDNode *User = *Op.getNode()->use_begin(); 6888 if ((User->getOpcode() != ISD::STORE || 6889 (isa<ConstantSDNode>(Op.getOperand(1)) && 6890 cast<ConstantSDNode>(Op.getOperand(1))->isNullValue())) && 6891 (User->getOpcode() != ISD::BITCAST || 6892 User->getValueType(0) != MVT::i32)) 6893 return SDValue(); 6894 SDValue Extract = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6895 DAG.getNode(ISD::BITCAST, dl, MVT::v4i32, 6896 Op.getOperand(0)), 6897 Op.getOperand(1)); 6898 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, Extract); 6899 } else if (VT == MVT::i32) { 6900 // ExtractPS works with constant index. 6901 if (isa<ConstantSDNode>(Op.getOperand(1))) 6902 return Op; 6903 } 6904 return SDValue(); 6905 } 6906 6907 6908 SDValue 6909 X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, 6910 SelectionDAG &DAG) const { 6911 if (!isa<ConstantSDNode>(Op.getOperand(1))) 6912 return SDValue(); 6913 6914 SDValue Vec = Op.getOperand(0); 6915 EVT VecVT = Vec.getValueType(); 6916 6917 // If this is a 256-bit vector result, first extract the 128-bit vector and 6918 // then extract the element from the 128-bit vector. 6919 if (VecVT.getSizeInBits() == 256) { 6920 DebugLoc dl = Op.getNode()->getDebugLoc(); 6921 unsigned NumElems = VecVT.getVectorNumElements(); 6922 SDValue Idx = Op.getOperand(1); 6923 unsigned IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue(); 6924 6925 // Get the 128-bit vector. 6926 bool Upper = IdxVal >= NumElems/2; 6927 Vec = Extract128BitVector(Vec, 6928 DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32), DAG, dl); 6929 6930 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, Op.getValueType(), Vec, 6931 Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : Idx); 6932 } 6933 6934 assert(Vec.getValueSizeInBits() <= 128 && "Unexpected vector length"); 6935 6936 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) { 6937 SDValue Res = LowerEXTRACT_VECTOR_ELT_SSE4(Op, DAG); 6938 if (Res.getNode()) 6939 return Res; 6940 } 6941 6942 EVT VT = Op.getValueType(); 6943 DebugLoc dl = Op.getDebugLoc(); 6944 // TODO: handle v16i8. 6945 if (VT.getSizeInBits() == 16) { 6946 SDValue Vec = Op.getOperand(0); 6947 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6948 if (Idx == 0) 6949 return DAG.getNode(ISD::TRUNCATE, dl, MVT::i16, 6950 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::i32, 6951 DAG.getNode(ISD::BITCAST, dl, 6952 MVT::v4i32, Vec), 6953 Op.getOperand(1))); 6954 // Transform it so it match pextrw which produces a 32-bit result. 6955 EVT EltVT = MVT::i32; 6956 SDValue Extract = DAG.getNode(X86ISD::PEXTRW, dl, EltVT, 6957 Op.getOperand(0), Op.getOperand(1)); 6958 SDValue Assert = DAG.getNode(ISD::AssertZext, dl, EltVT, Extract, 6959 DAG.getValueType(VT)); 6960 return DAG.getNode(ISD::TRUNCATE, dl, VT, Assert); 6961 } else if (VT.getSizeInBits() == 32) { 6962 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6963 if (Idx == 0) 6964 return Op; 6965 6966 // SHUFPS the element to the lowest double word, then movss. 6967 int Mask[4] = { static_cast<int>(Idx), -1, -1, -1 }; 6968 EVT VVT = Op.getOperand(0).getValueType(); 6969 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6970 DAG.getUNDEF(VVT), Mask); 6971 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6972 DAG.getIntPtrConstant(0)); 6973 } else if (VT.getSizeInBits() == 64) { 6974 // FIXME: .td only matches this for <2 x f64>, not <2 x i64> on 32b 6975 // FIXME: seems like this should be unnecessary if mov{h,l}pd were taught 6976 // to match extract_elt for f64. 6977 unsigned Idx = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 6978 if (Idx == 0) 6979 return Op; 6980 6981 // UNPCKHPD the element to the lowest double word, then movsd. 6982 // Note if the lower 64 bits of the result of the UNPCKHPD is then stored 6983 // to a f64mem, the whole operation is folded into a single MOVHPDmr. 6984 int Mask[2] = { 1, -1 }; 6985 EVT VVT = Op.getOperand(0).getValueType(); 6986 SDValue Vec = DAG.getVectorShuffle(VVT, dl, Op.getOperand(0), 6987 DAG.getUNDEF(VVT), Mask); 6988 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, Vec, 6989 DAG.getIntPtrConstant(0)); 6990 } 6991 6992 return SDValue(); 6993 } 6994 6995 SDValue 6996 X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, 6997 SelectionDAG &DAG) const { 6998 EVT VT = Op.getValueType(); 6999 EVT EltVT = VT.getVectorElementType(); 7000 DebugLoc dl = Op.getDebugLoc(); 7001 7002 SDValue N0 = Op.getOperand(0); 7003 SDValue N1 = Op.getOperand(1); 7004 SDValue N2 = Op.getOperand(2); 7005 7006 if (VT.getSizeInBits() == 256) 7007 return SDValue(); 7008 7009 if ((EltVT.getSizeInBits() == 8 || EltVT.getSizeInBits() == 16) && 7010 isa<ConstantSDNode>(N2)) { 7011 unsigned Opc; 7012 if (VT == MVT::v8i16) 7013 Opc = X86ISD::PINSRW; 7014 else if (VT == MVT::v16i8) 7015 Opc = X86ISD::PINSRB; 7016 else 7017 Opc = X86ISD::PINSRB; 7018 7019 // Transform it so it match pinsr{b,w} which expects a GR32 as its second 7020 // argument. 7021 if (N1.getValueType() != MVT::i32) 7022 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7023 if (N2.getValueType() != MVT::i32) 7024 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7025 return DAG.getNode(Opc, dl, VT, N0, N1, N2); 7026 } else if (EltVT == MVT::f32 && isa<ConstantSDNode>(N2)) { 7027 // Bits [7:6] of the constant are the source select. This will always be 7028 // zero here. The DAG Combiner may combine an extract_elt index into these 7029 // bits. For example (insert (extract, 3), 2) could be matched by putting 7030 // the '3' into bits [7:6] of X86ISD::INSERTPS. 7031 // Bits [5:4] of the constant are the destination select. This is the 7032 // value of the incoming immediate. 7033 // Bits [3:0] of the constant are the zero mask. The DAG Combiner may 7034 // combine either bitwise AND or insert of float 0.0 to set these bits. 7035 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4); 7036 // Create this as a scalar to vector.. 7037 N1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4f32, N1); 7038 return DAG.getNode(X86ISD::INSERTPS, dl, VT, N0, N1, N2); 7039 } else if (EltVT == MVT::i32 && isa<ConstantSDNode>(N2)) { 7040 // PINSR* works with constant index. 7041 return Op; 7042 } 7043 return SDValue(); 7044 } 7045 7046 SDValue 7047 X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 7048 EVT VT = Op.getValueType(); 7049 EVT EltVT = VT.getVectorElementType(); 7050 7051 DebugLoc dl = Op.getDebugLoc(); 7052 SDValue N0 = Op.getOperand(0); 7053 SDValue N1 = Op.getOperand(1); 7054 SDValue N2 = Op.getOperand(2); 7055 7056 // If this is a 256-bit vector result, first extract the 128-bit vector, 7057 // insert the element into the extracted half and then place it back. 7058 if (VT.getSizeInBits() == 256) { 7059 if (!isa<ConstantSDNode>(N2)) 7060 return SDValue(); 7061 7062 // Get the desired 128-bit vector half. 7063 unsigned NumElems = VT.getVectorNumElements(); 7064 unsigned IdxVal = cast<ConstantSDNode>(N2)->getZExtValue(); 7065 bool Upper = IdxVal >= NumElems/2; 7066 SDValue Ins128Idx = DAG.getConstant(Upper ? NumElems/2 : 0, MVT::i32); 7067 SDValue V = Extract128BitVector(N0, Ins128Idx, DAG, dl); 7068 7069 // Insert the element into the desired half. 7070 V = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, V.getValueType(), V, 7071 N1, Upper ? DAG.getConstant(IdxVal-NumElems/2, MVT::i32) : N2); 7072 7073 // Insert the changed part back to the 256-bit vector 7074 return Insert128BitVector(N0, V, Ins128Idx, DAG, dl); 7075 } 7076 7077 if (Subtarget->hasSSE41() || Subtarget->hasAVX()) 7078 return LowerINSERT_VECTOR_ELT_SSE4(Op, DAG); 7079 7080 if (EltVT == MVT::i8) 7081 return SDValue(); 7082 7083 if (EltVT.getSizeInBits() == 16 && isa<ConstantSDNode>(N2)) { 7084 // Transform it so it match pinsrw which expects a 16-bit value in a GR32 7085 // as its second argument. 7086 if (N1.getValueType() != MVT::i32) 7087 N1 = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, N1); 7088 if (N2.getValueType() != MVT::i32) 7089 N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue()); 7090 return DAG.getNode(X86ISD::PINSRW, dl, VT, N0, N1, N2); 7091 } 7092 return SDValue(); 7093 } 7094 7095 SDValue 7096 X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const { 7097 LLVMContext *Context = DAG.getContext(); 7098 DebugLoc dl = Op.getDebugLoc(); 7099 EVT OpVT = Op.getValueType(); 7100 7101 // If this is a 256-bit vector result, first insert into a 128-bit 7102 // vector and then insert into the 256-bit vector. 7103 if (OpVT.getSizeInBits() > 128) { 7104 // Insert into a 128-bit vector. 7105 EVT VT128 = EVT::getVectorVT(*Context, 7106 OpVT.getVectorElementType(), 7107 OpVT.getVectorNumElements() / 2); 7108 7109 Op = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT128, Op.getOperand(0)); 7110 7111 // Insert the 128-bit vector. 7112 return Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, OpVT), Op, 7113 DAG.getConstant(0, MVT::i32), 7114 DAG, dl); 7115 } 7116 7117 if (Op.getValueType() == MVT::v1i64 && 7118 Op.getOperand(0).getValueType() == MVT::i64) 7119 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0)); 7120 7121 SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0)); 7122 assert(Op.getValueType().getSimpleVT().getSizeInBits() == 128 && 7123 "Expected an SSE type!"); 7124 return DAG.getNode(ISD::BITCAST, dl, Op.getValueType(), 7125 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,AnyExt)); 7126 } 7127 7128 // Lower a node with an EXTRACT_SUBVECTOR opcode. This may result in 7129 // a simple subregister reference or explicit instructions to grab 7130 // upper bits of a vector. 7131 SDValue 7132 X86TargetLowering::LowerEXTRACT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7133 if (Subtarget->hasAVX()) { 7134 DebugLoc dl = Op.getNode()->getDebugLoc(); 7135 SDValue Vec = Op.getNode()->getOperand(0); 7136 SDValue Idx = Op.getNode()->getOperand(1); 7137 7138 if (Op.getNode()->getValueType(0).getSizeInBits() == 128 7139 && Vec.getNode()->getValueType(0).getSizeInBits() == 256) { 7140 return Extract128BitVector(Vec, Idx, DAG, dl); 7141 } 7142 } 7143 return SDValue(); 7144 } 7145 7146 // Lower a node with an INSERT_SUBVECTOR opcode. This may result in a 7147 // simple superregister reference or explicit instructions to insert 7148 // the upper bits of a vector. 7149 SDValue 7150 X86TargetLowering::LowerINSERT_SUBVECTOR(SDValue Op, SelectionDAG &DAG) const { 7151 if (Subtarget->hasAVX()) { 7152 DebugLoc dl = Op.getNode()->getDebugLoc(); 7153 SDValue Vec = Op.getNode()->getOperand(0); 7154 SDValue SubVec = Op.getNode()->getOperand(1); 7155 SDValue Idx = Op.getNode()->getOperand(2); 7156 7157 if (Op.getNode()->getValueType(0).getSizeInBits() == 256 7158 && SubVec.getNode()->getValueType(0).getSizeInBits() == 128) { 7159 return Insert128BitVector(Vec, SubVec, Idx, DAG, dl); 7160 } 7161 } 7162 return SDValue(); 7163 } 7164 7165 // ConstantPool, JumpTable, GlobalAddress, and ExternalSymbol are lowered as 7166 // their target countpart wrapped in the X86ISD::Wrapper node. Suppose N is 7167 // one of the above mentioned nodes. It has to be wrapped because otherwise 7168 // Select(N) returns N. So the raw TargetGlobalAddress nodes, etc. can only 7169 // be used to form addressing mode. These wrapped nodes will be selected 7170 // into MOV32ri. 7171 SDValue 7172 X86TargetLowering::LowerConstantPool(SDValue Op, SelectionDAG &DAG) const { 7173 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op); 7174 7175 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7176 // global base reg. 7177 unsigned char OpFlag = 0; 7178 unsigned WrapperKind = X86ISD::Wrapper; 7179 CodeModel::Model M = getTargetMachine().getCodeModel(); 7180 7181 if (Subtarget->isPICStyleRIPRel() && 7182 (M == CodeModel::Small || M == CodeModel::Kernel)) 7183 WrapperKind = X86ISD::WrapperRIP; 7184 else if (Subtarget->isPICStyleGOT()) 7185 OpFlag = X86II::MO_GOTOFF; 7186 else if (Subtarget->isPICStyleStubPIC()) 7187 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7188 7189 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(), 7190 CP->getAlignment(), 7191 CP->getOffset(), OpFlag); 7192 DebugLoc DL = CP->getDebugLoc(); 7193 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7194 // With PIC, the address is actually $g + Offset. 7195 if (OpFlag) { 7196 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7197 DAG.getNode(X86ISD::GlobalBaseReg, 7198 DebugLoc(), getPointerTy()), 7199 Result); 7200 } 7201 7202 return Result; 7203 } 7204 7205 SDValue X86TargetLowering::LowerJumpTable(SDValue Op, SelectionDAG &DAG) const { 7206 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op); 7207 7208 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7209 // global base reg. 7210 unsigned char OpFlag = 0; 7211 unsigned WrapperKind = X86ISD::Wrapper; 7212 CodeModel::Model M = getTargetMachine().getCodeModel(); 7213 7214 if (Subtarget->isPICStyleRIPRel() && 7215 (M == CodeModel::Small || M == CodeModel::Kernel)) 7216 WrapperKind = X86ISD::WrapperRIP; 7217 else if (Subtarget->isPICStyleGOT()) 7218 OpFlag = X86II::MO_GOTOFF; 7219 else if (Subtarget->isPICStyleStubPIC()) 7220 OpFlag = X86II::MO_PIC_BASE_OFFSET; 7221 7222 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy(), 7223 OpFlag); 7224 DebugLoc DL = JT->getDebugLoc(); 7225 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7226 7227 // With PIC, the address is actually $g + Offset. 7228 if (OpFlag) 7229 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7230 DAG.getNode(X86ISD::GlobalBaseReg, 7231 DebugLoc(), getPointerTy()), 7232 Result); 7233 7234 return Result; 7235 } 7236 7237 SDValue 7238 X86TargetLowering::LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const { 7239 const char *Sym = cast<ExternalSymbolSDNode>(Op)->getSymbol(); 7240 7241 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7242 // global base reg. 7243 unsigned char OpFlag = 0; 7244 unsigned WrapperKind = X86ISD::Wrapper; 7245 CodeModel::Model M = getTargetMachine().getCodeModel(); 7246 7247 if (Subtarget->isPICStyleRIPRel() && 7248 (M == CodeModel::Small || M == CodeModel::Kernel)) { 7249 if (Subtarget->isTargetDarwin() || Subtarget->isTargetELF()) 7250 OpFlag = X86II::MO_GOTPCREL; 7251 WrapperKind = X86ISD::WrapperRIP; 7252 } else if (Subtarget->isPICStyleGOT()) { 7253 OpFlag = X86II::MO_GOT; 7254 } else if (Subtarget->isPICStyleStubPIC()) { 7255 OpFlag = X86II::MO_DARWIN_NONLAZY_PIC_BASE; 7256 } else if (Subtarget->isPICStyleStubNoDynamic()) { 7257 OpFlag = X86II::MO_DARWIN_NONLAZY; 7258 } 7259 7260 SDValue Result = DAG.getTargetExternalSymbol(Sym, getPointerTy(), OpFlag); 7261 7262 DebugLoc DL = Op.getDebugLoc(); 7263 Result = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7264 7265 7266 // With PIC, the address is actually $g + Offset. 7267 if (getTargetMachine().getRelocationModel() == Reloc::PIC_ && 7268 !Subtarget->is64Bit()) { 7269 Result = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7270 DAG.getNode(X86ISD::GlobalBaseReg, 7271 DebugLoc(), getPointerTy()), 7272 Result); 7273 } 7274 7275 // For symbols that require a load from a stub to get the address, emit the 7276 // load. 7277 if (isGlobalStubReference(OpFlag)) 7278 Result = DAG.getLoad(getPointerTy(), DL, DAG.getEntryNode(), Result, 7279 MachinePointerInfo::getGOT(), false, false, 0); 7280 7281 return Result; 7282 } 7283 7284 SDValue 7285 X86TargetLowering::LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const { 7286 // Create the TargetBlockAddressAddress node. 7287 unsigned char OpFlags = 7288 Subtarget->ClassifyBlockAddressReference(); 7289 CodeModel::Model M = getTargetMachine().getCodeModel(); 7290 const BlockAddress *BA = cast<BlockAddressSDNode>(Op)->getBlockAddress(); 7291 DebugLoc dl = Op.getDebugLoc(); 7292 SDValue Result = DAG.getBlockAddress(BA, getPointerTy(), 7293 /*isTarget=*/true, OpFlags); 7294 7295 if (Subtarget->isPICStyleRIPRel() && 7296 (M == CodeModel::Small || M == CodeModel::Kernel)) 7297 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7298 else 7299 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7300 7301 // With PIC, the address is actually $g + Offset. 7302 if (isGlobalRelativeToPICBase(OpFlags)) { 7303 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7304 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7305 Result); 7306 } 7307 7308 return Result; 7309 } 7310 7311 SDValue 7312 X86TargetLowering::LowerGlobalAddress(const GlobalValue *GV, DebugLoc dl, 7313 int64_t Offset, 7314 SelectionDAG &DAG) const { 7315 // Create the TargetGlobalAddress node, folding in the constant 7316 // offset if it is legal. 7317 unsigned char OpFlags = 7318 Subtarget->ClassifyGlobalReference(GV, getTargetMachine()); 7319 CodeModel::Model M = getTargetMachine().getCodeModel(); 7320 SDValue Result; 7321 if (OpFlags == X86II::MO_NO_FLAG && 7322 X86::isOffsetSuitableForCodeModel(Offset, M)) { 7323 // A direct static reference to a global. 7324 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), Offset); 7325 Offset = 0; 7326 } else { 7327 Result = DAG.getTargetGlobalAddress(GV, dl, getPointerTy(), 0, OpFlags); 7328 } 7329 7330 if (Subtarget->isPICStyleRIPRel() && 7331 (M == CodeModel::Small || M == CodeModel::Kernel)) 7332 Result = DAG.getNode(X86ISD::WrapperRIP, dl, getPointerTy(), Result); 7333 else 7334 Result = DAG.getNode(X86ISD::Wrapper, dl, getPointerTy(), Result); 7335 7336 // With PIC, the address is actually $g + Offset. 7337 if (isGlobalRelativeToPICBase(OpFlags)) { 7338 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), 7339 DAG.getNode(X86ISD::GlobalBaseReg, dl, getPointerTy()), 7340 Result); 7341 } 7342 7343 // For globals that require a load from a stub to get the address, emit the 7344 // load. 7345 if (isGlobalStubReference(OpFlags)) 7346 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result, 7347 MachinePointerInfo::getGOT(), false, false, 0); 7348 7349 // If there was a non-zero offset that we didn't fold, create an explicit 7350 // addition for it. 7351 if (Offset != 0) 7352 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result, 7353 DAG.getConstant(Offset, getPointerTy())); 7354 7355 return Result; 7356 } 7357 7358 SDValue 7359 X86TargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const { 7360 const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal(); 7361 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset(); 7362 return LowerGlobalAddress(GV, Op.getDebugLoc(), Offset, DAG); 7363 } 7364 7365 static SDValue 7366 GetTLSADDR(SelectionDAG &DAG, SDValue Chain, GlobalAddressSDNode *GA, 7367 SDValue *InFlag, const EVT PtrVT, unsigned ReturnReg, 7368 unsigned char OperandFlags) { 7369 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7370 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7371 DebugLoc dl = GA->getDebugLoc(); 7372 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7373 GA->getValueType(0), 7374 GA->getOffset(), 7375 OperandFlags); 7376 if (InFlag) { 7377 SDValue Ops[] = { Chain, TGA, *InFlag }; 7378 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 3); 7379 } else { 7380 SDValue Ops[] = { Chain, TGA }; 7381 Chain = DAG.getNode(X86ISD::TLSADDR, dl, NodeTys, Ops, 2); 7382 } 7383 7384 // TLSADDR will be codegen'ed as call. Inform MFI that function has calls. 7385 MFI->setAdjustsStack(true); 7386 7387 SDValue Flag = Chain.getValue(1); 7388 return DAG.getCopyFromReg(Chain, dl, ReturnReg, PtrVT, Flag); 7389 } 7390 7391 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 32 bit 7392 static SDValue 7393 LowerToTLSGeneralDynamicModel32(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7394 const EVT PtrVT) { 7395 SDValue InFlag; 7396 DebugLoc dl = GA->getDebugLoc(); // ? function entry point might be better 7397 SDValue Chain = DAG.getCopyToReg(DAG.getEntryNode(), dl, X86::EBX, 7398 DAG.getNode(X86ISD::GlobalBaseReg, 7399 DebugLoc(), PtrVT), InFlag); 7400 InFlag = Chain.getValue(1); 7401 7402 return GetTLSADDR(DAG, Chain, GA, &InFlag, PtrVT, X86::EAX, X86II::MO_TLSGD); 7403 } 7404 7405 // Lower ISD::GlobalTLSAddress using the "general dynamic" model, 64 bit 7406 static SDValue 7407 LowerToTLSGeneralDynamicModel64(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7408 const EVT PtrVT) { 7409 return GetTLSADDR(DAG, DAG.getEntryNode(), GA, NULL, PtrVT, 7410 X86::RAX, X86II::MO_TLSGD); 7411 } 7412 7413 // Lower ISD::GlobalTLSAddress using the "initial exec" (for no-pic) or 7414 // "local exec" model. 7415 static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG, 7416 const EVT PtrVT, TLSModel::Model model, 7417 bool is64Bit) { 7418 DebugLoc dl = GA->getDebugLoc(); 7419 7420 // Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit). 7421 Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(), 7422 is64Bit ? 257 : 256)); 7423 7424 SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), 7425 DAG.getIntPtrConstant(0), 7426 MachinePointerInfo(Ptr), false, false, 0); 7427 7428 unsigned char OperandFlags = 0; 7429 // Most TLS accesses are not RIP relative, even on x86-64. One exception is 7430 // initialexec. 7431 unsigned WrapperKind = X86ISD::Wrapper; 7432 if (model == TLSModel::LocalExec) { 7433 OperandFlags = is64Bit ? X86II::MO_TPOFF : X86II::MO_NTPOFF; 7434 } else if (is64Bit) { 7435 assert(model == TLSModel::InitialExec); 7436 OperandFlags = X86II::MO_GOTTPOFF; 7437 WrapperKind = X86ISD::WrapperRIP; 7438 } else { 7439 assert(model == TLSModel::InitialExec); 7440 OperandFlags = X86II::MO_INDNTPOFF; 7441 } 7442 7443 // emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial 7444 // exec) 7445 SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl, 7446 GA->getValueType(0), 7447 GA->getOffset(), OperandFlags); 7448 SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA); 7449 7450 if (model == TLSModel::InitialExec) 7451 Offset = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(), Offset, 7452 MachinePointerInfo::getGOT(), false, false, 0); 7453 7454 // The address of the thread local variable is the add of the thread 7455 // pointer with the offset of the variable. 7456 return DAG.getNode(ISD::ADD, dl, PtrVT, ThreadPointer, Offset); 7457 } 7458 7459 SDValue 7460 X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { 7461 7462 GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op); 7463 const GlobalValue *GV = GA->getGlobal(); 7464 7465 if (Subtarget->isTargetELF()) { 7466 // TODO: implement the "local dynamic" model 7467 // TODO: implement the "initial exec"model for pic executables 7468 7469 // If GV is an alias then use the aliasee for determining 7470 // thread-localness. 7471 if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV)) 7472 GV = GA->resolveAliasedGlobal(false); 7473 7474 TLSModel::Model model 7475 = getTLSModel(GV, getTargetMachine().getRelocationModel()); 7476 7477 switch (model) { 7478 case TLSModel::GeneralDynamic: 7479 case TLSModel::LocalDynamic: // not implemented 7480 if (Subtarget->is64Bit()) 7481 return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy()); 7482 return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy()); 7483 7484 case TLSModel::InitialExec: 7485 case TLSModel::LocalExec: 7486 return LowerToTLSExecModel(GA, DAG, getPointerTy(), model, 7487 Subtarget->is64Bit()); 7488 } 7489 } else if (Subtarget->isTargetDarwin()) { 7490 // Darwin only has one model of TLS. Lower to that. 7491 unsigned char OpFlag = 0; 7492 unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ? 7493 X86ISD::WrapperRIP : X86ISD::Wrapper; 7494 7495 // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the 7496 // global base reg. 7497 bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) && 7498 !Subtarget->is64Bit(); 7499 if (PIC32) 7500 OpFlag = X86II::MO_TLVP_PIC_BASE; 7501 else 7502 OpFlag = X86II::MO_TLVP; 7503 DebugLoc DL = Op.getDebugLoc(); 7504 SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, 7505 GA->getValueType(0), 7506 GA->getOffset(), OpFlag); 7507 SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result); 7508 7509 // With PIC32, the address is actually $g + Offset. 7510 if (PIC32) 7511 Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(), 7512 DAG.getNode(X86ISD::GlobalBaseReg, 7513 DebugLoc(), getPointerTy()), 7514 Offset); 7515 7516 // Lowering the machine isd will make sure everything is in the right 7517 // location. 7518 SDValue Chain = DAG.getEntryNode(); 7519 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 7520 SDValue Args[] = { Chain, Offset }; 7521 Chain = DAG.getNode(X86ISD::TLSCALL, DL, NodeTys, Args, 2); 7522 7523 // TLSCALL will be codegen'ed as call. Inform MFI that function has calls. 7524 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 7525 MFI->setAdjustsStack(true); 7526 7527 // And our return value (tls address) is in the standard call return value 7528 // location. 7529 unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 7530 return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy()); 7531 } 7532 7533 assert(false && 7534 "TLS not implemented for this target."); 7535 7536 llvm_unreachable("Unreachable"); 7537 return SDValue(); 7538 } 7539 7540 7541 /// LowerShiftParts - Lower SRA_PARTS and friends, which return two i32 values and 7542 /// take a 2 x i32 value to shift plus a shift amount. 7543 SDValue X86TargetLowering::LowerShiftParts(SDValue Op, SelectionDAG &DAG) const { 7544 assert(Op.getNumOperands() == 3 && "Not a double-shift!"); 7545 EVT VT = Op.getValueType(); 7546 unsigned VTBits = VT.getSizeInBits(); 7547 DebugLoc dl = Op.getDebugLoc(); 7548 bool isSRA = Op.getOpcode() == ISD::SRA_PARTS; 7549 SDValue ShOpLo = Op.getOperand(0); 7550 SDValue ShOpHi = Op.getOperand(1); 7551 SDValue ShAmt = Op.getOperand(2); 7552 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, 7553 DAG.getConstant(VTBits - 1, MVT::i8)) 7554 : DAG.getConstant(0, VT); 7555 7556 SDValue Tmp2, Tmp3; 7557 if (Op.getOpcode() == ISD::SHL_PARTS) { 7558 Tmp2 = DAG.getNode(X86ISD::SHLD, dl, VT, ShOpHi, ShOpLo, ShAmt); 7559 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); 7560 } else { 7561 Tmp2 = DAG.getNode(X86ISD::SHRD, dl, VT, ShOpLo, ShOpHi, ShAmt); 7562 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); 7563 } 7564 7565 SDValue AndNode = DAG.getNode(ISD::AND, dl, MVT::i8, ShAmt, 7566 DAG.getConstant(VTBits, MVT::i8)); 7567 SDValue Cond = DAG.getNode(X86ISD::CMP, dl, MVT::i32, 7568 AndNode, DAG.getConstant(0, MVT::i8)); 7569 7570 SDValue Hi, Lo; 7571 SDValue CC = DAG.getConstant(X86::COND_NE, MVT::i8); 7572 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; 7573 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; 7574 7575 if (Op.getOpcode() == ISD::SHL_PARTS) { 7576 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7577 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7578 } else { 7579 Lo = DAG.getNode(X86ISD::CMOV, dl, VT, Ops0, 4); 7580 Hi = DAG.getNode(X86ISD::CMOV, dl, VT, Ops1, 4); 7581 } 7582 7583 SDValue Ops[2] = { Lo, Hi }; 7584 return DAG.getMergeValues(Ops, 2, dl); 7585 } 7586 7587 SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op, 7588 SelectionDAG &DAG) const { 7589 EVT SrcVT = Op.getOperand(0).getValueType(); 7590 7591 if (SrcVT.isVector()) 7592 return SDValue(); 7593 7594 assert(SrcVT.getSimpleVT() <= MVT::i64 && SrcVT.getSimpleVT() >= MVT::i16 && 7595 "Unknown SINT_TO_FP to lower!"); 7596 7597 // These are really Legal; return the operand so the caller accepts it as 7598 // Legal. 7599 if (SrcVT == MVT::i32 && isScalarFPTypeInSSEReg(Op.getValueType())) 7600 return Op; 7601 if (SrcVT == MVT::i64 && isScalarFPTypeInSSEReg(Op.getValueType()) && 7602 Subtarget->is64Bit()) { 7603 return Op; 7604 } 7605 7606 DebugLoc dl = Op.getDebugLoc(); 7607 unsigned Size = SrcVT.getSizeInBits()/8; 7608 MachineFunction &MF = DAG.getMachineFunction(); 7609 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false); 7610 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7611 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7612 StackSlot, 7613 MachinePointerInfo::getFixedStack(SSFI), 7614 false, false, 0); 7615 return BuildFILD(Op, SrcVT, Chain, StackSlot, DAG); 7616 } 7617 7618 SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, 7619 SDValue StackSlot, 7620 SelectionDAG &DAG) const { 7621 // Build the FILD 7622 DebugLoc DL = Op.getDebugLoc(); 7623 SDVTList Tys; 7624 bool useSSE = isScalarFPTypeInSSEReg(Op.getValueType()); 7625 if (useSSE) 7626 Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Glue); 7627 else 7628 Tys = DAG.getVTList(Op.getValueType(), MVT::Other); 7629 7630 unsigned ByteSize = SrcVT.getSizeInBits()/8; 7631 7632 FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(StackSlot); 7633 MachineMemOperand *MMO; 7634 if (FI) { 7635 int SSFI = FI->getIndex(); 7636 MMO = 7637 DAG.getMachineFunction() 7638 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7639 MachineMemOperand::MOLoad, ByteSize, ByteSize); 7640 } else { 7641 MMO = cast<LoadSDNode>(StackSlot)->getMemOperand(); 7642 StackSlot = StackSlot.getOperand(1); 7643 } 7644 SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) }; 7645 SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG : 7646 X86ISD::FILD, DL, 7647 Tys, Ops, array_lengthof(Ops), 7648 SrcVT, MMO); 7649 7650 if (useSSE) { 7651 Chain = Result.getValue(1); 7652 SDValue InFlag = Result.getValue(2); 7653 7654 // FIXME: Currently the FST is flagged to the FILD_FLAG. This 7655 // shouldn't be necessary except that RFP cannot be live across 7656 // multiple blocks. When stackifier is fixed, they can be uncoupled. 7657 MachineFunction &MF = DAG.getMachineFunction(); 7658 unsigned SSFISize = Op.getValueType().getSizeInBits()/8; 7659 int SSFI = MF.getFrameInfo()->CreateStackObject(SSFISize, SSFISize, false); 7660 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7661 Tys = DAG.getVTList(MVT::Other); 7662 SDValue Ops[] = { 7663 Chain, Result, StackSlot, DAG.getValueType(Op.getValueType()), InFlag 7664 }; 7665 MachineMemOperand *MMO = 7666 DAG.getMachineFunction() 7667 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7668 MachineMemOperand::MOStore, SSFISize, SSFISize); 7669 7670 Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys, 7671 Ops, array_lengthof(Ops), 7672 Op.getValueType(), MMO); 7673 Result = DAG.getLoad(Op.getValueType(), DL, Chain, StackSlot, 7674 MachinePointerInfo::getFixedStack(SSFI), 7675 false, false, 0); 7676 } 7677 7678 return Result; 7679 } 7680 7681 // LowerUINT_TO_FP_i64 - 64-bit unsigned integer to double expansion. 7682 SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, 7683 SelectionDAG &DAG) const { 7684 // This algorithm is not obvious. Here it is in C code, more or less: 7685 /* 7686 double uint64_to_double( uint32_t hi, uint32_t lo ) { 7687 static const __m128i exp = { 0x4330000045300000ULL, 0 }; 7688 static const __m128d bias = { 0x1.0p84, 0x1.0p52 }; 7689 7690 // Copy ints to xmm registers. 7691 __m128i xh = _mm_cvtsi32_si128( hi ); 7692 __m128i xl = _mm_cvtsi32_si128( lo ); 7693 7694 // Combine into low half of a single xmm register. 7695 __m128i x = _mm_unpacklo_epi32( xh, xl ); 7696 __m128d d; 7697 double sd; 7698 7699 // Merge in appropriate exponents to give the integer bits the right 7700 // magnitude. 7701 x = _mm_unpacklo_epi32( x, exp ); 7702 7703 // Subtract away the biases to deal with the IEEE-754 double precision 7704 // implicit 1. 7705 d = _mm_sub_pd( (__m128d) x, bias ); 7706 7707 // All conversions up to here are exact. The correctly rounded result is 7708 // calculated using the current rounding mode using the following 7709 // horizontal add. 7710 d = _mm_add_sd( d, _mm_unpackhi_pd( d, d ) ); 7711 _mm_store_sd( &sd, d ); // Because we are returning doubles in XMM, this 7712 // store doesn't really need to be here (except 7713 // maybe to zero the other double) 7714 return sd; 7715 } 7716 */ 7717 7718 DebugLoc dl = Op.getDebugLoc(); 7719 LLVMContext *Context = DAG.getContext(); 7720 7721 // Build some magic constants. 7722 std::vector<Constant*> CV0; 7723 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x45300000))); 7724 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0x43300000))); 7725 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7726 CV0.push_back(ConstantInt::get(*Context, APInt(32, 0))); 7727 Constant *C0 = ConstantVector::get(CV0); 7728 SDValue CPIdx0 = DAG.getConstantPool(C0, getPointerTy(), 16); 7729 7730 std::vector<Constant*> CV1; 7731 CV1.push_back( 7732 ConstantFP::get(*Context, APFloat(APInt(64, 0x4530000000000000ULL)))); 7733 CV1.push_back( 7734 ConstantFP::get(*Context, APFloat(APInt(64, 0x4330000000000000ULL)))); 7735 Constant *C1 = ConstantVector::get(CV1); 7736 SDValue CPIdx1 = DAG.getConstantPool(C1, getPointerTy(), 16); 7737 7738 SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7739 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7740 Op.getOperand(0), 7741 DAG.getIntPtrConstant(1))); 7742 SDValue XR2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7743 DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 7744 Op.getOperand(0), 7745 DAG.getIntPtrConstant(0))); 7746 SDValue Unpck1 = getUnpackl(DAG, dl, MVT::v4i32, XR1, XR2); 7747 SDValue CLod0 = DAG.getLoad(MVT::v4i32, dl, DAG.getEntryNode(), CPIdx0, 7748 MachinePointerInfo::getConstantPool(), 7749 false, false, 16); 7750 SDValue Unpck2 = getUnpackl(DAG, dl, MVT::v4i32, Unpck1, CLod0); 7751 SDValue XR2F = DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Unpck2); 7752 SDValue CLod1 = DAG.getLoad(MVT::v2f64, dl, CLod0.getValue(1), CPIdx1, 7753 MachinePointerInfo::getConstantPool(), 7754 false, false, 16); 7755 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::v2f64, XR2F, CLod1); 7756 7757 // Add the halves; easiest way is to swap them into another reg first. 7758 int ShufMask[2] = { 1, -1 }; 7759 SDValue Shuf = DAG.getVectorShuffle(MVT::v2f64, dl, Sub, 7760 DAG.getUNDEF(MVT::v2f64), ShufMask); 7761 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::v2f64, Shuf, Sub); 7762 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, Add, 7763 DAG.getIntPtrConstant(0)); 7764 } 7765 7766 // LowerUINT_TO_FP_i32 - 32-bit unsigned integer to float expansion. 7767 SDValue X86TargetLowering::LowerUINT_TO_FP_i32(SDValue Op, 7768 SelectionDAG &DAG) const { 7769 DebugLoc dl = Op.getDebugLoc(); 7770 // FP constant to bias correct the final result. 7771 SDValue Bias = DAG.getConstantFP(BitsToDouble(0x4330000000000000ULL), 7772 MVT::f64); 7773 7774 // Load the 32-bit value into an XMM register. 7775 SDValue Load = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32, 7776 Op.getOperand(0)); 7777 7778 // Zero out the upper parts of the register. 7779 Load = getShuffleVectorZeroOrUndef(Load, 0, true, Subtarget->hasXMMInt(), 7780 DAG); 7781 7782 Load = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7783 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Load), 7784 DAG.getIntPtrConstant(0)); 7785 7786 // Or the load with the bias. 7787 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::v2i64, 7788 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7789 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7790 MVT::v2f64, Load)), 7791 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 7792 DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 7793 MVT::v2f64, Bias))); 7794 Or = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f64, 7795 DAG.getNode(ISD::BITCAST, dl, MVT::v2f64, Or), 7796 DAG.getIntPtrConstant(0)); 7797 7798 // Subtract the bias. 7799 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Or, Bias); 7800 7801 // Handle final rounding. 7802 EVT DestVT = Op.getValueType(); 7803 7804 if (DestVT.bitsLT(MVT::f64)) { 7805 return DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 7806 DAG.getIntPtrConstant(0)); 7807 } else if (DestVT.bitsGT(MVT::f64)) { 7808 return DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 7809 } 7810 7811 // Handle final rounding. 7812 return Sub; 7813 } 7814 7815 SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op, 7816 SelectionDAG &DAG) const { 7817 SDValue N0 = Op.getOperand(0); 7818 DebugLoc dl = Op.getDebugLoc(); 7819 7820 // Since UINT_TO_FP is legal (it's marked custom), dag combiner won't 7821 // optimize it to a SINT_TO_FP when the sign bit is known zero. Perform 7822 // the optimization here. 7823 if (DAG.SignBitIsZero(N0)) 7824 return DAG.getNode(ISD::SINT_TO_FP, dl, Op.getValueType(), N0); 7825 7826 EVT SrcVT = N0.getValueType(); 7827 EVT DstVT = Op.getValueType(); 7828 if (SrcVT == MVT::i64 && DstVT == MVT::f64 && X86ScalarSSEf64) 7829 return LowerUINT_TO_FP_i64(Op, DAG); 7830 else if (SrcVT == MVT::i32 && X86ScalarSSEf64) 7831 return LowerUINT_TO_FP_i32(Op, DAG); 7832 7833 // Make a 64-bit buffer, and use it to build an FILD. 7834 SDValue StackSlot = DAG.CreateStackTemporary(MVT::i64); 7835 if (SrcVT == MVT::i32) { 7836 SDValue WordOff = DAG.getConstant(4, getPointerTy()); 7837 SDValue OffsetSlot = DAG.getNode(ISD::ADD, dl, 7838 getPointerTy(), StackSlot, WordOff); 7839 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7840 StackSlot, MachinePointerInfo(), 7841 false, false, 0); 7842 SDValue Store2 = DAG.getStore(Store1, dl, DAG.getConstant(0, MVT::i32), 7843 OffsetSlot, MachinePointerInfo(), 7844 false, false, 0); 7845 SDValue Fild = BuildFILD(Op, MVT::i64, Store2, StackSlot, DAG); 7846 return Fild; 7847 } 7848 7849 assert(SrcVT == MVT::i64 && "Unexpected type in UINT_TO_FP"); 7850 SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0), 7851 StackSlot, MachinePointerInfo(), 7852 false, false, 0); 7853 // For i64 source, we need to add the appropriate power of 2 if the input 7854 // was negative. This is the same as the optimization in 7855 // DAGTypeLegalizer::ExpandIntOp_UNIT_TO_FP, and for it to be safe here, 7856 // we must be careful to do the computation in x87 extended precision, not 7857 // in SSE. (The generic code can't know it's OK to do this, or how to.) 7858 int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex(); 7859 MachineMemOperand *MMO = 7860 DAG.getMachineFunction() 7861 .getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7862 MachineMemOperand::MOLoad, 8, 8); 7863 7864 SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other); 7865 SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) }; 7866 SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3, 7867 MVT::i64, MMO); 7868 7869 APInt FF(32, 0x5F800000ULL); 7870 7871 // Check whether the sign bit is set. 7872 SDValue SignSet = DAG.getSetCC(dl, getSetCCResultType(MVT::i64), 7873 Op.getOperand(0), DAG.getConstant(0, MVT::i64), 7874 ISD::SETLT); 7875 7876 // Build a 64 bit pair (0, FF) in the constant pool, with FF in the lo bits. 7877 SDValue FudgePtr = DAG.getConstantPool( 7878 ConstantInt::get(*DAG.getContext(), FF.zext(64)), 7879 getPointerTy()); 7880 7881 // Get a pointer to FF if the sign bit was set, or to 0 otherwise. 7882 SDValue Zero = DAG.getIntPtrConstant(0); 7883 SDValue Four = DAG.getIntPtrConstant(4); 7884 SDValue Offset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), SignSet, 7885 Zero, Four); 7886 FudgePtr = DAG.getNode(ISD::ADD, dl, getPointerTy(), FudgePtr, Offset); 7887 7888 // Load the value out, extending it from f32 to f80. 7889 // FIXME: Avoid the extend by constructing the right constant pool? 7890 SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, MVT::f80, DAG.getEntryNode(), 7891 FudgePtr, MachinePointerInfo::getConstantPool(), 7892 MVT::f32, false, false, 4); 7893 // Extend everything to 80 bits to force it to be done on x87. 7894 SDValue Add = DAG.getNode(ISD::FADD, dl, MVT::f80, Fild, Fudge); 7895 return DAG.getNode(ISD::FP_ROUND, dl, DstVT, Add, DAG.getIntPtrConstant(0)); 7896 } 7897 7898 std::pair<SDValue,SDValue> X86TargetLowering:: 7899 FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const { 7900 DebugLoc DL = Op.getDebugLoc(); 7901 7902 EVT DstTy = Op.getValueType(); 7903 7904 if (!IsSigned) { 7905 assert(DstTy == MVT::i32 && "Unexpected FP_TO_UINT"); 7906 DstTy = MVT::i64; 7907 } 7908 7909 assert(DstTy.getSimpleVT() <= MVT::i64 && 7910 DstTy.getSimpleVT() >= MVT::i16 && 7911 "Unknown FP_TO_SINT to lower!"); 7912 7913 // These are really Legal. 7914 if (DstTy == MVT::i32 && 7915 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7916 return std::make_pair(SDValue(), SDValue()); 7917 if (Subtarget->is64Bit() && 7918 DstTy == MVT::i64 && 7919 isScalarFPTypeInSSEReg(Op.getOperand(0).getValueType())) 7920 return std::make_pair(SDValue(), SDValue()); 7921 7922 // We lower FP->sint64 into FISTP64, followed by a load, all to a temporary 7923 // stack slot. 7924 MachineFunction &MF = DAG.getMachineFunction(); 7925 unsigned MemSize = DstTy.getSizeInBits()/8; 7926 int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7927 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7928 7929 7930 7931 unsigned Opc; 7932 switch (DstTy.getSimpleVT().SimpleTy) { 7933 default: llvm_unreachable("Invalid FP_TO_SINT to lower!"); 7934 case MVT::i16: Opc = X86ISD::FP_TO_INT16_IN_MEM; break; 7935 case MVT::i32: Opc = X86ISD::FP_TO_INT32_IN_MEM; break; 7936 case MVT::i64: Opc = X86ISD::FP_TO_INT64_IN_MEM; break; 7937 } 7938 7939 SDValue Chain = DAG.getEntryNode(); 7940 SDValue Value = Op.getOperand(0); 7941 EVT TheVT = Op.getOperand(0).getValueType(); 7942 if (isScalarFPTypeInSSEReg(TheVT)) { 7943 assert(DstTy == MVT::i64 && "Invalid FP_TO_SINT to lower!"); 7944 Chain = DAG.getStore(Chain, DL, Value, StackSlot, 7945 MachinePointerInfo::getFixedStack(SSFI), 7946 false, false, 0); 7947 SDVTList Tys = DAG.getVTList(Op.getOperand(0).getValueType(), MVT::Other); 7948 SDValue Ops[] = { 7949 Chain, StackSlot, DAG.getValueType(TheVT) 7950 }; 7951 7952 MachineMemOperand *MMO = 7953 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7954 MachineMemOperand::MOLoad, MemSize, MemSize); 7955 Value = DAG.getMemIntrinsicNode(X86ISD::FLD, DL, Tys, Ops, 3, 7956 DstTy, MMO); 7957 Chain = Value.getValue(1); 7958 SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false); 7959 StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 7960 } 7961 7962 MachineMemOperand *MMO = 7963 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 7964 MachineMemOperand::MOStore, MemSize, MemSize); 7965 7966 // Build the FP_TO_INT*_IN_MEM 7967 SDValue Ops[] = { Chain, Value, StackSlot }; 7968 SDValue FIST = DAG.getMemIntrinsicNode(Opc, DL, DAG.getVTList(MVT::Other), 7969 Ops, 3, DstTy, MMO); 7970 7971 return std::make_pair(FIST, StackSlot); 7972 } 7973 7974 SDValue X86TargetLowering::LowerFP_TO_SINT(SDValue Op, 7975 SelectionDAG &DAG) const { 7976 if (Op.getValueType().isVector()) 7977 return SDValue(); 7978 7979 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, true); 7980 SDValue FIST = Vals.first, StackSlot = Vals.second; 7981 // If FP_TO_INTHelper failed, the node is actually supposed to be Legal. 7982 if (FIST.getNode() == 0) return Op; 7983 7984 // Load the result. 7985 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7986 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7987 } 7988 7989 SDValue X86TargetLowering::LowerFP_TO_UINT(SDValue Op, 7990 SelectionDAG &DAG) const { 7991 std::pair<SDValue,SDValue> Vals = FP_TO_INTHelper(Op, DAG, false); 7992 SDValue FIST = Vals.first, StackSlot = Vals.second; 7993 assert(FIST.getNode() && "Unexpected failure"); 7994 7995 // Load the result. 7996 return DAG.getLoad(Op.getValueType(), Op.getDebugLoc(), 7997 FIST, StackSlot, MachinePointerInfo(), false, false, 0); 7998 } 7999 8000 SDValue X86TargetLowering::LowerFABS(SDValue Op, 8001 SelectionDAG &DAG) const { 8002 LLVMContext *Context = DAG.getContext(); 8003 DebugLoc dl = Op.getDebugLoc(); 8004 EVT VT = Op.getValueType(); 8005 EVT EltVT = VT; 8006 if (VT.isVector()) 8007 EltVT = VT.getVectorElementType(); 8008 std::vector<Constant*> CV; 8009 if (EltVT == MVT::f64) { 8010 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63)))); 8011 CV.push_back(C); 8012 CV.push_back(C); 8013 } else { 8014 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31)))); 8015 CV.push_back(C); 8016 CV.push_back(C); 8017 CV.push_back(C); 8018 CV.push_back(C); 8019 } 8020 Constant *C = ConstantVector::get(CV); 8021 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8022 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8023 MachinePointerInfo::getConstantPool(), 8024 false, false, 16); 8025 return DAG.getNode(X86ISD::FAND, dl, VT, Op.getOperand(0), Mask); 8026 } 8027 8028 SDValue X86TargetLowering::LowerFNEG(SDValue Op, SelectionDAG &DAG) const { 8029 LLVMContext *Context = DAG.getContext(); 8030 DebugLoc dl = Op.getDebugLoc(); 8031 EVT VT = Op.getValueType(); 8032 EVT EltVT = VT; 8033 if (VT.isVector()) 8034 EltVT = VT.getVectorElementType(); 8035 std::vector<Constant*> CV; 8036 if (EltVT == MVT::f64) { 8037 Constant *C = ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63))); 8038 CV.push_back(C); 8039 CV.push_back(C); 8040 } else { 8041 Constant *C = ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31))); 8042 CV.push_back(C); 8043 CV.push_back(C); 8044 CV.push_back(C); 8045 CV.push_back(C); 8046 } 8047 Constant *C = ConstantVector::get(CV); 8048 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8049 SDValue Mask = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8050 MachinePointerInfo::getConstantPool(), 8051 false, false, 16); 8052 if (VT.isVector()) { 8053 return DAG.getNode(ISD::BITCAST, dl, VT, 8054 DAG.getNode(ISD::XOR, dl, MVT::v2i64, 8055 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, 8056 Op.getOperand(0)), 8057 DAG.getNode(ISD::BITCAST, dl, MVT::v2i64, Mask))); 8058 } else { 8059 return DAG.getNode(X86ISD::FXOR, dl, VT, Op.getOperand(0), Mask); 8060 } 8061 } 8062 8063 SDValue X86TargetLowering::LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const { 8064 LLVMContext *Context = DAG.getContext(); 8065 SDValue Op0 = Op.getOperand(0); 8066 SDValue Op1 = Op.getOperand(1); 8067 DebugLoc dl = Op.getDebugLoc(); 8068 EVT VT = Op.getValueType(); 8069 EVT SrcVT = Op1.getValueType(); 8070 8071 // If second operand is smaller, extend it first. 8072 if (SrcVT.bitsLT(VT)) { 8073 Op1 = DAG.getNode(ISD::FP_EXTEND, dl, VT, Op1); 8074 SrcVT = VT; 8075 } 8076 // And if it is bigger, shrink it first. 8077 if (SrcVT.bitsGT(VT)) { 8078 Op1 = DAG.getNode(ISD::FP_ROUND, dl, VT, Op1, DAG.getIntPtrConstant(1)); 8079 SrcVT = VT; 8080 } 8081 8082 // At this point the operands and the result should have the same 8083 // type, and that won't be f80 since that is not custom lowered. 8084 8085 // First get the sign bit of second operand. 8086 std::vector<Constant*> CV; 8087 if (SrcVT == MVT::f64) { 8088 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 1ULL << 63)))); 8089 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8090 } else { 8091 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 1U << 31)))); 8092 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8093 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8094 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8095 } 8096 Constant *C = ConstantVector::get(CV); 8097 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8098 SDValue Mask1 = DAG.getLoad(SrcVT, dl, DAG.getEntryNode(), CPIdx, 8099 MachinePointerInfo::getConstantPool(), 8100 false, false, 16); 8101 SDValue SignBit = DAG.getNode(X86ISD::FAND, dl, SrcVT, Op1, Mask1); 8102 8103 // Shift sign bit right or left if the two operands have different types. 8104 if (SrcVT.bitsGT(VT)) { 8105 // Op0 is MVT::f32, Op1 is MVT::f64. 8106 SignBit = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f64, SignBit); 8107 SignBit = DAG.getNode(X86ISD::FSRL, dl, MVT::v2f64, SignBit, 8108 DAG.getConstant(32, MVT::i32)); 8109 SignBit = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, SignBit); 8110 SignBit = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, MVT::f32, SignBit, 8111 DAG.getIntPtrConstant(0)); 8112 } 8113 8114 // Clear first operand sign bit. 8115 CV.clear(); 8116 if (VT == MVT::f64) { 8117 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, ~(1ULL << 63))))); 8118 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(64, 0)))); 8119 } else { 8120 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, ~(1U << 31))))); 8121 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8122 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8123 CV.push_back(ConstantFP::get(*Context, APFloat(APInt(32, 0)))); 8124 } 8125 C = ConstantVector::get(CV); 8126 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 8127 SDValue Mask2 = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 8128 MachinePointerInfo::getConstantPool(), 8129 false, false, 16); 8130 SDValue Val = DAG.getNode(X86ISD::FAND, dl, VT, Op0, Mask2); 8131 8132 // Or the value with the sign bit. 8133 return DAG.getNode(X86ISD::FOR, dl, VT, Val, SignBit); 8134 } 8135 8136 SDValue X86TargetLowering::LowerFGETSIGN(SDValue Op, SelectionDAG &DAG) const { 8137 SDValue N0 = Op.getOperand(0); 8138 DebugLoc dl = Op.getDebugLoc(); 8139 EVT VT = Op.getValueType(); 8140 8141 // Lower ISD::FGETSIGN to (AND (X86ISD::FGETSIGNx86 ...) 1). 8142 SDValue xFGETSIGN = DAG.getNode(X86ISD::FGETSIGNx86, dl, VT, N0, 8143 DAG.getConstant(1, VT)); 8144 return DAG.getNode(ISD::AND, dl, VT, xFGETSIGN, DAG.getConstant(1, VT)); 8145 } 8146 8147 /// Emit nodes that will be selected as "test Op0,Op0", or something 8148 /// equivalent. 8149 SDValue X86TargetLowering::EmitTest(SDValue Op, unsigned X86CC, 8150 SelectionDAG &DAG) const { 8151 DebugLoc dl = Op.getDebugLoc(); 8152 8153 // CF and OF aren't always set the way we want. Determine which 8154 // of these we need. 8155 bool NeedCF = false; 8156 bool NeedOF = false; 8157 switch (X86CC) { 8158 default: break; 8159 case X86::COND_A: case X86::COND_AE: 8160 case X86::COND_B: case X86::COND_BE: 8161 NeedCF = true; 8162 break; 8163 case X86::COND_G: case X86::COND_GE: 8164 case X86::COND_L: case X86::COND_LE: 8165 case X86::COND_O: case X86::COND_NO: 8166 NeedOF = true; 8167 break; 8168 } 8169 8170 // See if we can use the EFLAGS value from the operand instead of 8171 // doing a separate TEST. TEST always sets OF and CF to 0, so unless 8172 // we prove that the arithmetic won't overflow, we can't use OF or CF. 8173 if (Op.getResNo() != 0 || NeedOF || NeedCF) 8174 // Emit a CMP with 0, which is the TEST pattern. 8175 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8176 DAG.getConstant(0, Op.getValueType())); 8177 8178 unsigned Opcode = 0; 8179 unsigned NumOperands = 0; 8180 switch (Op.getNode()->getOpcode()) { 8181 case ISD::ADD: 8182 // Due to an isel shortcoming, be conservative if this add is likely to be 8183 // selected as part of a load-modify-store instruction. When the root node 8184 // in a match is a store, isel doesn't know how to remap non-chain non-flag 8185 // uses of other nodes in the match, such as the ADD in this case. This 8186 // leads to the ADD being left around and reselected, with the result being 8187 // two adds in the output. Alas, even if none our users are stores, that 8188 // doesn't prove we're O.K. Ergo, if we have any parents that aren't 8189 // CopyToReg or SETCC, eschew INC/DEC. A better fix seems to require 8190 // climbing the DAG back to the root, and it doesn't seem to be worth the 8191 // effort. 8192 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8193 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8194 if (UI->getOpcode() != ISD::CopyToReg && UI->getOpcode() != ISD::SETCC) 8195 goto default_case; 8196 8197 if (ConstantSDNode *C = 8198 dyn_cast<ConstantSDNode>(Op.getNode()->getOperand(1))) { 8199 // An add of one will be selected as an INC. 8200 if (C->getAPIntValue() == 1) { 8201 Opcode = X86ISD::INC; 8202 NumOperands = 1; 8203 break; 8204 } 8205 8206 // An add of negative one (subtract of one) will be selected as a DEC. 8207 if (C->getAPIntValue().isAllOnesValue()) { 8208 Opcode = X86ISD::DEC; 8209 NumOperands = 1; 8210 break; 8211 } 8212 } 8213 8214 // Otherwise use a regular EFLAGS-setting add. 8215 Opcode = X86ISD::ADD; 8216 NumOperands = 2; 8217 break; 8218 case ISD::AND: { 8219 // If the primary and result isn't used, don't bother using X86ISD::AND, 8220 // because a TEST instruction will be better. 8221 bool NonFlagUse = false; 8222 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8223 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 8224 SDNode *User = *UI; 8225 unsigned UOpNo = UI.getOperandNo(); 8226 if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse()) { 8227 // Look pass truncate. 8228 UOpNo = User->use_begin().getOperandNo(); 8229 User = *User->use_begin(); 8230 } 8231 8232 if (User->getOpcode() != ISD::BRCOND && 8233 User->getOpcode() != ISD::SETCC && 8234 (User->getOpcode() != ISD::SELECT || UOpNo != 0)) { 8235 NonFlagUse = true; 8236 break; 8237 } 8238 } 8239 8240 if (!NonFlagUse) 8241 break; 8242 } 8243 // FALL THROUGH 8244 case ISD::SUB: 8245 case ISD::OR: 8246 case ISD::XOR: 8247 // Due to the ISEL shortcoming noted above, be conservative if this op is 8248 // likely to be selected as part of a load-modify-store instruction. 8249 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 8250 UE = Op.getNode()->use_end(); UI != UE; ++UI) 8251 if (UI->getOpcode() == ISD::STORE) 8252 goto default_case; 8253 8254 // Otherwise use a regular EFLAGS-setting instruction. 8255 switch (Op.getNode()->getOpcode()) { 8256 default: llvm_unreachable("unexpected operator!"); 8257 case ISD::SUB: Opcode = X86ISD::SUB; break; 8258 case ISD::OR: Opcode = X86ISD::OR; break; 8259 case ISD::XOR: Opcode = X86ISD::XOR; break; 8260 case ISD::AND: Opcode = X86ISD::AND; break; 8261 } 8262 8263 NumOperands = 2; 8264 break; 8265 case X86ISD::ADD: 8266 case X86ISD::SUB: 8267 case X86ISD::INC: 8268 case X86ISD::DEC: 8269 case X86ISD::OR: 8270 case X86ISD::XOR: 8271 case X86ISD::AND: 8272 return SDValue(Op.getNode(), 1); 8273 default: 8274 default_case: 8275 break; 8276 } 8277 8278 if (Opcode == 0) 8279 // Emit a CMP with 0, which is the TEST pattern. 8280 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op, 8281 DAG.getConstant(0, Op.getValueType())); 8282 8283 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::i32); 8284 SmallVector<SDValue, 4> Ops; 8285 for (unsigned i = 0; i != NumOperands; ++i) 8286 Ops.push_back(Op.getOperand(i)); 8287 8288 SDValue New = DAG.getNode(Opcode, dl, VTs, &Ops[0], NumOperands); 8289 DAG.ReplaceAllUsesWith(Op, New); 8290 return SDValue(New.getNode(), 1); 8291 } 8292 8293 /// Emit nodes that will be selected as "cmp Op0,Op1", or something 8294 /// equivalent. 8295 SDValue X86TargetLowering::EmitCmp(SDValue Op0, SDValue Op1, unsigned X86CC, 8296 SelectionDAG &DAG) const { 8297 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op1)) 8298 if (C->getAPIntValue() == 0) 8299 return EmitTest(Op0, X86CC, DAG); 8300 8301 DebugLoc dl = Op0.getDebugLoc(); 8302 return DAG.getNode(X86ISD::CMP, dl, MVT::i32, Op0, Op1); 8303 } 8304 8305 /// LowerToBT - Result of 'and' is compared against zero. Turn it into a BT node 8306 /// if it's possible. 8307 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, 8308 DebugLoc dl, SelectionDAG &DAG) const { 8309 SDValue Op0 = And.getOperand(0); 8310 SDValue Op1 = And.getOperand(1); 8311 if (Op0.getOpcode() == ISD::TRUNCATE) 8312 Op0 = Op0.getOperand(0); 8313 if (Op1.getOpcode() == ISD::TRUNCATE) 8314 Op1 = Op1.getOperand(0); 8315 8316 SDValue LHS, RHS; 8317 if (Op1.getOpcode() == ISD::SHL) 8318 std::swap(Op0, Op1); 8319 if (Op0.getOpcode() == ISD::SHL) { 8320 if (ConstantSDNode *And00C = dyn_cast<ConstantSDNode>(Op0.getOperand(0))) 8321 if (And00C->getZExtValue() == 1) { 8322 // If we looked past a truncate, check that it's only truncating away 8323 // known zeros. 8324 unsigned BitWidth = Op0.getValueSizeInBits(); 8325 unsigned AndBitWidth = And.getValueSizeInBits(); 8326 if (BitWidth > AndBitWidth) { 8327 APInt Mask = APInt::getAllOnesValue(BitWidth), Zeros, Ones; 8328 DAG.ComputeMaskedBits(Op0, Mask, Zeros, Ones); 8329 if (Zeros.countLeadingOnes() < BitWidth - AndBitWidth) 8330 return SDValue(); 8331 } 8332 LHS = Op1; 8333 RHS = Op0.getOperand(1); 8334 } 8335 } else if (Op1.getOpcode() == ISD::Constant) { 8336 ConstantSDNode *AndRHS = cast<ConstantSDNode>(Op1); 8337 SDValue AndLHS = Op0; 8338 if (AndRHS->getZExtValue() == 1 && AndLHS.getOpcode() == ISD::SRL) { 8339 LHS = AndLHS.getOperand(0); 8340 RHS = AndLHS.getOperand(1); 8341 } 8342 } 8343 8344 if (LHS.getNode()) { 8345 // If LHS is i8, promote it to i32 with any_extend. There is no i8 BT 8346 // instruction. Since the shift amount is in-range-or-undefined, we know 8347 // that doing a bittest on the i32 value is ok. We extend to i32 because 8348 // the encoding for the i16 version is larger than the i32 version. 8349 // Also promote i16 to i32 for performance / code size reason. 8350 if (LHS.getValueType() == MVT::i8 || 8351 LHS.getValueType() == MVT::i16) 8352 LHS = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, LHS); 8353 8354 // If the operand types disagree, extend the shift amount to match. Since 8355 // BT ignores high bits (like shifts) we can use anyextend. 8356 if (LHS.getValueType() != RHS.getValueType()) 8357 RHS = DAG.getNode(ISD::ANY_EXTEND, dl, LHS.getValueType(), RHS); 8358 8359 SDValue BT = DAG.getNode(X86ISD::BT, dl, MVT::i32, LHS, RHS); 8360 unsigned Cond = CC == ISD::SETEQ ? X86::COND_AE : X86::COND_B; 8361 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8362 DAG.getConstant(Cond, MVT::i8), BT); 8363 } 8364 8365 return SDValue(); 8366 } 8367 8368 SDValue X86TargetLowering::LowerSETCC(SDValue Op, SelectionDAG &DAG) const { 8369 8370 if (Op.getValueType().isVector()) return LowerVSETCC(Op, DAG); 8371 8372 assert(Op.getValueType() == MVT::i8 && "SetCC type must be 8-bit integer"); 8373 SDValue Op0 = Op.getOperand(0); 8374 SDValue Op1 = Op.getOperand(1); 8375 DebugLoc dl = Op.getDebugLoc(); 8376 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); 8377 8378 // Optimize to BT if possible. 8379 // Lower (X & (1 << N)) == 0 to BT(X, N). 8380 // Lower ((X >>u N) & 1) != 0 to BT(X, N). 8381 // Lower ((X >>s N) & 1) != 0 to BT(X, N). 8382 if (Op0.getOpcode() == ISD::AND && Op0.hasOneUse() && 8383 Op1.getOpcode() == ISD::Constant && 8384 cast<ConstantSDNode>(Op1)->isNullValue() && 8385 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8386 SDValue NewSetCC = LowerToBT(Op0, CC, dl, DAG); 8387 if (NewSetCC.getNode()) 8388 return NewSetCC; 8389 } 8390 8391 // Look for X == 0, X == 1, X != 0, or X != 1. We can simplify some forms of 8392 // these. 8393 if (Op1.getOpcode() == ISD::Constant && 8394 (cast<ConstantSDNode>(Op1)->getZExtValue() == 1 || 8395 cast<ConstantSDNode>(Op1)->isNullValue()) && 8396 (CC == ISD::SETEQ || CC == ISD::SETNE)) { 8397 8398 // If the input is a setcc, then reuse the input setcc or use a new one with 8399 // the inverted condition. 8400 if (Op0.getOpcode() == X86ISD::SETCC) { 8401 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); 8402 bool Invert = (CC == ISD::SETNE) ^ 8403 cast<ConstantSDNode>(Op1)->isNullValue(); 8404 if (!Invert) return Op0; 8405 8406 CCode = X86::GetOppositeBranchCondition(CCode); 8407 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8408 DAG.getConstant(CCode, MVT::i8), Op0.getOperand(1)); 8409 } 8410 } 8411 8412 bool isFP = Op1.getValueType().isFloatingPoint(); 8413 unsigned X86CC = TranslateX86CC(CC, isFP, Op0, Op1, DAG); 8414 if (X86CC == X86::COND_INVALID) 8415 return SDValue(); 8416 8417 SDValue EFLAGS = EmitCmp(Op0, Op1, X86CC, DAG); 8418 return DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 8419 DAG.getConstant(X86CC, MVT::i8), EFLAGS); 8420 } 8421 8422 // Lower256IntVSETCC - Break a VSETCC 256-bit integer VSETCC into two new 128 8423 // ones, and then concatenate the result back. 8424 static SDValue Lower256IntVSETCC(SDValue Op, SelectionDAG &DAG) { 8425 EVT VT = Op.getValueType(); 8426 8427 assert(VT.getSizeInBits() == 256 && Op.getOpcode() == ISD::SETCC && 8428 "Unsupported value type for operation"); 8429 8430 int NumElems = VT.getVectorNumElements(); 8431 DebugLoc dl = Op.getDebugLoc(); 8432 SDValue CC = Op.getOperand(2); 8433 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 8434 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 8435 8436 // Extract the LHS vectors 8437 SDValue LHS = Op.getOperand(0); 8438 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 8439 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 8440 8441 // Extract the RHS vectors 8442 SDValue RHS = Op.getOperand(1); 8443 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 8444 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 8445 8446 // Issue the operation on the smaller types and concatenate the result back 8447 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 8448 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 8449 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 8450 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1, CC), 8451 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2, CC)); 8452 } 8453 8454 8455 SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) const { 8456 SDValue Cond; 8457 SDValue Op0 = Op.getOperand(0); 8458 SDValue Op1 = Op.getOperand(1); 8459 SDValue CC = Op.getOperand(2); 8460 EVT VT = Op.getValueType(); 8461 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); 8462 bool isFP = Op.getOperand(1).getValueType().isFloatingPoint(); 8463 DebugLoc dl = Op.getDebugLoc(); 8464 8465 if (isFP) { 8466 unsigned SSECC = 8; 8467 EVT EltVT = Op0.getValueType().getVectorElementType(); 8468 assert(EltVT == MVT::f32 || EltVT == MVT::f64); 8469 8470 unsigned Opc = EltVT == MVT::f32 ? X86ISD::CMPPS : X86ISD::CMPPD; 8471 bool Swap = false; 8472 8473 // SSE Condition code mapping: 8474 // 0 - EQ 8475 // 1 - LT 8476 // 2 - LE 8477 // 3 - UNORD 8478 // 4 - NEQ 8479 // 5 - NLT 8480 // 6 - NLE 8481 // 7 - ORD 8482 switch (SetCCOpcode) { 8483 default: break; 8484 case ISD::SETOEQ: 8485 case ISD::SETEQ: SSECC = 0; break; 8486 case ISD::SETOGT: 8487 case ISD::SETGT: Swap = true; // Fallthrough 8488 case ISD::SETLT: 8489 case ISD::SETOLT: SSECC = 1; break; 8490 case ISD::SETOGE: 8491 case ISD::SETGE: Swap = true; // Fallthrough 8492 case ISD::SETLE: 8493 case ISD::SETOLE: SSECC = 2; break; 8494 case ISD::SETUO: SSECC = 3; break; 8495 case ISD::SETUNE: 8496 case ISD::SETNE: SSECC = 4; break; 8497 case ISD::SETULE: Swap = true; 8498 case ISD::SETUGE: SSECC = 5; break; 8499 case ISD::SETULT: Swap = true; 8500 case ISD::SETUGT: SSECC = 6; break; 8501 case ISD::SETO: SSECC = 7; break; 8502 } 8503 if (Swap) 8504 std::swap(Op0, Op1); 8505 8506 // In the two special cases we can't handle, emit two comparisons. 8507 if (SSECC == 8) { 8508 if (SetCCOpcode == ISD::SETUEQ) { 8509 SDValue UNORD, EQ; 8510 UNORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(3, MVT::i8)); 8511 EQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(0, MVT::i8)); 8512 return DAG.getNode(ISD::OR, dl, VT, UNORD, EQ); 8513 } 8514 else if (SetCCOpcode == ISD::SETONE) { 8515 SDValue ORD, NEQ; 8516 ORD = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(7, MVT::i8)); 8517 NEQ = DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(4, MVT::i8)); 8518 return DAG.getNode(ISD::AND, dl, VT, ORD, NEQ); 8519 } 8520 llvm_unreachable("Illegal FP comparison"); 8521 } 8522 // Handle all other FP comparisons here. 8523 return DAG.getNode(Opc, dl, VT, Op0, Op1, DAG.getConstant(SSECC, MVT::i8)); 8524 } 8525 8526 // Break 256-bit integer vector compare into smaller ones. 8527 if (!isFP && VT.getSizeInBits() == 256) 8528 return Lower256IntVSETCC(Op, DAG); 8529 8530 // We are handling one of the integer comparisons here. Since SSE only has 8531 // GT and EQ comparisons for integer, swapping operands and multiple 8532 // operations may be required for some comparisons. 8533 unsigned Opc = 0, EQOpc = 0, GTOpc = 0; 8534 bool Swap = false, Invert = false, FlipSigns = false; 8535 8536 switch (VT.getSimpleVT().SimpleTy) { 8537 default: break; 8538 case MVT::v16i8: EQOpc = X86ISD::PCMPEQB; GTOpc = X86ISD::PCMPGTB; break; 8539 case MVT::v8i16: EQOpc = X86ISD::PCMPEQW; GTOpc = X86ISD::PCMPGTW; break; 8540 case MVT::v4i32: EQOpc = X86ISD::PCMPEQD; GTOpc = X86ISD::PCMPGTD; break; 8541 case MVT::v2i64: EQOpc = X86ISD::PCMPEQQ; GTOpc = X86ISD::PCMPGTQ; break; 8542 } 8543 8544 switch (SetCCOpcode) { 8545 default: break; 8546 case ISD::SETNE: Invert = true; 8547 case ISD::SETEQ: Opc = EQOpc; break; 8548 case ISD::SETLT: Swap = true; 8549 case ISD::SETGT: Opc = GTOpc; break; 8550 case ISD::SETGE: Swap = true; 8551 case ISD::SETLE: Opc = GTOpc; Invert = true; break; 8552 case ISD::SETULT: Swap = true; 8553 case ISD::SETUGT: Opc = GTOpc; FlipSigns = true; break; 8554 case ISD::SETUGE: Swap = true; 8555 case ISD::SETULE: Opc = GTOpc; FlipSigns = true; Invert = true; break; 8556 } 8557 if (Swap) 8558 std::swap(Op0, Op1); 8559 8560 // Check that the operation in question is available (most are plain SSE2, 8561 // but PCMPGTQ and PCMPEQQ have different requirements). 8562 if (Opc == X86ISD::PCMPGTQ && !Subtarget->hasSSE42() && !Subtarget->hasAVX()) 8563 return SDValue(); 8564 if (Opc == X86ISD::PCMPEQQ && !Subtarget->hasSSE41() && !Subtarget->hasAVX()) 8565 return SDValue(); 8566 8567 // Since SSE has no unsigned integer comparisons, we need to flip the sign 8568 // bits of the inputs before performing those operations. 8569 if (FlipSigns) { 8570 EVT EltVT = VT.getVectorElementType(); 8571 SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()), 8572 EltVT); 8573 std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit); 8574 SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0], 8575 SignBits.size()); 8576 Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec); 8577 Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec); 8578 } 8579 8580 SDValue Result = DAG.getNode(Opc, dl, VT, Op0, Op1); 8581 8582 // If the logical-not of the result is required, perform that now. 8583 if (Invert) 8584 Result = DAG.getNOT(dl, Result, VT); 8585 8586 return Result; 8587 } 8588 8589 // isX86LogicalCmp - Return true if opcode is a X86 logical comparison. 8590 static bool isX86LogicalCmp(SDValue Op) { 8591 unsigned Opc = Op.getNode()->getOpcode(); 8592 if (Opc == X86ISD::CMP || Opc == X86ISD::COMI || Opc == X86ISD::UCOMI) 8593 return true; 8594 if (Op.getResNo() == 1 && 8595 (Opc == X86ISD::ADD || 8596 Opc == X86ISD::SUB || 8597 Opc == X86ISD::ADC || 8598 Opc == X86ISD::SBB || 8599 Opc == X86ISD::SMUL || 8600 Opc == X86ISD::UMUL || 8601 Opc == X86ISD::INC || 8602 Opc == X86ISD::DEC || 8603 Opc == X86ISD::OR || 8604 Opc == X86ISD::XOR || 8605 Opc == X86ISD::AND)) 8606 return true; 8607 8608 if (Op.getResNo() == 2 && Opc == X86ISD::UMUL) 8609 return true; 8610 8611 return false; 8612 } 8613 8614 static bool isZero(SDValue V) { 8615 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8616 return C && C->isNullValue(); 8617 } 8618 8619 static bool isAllOnes(SDValue V) { 8620 ConstantSDNode *C = dyn_cast<ConstantSDNode>(V); 8621 return C && C->isAllOnesValue(); 8622 } 8623 8624 SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const { 8625 bool addTest = true; 8626 SDValue Cond = Op.getOperand(0); 8627 SDValue Op1 = Op.getOperand(1); 8628 SDValue Op2 = Op.getOperand(2); 8629 DebugLoc DL = Op.getDebugLoc(); 8630 SDValue CC; 8631 8632 if (Cond.getOpcode() == ISD::SETCC) { 8633 SDValue NewCond = LowerSETCC(Cond, DAG); 8634 if (NewCond.getNode()) 8635 Cond = NewCond; 8636 } 8637 8638 // (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 8639 // (select (x == 0), y, -1) -> ~(sign_bit (x - 1)) | y 8640 // (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y 8641 // (select (x != 0), -1, y) -> ~(sign_bit (x - 1)) | y 8642 if (Cond.getOpcode() == X86ISD::SETCC && 8643 Cond.getOperand(1).getOpcode() == X86ISD::CMP && 8644 isZero(Cond.getOperand(1).getOperand(1))) { 8645 SDValue Cmp = Cond.getOperand(1); 8646 8647 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); 8648 8649 if ((isAllOnes(Op1) || isAllOnes(Op2)) && 8650 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { 8651 SDValue Y = isAllOnes(Op2) ? Op1 : Op2; 8652 8653 SDValue CmpOp0 = Cmp.getOperand(0); 8654 Cmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, 8655 CmpOp0, DAG.getConstant(1, CmpOp0.getValueType())); 8656 8657 SDValue Res = // Res = 0 or -1. 8658 DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8659 DAG.getConstant(X86::COND_B, MVT::i8), Cmp); 8660 8661 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) 8662 Res = DAG.getNOT(DL, Res, Res.getValueType()); 8663 8664 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(Op2); 8665 if (N2C == 0 || !N2C->isNullValue()) 8666 Res = DAG.getNode(ISD::OR, DL, Res.getValueType(), Res, Y); 8667 return Res; 8668 } 8669 } 8670 8671 // Look past (and (setcc_carry (cmp ...)), 1). 8672 if (Cond.getOpcode() == ISD::AND && 8673 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8674 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8675 if (C && C->getAPIntValue() == 1) 8676 Cond = Cond.getOperand(0); 8677 } 8678 8679 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8680 // setting operand in place of the X86ISD::SETCC. 8681 if (Cond.getOpcode() == X86ISD::SETCC || 8682 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8683 CC = Cond.getOperand(0); 8684 8685 SDValue Cmp = Cond.getOperand(1); 8686 unsigned Opc = Cmp.getOpcode(); 8687 EVT VT = Op.getValueType(); 8688 8689 bool IllegalFPCMov = false; 8690 if (VT.isFloatingPoint() && !VT.isVector() && 8691 !isScalarFPTypeInSSEReg(VT)) // FPStack? 8692 IllegalFPCMov = !hasFPCMov(cast<ConstantSDNode>(CC)->getSExtValue()); 8693 8694 if ((isX86LogicalCmp(Cmp) && !IllegalFPCMov) || 8695 Opc == X86ISD::BT) { // FIXME 8696 Cond = Cmp; 8697 addTest = false; 8698 } 8699 } 8700 8701 if (addTest) { 8702 // Look pass the truncate. 8703 if (Cond.getOpcode() == ISD::TRUNCATE) 8704 Cond = Cond.getOperand(0); 8705 8706 // We know the result of AND is compared against zero. Try to match 8707 // it to BT. 8708 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8709 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); 8710 if (NewSetCC.getNode()) { 8711 CC = NewSetCC.getOperand(0); 8712 Cond = NewSetCC.getOperand(1); 8713 addTest = false; 8714 } 8715 } 8716 } 8717 8718 if (addTest) { 8719 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8720 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8721 } 8722 8723 // a < b ? -1 : 0 -> RES = ~setcc_carry 8724 // a < b ? 0 : -1 -> RES = setcc_carry 8725 // a >= b ? -1 : 0 -> RES = setcc_carry 8726 // a >= b ? 0 : -1 -> RES = ~setcc_carry 8727 if (Cond.getOpcode() == X86ISD::CMP) { 8728 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); 8729 8730 if ((CondCode == X86::COND_AE || CondCode == X86::COND_B) && 8731 (isAllOnes(Op1) || isAllOnes(Op2)) && (isZero(Op1) || isZero(Op2))) { 8732 SDValue Res = DAG.getNode(X86ISD::SETCC_CARRY, DL, Op.getValueType(), 8733 DAG.getConstant(X86::COND_B, MVT::i8), Cond); 8734 if (isAllOnes(Op1) != (CondCode == X86::COND_B)) 8735 return DAG.getNOT(DL, Res, Res.getValueType()); 8736 return Res; 8737 } 8738 } 8739 8740 // X86ISD::CMOV means set the result (which is operand 1) to the RHS if 8741 // condition is true. 8742 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue); 8743 SDValue Ops[] = { Op2, Op1, CC, Cond }; 8744 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops)); 8745 } 8746 8747 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or 8748 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart 8749 // from the AND / OR. 8750 static bool isAndOrOfSetCCs(SDValue Op, unsigned &Opc) { 8751 Opc = Op.getOpcode(); 8752 if (Opc != ISD::OR && Opc != ISD::AND) 8753 return false; 8754 return (Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8755 Op.getOperand(0).hasOneUse() && 8756 Op.getOperand(1).getOpcode() == X86ISD::SETCC && 8757 Op.getOperand(1).hasOneUse()); 8758 } 8759 8760 // isXor1OfSetCC - Return true if node is an ISD::XOR of a X86ISD::SETCC and 8761 // 1 and that the SETCC node has a single use. 8762 static bool isXor1OfSetCC(SDValue Op) { 8763 if (Op.getOpcode() != ISD::XOR) 8764 return false; 8765 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); 8766 if (N1C && N1C->getAPIntValue() == 1) { 8767 return Op.getOperand(0).getOpcode() == X86ISD::SETCC && 8768 Op.getOperand(0).hasOneUse(); 8769 } 8770 return false; 8771 } 8772 8773 SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const { 8774 bool addTest = true; 8775 SDValue Chain = Op.getOperand(0); 8776 SDValue Cond = Op.getOperand(1); 8777 SDValue Dest = Op.getOperand(2); 8778 DebugLoc dl = Op.getDebugLoc(); 8779 SDValue CC; 8780 8781 if (Cond.getOpcode() == ISD::SETCC) { 8782 SDValue NewCond = LowerSETCC(Cond, DAG); 8783 if (NewCond.getNode()) 8784 Cond = NewCond; 8785 } 8786 #if 0 8787 // FIXME: LowerXALUO doesn't handle these!! 8788 else if (Cond.getOpcode() == X86ISD::ADD || 8789 Cond.getOpcode() == X86ISD::SUB || 8790 Cond.getOpcode() == X86ISD::SMUL || 8791 Cond.getOpcode() == X86ISD::UMUL) 8792 Cond = LowerXALUO(Cond, DAG); 8793 #endif 8794 8795 // Look pass (and (setcc_carry (cmp ...)), 1). 8796 if (Cond.getOpcode() == ISD::AND && 8797 Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) { 8798 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1)); 8799 if (C && C->getAPIntValue() == 1) 8800 Cond = Cond.getOperand(0); 8801 } 8802 8803 // If condition flag is set by a X86ISD::CMP, then use it as the condition 8804 // setting operand in place of the X86ISD::SETCC. 8805 if (Cond.getOpcode() == X86ISD::SETCC || 8806 Cond.getOpcode() == X86ISD::SETCC_CARRY) { 8807 CC = Cond.getOperand(0); 8808 8809 SDValue Cmp = Cond.getOperand(1); 8810 unsigned Opc = Cmp.getOpcode(); 8811 // FIXME: WHY THE SPECIAL CASING OF LogicalCmp?? 8812 if (isX86LogicalCmp(Cmp) || Opc == X86ISD::BT) { 8813 Cond = Cmp; 8814 addTest = false; 8815 } else { 8816 switch (cast<ConstantSDNode>(CC)->getZExtValue()) { 8817 default: break; 8818 case X86::COND_O: 8819 case X86::COND_B: 8820 // These can only come from an arithmetic instruction with overflow, 8821 // e.g. SADDO, UADDO. 8822 Cond = Cond.getNode()->getOperand(1); 8823 addTest = false; 8824 break; 8825 } 8826 } 8827 } else { 8828 unsigned CondOpc; 8829 if (Cond.hasOneUse() && isAndOrOfSetCCs(Cond, CondOpc)) { 8830 SDValue Cmp = Cond.getOperand(0).getOperand(1); 8831 if (CondOpc == ISD::OR) { 8832 // Also, recognize the pattern generated by an FCMP_UNE. We can emit 8833 // two branches instead of an explicit OR instruction with a 8834 // separate test. 8835 if (Cmp == Cond.getOperand(1).getOperand(1) && 8836 isX86LogicalCmp(Cmp)) { 8837 CC = Cond.getOperand(0).getOperand(0); 8838 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8839 Chain, Dest, CC, Cmp); 8840 CC = Cond.getOperand(1).getOperand(0); 8841 Cond = Cmp; 8842 addTest = false; 8843 } 8844 } else { // ISD::AND 8845 // Also, recognize the pattern generated by an FCMP_OEQ. We can emit 8846 // two branches instead of an explicit AND instruction with a 8847 // separate test. However, we only do this if this block doesn't 8848 // have a fall-through edge, because this requires an explicit 8849 // jmp when the condition is false. 8850 if (Cmp == Cond.getOperand(1).getOperand(1) && 8851 isX86LogicalCmp(Cmp) && 8852 Op.getNode()->hasOneUse()) { 8853 X86::CondCode CCode = 8854 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8855 CCode = X86::GetOppositeBranchCondition(CCode); 8856 CC = DAG.getConstant(CCode, MVT::i8); 8857 SDNode *User = *Op.getNode()->use_begin(); 8858 // Look for an unconditional branch following this conditional branch. 8859 // We need this because we need to reverse the successors in order 8860 // to implement FCMP_OEQ. 8861 if (User->getOpcode() == ISD::BR) { 8862 SDValue FalseBB = User->getOperand(1); 8863 SDNode *NewBR = 8864 DAG.UpdateNodeOperands(User, User->getOperand(0), Dest); 8865 assert(NewBR == User); 8866 (void)NewBR; 8867 Dest = FalseBB; 8868 8869 Chain = DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8870 Chain, Dest, CC, Cmp); 8871 X86::CondCode CCode = 8872 (X86::CondCode)Cond.getOperand(1).getConstantOperandVal(0); 8873 CCode = X86::GetOppositeBranchCondition(CCode); 8874 CC = DAG.getConstant(CCode, MVT::i8); 8875 Cond = Cmp; 8876 addTest = false; 8877 } 8878 } 8879 } 8880 } else if (Cond.hasOneUse() && isXor1OfSetCC(Cond)) { 8881 // Recognize for xorb (setcc), 1 patterns. The xor inverts the condition. 8882 // It should be transformed during dag combiner except when the condition 8883 // is set by a arithmetics with overflow node. 8884 X86::CondCode CCode = 8885 (X86::CondCode)Cond.getOperand(0).getConstantOperandVal(0); 8886 CCode = X86::GetOppositeBranchCondition(CCode); 8887 CC = DAG.getConstant(CCode, MVT::i8); 8888 Cond = Cond.getOperand(0).getOperand(1); 8889 addTest = false; 8890 } 8891 } 8892 8893 if (addTest) { 8894 // Look pass the truncate. 8895 if (Cond.getOpcode() == ISD::TRUNCATE) 8896 Cond = Cond.getOperand(0); 8897 8898 // We know the result of AND is compared against zero. Try to match 8899 // it to BT. 8900 if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) { 8901 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); 8902 if (NewSetCC.getNode()) { 8903 CC = NewSetCC.getOperand(0); 8904 Cond = NewSetCC.getOperand(1); 8905 addTest = false; 8906 } 8907 } 8908 } 8909 8910 if (addTest) { 8911 CC = DAG.getConstant(X86::COND_NE, MVT::i8); 8912 Cond = EmitTest(Cond, X86::COND_NE, DAG); 8913 } 8914 return DAG.getNode(X86ISD::BRCOND, dl, Op.getValueType(), 8915 Chain, Dest, CC, Cond); 8916 } 8917 8918 8919 // Lower dynamic stack allocation to _alloca call for Cygwin/Mingw targets. 8920 // Calls to _alloca is needed to probe the stack when allocating more than 4k 8921 // bytes in one go. Touching the stack at 4K increments is necessary to ensure 8922 // that the guard pages used by the OS virtual memory manager are allocated in 8923 // correct sequence. 8924 SDValue 8925 X86TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, 8926 SelectionDAG &DAG) const { 8927 assert((Subtarget->isTargetCygMing() || Subtarget->isTargetWindows() || 8928 EnableSegmentedStacks) && 8929 "This should be used only on Windows targets or when segmented stacks " 8930 "are being used"); 8931 assert(!Subtarget->isTargetEnvMacho() && "Not implemented"); 8932 DebugLoc dl = Op.getDebugLoc(); 8933 8934 // Get the inputs. 8935 SDValue Chain = Op.getOperand(0); 8936 SDValue Size = Op.getOperand(1); 8937 // FIXME: Ensure alignment here 8938 8939 bool Is64Bit = Subtarget->is64Bit(); 8940 EVT SPTy = Is64Bit ? MVT::i64 : MVT::i32; 8941 8942 if (EnableSegmentedStacks) { 8943 MachineFunction &MF = DAG.getMachineFunction(); 8944 MachineRegisterInfo &MRI = MF.getRegInfo(); 8945 8946 if (Is64Bit) { 8947 // The 64 bit implementation of segmented stacks needs to clobber both r10 8948 // r11. This makes it impossible to use it along with nested parameters. 8949 const Function *F = MF.getFunction(); 8950 8951 for (Function::const_arg_iterator I = F->arg_begin(), E = F->arg_end(); 8952 I != E; I++) 8953 if (I->hasNestAttr()) 8954 report_fatal_error("Cannot use segmented stacks with functions that " 8955 "have nested arguments."); 8956 } 8957 8958 const TargetRegisterClass *AddrRegClass = 8959 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); 8960 unsigned Vreg = MRI.createVirtualRegister(AddrRegClass); 8961 Chain = DAG.getCopyToReg(Chain, dl, Vreg, Size); 8962 SDValue Value = DAG.getNode(X86ISD::SEG_ALLOCA, dl, SPTy, Chain, 8963 DAG.getRegister(Vreg, SPTy)); 8964 SDValue Ops1[2] = { Value, Chain }; 8965 return DAG.getMergeValues(Ops1, 2, dl); 8966 } else { 8967 SDValue Flag; 8968 unsigned Reg = (Subtarget->is64Bit() ? X86::RAX : X86::EAX); 8969 8970 Chain = DAG.getCopyToReg(Chain, dl, Reg, Size, Flag); 8971 Flag = Chain.getValue(1); 8972 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); 8973 8974 Chain = DAG.getNode(X86ISD::WIN_ALLOCA, dl, NodeTys, Chain, Flag); 8975 Flag = Chain.getValue(1); 8976 8977 Chain = DAG.getCopyFromReg(Chain, dl, X86StackPtr, SPTy).getValue(1); 8978 8979 SDValue Ops1[2] = { Chain.getValue(0), Chain }; 8980 return DAG.getMergeValues(Ops1, 2, dl); 8981 } 8982 } 8983 8984 SDValue X86TargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { 8985 MachineFunction &MF = DAG.getMachineFunction(); 8986 X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>(); 8987 8988 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 8989 DebugLoc DL = Op.getDebugLoc(); 8990 8991 if (!Subtarget->is64Bit() || Subtarget->isTargetWin64()) { 8992 // vastart just stores the address of the VarArgsFrameIndex slot into the 8993 // memory location argument. 8994 SDValue FR = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 8995 getPointerTy()); 8996 return DAG.getStore(Op.getOperand(0), DL, FR, Op.getOperand(1), 8997 MachinePointerInfo(SV), false, false, 0); 8998 } 8999 9000 // __va_list_tag: 9001 // gp_offset (0 - 6 * 8) 9002 // fp_offset (48 - 48 + 8 * 16) 9003 // overflow_arg_area (point to parameters coming in memory). 9004 // reg_save_area 9005 SmallVector<SDValue, 8> MemOps; 9006 SDValue FIN = Op.getOperand(1); 9007 // Store gp_offset 9008 SDValue Store = DAG.getStore(Op.getOperand(0), DL, 9009 DAG.getConstant(FuncInfo->getVarArgsGPOffset(), 9010 MVT::i32), 9011 FIN, MachinePointerInfo(SV), false, false, 0); 9012 MemOps.push_back(Store); 9013 9014 // Store fp_offset 9015 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9016 FIN, DAG.getIntPtrConstant(4)); 9017 Store = DAG.getStore(Op.getOperand(0), DL, 9018 DAG.getConstant(FuncInfo->getVarArgsFPOffset(), 9019 MVT::i32), 9020 FIN, MachinePointerInfo(SV, 4), false, false, 0); 9021 MemOps.push_back(Store); 9022 9023 // Store ptr to overflow_arg_area 9024 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9025 FIN, DAG.getIntPtrConstant(4)); 9026 SDValue OVFIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), 9027 getPointerTy()); 9028 Store = DAG.getStore(Op.getOperand(0), DL, OVFIN, FIN, 9029 MachinePointerInfo(SV, 8), 9030 false, false, 0); 9031 MemOps.push_back(Store); 9032 9033 // Store ptr to reg_save_area. 9034 FIN = DAG.getNode(ISD::ADD, DL, getPointerTy(), 9035 FIN, DAG.getIntPtrConstant(8)); 9036 SDValue RSFIN = DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), 9037 getPointerTy()); 9038 Store = DAG.getStore(Op.getOperand(0), DL, RSFIN, FIN, 9039 MachinePointerInfo(SV, 16), false, false, 0); 9040 MemOps.push_back(Store); 9041 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, 9042 &MemOps[0], MemOps.size()); 9043 } 9044 9045 SDValue X86TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const { 9046 assert(Subtarget->is64Bit() && 9047 "LowerVAARG only handles 64-bit va_arg!"); 9048 assert((Subtarget->isTargetLinux() || 9049 Subtarget->isTargetDarwin()) && 9050 "Unhandled target in LowerVAARG"); 9051 assert(Op.getNode()->getNumOperands() == 4); 9052 SDValue Chain = Op.getOperand(0); 9053 SDValue SrcPtr = Op.getOperand(1); 9054 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue(); 9055 unsigned Align = Op.getConstantOperandVal(3); 9056 DebugLoc dl = Op.getDebugLoc(); 9057 9058 EVT ArgVT = Op.getNode()->getValueType(0); 9059 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 9060 uint32_t ArgSize = getTargetData()->getTypeAllocSize(ArgTy); 9061 uint8_t ArgMode; 9062 9063 // Decide which area this value should be read from. 9064 // TODO: Implement the AMD64 ABI in its entirety. This simple 9065 // selection mechanism works only for the basic types. 9066 if (ArgVT == MVT::f80) { 9067 llvm_unreachable("va_arg for f80 not yet implemented"); 9068 } else if (ArgVT.isFloatingPoint() && ArgSize <= 16 /*bytes*/) { 9069 ArgMode = 2; // Argument passed in XMM register. Use fp_offset. 9070 } else if (ArgVT.isInteger() && ArgSize <= 32 /*bytes*/) { 9071 ArgMode = 1; // Argument passed in GPR64 register(s). Use gp_offset. 9072 } else { 9073 llvm_unreachable("Unhandled argument type in LowerVAARG"); 9074 } 9075 9076 if (ArgMode == 2) { 9077 // Sanity Check: Make sure using fp_offset makes sense. 9078 assert(!UseSoftFloat && 9079 !(DAG.getMachineFunction() 9080 .getFunction()->hasFnAttr(Attribute::NoImplicitFloat)) && 9081 Subtarget->hasXMM()); 9082 } 9083 9084 // Insert VAARG_64 node into the DAG 9085 // VAARG_64 returns two values: Variable Argument Address, Chain 9086 SmallVector<SDValue, 11> InstOps; 9087 InstOps.push_back(Chain); 9088 InstOps.push_back(SrcPtr); 9089 InstOps.push_back(DAG.getConstant(ArgSize, MVT::i32)); 9090 InstOps.push_back(DAG.getConstant(ArgMode, MVT::i8)); 9091 InstOps.push_back(DAG.getConstant(Align, MVT::i32)); 9092 SDVTList VTs = DAG.getVTList(getPointerTy(), MVT::Other); 9093 SDValue VAARG = DAG.getMemIntrinsicNode(X86ISD::VAARG_64, dl, 9094 VTs, &InstOps[0], InstOps.size(), 9095 MVT::i64, 9096 MachinePointerInfo(SV), 9097 /*Align=*/0, 9098 /*Volatile=*/false, 9099 /*ReadMem=*/true, 9100 /*WriteMem=*/true); 9101 Chain = VAARG.getValue(1); 9102 9103 // Load the next argument and return it 9104 return DAG.getLoad(ArgVT, dl, 9105 Chain, 9106 VAARG, 9107 MachinePointerInfo(), 9108 false, false, 0); 9109 } 9110 9111 SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const { 9112 // X86-64 va_list is a struct { i32, i32, i8*, i8* }. 9113 assert(Subtarget->is64Bit() && "This code only handles 64-bit va_copy!"); 9114 SDValue Chain = Op.getOperand(0); 9115 SDValue DstPtr = Op.getOperand(1); 9116 SDValue SrcPtr = Op.getOperand(2); 9117 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue(); 9118 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9119 DebugLoc DL = Op.getDebugLoc(); 9120 9121 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, 9122 DAG.getIntPtrConstant(24), 8, /*isVolatile*/false, 9123 false, 9124 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV)); 9125 } 9126 9127 SDValue 9128 X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const { 9129 DebugLoc dl = Op.getDebugLoc(); 9130 unsigned IntNo = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9131 switch (IntNo) { 9132 default: return SDValue(); // Don't custom lower most intrinsics. 9133 // Comparison intrinsics. 9134 case Intrinsic::x86_sse_comieq_ss: 9135 case Intrinsic::x86_sse_comilt_ss: 9136 case Intrinsic::x86_sse_comile_ss: 9137 case Intrinsic::x86_sse_comigt_ss: 9138 case Intrinsic::x86_sse_comige_ss: 9139 case Intrinsic::x86_sse_comineq_ss: 9140 case Intrinsic::x86_sse_ucomieq_ss: 9141 case Intrinsic::x86_sse_ucomilt_ss: 9142 case Intrinsic::x86_sse_ucomile_ss: 9143 case Intrinsic::x86_sse_ucomigt_ss: 9144 case Intrinsic::x86_sse_ucomige_ss: 9145 case Intrinsic::x86_sse_ucomineq_ss: 9146 case Intrinsic::x86_sse2_comieq_sd: 9147 case Intrinsic::x86_sse2_comilt_sd: 9148 case Intrinsic::x86_sse2_comile_sd: 9149 case Intrinsic::x86_sse2_comigt_sd: 9150 case Intrinsic::x86_sse2_comige_sd: 9151 case Intrinsic::x86_sse2_comineq_sd: 9152 case Intrinsic::x86_sse2_ucomieq_sd: 9153 case Intrinsic::x86_sse2_ucomilt_sd: 9154 case Intrinsic::x86_sse2_ucomile_sd: 9155 case Intrinsic::x86_sse2_ucomigt_sd: 9156 case Intrinsic::x86_sse2_ucomige_sd: 9157 case Intrinsic::x86_sse2_ucomineq_sd: { 9158 unsigned Opc = 0; 9159 ISD::CondCode CC = ISD::SETCC_INVALID; 9160 switch (IntNo) { 9161 default: break; 9162 case Intrinsic::x86_sse_comieq_ss: 9163 case Intrinsic::x86_sse2_comieq_sd: 9164 Opc = X86ISD::COMI; 9165 CC = ISD::SETEQ; 9166 break; 9167 case Intrinsic::x86_sse_comilt_ss: 9168 case Intrinsic::x86_sse2_comilt_sd: 9169 Opc = X86ISD::COMI; 9170 CC = ISD::SETLT; 9171 break; 9172 case Intrinsic::x86_sse_comile_ss: 9173 case Intrinsic::x86_sse2_comile_sd: 9174 Opc = X86ISD::COMI; 9175 CC = ISD::SETLE; 9176 break; 9177 case Intrinsic::x86_sse_comigt_ss: 9178 case Intrinsic::x86_sse2_comigt_sd: 9179 Opc = X86ISD::COMI; 9180 CC = ISD::SETGT; 9181 break; 9182 case Intrinsic::x86_sse_comige_ss: 9183 case Intrinsic::x86_sse2_comige_sd: 9184 Opc = X86ISD::COMI; 9185 CC = ISD::SETGE; 9186 break; 9187 case Intrinsic::x86_sse_comineq_ss: 9188 case Intrinsic::x86_sse2_comineq_sd: 9189 Opc = X86ISD::COMI; 9190 CC = ISD::SETNE; 9191 break; 9192 case Intrinsic::x86_sse_ucomieq_ss: 9193 case Intrinsic::x86_sse2_ucomieq_sd: 9194 Opc = X86ISD::UCOMI; 9195 CC = ISD::SETEQ; 9196 break; 9197 case Intrinsic::x86_sse_ucomilt_ss: 9198 case Intrinsic::x86_sse2_ucomilt_sd: 9199 Opc = X86ISD::UCOMI; 9200 CC = ISD::SETLT; 9201 break; 9202 case Intrinsic::x86_sse_ucomile_ss: 9203 case Intrinsic::x86_sse2_ucomile_sd: 9204 Opc = X86ISD::UCOMI; 9205 CC = ISD::SETLE; 9206 break; 9207 case Intrinsic::x86_sse_ucomigt_ss: 9208 case Intrinsic::x86_sse2_ucomigt_sd: 9209 Opc = X86ISD::UCOMI; 9210 CC = ISD::SETGT; 9211 break; 9212 case Intrinsic::x86_sse_ucomige_ss: 9213 case Intrinsic::x86_sse2_ucomige_sd: 9214 Opc = X86ISD::UCOMI; 9215 CC = ISD::SETGE; 9216 break; 9217 case Intrinsic::x86_sse_ucomineq_ss: 9218 case Intrinsic::x86_sse2_ucomineq_sd: 9219 Opc = X86ISD::UCOMI; 9220 CC = ISD::SETNE; 9221 break; 9222 } 9223 9224 SDValue LHS = Op.getOperand(1); 9225 SDValue RHS = Op.getOperand(2); 9226 unsigned X86CC = TranslateX86CC(CC, true, LHS, RHS, DAG); 9227 assert(X86CC != X86::COND_INVALID && "Unexpected illegal condition!"); 9228 SDValue Cond = DAG.getNode(Opc, dl, MVT::i32, LHS, RHS); 9229 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, 9230 DAG.getConstant(X86CC, MVT::i8), Cond); 9231 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9232 } 9233 // Arithmetic intrinsics. 9234 case Intrinsic::x86_sse3_hadd_ps: 9235 case Intrinsic::x86_sse3_hadd_pd: 9236 case Intrinsic::x86_avx_hadd_ps_256: 9237 case Intrinsic::x86_avx_hadd_pd_256: 9238 return DAG.getNode(X86ISD::FHADD, dl, Op.getValueType(), 9239 Op.getOperand(1), Op.getOperand(2)); 9240 case Intrinsic::x86_sse3_hsub_ps: 9241 case Intrinsic::x86_sse3_hsub_pd: 9242 case Intrinsic::x86_avx_hsub_ps_256: 9243 case Intrinsic::x86_avx_hsub_pd_256: 9244 return DAG.getNode(X86ISD::FHSUB, dl, Op.getValueType(), 9245 Op.getOperand(1), Op.getOperand(2)); 9246 // ptest and testp intrinsics. The intrinsic these come from are designed to 9247 // return an integer value, not just an instruction so lower it to the ptest 9248 // or testp pattern and a setcc for the result. 9249 case Intrinsic::x86_sse41_ptestz: 9250 case Intrinsic::x86_sse41_ptestc: 9251 case Intrinsic::x86_sse41_ptestnzc: 9252 case Intrinsic::x86_avx_ptestz_256: 9253 case Intrinsic::x86_avx_ptestc_256: 9254 case Intrinsic::x86_avx_ptestnzc_256: 9255 case Intrinsic::x86_avx_vtestz_ps: 9256 case Intrinsic::x86_avx_vtestc_ps: 9257 case Intrinsic::x86_avx_vtestnzc_ps: 9258 case Intrinsic::x86_avx_vtestz_pd: 9259 case Intrinsic::x86_avx_vtestc_pd: 9260 case Intrinsic::x86_avx_vtestnzc_pd: 9261 case Intrinsic::x86_avx_vtestz_ps_256: 9262 case Intrinsic::x86_avx_vtestc_ps_256: 9263 case Intrinsic::x86_avx_vtestnzc_ps_256: 9264 case Intrinsic::x86_avx_vtestz_pd_256: 9265 case Intrinsic::x86_avx_vtestc_pd_256: 9266 case Intrinsic::x86_avx_vtestnzc_pd_256: { 9267 bool IsTestPacked = false; 9268 unsigned X86CC = 0; 9269 switch (IntNo) { 9270 default: llvm_unreachable("Bad fallthrough in Intrinsic lowering."); 9271 case Intrinsic::x86_avx_vtestz_ps: 9272 case Intrinsic::x86_avx_vtestz_pd: 9273 case Intrinsic::x86_avx_vtestz_ps_256: 9274 case Intrinsic::x86_avx_vtestz_pd_256: 9275 IsTestPacked = true; // Fallthrough 9276 case Intrinsic::x86_sse41_ptestz: 9277 case Intrinsic::x86_avx_ptestz_256: 9278 // ZF = 1 9279 X86CC = X86::COND_E; 9280 break; 9281 case Intrinsic::x86_avx_vtestc_ps: 9282 case Intrinsic::x86_avx_vtestc_pd: 9283 case Intrinsic::x86_avx_vtestc_ps_256: 9284 case Intrinsic::x86_avx_vtestc_pd_256: 9285 IsTestPacked = true; // Fallthrough 9286 case Intrinsic::x86_sse41_ptestc: 9287 case Intrinsic::x86_avx_ptestc_256: 9288 // CF = 1 9289 X86CC = X86::COND_B; 9290 break; 9291 case Intrinsic::x86_avx_vtestnzc_ps: 9292 case Intrinsic::x86_avx_vtestnzc_pd: 9293 case Intrinsic::x86_avx_vtestnzc_ps_256: 9294 case Intrinsic::x86_avx_vtestnzc_pd_256: 9295 IsTestPacked = true; // Fallthrough 9296 case Intrinsic::x86_sse41_ptestnzc: 9297 case Intrinsic::x86_avx_ptestnzc_256: 9298 // ZF and CF = 0 9299 X86CC = X86::COND_A; 9300 break; 9301 } 9302 9303 SDValue LHS = Op.getOperand(1); 9304 SDValue RHS = Op.getOperand(2); 9305 unsigned TestOpc = IsTestPacked ? X86ISD::TESTP : X86ISD::PTEST; 9306 SDValue Test = DAG.getNode(TestOpc, dl, MVT::i32, LHS, RHS); 9307 SDValue CC = DAG.getConstant(X86CC, MVT::i8); 9308 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8, CC, Test); 9309 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); 9310 } 9311 9312 // Fix vector shift instructions where the last operand is a non-immediate 9313 // i32 value. 9314 case Intrinsic::x86_sse2_pslli_w: 9315 case Intrinsic::x86_sse2_pslli_d: 9316 case Intrinsic::x86_sse2_pslli_q: 9317 case Intrinsic::x86_sse2_psrli_w: 9318 case Intrinsic::x86_sse2_psrli_d: 9319 case Intrinsic::x86_sse2_psrli_q: 9320 case Intrinsic::x86_sse2_psrai_w: 9321 case Intrinsic::x86_sse2_psrai_d: 9322 case Intrinsic::x86_mmx_pslli_w: 9323 case Intrinsic::x86_mmx_pslli_d: 9324 case Intrinsic::x86_mmx_pslli_q: 9325 case Intrinsic::x86_mmx_psrli_w: 9326 case Intrinsic::x86_mmx_psrli_d: 9327 case Intrinsic::x86_mmx_psrli_q: 9328 case Intrinsic::x86_mmx_psrai_w: 9329 case Intrinsic::x86_mmx_psrai_d: { 9330 SDValue ShAmt = Op.getOperand(2); 9331 if (isa<ConstantSDNode>(ShAmt)) 9332 return SDValue(); 9333 9334 unsigned NewIntNo = 0; 9335 EVT ShAmtVT = MVT::v4i32; 9336 switch (IntNo) { 9337 case Intrinsic::x86_sse2_pslli_w: 9338 NewIntNo = Intrinsic::x86_sse2_psll_w; 9339 break; 9340 case Intrinsic::x86_sse2_pslli_d: 9341 NewIntNo = Intrinsic::x86_sse2_psll_d; 9342 break; 9343 case Intrinsic::x86_sse2_pslli_q: 9344 NewIntNo = Intrinsic::x86_sse2_psll_q; 9345 break; 9346 case Intrinsic::x86_sse2_psrli_w: 9347 NewIntNo = Intrinsic::x86_sse2_psrl_w; 9348 break; 9349 case Intrinsic::x86_sse2_psrli_d: 9350 NewIntNo = Intrinsic::x86_sse2_psrl_d; 9351 break; 9352 case Intrinsic::x86_sse2_psrli_q: 9353 NewIntNo = Intrinsic::x86_sse2_psrl_q; 9354 break; 9355 case Intrinsic::x86_sse2_psrai_w: 9356 NewIntNo = Intrinsic::x86_sse2_psra_w; 9357 break; 9358 case Intrinsic::x86_sse2_psrai_d: 9359 NewIntNo = Intrinsic::x86_sse2_psra_d; 9360 break; 9361 default: { 9362 ShAmtVT = MVT::v2i32; 9363 switch (IntNo) { 9364 case Intrinsic::x86_mmx_pslli_w: 9365 NewIntNo = Intrinsic::x86_mmx_psll_w; 9366 break; 9367 case Intrinsic::x86_mmx_pslli_d: 9368 NewIntNo = Intrinsic::x86_mmx_psll_d; 9369 break; 9370 case Intrinsic::x86_mmx_pslli_q: 9371 NewIntNo = Intrinsic::x86_mmx_psll_q; 9372 break; 9373 case Intrinsic::x86_mmx_psrli_w: 9374 NewIntNo = Intrinsic::x86_mmx_psrl_w; 9375 break; 9376 case Intrinsic::x86_mmx_psrli_d: 9377 NewIntNo = Intrinsic::x86_mmx_psrl_d; 9378 break; 9379 case Intrinsic::x86_mmx_psrli_q: 9380 NewIntNo = Intrinsic::x86_mmx_psrl_q; 9381 break; 9382 case Intrinsic::x86_mmx_psrai_w: 9383 NewIntNo = Intrinsic::x86_mmx_psra_w; 9384 break; 9385 case Intrinsic::x86_mmx_psrai_d: 9386 NewIntNo = Intrinsic::x86_mmx_psra_d; 9387 break; 9388 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 9389 } 9390 break; 9391 } 9392 } 9393 9394 // The vector shift intrinsics with scalars uses 32b shift amounts but 9395 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 9396 // to be zero. 9397 SDValue ShOps[4]; 9398 ShOps[0] = ShAmt; 9399 ShOps[1] = DAG.getConstant(0, MVT::i32); 9400 if (ShAmtVT == MVT::v4i32) { 9401 ShOps[2] = DAG.getUNDEF(MVT::i32); 9402 ShOps[3] = DAG.getUNDEF(MVT::i32); 9403 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4); 9404 } else { 9405 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 9406 // FIXME this must be lowered to get rid of the invalid type. 9407 } 9408 9409 EVT VT = Op.getValueType(); 9410 ShAmt = DAG.getNode(ISD::BITCAST, dl, VT, ShAmt); 9411 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9412 DAG.getConstant(NewIntNo, MVT::i32), 9413 Op.getOperand(1), ShAmt); 9414 } 9415 } 9416 } 9417 9418 SDValue X86TargetLowering::LowerRETURNADDR(SDValue Op, 9419 SelectionDAG &DAG) const { 9420 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9421 MFI->setReturnAddressIsTaken(true); 9422 9423 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9424 DebugLoc dl = Op.getDebugLoc(); 9425 9426 if (Depth > 0) { 9427 SDValue FrameAddr = LowerFRAMEADDR(Op, DAG); 9428 SDValue Offset = 9429 DAG.getConstant(TD->getPointerSize(), 9430 Subtarget->is64Bit() ? MVT::i64 : MVT::i32); 9431 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9432 DAG.getNode(ISD::ADD, dl, getPointerTy(), 9433 FrameAddr, Offset), 9434 MachinePointerInfo(), false, false, 0); 9435 } 9436 9437 // Just load the return address. 9438 SDValue RetAddrFI = getReturnAddressFrameIndex(DAG); 9439 return DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), 9440 RetAddrFI, MachinePointerInfo(), false, false, 0); 9441 } 9442 9443 SDValue X86TargetLowering::LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const { 9444 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 9445 MFI->setFrameAddressIsTaken(true); 9446 9447 EVT VT = Op.getValueType(); 9448 DebugLoc dl = Op.getDebugLoc(); // FIXME probably not meaningful 9449 unsigned Depth = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 9450 unsigned FrameReg = Subtarget->is64Bit() ? X86::RBP : X86::EBP; 9451 SDValue FrameAddr = DAG.getCopyFromReg(DAG.getEntryNode(), dl, FrameReg, VT); 9452 while (Depth--) 9453 FrameAddr = DAG.getLoad(VT, dl, DAG.getEntryNode(), FrameAddr, 9454 MachinePointerInfo(), 9455 false, false, 0); 9456 return FrameAddr; 9457 } 9458 9459 SDValue X86TargetLowering::LowerFRAME_TO_ARGS_OFFSET(SDValue Op, 9460 SelectionDAG &DAG) const { 9461 return DAG.getIntPtrConstant(2*TD->getPointerSize()); 9462 } 9463 9464 SDValue X86TargetLowering::LowerEH_RETURN(SDValue Op, SelectionDAG &DAG) const { 9465 MachineFunction &MF = DAG.getMachineFunction(); 9466 SDValue Chain = Op.getOperand(0); 9467 SDValue Offset = Op.getOperand(1); 9468 SDValue Handler = Op.getOperand(2); 9469 DebugLoc dl = Op.getDebugLoc(); 9470 9471 SDValue Frame = DAG.getCopyFromReg(DAG.getEntryNode(), dl, 9472 Subtarget->is64Bit() ? X86::RBP : X86::EBP, 9473 getPointerTy()); 9474 unsigned StoreAddrReg = (Subtarget->is64Bit() ? X86::RCX : X86::ECX); 9475 9476 SDValue StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), Frame, 9477 DAG.getIntPtrConstant(TD->getPointerSize())); 9478 StoreAddr = DAG.getNode(ISD::ADD, dl, getPointerTy(), StoreAddr, Offset); 9479 Chain = DAG.getStore(Chain, dl, Handler, StoreAddr, MachinePointerInfo(), 9480 false, false, 0); 9481 Chain = DAG.getCopyToReg(Chain, dl, StoreAddrReg, StoreAddr); 9482 MF.getRegInfo().addLiveOut(StoreAddrReg); 9483 9484 return DAG.getNode(X86ISD::EH_RETURN, dl, 9485 MVT::Other, 9486 Chain, DAG.getRegister(StoreAddrReg, getPointerTy())); 9487 } 9488 9489 SDValue X86TargetLowering::LowerADJUST_TRAMPOLINE(SDValue Op, 9490 SelectionDAG &DAG) const { 9491 return Op.getOperand(0); 9492 } 9493 9494 SDValue X86TargetLowering::LowerINIT_TRAMPOLINE(SDValue Op, 9495 SelectionDAG &DAG) const { 9496 SDValue Root = Op.getOperand(0); 9497 SDValue Trmp = Op.getOperand(1); // trampoline 9498 SDValue FPtr = Op.getOperand(2); // nested function 9499 SDValue Nest = Op.getOperand(3); // 'nest' parameter value 9500 DebugLoc dl = Op.getDebugLoc(); 9501 9502 const Value *TrmpAddr = cast<SrcValueSDNode>(Op.getOperand(4))->getValue(); 9503 9504 if (Subtarget->is64Bit()) { 9505 SDValue OutChains[6]; 9506 9507 // Large code-model. 9508 const unsigned char JMP64r = 0xFF; // 64-bit jmp through register opcode. 9509 const unsigned char MOV64ri = 0xB8; // X86::MOV64ri opcode. 9510 9511 const unsigned char N86R10 = X86_MC::getX86RegNum(X86::R10); 9512 const unsigned char N86R11 = X86_MC::getX86RegNum(X86::R11); 9513 9514 const unsigned char REX_WB = 0x40 | 0x08 | 0x01; // REX prefix 9515 9516 // Load the pointer to the nested function into R11. 9517 unsigned OpCode = ((MOV64ri | N86R11) << 8) | REX_WB; // movabsq r11 9518 SDValue Addr = Trmp; 9519 OutChains[0] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9520 Addr, MachinePointerInfo(TrmpAddr), 9521 false, false, 0); 9522 9523 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9524 DAG.getConstant(2, MVT::i64)); 9525 OutChains[1] = DAG.getStore(Root, dl, FPtr, Addr, 9526 MachinePointerInfo(TrmpAddr, 2), 9527 false, false, 2); 9528 9529 // Load the 'nest' parameter value into R10. 9530 // R10 is specified in X86CallingConv.td 9531 OpCode = ((MOV64ri | N86R10) << 8) | REX_WB; // movabsq r10 9532 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9533 DAG.getConstant(10, MVT::i64)); 9534 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9535 Addr, MachinePointerInfo(TrmpAddr, 10), 9536 false, false, 0); 9537 9538 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9539 DAG.getConstant(12, MVT::i64)); 9540 OutChains[3] = DAG.getStore(Root, dl, Nest, Addr, 9541 MachinePointerInfo(TrmpAddr, 12), 9542 false, false, 2); 9543 9544 // Jump to the nested function. 9545 OpCode = (JMP64r << 8) | REX_WB; // jmpq *... 9546 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9547 DAG.getConstant(20, MVT::i64)); 9548 OutChains[4] = DAG.getStore(Root, dl, DAG.getConstant(OpCode, MVT::i16), 9549 Addr, MachinePointerInfo(TrmpAddr, 20), 9550 false, false, 0); 9551 9552 unsigned char ModRM = N86R11 | (4 << 3) | (3 << 6); // ...r11 9553 Addr = DAG.getNode(ISD::ADD, dl, MVT::i64, Trmp, 9554 DAG.getConstant(22, MVT::i64)); 9555 OutChains[5] = DAG.getStore(Root, dl, DAG.getConstant(ModRM, MVT::i8), Addr, 9556 MachinePointerInfo(TrmpAddr, 22), 9557 false, false, 0); 9558 9559 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 6); 9560 } else { 9561 const Function *Func = 9562 cast<Function>(cast<SrcValueSDNode>(Op.getOperand(5))->getValue()); 9563 CallingConv::ID CC = Func->getCallingConv(); 9564 unsigned NestReg; 9565 9566 switch (CC) { 9567 default: 9568 llvm_unreachable("Unsupported calling convention"); 9569 case CallingConv::C: 9570 case CallingConv::X86_StdCall: { 9571 // Pass 'nest' parameter in ECX. 9572 // Must be kept in sync with X86CallingConv.td 9573 NestReg = X86::ECX; 9574 9575 // Check that ECX wasn't needed by an 'inreg' parameter. 9576 FunctionType *FTy = Func->getFunctionType(); 9577 const AttrListPtr &Attrs = Func->getAttributes(); 9578 9579 if (!Attrs.isEmpty() && !Func->isVarArg()) { 9580 unsigned InRegCount = 0; 9581 unsigned Idx = 1; 9582 9583 for (FunctionType::param_iterator I = FTy->param_begin(), 9584 E = FTy->param_end(); I != E; ++I, ++Idx) 9585 if (Attrs.paramHasAttr(Idx, Attribute::InReg)) 9586 // FIXME: should only count parameters that are lowered to integers. 9587 InRegCount += (TD->getTypeSizeInBits(*I) + 31) / 32; 9588 9589 if (InRegCount > 2) { 9590 report_fatal_error("Nest register in use - reduce number of inreg" 9591 " parameters!"); 9592 } 9593 } 9594 break; 9595 } 9596 case CallingConv::X86_FastCall: 9597 case CallingConv::X86_ThisCall: 9598 case CallingConv::Fast: 9599 // Pass 'nest' parameter in EAX. 9600 // Must be kept in sync with X86CallingConv.td 9601 NestReg = X86::EAX; 9602 break; 9603 } 9604 9605 SDValue OutChains[4]; 9606 SDValue Addr, Disp; 9607 9608 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9609 DAG.getConstant(10, MVT::i32)); 9610 Disp = DAG.getNode(ISD::SUB, dl, MVT::i32, FPtr, Addr); 9611 9612 // This is storing the opcode for MOV32ri. 9613 const unsigned char MOV32ri = 0xB8; // X86::MOV32ri's opcode byte. 9614 const unsigned char N86Reg = X86_MC::getX86RegNum(NestReg); 9615 OutChains[0] = DAG.getStore(Root, dl, 9616 DAG.getConstant(MOV32ri|N86Reg, MVT::i8), 9617 Trmp, MachinePointerInfo(TrmpAddr), 9618 false, false, 0); 9619 9620 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9621 DAG.getConstant(1, MVT::i32)); 9622 OutChains[1] = DAG.getStore(Root, dl, Nest, Addr, 9623 MachinePointerInfo(TrmpAddr, 1), 9624 false, false, 1); 9625 9626 const unsigned char JMP = 0xE9; // jmp <32bit dst> opcode. 9627 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9628 DAG.getConstant(5, MVT::i32)); 9629 OutChains[2] = DAG.getStore(Root, dl, DAG.getConstant(JMP, MVT::i8), Addr, 9630 MachinePointerInfo(TrmpAddr, 5), 9631 false, false, 1); 9632 9633 Addr = DAG.getNode(ISD::ADD, dl, MVT::i32, Trmp, 9634 DAG.getConstant(6, MVT::i32)); 9635 OutChains[3] = DAG.getStore(Root, dl, Disp, Addr, 9636 MachinePointerInfo(TrmpAddr, 6), 9637 false, false, 1); 9638 9639 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains, 4); 9640 } 9641 } 9642 9643 SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op, 9644 SelectionDAG &DAG) const { 9645 /* 9646 The rounding mode is in bits 11:10 of FPSR, and has the following 9647 settings: 9648 00 Round to nearest 9649 01 Round to -inf 9650 10 Round to +inf 9651 11 Round to 0 9652 9653 FLT_ROUNDS, on the other hand, expects the following: 9654 -1 Undefined 9655 0 Round to 0 9656 1 Round to nearest 9657 2 Round to +inf 9658 3 Round to -inf 9659 9660 To perform the conversion, we do: 9661 (((((FPSR & 0x800) >> 11) | ((FPSR & 0x400) >> 9)) + 1) & 3) 9662 */ 9663 9664 MachineFunction &MF = DAG.getMachineFunction(); 9665 const TargetMachine &TM = MF.getTarget(); 9666 const TargetFrameLowering &TFI = *TM.getFrameLowering(); 9667 unsigned StackAlignment = TFI.getStackAlignment(); 9668 EVT VT = Op.getValueType(); 9669 DebugLoc DL = Op.getDebugLoc(); 9670 9671 // Save FP Control Word to stack slot 9672 int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false); 9673 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy()); 9674 9675 9676 MachineMemOperand *MMO = 9677 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI), 9678 MachineMemOperand::MOStore, 2, 2); 9679 9680 SDValue Ops[] = { DAG.getEntryNode(), StackSlot }; 9681 SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL, 9682 DAG.getVTList(MVT::Other), 9683 Ops, 2, MVT::i16, MMO); 9684 9685 // Load FP Control Word from stack slot 9686 SDValue CWD = DAG.getLoad(MVT::i16, DL, Chain, StackSlot, 9687 MachinePointerInfo(), false, false, 0); 9688 9689 // Transform as necessary 9690 SDValue CWD1 = 9691 DAG.getNode(ISD::SRL, DL, MVT::i16, 9692 DAG.getNode(ISD::AND, DL, MVT::i16, 9693 CWD, DAG.getConstant(0x800, MVT::i16)), 9694 DAG.getConstant(11, MVT::i8)); 9695 SDValue CWD2 = 9696 DAG.getNode(ISD::SRL, DL, MVT::i16, 9697 DAG.getNode(ISD::AND, DL, MVT::i16, 9698 CWD, DAG.getConstant(0x400, MVT::i16)), 9699 DAG.getConstant(9, MVT::i8)); 9700 9701 SDValue RetVal = 9702 DAG.getNode(ISD::AND, DL, MVT::i16, 9703 DAG.getNode(ISD::ADD, DL, MVT::i16, 9704 DAG.getNode(ISD::OR, DL, MVT::i16, CWD1, CWD2), 9705 DAG.getConstant(1, MVT::i16)), 9706 DAG.getConstant(3, MVT::i16)); 9707 9708 9709 return DAG.getNode((VT.getSizeInBits() < 16 ? 9710 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); 9711 } 9712 9713 SDValue X86TargetLowering::LowerCTLZ(SDValue Op, SelectionDAG &DAG) const { 9714 EVT VT = Op.getValueType(); 9715 EVT OpVT = VT; 9716 unsigned NumBits = VT.getSizeInBits(); 9717 DebugLoc dl = Op.getDebugLoc(); 9718 9719 Op = Op.getOperand(0); 9720 if (VT == MVT::i8) { 9721 // Zero extend to i32 since there is not an i8 bsr. 9722 OpVT = MVT::i32; 9723 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9724 } 9725 9726 // Issue a bsr (scan bits in reverse) which also sets EFLAGS. 9727 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9728 Op = DAG.getNode(X86ISD::BSR, dl, VTs, Op); 9729 9730 // If src is zero (i.e. bsr sets ZF), returns NumBits. 9731 SDValue Ops[] = { 9732 Op, 9733 DAG.getConstant(NumBits+NumBits-1, OpVT), 9734 DAG.getConstant(X86::COND_E, MVT::i8), 9735 Op.getValue(1) 9736 }; 9737 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9738 9739 // Finally xor with NumBits-1. 9740 Op = DAG.getNode(ISD::XOR, dl, OpVT, Op, DAG.getConstant(NumBits-1, OpVT)); 9741 9742 if (VT == MVT::i8) 9743 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9744 return Op; 9745 } 9746 9747 SDValue X86TargetLowering::LowerCTTZ(SDValue Op, SelectionDAG &DAG) const { 9748 EVT VT = Op.getValueType(); 9749 EVT OpVT = VT; 9750 unsigned NumBits = VT.getSizeInBits(); 9751 DebugLoc dl = Op.getDebugLoc(); 9752 9753 Op = Op.getOperand(0); 9754 if (VT == MVT::i8) { 9755 OpVT = MVT::i32; 9756 Op = DAG.getNode(ISD::ZERO_EXTEND, dl, OpVT, Op); 9757 } 9758 9759 // Issue a bsf (scan bits forward) which also sets EFLAGS. 9760 SDVTList VTs = DAG.getVTList(OpVT, MVT::i32); 9761 Op = DAG.getNode(X86ISD::BSF, dl, VTs, Op); 9762 9763 // If src is zero (i.e. bsf sets ZF), returns NumBits. 9764 SDValue Ops[] = { 9765 Op, 9766 DAG.getConstant(NumBits, OpVT), 9767 DAG.getConstant(X86::COND_E, MVT::i8), 9768 Op.getValue(1) 9769 }; 9770 Op = DAG.getNode(X86ISD::CMOV, dl, OpVT, Ops, array_lengthof(Ops)); 9771 9772 if (VT == MVT::i8) 9773 Op = DAG.getNode(ISD::TRUNCATE, dl, MVT::i8, Op); 9774 return Op; 9775 } 9776 9777 // Lower256IntArith - Break a 256-bit integer operation into two new 128-bit 9778 // ones, and then concatenate the result back. 9779 static SDValue Lower256IntArith(SDValue Op, SelectionDAG &DAG) { 9780 EVT VT = Op.getValueType(); 9781 9782 assert(VT.getSizeInBits() == 256 && VT.isInteger() && 9783 "Unsupported value type for operation"); 9784 9785 int NumElems = VT.getVectorNumElements(); 9786 DebugLoc dl = Op.getDebugLoc(); 9787 SDValue Idx0 = DAG.getConstant(0, MVT::i32); 9788 SDValue Idx1 = DAG.getConstant(NumElems/2, MVT::i32); 9789 9790 // Extract the LHS vectors 9791 SDValue LHS = Op.getOperand(0); 9792 SDValue LHS1 = Extract128BitVector(LHS, Idx0, DAG, dl); 9793 SDValue LHS2 = Extract128BitVector(LHS, Idx1, DAG, dl); 9794 9795 // Extract the RHS vectors 9796 SDValue RHS = Op.getOperand(1); 9797 SDValue RHS1 = Extract128BitVector(RHS, Idx0, DAG, dl); 9798 SDValue RHS2 = Extract128BitVector(RHS, Idx1, DAG, dl); 9799 9800 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9801 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9802 9803 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, 9804 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS1, RHS1), 9805 DAG.getNode(Op.getOpcode(), dl, NewVT, LHS2, RHS2)); 9806 } 9807 9808 SDValue X86TargetLowering::LowerADD(SDValue Op, SelectionDAG &DAG) const { 9809 assert(Op.getValueType().getSizeInBits() == 256 && 9810 Op.getValueType().isInteger() && 9811 "Only handle AVX 256-bit vector integer operation"); 9812 return Lower256IntArith(Op, DAG); 9813 } 9814 9815 SDValue X86TargetLowering::LowerSUB(SDValue Op, SelectionDAG &DAG) const { 9816 assert(Op.getValueType().getSizeInBits() == 256 && 9817 Op.getValueType().isInteger() && 9818 "Only handle AVX 256-bit vector integer operation"); 9819 return Lower256IntArith(Op, DAG); 9820 } 9821 9822 SDValue X86TargetLowering::LowerMUL(SDValue Op, SelectionDAG &DAG) const { 9823 EVT VT = Op.getValueType(); 9824 9825 // Decompose 256-bit ops into smaller 128-bit ops. 9826 if (VT.getSizeInBits() == 256) 9827 return Lower256IntArith(Op, DAG); 9828 9829 assert(VT == MVT::v2i64 && "Only know how to lower V2I64 multiply"); 9830 DebugLoc dl = Op.getDebugLoc(); 9831 9832 // ulong2 Ahi = __builtin_ia32_psrlqi128( a, 32); 9833 // ulong2 Bhi = __builtin_ia32_psrlqi128( b, 32); 9834 // ulong2 AloBlo = __builtin_ia32_pmuludq128( a, b ); 9835 // ulong2 AloBhi = __builtin_ia32_pmuludq128( a, Bhi ); 9836 // ulong2 AhiBlo = __builtin_ia32_pmuludq128( Ahi, b ); 9837 // 9838 // AloBhi = __builtin_ia32_psllqi128( AloBhi, 32 ); 9839 // AhiBlo = __builtin_ia32_psllqi128( AhiBlo, 32 ); 9840 // return AloBlo + AloBhi + AhiBlo; 9841 9842 SDValue A = Op.getOperand(0); 9843 SDValue B = Op.getOperand(1); 9844 9845 SDValue Ahi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9846 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9847 A, DAG.getConstant(32, MVT::i32)); 9848 SDValue Bhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9849 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9850 B, DAG.getConstant(32, MVT::i32)); 9851 SDValue AloBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9852 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9853 A, B); 9854 SDValue AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9855 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9856 A, Bhi); 9857 SDValue AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9858 DAG.getConstant(Intrinsic::x86_sse2_pmulu_dq, MVT::i32), 9859 Ahi, B); 9860 AloBhi = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9861 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9862 AloBhi, DAG.getConstant(32, MVT::i32)); 9863 AhiBlo = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9864 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9865 AhiBlo, DAG.getConstant(32, MVT::i32)); 9866 SDValue Res = DAG.getNode(ISD::ADD, dl, VT, AloBlo, AloBhi); 9867 Res = DAG.getNode(ISD::ADD, dl, VT, Res, AhiBlo); 9868 return Res; 9869 } 9870 9871 SDValue X86TargetLowering::LowerShift(SDValue Op, SelectionDAG &DAG) const { 9872 9873 EVT VT = Op.getValueType(); 9874 DebugLoc dl = Op.getDebugLoc(); 9875 SDValue R = Op.getOperand(0); 9876 SDValue Amt = Op.getOperand(1); 9877 LLVMContext *Context = DAG.getContext(); 9878 9879 if (!Subtarget->hasXMMInt()) 9880 return SDValue(); 9881 9882 // Decompose 256-bit shifts into smaller 128-bit shifts. 9883 if (VT.getSizeInBits() == 256) { 9884 int NumElems = VT.getVectorNumElements(); 9885 MVT EltVT = VT.getVectorElementType().getSimpleVT(); 9886 EVT NewVT = MVT::getVectorVT(EltVT, NumElems/2); 9887 9888 // Extract the two vectors 9889 SDValue V1 = Extract128BitVector(R, DAG.getConstant(0, MVT::i32), DAG, dl); 9890 SDValue V2 = Extract128BitVector(R, DAG.getConstant(NumElems/2, MVT::i32), 9891 DAG, dl); 9892 9893 // Recreate the shift amount vectors 9894 SDValue Amt1, Amt2; 9895 if (Amt.getOpcode() == ISD::BUILD_VECTOR) { 9896 // Constant shift amount 9897 SmallVector<SDValue, 4> Amt1Csts; 9898 SmallVector<SDValue, 4> Amt2Csts; 9899 for (int i = 0; i < NumElems/2; ++i) 9900 Amt1Csts.push_back(Amt->getOperand(i)); 9901 for (int i = NumElems/2; i < NumElems; ++i) 9902 Amt2Csts.push_back(Amt->getOperand(i)); 9903 9904 Amt1 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9905 &Amt1Csts[0], NumElems/2); 9906 Amt2 = DAG.getNode(ISD::BUILD_VECTOR, dl, NewVT, 9907 &Amt2Csts[0], NumElems/2); 9908 } else { 9909 // Variable shift amount 9910 Amt1 = Extract128BitVector(Amt, DAG.getConstant(0, MVT::i32), DAG, dl); 9911 Amt2 = Extract128BitVector(Amt, DAG.getConstant(NumElems/2, MVT::i32), 9912 DAG, dl); 9913 } 9914 9915 // Issue new vector shifts for the smaller types 9916 V1 = DAG.getNode(Op.getOpcode(), dl, NewVT, V1, Amt1); 9917 V2 = DAG.getNode(Op.getOpcode(), dl, NewVT, V2, Amt2); 9918 9919 // Concatenate the result back 9920 return DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, V1, V2); 9921 } 9922 9923 // Optimize shl/srl/sra with constant shift amount. 9924 if (isSplatVector(Amt.getNode())) { 9925 SDValue SclrAmt = Amt->getOperand(0); 9926 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(SclrAmt)) { 9927 uint64_t ShiftAmt = C->getZExtValue(); 9928 9929 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SHL) 9930 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9931 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 9932 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9933 9934 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SHL) 9935 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9936 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9937 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9938 9939 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SHL) 9940 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9941 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9942 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9943 9944 if (VT == MVT::v2i64 && Op.getOpcode() == ISD::SRL) 9945 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9946 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 9947 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9948 9949 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRL) 9950 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9951 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 9952 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9953 9954 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRL) 9955 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9956 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 9957 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9958 9959 if (VT == MVT::v4i32 && Op.getOpcode() == ISD::SRA) 9960 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9961 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 9962 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9963 9964 if (VT == MVT::v8i16 && Op.getOpcode() == ISD::SRA) 9965 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9966 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 9967 R, DAG.getConstant(ShiftAmt, MVT::i32)); 9968 } 9969 } 9970 9971 // Lower SHL with variable shift amount. 9972 if (VT == MVT::v4i32 && Op->getOpcode() == ISD::SHL) { 9973 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9974 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 9975 Op.getOperand(1), DAG.getConstant(23, MVT::i32)); 9976 9977 ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U)); 9978 9979 std::vector<Constant*> CV(4, CI); 9980 Constant *C = ConstantVector::get(CV); 9981 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 9982 SDValue Addend = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 9983 MachinePointerInfo::getConstantPool(), 9984 false, false, 16); 9985 9986 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Addend); 9987 Op = DAG.getNode(ISD::BITCAST, dl, MVT::v4f32, Op); 9988 Op = DAG.getNode(ISD::FP_TO_SINT, dl, VT, Op); 9989 return DAG.getNode(ISD::MUL, dl, VT, Op, R); 9990 } 9991 if (VT == MVT::v16i8 && Op->getOpcode() == ISD::SHL) { 9992 // a = a << 5; 9993 Op = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 9994 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 9995 Op.getOperand(1), DAG.getConstant(5, MVT::i32)); 9996 9997 ConstantInt *CM1 = ConstantInt::get(*Context, APInt(8, 15)); 9998 ConstantInt *CM2 = ConstantInt::get(*Context, APInt(8, 63)); 9999 10000 std::vector<Constant*> CVM1(16, CM1); 10001 std::vector<Constant*> CVM2(16, CM2); 10002 Constant *C = ConstantVector::get(CVM1); 10003 SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10004 SDValue M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10005 MachinePointerInfo::getConstantPool(), 10006 false, false, 16); 10007 10008 // r = pblendv(r, psllw(r & (char16)15, 4), a); 10009 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10010 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10011 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10012 DAG.getConstant(4, MVT::i32)); 10013 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10014 // a += a 10015 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10016 10017 C = ConstantVector::get(CVM2); 10018 CPIdx = DAG.getConstantPool(C, getPointerTy(), 16); 10019 M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 10020 MachinePointerInfo::getConstantPool(), 10021 false, false, 16); 10022 10023 // r = pblendv(r, psllw(r & (char16)63, 2), a); 10024 M = DAG.getNode(ISD::AND, dl, VT, R, M); 10025 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10026 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M, 10027 DAG.getConstant(2, MVT::i32)); 10028 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M); 10029 // a += a 10030 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op); 10031 10032 // return pblendv(r, r+r, a); 10033 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, 10034 R, DAG.getNode(ISD::ADD, dl, VT, R, R)); 10035 return R; 10036 } 10037 return SDValue(); 10038 } 10039 10040 SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const { 10041 // Lower the "add/sub/mul with overflow" instruction into a regular ins plus 10042 // a "setcc" instruction that checks the overflow flag. The "brcond" lowering 10043 // looks for this combo and may remove the "setcc" instruction if the "setcc" 10044 // has only one use. 10045 SDNode *N = Op.getNode(); 10046 SDValue LHS = N->getOperand(0); 10047 SDValue RHS = N->getOperand(1); 10048 unsigned BaseOp = 0; 10049 unsigned Cond = 0; 10050 DebugLoc DL = Op.getDebugLoc(); 10051 switch (Op.getOpcode()) { 10052 default: llvm_unreachable("Unknown ovf instruction!"); 10053 case ISD::SADDO: 10054 // A subtract of one will be selected as a INC. Note that INC doesn't 10055 // set CF, so we can't do this for UADDO. 10056 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10057 if (C->isOne()) { 10058 BaseOp = X86ISD::INC; 10059 Cond = X86::COND_O; 10060 break; 10061 } 10062 BaseOp = X86ISD::ADD; 10063 Cond = X86::COND_O; 10064 break; 10065 case ISD::UADDO: 10066 BaseOp = X86ISD::ADD; 10067 Cond = X86::COND_B; 10068 break; 10069 case ISD::SSUBO: 10070 // A subtract of one will be selected as a DEC. Note that DEC doesn't 10071 // set CF, so we can't do this for USUBO. 10072 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(RHS)) 10073 if (C->isOne()) { 10074 BaseOp = X86ISD::DEC; 10075 Cond = X86::COND_O; 10076 break; 10077 } 10078 BaseOp = X86ISD::SUB; 10079 Cond = X86::COND_O; 10080 break; 10081 case ISD::USUBO: 10082 BaseOp = X86ISD::SUB; 10083 Cond = X86::COND_B; 10084 break; 10085 case ISD::SMULO: 10086 BaseOp = X86ISD::SMUL; 10087 Cond = X86::COND_O; 10088 break; 10089 case ISD::UMULO: { // i64, i8 = umulo lhs, rhs --> i64, i64, i32 umul lhs,rhs 10090 SDVTList VTs = DAG.getVTList(N->getValueType(0), N->getValueType(0), 10091 MVT::i32); 10092 SDValue Sum = DAG.getNode(X86ISD::UMUL, DL, VTs, LHS, RHS); 10093 10094 SDValue SetCC = 10095 DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 10096 DAG.getConstant(X86::COND_O, MVT::i32), 10097 SDValue(Sum.getNode(), 2)); 10098 10099 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10100 } 10101 } 10102 10103 // Also sets EFLAGS. 10104 SDVTList VTs = DAG.getVTList(N->getValueType(0), MVT::i32); 10105 SDValue Sum = DAG.getNode(BaseOp, DL, VTs, LHS, RHS); 10106 10107 SDValue SetCC = 10108 DAG.getNode(X86ISD::SETCC, DL, N->getValueType(1), 10109 DAG.getConstant(Cond, MVT::i32), 10110 SDValue(Sum.getNode(), 1)); 10111 10112 return DAG.getNode(ISD::MERGE_VALUES, DL, N->getVTList(), Sum, SetCC); 10113 } 10114 10115 SDValue X86TargetLowering::LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const{ 10116 DebugLoc dl = Op.getDebugLoc(); 10117 SDNode* Node = Op.getNode(); 10118 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 10119 EVT VT = Node->getValueType(0); 10120 if (Subtarget->hasXMMInt() && VT.isVector()) { 10121 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 10122 ExtraVT.getScalarType().getSizeInBits(); 10123 SDValue ShAmt = DAG.getConstant(BitsDiff, MVT::i32); 10124 10125 unsigned SHLIntrinsicsID = 0; 10126 unsigned SRAIntrinsicsID = 0; 10127 switch (VT.getSimpleVT().SimpleTy) { 10128 default: 10129 return SDValue(); 10130 case MVT::v4i32: { 10131 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_d; 10132 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_d; 10133 break; 10134 } 10135 case MVT::v8i16: { 10136 SHLIntrinsicsID = Intrinsic::x86_sse2_pslli_w; 10137 SRAIntrinsicsID = Intrinsic::x86_sse2_psrai_w; 10138 break; 10139 } 10140 } 10141 10142 SDValue Tmp1 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10143 DAG.getConstant(SHLIntrinsicsID, MVT::i32), 10144 Node->getOperand(0), ShAmt); 10145 10146 // In case of 1 bit sext, no need to shr 10147 if (ExtraVT.getScalarType().getSizeInBits() == 1) return Tmp1; 10148 10149 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT, 10150 DAG.getConstant(SRAIntrinsicsID, MVT::i32), 10151 Tmp1, ShAmt); 10152 } 10153 10154 return SDValue(); 10155 } 10156 10157 10158 SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{ 10159 DebugLoc dl = Op.getDebugLoc(); 10160 10161 // Go ahead and emit the fence on x86-64 even if we asked for no-sse2. 10162 // There isn't any reason to disable it if the target processor supports it. 10163 if (!Subtarget->hasXMMInt() && !Subtarget->is64Bit()) { 10164 SDValue Chain = Op.getOperand(0); 10165 SDValue Zero = DAG.getConstant(0, MVT::i32); 10166 SDValue Ops[] = { 10167 DAG.getRegister(X86::ESP, MVT::i32), // Base 10168 DAG.getTargetConstant(1, MVT::i8), // Scale 10169 DAG.getRegister(0, MVT::i32), // Index 10170 DAG.getTargetConstant(0, MVT::i32), // Disp 10171 DAG.getRegister(0, MVT::i32), // Segment. 10172 Zero, 10173 Chain 10174 }; 10175 SDNode *Res = 10176 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10177 array_lengthof(Ops)); 10178 return SDValue(Res, 0); 10179 } 10180 10181 unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue(); 10182 if (!isDev) 10183 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10184 10185 unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue(); 10186 unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue(); 10187 unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue(); 10188 unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue(); 10189 10190 // def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>; 10191 if (!Op1 && !Op2 && !Op3 && Op4) 10192 return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0)); 10193 10194 // def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>; 10195 if (Op1 && !Op2 && !Op3 && !Op4) 10196 return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0)); 10197 10198 // def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)), 10199 // (MFENCE)>; 10200 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10201 } 10202 10203 SDValue X86TargetLowering::LowerATOMIC_FENCE(SDValue Op, 10204 SelectionDAG &DAG) const { 10205 DebugLoc dl = Op.getDebugLoc(); 10206 AtomicOrdering FenceOrdering = static_cast<AtomicOrdering>( 10207 cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue()); 10208 SynchronizationScope FenceScope = static_cast<SynchronizationScope>( 10209 cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue()); 10210 10211 // The only fence that needs an instruction is a sequentially-consistent 10212 // cross-thread fence. 10213 if (FenceOrdering == SequentiallyConsistent && FenceScope == CrossThread) { 10214 // Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 10215 // no-sse2). There isn't any reason to disable it if the target processor 10216 // supports it. 10217 if (Subtarget->hasXMMInt() || Subtarget->is64Bit()) 10218 return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0)); 10219 10220 SDValue Chain = Op.getOperand(0); 10221 SDValue Zero = DAG.getConstant(0, MVT::i32); 10222 SDValue Ops[] = { 10223 DAG.getRegister(X86::ESP, MVT::i32), // Base 10224 DAG.getTargetConstant(1, MVT::i8), // Scale 10225 DAG.getRegister(0, MVT::i32), // Index 10226 DAG.getTargetConstant(0, MVT::i32), // Disp 10227 DAG.getRegister(0, MVT::i32), // Segment. 10228 Zero, 10229 Chain 10230 }; 10231 SDNode *Res = 10232 DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops, 10233 array_lengthof(Ops)); 10234 return SDValue(Res, 0); 10235 } 10236 10237 // MEMBARRIER is a compiler barrier; it codegens to a no-op. 10238 return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0)); 10239 } 10240 10241 10242 SDValue X86TargetLowering::LowerCMP_SWAP(SDValue Op, SelectionDAG &DAG) const { 10243 EVT T = Op.getValueType(); 10244 DebugLoc DL = Op.getDebugLoc(); 10245 unsigned Reg = 0; 10246 unsigned size = 0; 10247 switch(T.getSimpleVT().SimpleTy) { 10248 default: 10249 assert(false && "Invalid value type!"); 10250 case MVT::i8: Reg = X86::AL; size = 1; break; 10251 case MVT::i16: Reg = X86::AX; size = 2; break; 10252 case MVT::i32: Reg = X86::EAX; size = 4; break; 10253 case MVT::i64: 10254 assert(Subtarget->is64Bit() && "Node not type legal!"); 10255 Reg = X86::RAX; size = 8; 10256 break; 10257 } 10258 SDValue cpIn = DAG.getCopyToReg(Op.getOperand(0), DL, Reg, 10259 Op.getOperand(2), SDValue()); 10260 SDValue Ops[] = { cpIn.getValue(0), 10261 Op.getOperand(1), 10262 Op.getOperand(3), 10263 DAG.getTargetConstant(size, MVT::i8), 10264 cpIn.getValue(1) }; 10265 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10266 MachineMemOperand *MMO = cast<AtomicSDNode>(Op)->getMemOperand(); 10267 SDValue Result = DAG.getMemIntrinsicNode(X86ISD::LCMPXCHG_DAG, DL, Tys, 10268 Ops, 5, T, MMO); 10269 SDValue cpOut = 10270 DAG.getCopyFromReg(Result.getValue(0), DL, Reg, T, Result.getValue(1)); 10271 return cpOut; 10272 } 10273 10274 SDValue X86TargetLowering::LowerREADCYCLECOUNTER(SDValue Op, 10275 SelectionDAG &DAG) const { 10276 assert(Subtarget->is64Bit() && "Result not type legalized?"); 10277 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10278 SDValue TheChain = Op.getOperand(0); 10279 DebugLoc dl = Op.getDebugLoc(); 10280 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10281 SDValue rax = DAG.getCopyFromReg(rd, dl, X86::RAX, MVT::i64, rd.getValue(1)); 10282 SDValue rdx = DAG.getCopyFromReg(rax.getValue(1), dl, X86::RDX, MVT::i64, 10283 rax.getValue(2)); 10284 SDValue Tmp = DAG.getNode(ISD::SHL, dl, MVT::i64, rdx, 10285 DAG.getConstant(32, MVT::i8)); 10286 SDValue Ops[] = { 10287 DAG.getNode(ISD::OR, dl, MVT::i64, rax, Tmp), 10288 rdx.getValue(1) 10289 }; 10290 return DAG.getMergeValues(Ops, 2, dl); 10291 } 10292 10293 SDValue X86TargetLowering::LowerBITCAST(SDValue Op, 10294 SelectionDAG &DAG) const { 10295 EVT SrcVT = Op.getOperand(0).getValueType(); 10296 EVT DstVT = Op.getValueType(); 10297 assert(Subtarget->is64Bit() && !Subtarget->hasXMMInt() && 10298 Subtarget->hasMMX() && "Unexpected custom BITCAST"); 10299 assert((DstVT == MVT::i64 || 10300 (DstVT.isVector() && DstVT.getSizeInBits()==64)) && 10301 "Unexpected custom BITCAST"); 10302 // i64 <=> MMX conversions are Legal. 10303 if (SrcVT==MVT::i64 && DstVT.isVector()) 10304 return Op; 10305 if (DstVT==MVT::i64 && SrcVT.isVector()) 10306 return Op; 10307 // MMX <=> MMX conversions are Legal. 10308 if (SrcVT.isVector() && DstVT.isVector()) 10309 return Op; 10310 // All other conversions need to be expanded. 10311 return SDValue(); 10312 } 10313 10314 SDValue X86TargetLowering::LowerLOAD_SUB(SDValue Op, SelectionDAG &DAG) const { 10315 SDNode *Node = Op.getNode(); 10316 DebugLoc dl = Node->getDebugLoc(); 10317 EVT T = Node->getValueType(0); 10318 SDValue negOp = DAG.getNode(ISD::SUB, dl, T, 10319 DAG.getConstant(0, T), Node->getOperand(2)); 10320 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, dl, 10321 cast<AtomicSDNode>(Node)->getMemoryVT(), 10322 Node->getOperand(0), 10323 Node->getOperand(1), negOp, 10324 cast<AtomicSDNode>(Node)->getSrcValue(), 10325 cast<AtomicSDNode>(Node)->getAlignment(), 10326 cast<AtomicSDNode>(Node)->getOrdering(), 10327 cast<AtomicSDNode>(Node)->getSynchScope()); 10328 } 10329 10330 static SDValue LowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) { 10331 SDNode *Node = Op.getNode(); 10332 DebugLoc dl = Node->getDebugLoc(); 10333 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10334 10335 // Convert seq_cst store -> xchg 10336 // Convert wide store -> swap (-> cmpxchg8b/cmpxchg16b) 10337 // FIXME: On 32-bit, store -> fist or movq would be more efficient 10338 // (The only way to get a 16-byte store is cmpxchg16b) 10339 // FIXME: 16-byte ATOMIC_SWAP isn't actually hooked up at the moment. 10340 if (cast<AtomicSDNode>(Node)->getOrdering() == SequentiallyConsistent || 10341 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 10342 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 10343 cast<AtomicSDNode>(Node)->getMemoryVT(), 10344 Node->getOperand(0), 10345 Node->getOperand(1), Node->getOperand(2), 10346 cast<AtomicSDNode>(Node)->getMemOperand(), 10347 cast<AtomicSDNode>(Node)->getOrdering(), 10348 cast<AtomicSDNode>(Node)->getSynchScope()); 10349 return Swap.getValue(1); 10350 } 10351 // Other atomic stores have a simple pattern. 10352 return Op; 10353 } 10354 10355 static SDValue LowerADDC_ADDE_SUBC_SUBE(SDValue Op, SelectionDAG &DAG) { 10356 EVT VT = Op.getNode()->getValueType(0); 10357 10358 // Let legalize expand this if it isn't a legal type yet. 10359 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) 10360 return SDValue(); 10361 10362 SDVTList VTs = DAG.getVTList(VT, MVT::i32); 10363 10364 unsigned Opc; 10365 bool ExtraOp = false; 10366 switch (Op.getOpcode()) { 10367 default: assert(0 && "Invalid code"); 10368 case ISD::ADDC: Opc = X86ISD::ADD; break; 10369 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; 10370 case ISD::SUBC: Opc = X86ISD::SUB; break; 10371 case ISD::SUBE: Opc = X86ISD::SBB; ExtraOp = true; break; 10372 } 10373 10374 if (!ExtraOp) 10375 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10376 Op.getOperand(1)); 10377 return DAG.getNode(Opc, Op->getDebugLoc(), VTs, Op.getOperand(0), 10378 Op.getOperand(1), Op.getOperand(2)); 10379 } 10380 10381 /// LowerOperation - Provide custom lowering hooks for some operations. 10382 /// 10383 SDValue X86TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 10384 switch (Op.getOpcode()) { 10385 default: llvm_unreachable("Should not custom lower this!"); 10386 case ISD::SIGN_EXTEND_INREG: return LowerSIGN_EXTEND_INREG(Op,DAG); 10387 case ISD::MEMBARRIER: return LowerMEMBARRIER(Op,DAG); 10388 case ISD::ATOMIC_FENCE: return LowerATOMIC_FENCE(Op,DAG); 10389 case ISD::ATOMIC_CMP_SWAP: return LowerCMP_SWAP(Op,DAG); 10390 case ISD::ATOMIC_LOAD_SUB: return LowerLOAD_SUB(Op,DAG); 10391 case ISD::ATOMIC_STORE: return LowerATOMIC_STORE(Op,DAG); 10392 case ISD::BUILD_VECTOR: return LowerBUILD_VECTOR(Op, DAG); 10393 case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG); 10394 case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG); 10395 case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG); 10396 case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG); 10397 case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG); 10398 case ISD::INSERT_SUBVECTOR: return LowerINSERT_SUBVECTOR(Op, DAG); 10399 case ISD::SCALAR_TO_VECTOR: return LowerSCALAR_TO_VECTOR(Op, DAG); 10400 case ISD::ConstantPool: return LowerConstantPool(Op, DAG); 10401 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG); 10402 case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG); 10403 case ISD::ExternalSymbol: return LowerExternalSymbol(Op, DAG); 10404 case ISD::BlockAddress: return LowerBlockAddress(Op, DAG); 10405 case ISD::SHL_PARTS: 10406 case ISD::SRA_PARTS: 10407 case ISD::SRL_PARTS: return LowerShiftParts(Op, DAG); 10408 case ISD::SINT_TO_FP: return LowerSINT_TO_FP(Op, DAG); 10409 case ISD::UINT_TO_FP: return LowerUINT_TO_FP(Op, DAG); 10410 case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG); 10411 case ISD::FP_TO_UINT: return LowerFP_TO_UINT(Op, DAG); 10412 case ISD::FABS: return LowerFABS(Op, DAG); 10413 case ISD::FNEG: return LowerFNEG(Op, DAG); 10414 case ISD::FCOPYSIGN: return LowerFCOPYSIGN(Op, DAG); 10415 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG); 10416 case ISD::SETCC: return LowerSETCC(Op, DAG); 10417 case ISD::SELECT: return LowerSELECT(Op, DAG); 10418 case ISD::BRCOND: return LowerBRCOND(Op, DAG); 10419 case ISD::JumpTable: return LowerJumpTable(Op, DAG); 10420 case ISD::VASTART: return LowerVASTART(Op, DAG); 10421 case ISD::VAARG: return LowerVAARG(Op, DAG); 10422 case ISD::VACOPY: return LowerVACOPY(Op, DAG); 10423 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); 10424 case ISD::RETURNADDR: return LowerRETURNADDR(Op, DAG); 10425 case ISD::FRAMEADDR: return LowerFRAMEADDR(Op, DAG); 10426 case ISD::FRAME_TO_ARGS_OFFSET: 10427 return LowerFRAME_TO_ARGS_OFFSET(Op, DAG); 10428 case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG); 10429 case ISD::EH_RETURN: return LowerEH_RETURN(Op, DAG); 10430 case ISD::INIT_TRAMPOLINE: return LowerINIT_TRAMPOLINE(Op, DAG); 10431 case ISD::ADJUST_TRAMPOLINE: return LowerADJUST_TRAMPOLINE(Op, DAG); 10432 case ISD::FLT_ROUNDS_: return LowerFLT_ROUNDS_(Op, DAG); 10433 case ISD::CTLZ: return LowerCTLZ(Op, DAG); 10434 case ISD::CTTZ: return LowerCTTZ(Op, DAG); 10435 case ISD::MUL: return LowerMUL(Op, DAG); 10436 case ISD::SRA: 10437 case ISD::SRL: 10438 case ISD::SHL: return LowerShift(Op, DAG); 10439 case ISD::SADDO: 10440 case ISD::UADDO: 10441 case ISD::SSUBO: 10442 case ISD::USUBO: 10443 case ISD::SMULO: 10444 case ISD::UMULO: return LowerXALUO(Op, DAG); 10445 case ISD::READCYCLECOUNTER: return LowerREADCYCLECOUNTER(Op, DAG); 10446 case ISD::BITCAST: return LowerBITCAST(Op, DAG); 10447 case ISD::ADDC: 10448 case ISD::ADDE: 10449 case ISD::SUBC: 10450 case ISD::SUBE: return LowerADDC_ADDE_SUBC_SUBE(Op, DAG); 10451 case ISD::ADD: return LowerADD(Op, DAG); 10452 case ISD::SUB: return LowerSUB(Op, DAG); 10453 } 10454 } 10455 10456 static void ReplaceATOMIC_LOAD(SDNode *Node, 10457 SmallVectorImpl<SDValue> &Results, 10458 SelectionDAG &DAG) { 10459 DebugLoc dl = Node->getDebugLoc(); 10460 EVT VT = cast<AtomicSDNode>(Node)->getMemoryVT(); 10461 10462 // Convert wide load -> cmpxchg8b/cmpxchg16b 10463 // FIXME: On 32-bit, load -> fild or movq would be more efficient 10464 // (The only way to get a 16-byte load is cmpxchg16b) 10465 // FIXME: 16-byte ATOMIC_CMP_SWAP isn't actually hooked up at the moment. 10466 SDValue Zero = DAG.getConstant(0, VT); 10467 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, VT, 10468 Node->getOperand(0), 10469 Node->getOperand(1), Zero, Zero, 10470 cast<AtomicSDNode>(Node)->getMemOperand(), 10471 cast<AtomicSDNode>(Node)->getOrdering(), 10472 cast<AtomicSDNode>(Node)->getSynchScope()); 10473 Results.push_back(Swap.getValue(0)); 10474 Results.push_back(Swap.getValue(1)); 10475 } 10476 10477 void X86TargetLowering:: 10478 ReplaceATOMIC_BINARY_64(SDNode *Node, SmallVectorImpl<SDValue>&Results, 10479 SelectionDAG &DAG, unsigned NewOp) const { 10480 DebugLoc dl = Node->getDebugLoc(); 10481 assert (Node->getValueType(0) == MVT::i64 && 10482 "Only know how to expand i64 atomics"); 10483 10484 SDValue Chain = Node->getOperand(0); 10485 SDValue In1 = Node->getOperand(1); 10486 SDValue In2L = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10487 Node->getOperand(2), DAG.getIntPtrConstant(0)); 10488 SDValue In2H = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, 10489 Node->getOperand(2), DAG.getIntPtrConstant(1)); 10490 SDValue Ops[] = { Chain, In1, In2L, In2H }; 10491 SDVTList Tys = DAG.getVTList(MVT::i32, MVT::i32, MVT::Other); 10492 SDValue Result = 10493 DAG.getMemIntrinsicNode(NewOp, dl, Tys, Ops, 4, MVT::i64, 10494 cast<MemSDNode>(Node)->getMemOperand()); 10495 SDValue OpsF[] = { Result.getValue(0), Result.getValue(1)}; 10496 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, OpsF, 2)); 10497 Results.push_back(Result.getValue(2)); 10498 } 10499 10500 /// ReplaceNodeResults - Replace a node with an illegal result type 10501 /// with a new node built out of custom code. 10502 void X86TargetLowering::ReplaceNodeResults(SDNode *N, 10503 SmallVectorImpl<SDValue>&Results, 10504 SelectionDAG &DAG) const { 10505 DebugLoc dl = N->getDebugLoc(); 10506 switch (N->getOpcode()) { 10507 default: 10508 assert(false && "Do not know how to custom type legalize this operation!"); 10509 return; 10510 case ISD::SIGN_EXTEND_INREG: 10511 case ISD::ADDC: 10512 case ISD::ADDE: 10513 case ISD::SUBC: 10514 case ISD::SUBE: 10515 // We don't want to expand or promote these. 10516 return; 10517 case ISD::FP_TO_SINT: { 10518 std::pair<SDValue,SDValue> Vals = 10519 FP_TO_INTHelper(SDValue(N, 0), DAG, true); 10520 SDValue FIST = Vals.first, StackSlot = Vals.second; 10521 if (FIST.getNode() != 0) { 10522 EVT VT = N->getValueType(0); 10523 // Return a load from the stack slot. 10524 Results.push_back(DAG.getLoad(VT, dl, FIST, StackSlot, 10525 MachinePointerInfo(), false, false, 0)); 10526 } 10527 return; 10528 } 10529 case ISD::READCYCLECOUNTER: { 10530 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10531 SDValue TheChain = N->getOperand(0); 10532 SDValue rd = DAG.getNode(X86ISD::RDTSC_DAG, dl, Tys, &TheChain, 1); 10533 SDValue eax = DAG.getCopyFromReg(rd, dl, X86::EAX, MVT::i32, 10534 rd.getValue(1)); 10535 SDValue edx = DAG.getCopyFromReg(eax.getValue(1), dl, X86::EDX, MVT::i32, 10536 eax.getValue(2)); 10537 // Use a buildpair to merge the two 32-bit values into a 64-bit one. 10538 SDValue Ops[] = { eax, edx }; 10539 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Ops, 2)); 10540 Results.push_back(edx.getValue(1)); 10541 return; 10542 } 10543 case ISD::ATOMIC_CMP_SWAP: { 10544 EVT T = N->getValueType(0); 10545 assert((T == MVT::i64 || T == MVT::i128) && "can only expand cmpxchg pair"); 10546 bool Regs64bit = T == MVT::i128; 10547 EVT HalfT = Regs64bit ? MVT::i64 : MVT::i32; 10548 SDValue cpInL, cpInH; 10549 cpInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10550 DAG.getConstant(0, HalfT)); 10551 cpInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(2), 10552 DAG.getConstant(1, HalfT)); 10553 cpInL = DAG.getCopyToReg(N->getOperand(0), dl, 10554 Regs64bit ? X86::RAX : X86::EAX, 10555 cpInL, SDValue()); 10556 cpInH = DAG.getCopyToReg(cpInL.getValue(0), dl, 10557 Regs64bit ? X86::RDX : X86::EDX, 10558 cpInH, cpInL.getValue(1)); 10559 SDValue swapInL, swapInH; 10560 swapInL = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10561 DAG.getConstant(0, HalfT)); 10562 swapInH = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, HalfT, N->getOperand(3), 10563 DAG.getConstant(1, HalfT)); 10564 swapInL = DAG.getCopyToReg(cpInH.getValue(0), dl, 10565 Regs64bit ? X86::RBX : X86::EBX, 10566 swapInL, cpInH.getValue(1)); 10567 swapInH = DAG.getCopyToReg(swapInL.getValue(0), dl, 10568 Regs64bit ? X86::RCX : X86::ECX, 10569 swapInH, swapInL.getValue(1)); 10570 SDValue Ops[] = { swapInH.getValue(0), 10571 N->getOperand(1), 10572 swapInH.getValue(1) }; 10573 SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue); 10574 MachineMemOperand *MMO = cast<AtomicSDNode>(N)->getMemOperand(); 10575 unsigned Opcode = Regs64bit ? X86ISD::LCMPXCHG16_DAG : 10576 X86ISD::LCMPXCHG8_DAG; 10577 SDValue Result = DAG.getMemIntrinsicNode(Opcode, dl, Tys, 10578 Ops, 3, T, MMO); 10579 SDValue cpOutL = DAG.getCopyFromReg(Result.getValue(0), dl, 10580 Regs64bit ? X86::RAX : X86::EAX, 10581 HalfT, Result.getValue(1)); 10582 SDValue cpOutH = DAG.getCopyFromReg(cpOutL.getValue(1), dl, 10583 Regs64bit ? X86::RDX : X86::EDX, 10584 HalfT, cpOutL.getValue(2)); 10585 SDValue OpsF[] = { cpOutL.getValue(0), cpOutH.getValue(0)}; 10586 Results.push_back(DAG.getNode(ISD::BUILD_PAIR, dl, T, OpsF, 2)); 10587 Results.push_back(cpOutH.getValue(1)); 10588 return; 10589 } 10590 case ISD::ATOMIC_LOAD_ADD: 10591 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMADD64_DAG); 10592 return; 10593 case ISD::ATOMIC_LOAD_AND: 10594 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMAND64_DAG); 10595 return; 10596 case ISD::ATOMIC_LOAD_NAND: 10597 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMNAND64_DAG); 10598 return; 10599 case ISD::ATOMIC_LOAD_OR: 10600 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMOR64_DAG); 10601 return; 10602 case ISD::ATOMIC_LOAD_SUB: 10603 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSUB64_DAG); 10604 return; 10605 case ISD::ATOMIC_LOAD_XOR: 10606 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMXOR64_DAG); 10607 return; 10608 case ISD::ATOMIC_SWAP: 10609 ReplaceATOMIC_BINARY_64(N, Results, DAG, X86ISD::ATOMSWAP64_DAG); 10610 return; 10611 case ISD::ATOMIC_LOAD: 10612 ReplaceATOMIC_LOAD(N, Results, DAG); 10613 } 10614 } 10615 10616 const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { 10617 switch (Opcode) { 10618 default: return NULL; 10619 case X86ISD::BSF: return "X86ISD::BSF"; 10620 case X86ISD::BSR: return "X86ISD::BSR"; 10621 case X86ISD::SHLD: return "X86ISD::SHLD"; 10622 case X86ISD::SHRD: return "X86ISD::SHRD"; 10623 case X86ISD::FAND: return "X86ISD::FAND"; 10624 case X86ISD::FOR: return "X86ISD::FOR"; 10625 case X86ISD::FXOR: return "X86ISD::FXOR"; 10626 case X86ISD::FSRL: return "X86ISD::FSRL"; 10627 case X86ISD::FILD: return "X86ISD::FILD"; 10628 case X86ISD::FILD_FLAG: return "X86ISD::FILD_FLAG"; 10629 case X86ISD::FP_TO_INT16_IN_MEM: return "X86ISD::FP_TO_INT16_IN_MEM"; 10630 case X86ISD::FP_TO_INT32_IN_MEM: return "X86ISD::FP_TO_INT32_IN_MEM"; 10631 case X86ISD::FP_TO_INT64_IN_MEM: return "X86ISD::FP_TO_INT64_IN_MEM"; 10632 case X86ISD::FLD: return "X86ISD::FLD"; 10633 case X86ISD::FST: return "X86ISD::FST"; 10634 case X86ISD::CALL: return "X86ISD::CALL"; 10635 case X86ISD::RDTSC_DAG: return "X86ISD::RDTSC_DAG"; 10636 case X86ISD::BT: return "X86ISD::BT"; 10637 case X86ISD::CMP: return "X86ISD::CMP"; 10638 case X86ISD::COMI: return "X86ISD::COMI"; 10639 case X86ISD::UCOMI: return "X86ISD::UCOMI"; 10640 case X86ISD::SETCC: return "X86ISD::SETCC"; 10641 case X86ISD::SETCC_CARRY: return "X86ISD::SETCC_CARRY"; 10642 case X86ISD::FSETCCsd: return "X86ISD::FSETCCsd"; 10643 case X86ISD::FSETCCss: return "X86ISD::FSETCCss"; 10644 case X86ISD::CMOV: return "X86ISD::CMOV"; 10645 case X86ISD::BRCOND: return "X86ISD::BRCOND"; 10646 case X86ISD::RET_FLAG: return "X86ISD::RET_FLAG"; 10647 case X86ISD::REP_STOS: return "X86ISD::REP_STOS"; 10648 case X86ISD::REP_MOVS: return "X86ISD::REP_MOVS"; 10649 case X86ISD::GlobalBaseReg: return "X86ISD::GlobalBaseReg"; 10650 case X86ISD::Wrapper: return "X86ISD::Wrapper"; 10651 case X86ISD::WrapperRIP: return "X86ISD::WrapperRIP"; 10652 case X86ISD::PEXTRB: return "X86ISD::PEXTRB"; 10653 case X86ISD::PEXTRW: return "X86ISD::PEXTRW"; 10654 case X86ISD::INSERTPS: return "X86ISD::INSERTPS"; 10655 case X86ISD::PINSRB: return "X86ISD::PINSRB"; 10656 case X86ISD::PINSRW: return "X86ISD::PINSRW"; 10657 case X86ISD::PSHUFB: return "X86ISD::PSHUFB"; 10658 case X86ISD::ANDNP: return "X86ISD::ANDNP"; 10659 case X86ISD::PSIGNB: return "X86ISD::PSIGNB"; 10660 case X86ISD::PSIGNW: return "X86ISD::PSIGNW"; 10661 case X86ISD::PSIGND: return "X86ISD::PSIGND"; 10662 case X86ISD::FMAX: return "X86ISD::FMAX"; 10663 case X86ISD::FMIN: return "X86ISD::FMIN"; 10664 case X86ISD::FRSQRT: return "X86ISD::FRSQRT"; 10665 case X86ISD::FRCP: return "X86ISD::FRCP"; 10666 case X86ISD::FHADD: return "X86ISD::FHADD"; 10667 case X86ISD::FHSUB: return "X86ISD::FHSUB"; 10668 case X86ISD::TLSADDR: return "X86ISD::TLSADDR"; 10669 case X86ISD::TLSCALL: return "X86ISD::TLSCALL"; 10670 case X86ISD::EH_RETURN: return "X86ISD::EH_RETURN"; 10671 case X86ISD::TC_RETURN: return "X86ISD::TC_RETURN"; 10672 case X86ISD::FNSTCW16m: return "X86ISD::FNSTCW16m"; 10673 case X86ISD::LCMPXCHG_DAG: return "X86ISD::LCMPXCHG_DAG"; 10674 case X86ISD::LCMPXCHG8_DAG: return "X86ISD::LCMPXCHG8_DAG"; 10675 case X86ISD::ATOMADD64_DAG: return "X86ISD::ATOMADD64_DAG"; 10676 case X86ISD::ATOMSUB64_DAG: return "X86ISD::ATOMSUB64_DAG"; 10677 case X86ISD::ATOMOR64_DAG: return "X86ISD::ATOMOR64_DAG"; 10678 case X86ISD::ATOMXOR64_DAG: return "X86ISD::ATOMXOR64_DAG"; 10679 case X86ISD::ATOMAND64_DAG: return "X86ISD::ATOMAND64_DAG"; 10680 case X86ISD::ATOMNAND64_DAG: return "X86ISD::ATOMNAND64_DAG"; 10681 case X86ISD::VZEXT_MOVL: return "X86ISD::VZEXT_MOVL"; 10682 case X86ISD::VZEXT_LOAD: return "X86ISD::VZEXT_LOAD"; 10683 case X86ISD::VSHL: return "X86ISD::VSHL"; 10684 case X86ISD::VSRL: return "X86ISD::VSRL"; 10685 case X86ISD::CMPPD: return "X86ISD::CMPPD"; 10686 case X86ISD::CMPPS: return "X86ISD::CMPPS"; 10687 case X86ISD::PCMPEQB: return "X86ISD::PCMPEQB"; 10688 case X86ISD::PCMPEQW: return "X86ISD::PCMPEQW"; 10689 case X86ISD::PCMPEQD: return "X86ISD::PCMPEQD"; 10690 case X86ISD::PCMPEQQ: return "X86ISD::PCMPEQQ"; 10691 case X86ISD::PCMPGTB: return "X86ISD::PCMPGTB"; 10692 case X86ISD::PCMPGTW: return "X86ISD::PCMPGTW"; 10693 case X86ISD::PCMPGTD: return "X86ISD::PCMPGTD"; 10694 case X86ISD::PCMPGTQ: return "X86ISD::PCMPGTQ"; 10695 case X86ISD::ADD: return "X86ISD::ADD"; 10696 case X86ISD::SUB: return "X86ISD::SUB"; 10697 case X86ISD::ADC: return "X86ISD::ADC"; 10698 case X86ISD::SBB: return "X86ISD::SBB"; 10699 case X86ISD::SMUL: return "X86ISD::SMUL"; 10700 case X86ISD::UMUL: return "X86ISD::UMUL"; 10701 case X86ISD::INC: return "X86ISD::INC"; 10702 case X86ISD::DEC: return "X86ISD::DEC"; 10703 case X86ISD::OR: return "X86ISD::OR"; 10704 case X86ISD::XOR: return "X86ISD::XOR"; 10705 case X86ISD::AND: return "X86ISD::AND"; 10706 case X86ISD::ANDN: return "X86ISD::ANDN"; 10707 case X86ISD::MUL_IMM: return "X86ISD::MUL_IMM"; 10708 case X86ISD::PTEST: return "X86ISD::PTEST"; 10709 case X86ISD::TESTP: return "X86ISD::TESTP"; 10710 case X86ISD::PALIGN: return "X86ISD::PALIGN"; 10711 case X86ISD::PSHUFD: return "X86ISD::PSHUFD"; 10712 case X86ISD::PSHUFHW: return "X86ISD::PSHUFHW"; 10713 case X86ISD::PSHUFHW_LD: return "X86ISD::PSHUFHW_LD"; 10714 case X86ISD::PSHUFLW: return "X86ISD::PSHUFLW"; 10715 case X86ISD::PSHUFLW_LD: return "X86ISD::PSHUFLW_LD"; 10716 case X86ISD::SHUFPS: return "X86ISD::SHUFPS"; 10717 case X86ISD::SHUFPD: return "X86ISD::SHUFPD"; 10718 case X86ISD::MOVLHPS: return "X86ISD::MOVLHPS"; 10719 case X86ISD::MOVLHPD: return "X86ISD::MOVLHPD"; 10720 case X86ISD::MOVHLPS: return "X86ISD::MOVHLPS"; 10721 case X86ISD::MOVHLPD: return "X86ISD::MOVHLPD"; 10722 case X86ISD::MOVLPS: return "X86ISD::MOVLPS"; 10723 case X86ISD::MOVLPD: return "X86ISD::MOVLPD"; 10724 case X86ISD::MOVDDUP: return "X86ISD::MOVDDUP"; 10725 case X86ISD::MOVSHDUP: return "X86ISD::MOVSHDUP"; 10726 case X86ISD::MOVSLDUP: return "X86ISD::MOVSLDUP"; 10727 case X86ISD::MOVSHDUP_LD: return "X86ISD::MOVSHDUP_LD"; 10728 case X86ISD::MOVSLDUP_LD: return "X86ISD::MOVSLDUP_LD"; 10729 case X86ISD::MOVSD: return "X86ISD::MOVSD"; 10730 case X86ISD::MOVSS: return "X86ISD::MOVSS"; 10731 case X86ISD::UNPCKLPS: return "X86ISD::UNPCKLPS"; 10732 case X86ISD::UNPCKLPD: return "X86ISD::UNPCKLPD"; 10733 case X86ISD::VUNPCKLPDY: return "X86ISD::VUNPCKLPDY"; 10734 case X86ISD::UNPCKHPS: return "X86ISD::UNPCKHPS"; 10735 case X86ISD::UNPCKHPD: return "X86ISD::UNPCKHPD"; 10736 case X86ISD::PUNPCKLBW: return "X86ISD::PUNPCKLBW"; 10737 case X86ISD::PUNPCKLWD: return "X86ISD::PUNPCKLWD"; 10738 case X86ISD::PUNPCKLDQ: return "X86ISD::PUNPCKLDQ"; 10739 case X86ISD::PUNPCKLQDQ: return "X86ISD::PUNPCKLQDQ"; 10740 case X86ISD::PUNPCKHBW: return "X86ISD::PUNPCKHBW"; 10741 case X86ISD::PUNPCKHWD: return "X86ISD::PUNPCKHWD"; 10742 case X86ISD::PUNPCKHDQ: return "X86ISD::PUNPCKHDQ"; 10743 case X86ISD::PUNPCKHQDQ: return "X86ISD::PUNPCKHQDQ"; 10744 case X86ISD::VBROADCAST: return "X86ISD::VBROADCAST"; 10745 case X86ISD::VPERMILPS: return "X86ISD::VPERMILPS"; 10746 case X86ISD::VPERMILPSY: return "X86ISD::VPERMILPSY"; 10747 case X86ISD::VPERMILPD: return "X86ISD::VPERMILPD"; 10748 case X86ISD::VPERMILPDY: return "X86ISD::VPERMILPDY"; 10749 case X86ISD::VPERM2F128: return "X86ISD::VPERM2F128"; 10750 case X86ISD::VASTART_SAVE_XMM_REGS: return "X86ISD::VASTART_SAVE_XMM_REGS"; 10751 case X86ISD::VAARG_64: return "X86ISD::VAARG_64"; 10752 case X86ISD::WIN_ALLOCA: return "X86ISD::WIN_ALLOCA"; 10753 case X86ISD::MEMBARRIER: return "X86ISD::MEMBARRIER"; 10754 case X86ISD::SEG_ALLOCA: return "X86ISD::SEG_ALLOCA"; 10755 } 10756 } 10757 10758 // isLegalAddressingMode - Return true if the addressing mode represented 10759 // by AM is legal for this target, for a load/store of the specified type. 10760 bool X86TargetLowering::isLegalAddressingMode(const AddrMode &AM, 10761 Type *Ty) const { 10762 // X86 supports extremely general addressing modes. 10763 CodeModel::Model M = getTargetMachine().getCodeModel(); 10764 Reloc::Model R = getTargetMachine().getRelocationModel(); 10765 10766 // X86 allows a sign-extended 32-bit immediate field as a displacement. 10767 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) 10768 return false; 10769 10770 if (AM.BaseGV) { 10771 unsigned GVFlags = 10772 Subtarget->ClassifyGlobalReference(AM.BaseGV, getTargetMachine()); 10773 10774 // If a reference to this global requires an extra load, we can't fold it. 10775 if (isGlobalStubReference(GVFlags)) 10776 return false; 10777 10778 // If BaseGV requires a register for the PIC base, we cannot also have a 10779 // BaseReg specified. 10780 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) 10781 return false; 10782 10783 // If lower 4G is not available, then we must use rip-relative addressing. 10784 if ((M != CodeModel::Small || R != Reloc::Static) && 10785 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) 10786 return false; 10787 } 10788 10789 switch (AM.Scale) { 10790 case 0: 10791 case 1: 10792 case 2: 10793 case 4: 10794 case 8: 10795 // These scales always work. 10796 break; 10797 case 3: 10798 case 5: 10799 case 9: 10800 // These scales are formed with basereg+scalereg. Only accept if there is 10801 // no basereg yet. 10802 if (AM.HasBaseReg) 10803 return false; 10804 break; 10805 default: // Other stuff never works. 10806 return false; 10807 } 10808 10809 return true; 10810 } 10811 10812 10813 bool X86TargetLowering::isTruncateFree(Type *Ty1, Type *Ty2) const { 10814 if (!Ty1->isIntegerTy() || !Ty2->isIntegerTy()) 10815 return false; 10816 unsigned NumBits1 = Ty1->getPrimitiveSizeInBits(); 10817 unsigned NumBits2 = Ty2->getPrimitiveSizeInBits(); 10818 if (NumBits1 <= NumBits2) 10819 return false; 10820 return true; 10821 } 10822 10823 bool X86TargetLowering::isTruncateFree(EVT VT1, EVT VT2) const { 10824 if (!VT1.isInteger() || !VT2.isInteger()) 10825 return false; 10826 unsigned NumBits1 = VT1.getSizeInBits(); 10827 unsigned NumBits2 = VT2.getSizeInBits(); 10828 if (NumBits1 <= NumBits2) 10829 return false; 10830 return true; 10831 } 10832 10833 bool X86TargetLowering::isZExtFree(Type *Ty1, Type *Ty2) const { 10834 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10835 return Ty1->isIntegerTy(32) && Ty2->isIntegerTy(64) && Subtarget->is64Bit(); 10836 } 10837 10838 bool X86TargetLowering::isZExtFree(EVT VT1, EVT VT2) const { 10839 // x86-64 implicitly zero-extends 32-bit results in 64-bit registers. 10840 return VT1 == MVT::i32 && VT2 == MVT::i64 && Subtarget->is64Bit(); 10841 } 10842 10843 bool X86TargetLowering::isNarrowingProfitable(EVT VT1, EVT VT2) const { 10844 // i16 instructions are longer (0x66 prefix) and potentially slower. 10845 return !(VT1 == MVT::i32 && VT2 == MVT::i16); 10846 } 10847 10848 /// isShuffleMaskLegal - Targets can use this to indicate that they only 10849 /// support *some* VECTOR_SHUFFLE operations, those with specific masks. 10850 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask values 10851 /// are assumed to be legal. 10852 bool 10853 X86TargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &M, 10854 EVT VT) const { 10855 // Very little shuffling can be done for 64-bit vectors right now. 10856 if (VT.getSizeInBits() == 64) 10857 return isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()); 10858 10859 // FIXME: pshufb, blends, shifts. 10860 return (VT.getVectorNumElements() == 2 || 10861 ShuffleVectorSDNode::isSplatMask(&M[0], VT) || 10862 isMOVLMask(M, VT) || 10863 isSHUFPMask(M, VT) || 10864 isPSHUFDMask(M, VT) || 10865 isPSHUFHWMask(M, VT) || 10866 isPSHUFLWMask(M, VT) || 10867 isPALIGNRMask(M, VT, Subtarget->hasSSSE3() || Subtarget->hasAVX()) || 10868 isUNPCKLMask(M, VT) || 10869 isUNPCKHMask(M, VT) || 10870 isUNPCKL_v_undef_Mask(M, VT) || 10871 isUNPCKH_v_undef_Mask(M, VT)); 10872 } 10873 10874 bool 10875 X86TargetLowering::isVectorClearMaskLegal(const SmallVectorImpl<int> &Mask, 10876 EVT VT) const { 10877 unsigned NumElts = VT.getVectorNumElements(); 10878 // FIXME: This collection of masks seems suspect. 10879 if (NumElts == 2) 10880 return true; 10881 if (NumElts == 4 && VT.getSizeInBits() == 128) { 10882 return (isMOVLMask(Mask, VT) || 10883 isCommutedMOVLMask(Mask, VT, true) || 10884 isSHUFPMask(Mask, VT) || 10885 isCommutedSHUFPMask(Mask, VT)); 10886 } 10887 return false; 10888 } 10889 10890 //===----------------------------------------------------------------------===// 10891 // X86 Scheduler Hooks 10892 //===----------------------------------------------------------------------===// 10893 10894 // private utility function 10895 MachineBasicBlock * 10896 X86TargetLowering::EmitAtomicBitwiseWithCustomInserter(MachineInstr *bInstr, 10897 MachineBasicBlock *MBB, 10898 unsigned regOpc, 10899 unsigned immOpc, 10900 unsigned LoadOpc, 10901 unsigned CXchgOpc, 10902 unsigned notOpc, 10903 unsigned EAXreg, 10904 TargetRegisterClass *RC, 10905 bool invSrc) const { 10906 // For the atomic bitwise operator, we generate 10907 // thisMBB: 10908 // newMBB: 10909 // ld t1 = [bitinstr.addr] 10910 // op t2 = t1, [bitinstr.val] 10911 // mov EAX = t1 10912 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 10913 // bz newMBB 10914 // fallthrough -->nextMBB 10915 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 10916 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 10917 MachineFunction::iterator MBBIter = MBB; 10918 ++MBBIter; 10919 10920 /// First build the CFG 10921 MachineFunction *F = MBB->getParent(); 10922 MachineBasicBlock *thisMBB = MBB; 10923 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 10924 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 10925 F->insert(MBBIter, newMBB); 10926 F->insert(MBBIter, nextMBB); 10927 10928 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 10929 nextMBB->splice(nextMBB->begin(), thisMBB, 10930 llvm::next(MachineBasicBlock::iterator(bInstr)), 10931 thisMBB->end()); 10932 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 10933 10934 // Update thisMBB to fall through to newMBB 10935 thisMBB->addSuccessor(newMBB); 10936 10937 // newMBB jumps to itself and fall through to nextMBB 10938 newMBB->addSuccessor(nextMBB); 10939 newMBB->addSuccessor(newMBB); 10940 10941 // Insert instructions into newMBB based on incoming instruction 10942 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 4 && 10943 "unexpected number of operands"); 10944 DebugLoc dl = bInstr->getDebugLoc(); 10945 MachineOperand& destOper = bInstr->getOperand(0); 10946 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 10947 int numArgs = bInstr->getNumOperands() - 1; 10948 for (int i=0; i < numArgs; ++i) 10949 argOpers[i] = &bInstr->getOperand(i+1); 10950 10951 // x86 address has 4 operands: base, index, scale, and displacement 10952 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 10953 int valArgIndx = lastAddrIndx + 1; 10954 10955 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 10956 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(LoadOpc), t1); 10957 for (int i=0; i <= lastAddrIndx; ++i) 10958 (*MIB).addOperand(*argOpers[i]); 10959 10960 unsigned tt = F->getRegInfo().createVirtualRegister(RC); 10961 if (invSrc) { 10962 MIB = BuildMI(newMBB, dl, TII->get(notOpc), tt).addReg(t1); 10963 } 10964 else 10965 tt = t1; 10966 10967 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 10968 assert((argOpers[valArgIndx]->isReg() || 10969 argOpers[valArgIndx]->isImm()) && 10970 "invalid operand"); 10971 if (argOpers[valArgIndx]->isReg()) 10972 MIB = BuildMI(newMBB, dl, TII->get(regOpc), t2); 10973 else 10974 MIB = BuildMI(newMBB, dl, TII->get(immOpc), t2); 10975 MIB.addReg(tt); 10976 (*MIB).addOperand(*argOpers[valArgIndx]); 10977 10978 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), EAXreg); 10979 MIB.addReg(t1); 10980 10981 MIB = BuildMI(newMBB, dl, TII->get(CXchgOpc)); 10982 for (int i=0; i <= lastAddrIndx; ++i) 10983 (*MIB).addOperand(*argOpers[i]); 10984 MIB.addReg(t2); 10985 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 10986 (*MIB).setMemRefs(bInstr->memoperands_begin(), 10987 bInstr->memoperands_end()); 10988 10989 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 10990 MIB.addReg(EAXreg); 10991 10992 // insert branch 10993 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 10994 10995 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 10996 return nextMBB; 10997 } 10998 10999 // private utility function: 64 bit atomics on 32 bit host. 11000 MachineBasicBlock * 11001 X86TargetLowering::EmitAtomicBit6432WithCustomInserter(MachineInstr *bInstr, 11002 MachineBasicBlock *MBB, 11003 unsigned regOpcL, 11004 unsigned regOpcH, 11005 unsigned immOpcL, 11006 unsigned immOpcH, 11007 bool invSrc) const { 11008 // For the atomic bitwise operator, we generate 11009 // thisMBB (instructions are in pairs, except cmpxchg8b) 11010 // ld t1,t2 = [bitinstr.addr] 11011 // newMBB: 11012 // out1, out2 = phi (thisMBB, t1/t2) (newMBB, t3/t4) 11013 // op t5, t6 <- out1, out2, [bitinstr.val] 11014 // (for SWAP, substitute: mov t5, t6 <- [bitinstr.val]) 11015 // mov ECX, EBX <- t5, t6 11016 // mov EAX, EDX <- t1, t2 11017 // cmpxchg8b [bitinstr.addr] [EAX, EDX, EBX, ECX implicit] 11018 // mov t3, t4 <- EAX, EDX 11019 // bz newMBB 11020 // result in out1, out2 11021 // fallthrough -->nextMBB 11022 11023 const TargetRegisterClass *RC = X86::GR32RegisterClass; 11024 const unsigned LoadOpc = X86::MOV32rm; 11025 const unsigned NotOpc = X86::NOT32r; 11026 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11027 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11028 MachineFunction::iterator MBBIter = MBB; 11029 ++MBBIter; 11030 11031 /// First build the CFG 11032 MachineFunction *F = MBB->getParent(); 11033 MachineBasicBlock *thisMBB = MBB; 11034 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11035 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11036 F->insert(MBBIter, newMBB); 11037 F->insert(MBBIter, nextMBB); 11038 11039 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11040 nextMBB->splice(nextMBB->begin(), thisMBB, 11041 llvm::next(MachineBasicBlock::iterator(bInstr)), 11042 thisMBB->end()); 11043 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11044 11045 // Update thisMBB to fall through to newMBB 11046 thisMBB->addSuccessor(newMBB); 11047 11048 // newMBB jumps to itself and fall through to nextMBB 11049 newMBB->addSuccessor(nextMBB); 11050 newMBB->addSuccessor(newMBB); 11051 11052 DebugLoc dl = bInstr->getDebugLoc(); 11053 // Insert instructions into newMBB based on incoming instruction 11054 // There are 8 "real" operands plus 9 implicit def/uses, ignored here. 11055 assert(bInstr->getNumOperands() < X86::AddrNumOperands + 14 && 11056 "unexpected number of operands"); 11057 MachineOperand& dest1Oper = bInstr->getOperand(0); 11058 MachineOperand& dest2Oper = bInstr->getOperand(1); 11059 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11060 for (int i=0; i < 2 + X86::AddrNumOperands; ++i) { 11061 argOpers[i] = &bInstr->getOperand(i+2); 11062 11063 // We use some of the operands multiple times, so conservatively just 11064 // clear any kill flags that might be present. 11065 if (argOpers[i]->isReg() && argOpers[i]->isUse()) 11066 argOpers[i]->setIsKill(false); 11067 } 11068 11069 // x86 address has 5 operands: base, index, scale, displacement, and segment. 11070 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11071 11072 unsigned t1 = F->getRegInfo().createVirtualRegister(RC); 11073 MachineInstrBuilder MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t1); 11074 for (int i=0; i <= lastAddrIndx; ++i) 11075 (*MIB).addOperand(*argOpers[i]); 11076 unsigned t2 = F->getRegInfo().createVirtualRegister(RC); 11077 MIB = BuildMI(thisMBB, dl, TII->get(LoadOpc), t2); 11078 // add 4 to displacement. 11079 for (int i=0; i <= lastAddrIndx-2; ++i) 11080 (*MIB).addOperand(*argOpers[i]); 11081 MachineOperand newOp3 = *(argOpers[3]); 11082 if (newOp3.isImm()) 11083 newOp3.setImm(newOp3.getImm()+4); 11084 else 11085 newOp3.setOffset(newOp3.getOffset()+4); 11086 (*MIB).addOperand(newOp3); 11087 (*MIB).addOperand(*argOpers[lastAddrIndx]); 11088 11089 // t3/4 are defined later, at the bottom of the loop 11090 unsigned t3 = F->getRegInfo().createVirtualRegister(RC); 11091 unsigned t4 = F->getRegInfo().createVirtualRegister(RC); 11092 BuildMI(newMBB, dl, TII->get(X86::PHI), dest1Oper.getReg()) 11093 .addReg(t1).addMBB(thisMBB).addReg(t3).addMBB(newMBB); 11094 BuildMI(newMBB, dl, TII->get(X86::PHI), dest2Oper.getReg()) 11095 .addReg(t2).addMBB(thisMBB).addReg(t4).addMBB(newMBB); 11096 11097 // The subsequent operations should be using the destination registers of 11098 //the PHI instructions. 11099 if (invSrc) { 11100 t1 = F->getRegInfo().createVirtualRegister(RC); 11101 t2 = F->getRegInfo().createVirtualRegister(RC); 11102 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t1).addReg(dest1Oper.getReg()); 11103 MIB = BuildMI(newMBB, dl, TII->get(NotOpc), t2).addReg(dest2Oper.getReg()); 11104 } else { 11105 t1 = dest1Oper.getReg(); 11106 t2 = dest2Oper.getReg(); 11107 } 11108 11109 int valArgIndx = lastAddrIndx + 1; 11110 assert((argOpers[valArgIndx]->isReg() || 11111 argOpers[valArgIndx]->isImm()) && 11112 "invalid operand"); 11113 unsigned t5 = F->getRegInfo().createVirtualRegister(RC); 11114 unsigned t6 = F->getRegInfo().createVirtualRegister(RC); 11115 if (argOpers[valArgIndx]->isReg()) 11116 MIB = BuildMI(newMBB, dl, TII->get(regOpcL), t5); 11117 else 11118 MIB = BuildMI(newMBB, dl, TII->get(immOpcL), t5); 11119 if (regOpcL != X86::MOV32rr) 11120 MIB.addReg(t1); 11121 (*MIB).addOperand(*argOpers[valArgIndx]); 11122 assert(argOpers[valArgIndx + 1]->isReg() == 11123 argOpers[valArgIndx]->isReg()); 11124 assert(argOpers[valArgIndx + 1]->isImm() == 11125 argOpers[valArgIndx]->isImm()); 11126 if (argOpers[valArgIndx + 1]->isReg()) 11127 MIB = BuildMI(newMBB, dl, TII->get(regOpcH), t6); 11128 else 11129 MIB = BuildMI(newMBB, dl, TII->get(immOpcH), t6); 11130 if (regOpcH != X86::MOV32rr) 11131 MIB.addReg(t2); 11132 (*MIB).addOperand(*argOpers[valArgIndx + 1]); 11133 11134 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11135 MIB.addReg(t1); 11136 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EDX); 11137 MIB.addReg(t2); 11138 11139 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EBX); 11140 MIB.addReg(t5); 11141 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::ECX); 11142 MIB.addReg(t6); 11143 11144 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG8B)); 11145 for (int i=0; i <= lastAddrIndx; ++i) 11146 (*MIB).addOperand(*argOpers[i]); 11147 11148 assert(bInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11149 (*MIB).setMemRefs(bInstr->memoperands_begin(), 11150 bInstr->memoperands_end()); 11151 11152 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t3); 11153 MIB.addReg(X86::EAX); 11154 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t4); 11155 MIB.addReg(X86::EDX); 11156 11157 // insert branch 11158 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11159 11160 bInstr->eraseFromParent(); // The pseudo instruction is gone now. 11161 return nextMBB; 11162 } 11163 11164 // private utility function 11165 MachineBasicBlock * 11166 X86TargetLowering::EmitAtomicMinMaxWithCustomInserter(MachineInstr *mInstr, 11167 MachineBasicBlock *MBB, 11168 unsigned cmovOpc) const { 11169 // For the atomic min/max operator, we generate 11170 // thisMBB: 11171 // newMBB: 11172 // ld t1 = [min/max.addr] 11173 // mov t2 = [min/max.val] 11174 // cmp t1, t2 11175 // cmov[cond] t2 = t1 11176 // mov EAX = t1 11177 // lcs dest = [bitinstr.addr], t2 [EAX is implicit] 11178 // bz newMBB 11179 // fallthrough -->nextMBB 11180 // 11181 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11182 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11183 MachineFunction::iterator MBBIter = MBB; 11184 ++MBBIter; 11185 11186 /// First build the CFG 11187 MachineFunction *F = MBB->getParent(); 11188 MachineBasicBlock *thisMBB = MBB; 11189 MachineBasicBlock *newMBB = F->CreateMachineBasicBlock(LLVM_BB); 11190 MachineBasicBlock *nextMBB = F->CreateMachineBasicBlock(LLVM_BB); 11191 F->insert(MBBIter, newMBB); 11192 F->insert(MBBIter, nextMBB); 11193 11194 // Transfer the remainder of thisMBB and its successor edges to nextMBB. 11195 nextMBB->splice(nextMBB->begin(), thisMBB, 11196 llvm::next(MachineBasicBlock::iterator(mInstr)), 11197 thisMBB->end()); 11198 nextMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11199 11200 // Update thisMBB to fall through to newMBB 11201 thisMBB->addSuccessor(newMBB); 11202 11203 // newMBB jumps to newMBB and fall through to nextMBB 11204 newMBB->addSuccessor(nextMBB); 11205 newMBB->addSuccessor(newMBB); 11206 11207 DebugLoc dl = mInstr->getDebugLoc(); 11208 // Insert instructions into newMBB based on incoming instruction 11209 assert(mInstr->getNumOperands() < X86::AddrNumOperands + 4 && 11210 "unexpected number of operands"); 11211 MachineOperand& destOper = mInstr->getOperand(0); 11212 MachineOperand* argOpers[2 + X86::AddrNumOperands]; 11213 int numArgs = mInstr->getNumOperands() - 1; 11214 for (int i=0; i < numArgs; ++i) 11215 argOpers[i] = &mInstr->getOperand(i+1); 11216 11217 // x86 address has 4 operands: base, index, scale, and displacement 11218 int lastAddrIndx = X86::AddrNumOperands - 1; // [0,3] 11219 int valArgIndx = lastAddrIndx + 1; 11220 11221 unsigned t1 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11222 MachineInstrBuilder MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rm), t1); 11223 for (int i=0; i <= lastAddrIndx; ++i) 11224 (*MIB).addOperand(*argOpers[i]); 11225 11226 // We only support register and immediate values 11227 assert((argOpers[valArgIndx]->isReg() || 11228 argOpers[valArgIndx]->isImm()) && 11229 "invalid operand"); 11230 11231 unsigned t2 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11232 if (argOpers[valArgIndx]->isReg()) 11233 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), t2); 11234 else 11235 MIB = BuildMI(newMBB, dl, TII->get(X86::MOV32rr), t2); 11236 (*MIB).addOperand(*argOpers[valArgIndx]); 11237 11238 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), X86::EAX); 11239 MIB.addReg(t1); 11240 11241 MIB = BuildMI(newMBB, dl, TII->get(X86::CMP32rr)); 11242 MIB.addReg(t1); 11243 MIB.addReg(t2); 11244 11245 // Generate movc 11246 unsigned t3 = F->getRegInfo().createVirtualRegister(X86::GR32RegisterClass); 11247 MIB = BuildMI(newMBB, dl, TII->get(cmovOpc),t3); 11248 MIB.addReg(t2); 11249 MIB.addReg(t1); 11250 11251 // Cmp and exchange if none has modified the memory location 11252 MIB = BuildMI(newMBB, dl, TII->get(X86::LCMPXCHG32)); 11253 for (int i=0; i <= lastAddrIndx; ++i) 11254 (*MIB).addOperand(*argOpers[i]); 11255 MIB.addReg(t3); 11256 assert(mInstr->hasOneMemOperand() && "Unexpected number of memoperand"); 11257 (*MIB).setMemRefs(mInstr->memoperands_begin(), 11258 mInstr->memoperands_end()); 11259 11260 MIB = BuildMI(newMBB, dl, TII->get(TargetOpcode::COPY), destOper.getReg()); 11261 MIB.addReg(X86::EAX); 11262 11263 // insert branch 11264 BuildMI(newMBB, dl, TII->get(X86::JNE_4)).addMBB(newMBB); 11265 11266 mInstr->eraseFromParent(); // The pseudo instruction is gone now. 11267 return nextMBB; 11268 } 11269 11270 // FIXME: When we get size specific XMM0 registers, i.e. XMM0_V16I8 11271 // or XMM0_V32I8 in AVX all of this code can be replaced with that 11272 // in the .td file. 11273 MachineBasicBlock * 11274 X86TargetLowering::EmitPCMP(MachineInstr *MI, MachineBasicBlock *BB, 11275 unsigned numArgs, bool memArg) const { 11276 assert((Subtarget->hasSSE42() || Subtarget->hasAVX()) && 11277 "Target must have SSE4.2 or AVX features enabled"); 11278 11279 DebugLoc dl = MI->getDebugLoc(); 11280 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11281 unsigned Opc; 11282 if (!Subtarget->hasAVX()) { 11283 if (memArg) 11284 Opc = numArgs == 3 ? X86::PCMPISTRM128rm : X86::PCMPESTRM128rm; 11285 else 11286 Opc = numArgs == 3 ? X86::PCMPISTRM128rr : X86::PCMPESTRM128rr; 11287 } else { 11288 if (memArg) 11289 Opc = numArgs == 3 ? X86::VPCMPISTRM128rm : X86::VPCMPESTRM128rm; 11290 else 11291 Opc = numArgs == 3 ? X86::VPCMPISTRM128rr : X86::VPCMPESTRM128rr; 11292 } 11293 11294 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(Opc)); 11295 for (unsigned i = 0; i < numArgs; ++i) { 11296 MachineOperand &Op = MI->getOperand(i+1); 11297 if (!(Op.isReg() && Op.isImplicit())) 11298 MIB.addOperand(Op); 11299 } 11300 BuildMI(*BB, MI, dl, 11301 TII->get(Subtarget->hasAVX() ? X86::VMOVAPSrr : X86::MOVAPSrr), 11302 MI->getOperand(0).getReg()) 11303 .addReg(X86::XMM0); 11304 11305 MI->eraseFromParent(); 11306 return BB; 11307 } 11308 11309 MachineBasicBlock * 11310 X86TargetLowering::EmitMonitor(MachineInstr *MI, MachineBasicBlock *BB) const { 11311 DebugLoc dl = MI->getDebugLoc(); 11312 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11313 11314 // Address into RAX/EAX, other two args into ECX, EDX. 11315 unsigned MemOpc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r; 11316 unsigned MemReg = Subtarget->is64Bit() ? X86::RAX : X86::EAX; 11317 MachineInstrBuilder MIB = BuildMI(*BB, MI, dl, TII->get(MemOpc), MemReg); 11318 for (int i = 0; i < X86::AddrNumOperands; ++i) 11319 MIB.addOperand(MI->getOperand(i)); 11320 11321 unsigned ValOps = X86::AddrNumOperands; 11322 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11323 .addReg(MI->getOperand(ValOps).getReg()); 11324 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EDX) 11325 .addReg(MI->getOperand(ValOps+1).getReg()); 11326 11327 // The instruction doesn't actually take any operands though. 11328 BuildMI(*BB, MI, dl, TII->get(X86::MONITORrrr)); 11329 11330 MI->eraseFromParent(); // The pseudo is gone now. 11331 return BB; 11332 } 11333 11334 MachineBasicBlock * 11335 X86TargetLowering::EmitMwait(MachineInstr *MI, MachineBasicBlock *BB) const { 11336 DebugLoc dl = MI->getDebugLoc(); 11337 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11338 11339 // First arg in ECX, the second in EAX. 11340 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::ECX) 11341 .addReg(MI->getOperand(0).getReg()); 11342 BuildMI(*BB, MI, dl, TII->get(TargetOpcode::COPY), X86::EAX) 11343 .addReg(MI->getOperand(1).getReg()); 11344 11345 // The instruction doesn't actually take any operands though. 11346 BuildMI(*BB, MI, dl, TII->get(X86::MWAITrr)); 11347 11348 MI->eraseFromParent(); // The pseudo is gone now. 11349 return BB; 11350 } 11351 11352 MachineBasicBlock * 11353 X86TargetLowering::EmitVAARG64WithCustomInserter( 11354 MachineInstr *MI, 11355 MachineBasicBlock *MBB) const { 11356 // Emit va_arg instruction on X86-64. 11357 11358 // Operands to this pseudo-instruction: 11359 // 0 ) Output : destination address (reg) 11360 // 1-5) Input : va_list address (addr, i64mem) 11361 // 6 ) ArgSize : Size (in bytes) of vararg type 11362 // 7 ) ArgMode : 0=overflow only, 1=use gp_offset, 2=use fp_offset 11363 // 8 ) Align : Alignment of type 11364 // 9 ) EFLAGS (implicit-def) 11365 11366 assert(MI->getNumOperands() == 10 && "VAARG_64 should have 10 operands!"); 11367 assert(X86::AddrNumOperands == 5 && "VAARG_64 assumes 5 address operands"); 11368 11369 unsigned DestReg = MI->getOperand(0).getReg(); 11370 MachineOperand &Base = MI->getOperand(1); 11371 MachineOperand &Scale = MI->getOperand(2); 11372 MachineOperand &Index = MI->getOperand(3); 11373 MachineOperand &Disp = MI->getOperand(4); 11374 MachineOperand &Segment = MI->getOperand(5); 11375 unsigned ArgSize = MI->getOperand(6).getImm(); 11376 unsigned ArgMode = MI->getOperand(7).getImm(); 11377 unsigned Align = MI->getOperand(8).getImm(); 11378 11379 // Memory Reference 11380 assert(MI->hasOneMemOperand() && "Expected VAARG_64 to have one memoperand"); 11381 MachineInstr::mmo_iterator MMOBegin = MI->memoperands_begin(); 11382 MachineInstr::mmo_iterator MMOEnd = MI->memoperands_end(); 11383 11384 // Machine Information 11385 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11386 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 11387 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); 11388 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); 11389 DebugLoc DL = MI->getDebugLoc(); 11390 11391 // struct va_list { 11392 // i32 gp_offset 11393 // i32 fp_offset 11394 // i64 overflow_area (address) 11395 // i64 reg_save_area (address) 11396 // } 11397 // sizeof(va_list) = 24 11398 // alignment(va_list) = 8 11399 11400 unsigned TotalNumIntRegs = 6; 11401 unsigned TotalNumXMMRegs = 8; 11402 bool UseGPOffset = (ArgMode == 1); 11403 bool UseFPOffset = (ArgMode == 2); 11404 unsigned MaxOffset = TotalNumIntRegs * 8 + 11405 (UseFPOffset ? TotalNumXMMRegs * 16 : 0); 11406 11407 /* Align ArgSize to a multiple of 8 */ 11408 unsigned ArgSizeA8 = (ArgSize + 7) & ~7; 11409 bool NeedsAlign = (Align > 8); 11410 11411 MachineBasicBlock *thisMBB = MBB; 11412 MachineBasicBlock *overflowMBB; 11413 MachineBasicBlock *offsetMBB; 11414 MachineBasicBlock *endMBB; 11415 11416 unsigned OffsetDestReg = 0; // Argument address computed by offsetMBB 11417 unsigned OverflowDestReg = 0; // Argument address computed by overflowMBB 11418 unsigned OffsetReg = 0; 11419 11420 if (!UseGPOffset && !UseFPOffset) { 11421 // If we only pull from the overflow region, we don't create a branch. 11422 // We don't need to alter control flow. 11423 OffsetDestReg = 0; // unused 11424 OverflowDestReg = DestReg; 11425 11426 offsetMBB = NULL; 11427 overflowMBB = thisMBB; 11428 endMBB = thisMBB; 11429 } else { 11430 // First emit code to check if gp_offset (or fp_offset) is below the bound. 11431 // If so, pull the argument from reg_save_area. (branch to offsetMBB) 11432 // If not, pull from overflow_area. (branch to overflowMBB) 11433 // 11434 // thisMBB 11435 // | . 11436 // | . 11437 // offsetMBB overflowMBB 11438 // | . 11439 // | . 11440 // endMBB 11441 11442 // Registers for the PHI in endMBB 11443 OffsetDestReg = MRI.createVirtualRegister(AddrRegClass); 11444 OverflowDestReg = MRI.createVirtualRegister(AddrRegClass); 11445 11446 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11447 MachineFunction *MF = MBB->getParent(); 11448 overflowMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11449 offsetMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11450 endMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11451 11452 MachineFunction::iterator MBBIter = MBB; 11453 ++MBBIter; 11454 11455 // Insert the new basic blocks 11456 MF->insert(MBBIter, offsetMBB); 11457 MF->insert(MBBIter, overflowMBB); 11458 MF->insert(MBBIter, endMBB); 11459 11460 // Transfer the remainder of MBB and its successor edges to endMBB. 11461 endMBB->splice(endMBB->begin(), thisMBB, 11462 llvm::next(MachineBasicBlock::iterator(MI)), 11463 thisMBB->end()); 11464 endMBB->transferSuccessorsAndUpdatePHIs(thisMBB); 11465 11466 // Make offsetMBB and overflowMBB successors of thisMBB 11467 thisMBB->addSuccessor(offsetMBB); 11468 thisMBB->addSuccessor(overflowMBB); 11469 11470 // endMBB is a successor of both offsetMBB and overflowMBB 11471 offsetMBB->addSuccessor(endMBB); 11472 overflowMBB->addSuccessor(endMBB); 11473 11474 // Load the offset value into a register 11475 OffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11476 BuildMI(thisMBB, DL, TII->get(X86::MOV32rm), OffsetReg) 11477 .addOperand(Base) 11478 .addOperand(Scale) 11479 .addOperand(Index) 11480 .addDisp(Disp, UseFPOffset ? 4 : 0) 11481 .addOperand(Segment) 11482 .setMemRefs(MMOBegin, MMOEnd); 11483 11484 // Check if there is enough room left to pull this argument. 11485 BuildMI(thisMBB, DL, TII->get(X86::CMP32ri)) 11486 .addReg(OffsetReg) 11487 .addImm(MaxOffset + 8 - ArgSizeA8); 11488 11489 // Branch to "overflowMBB" if offset >= max 11490 // Fall through to "offsetMBB" otherwise 11491 BuildMI(thisMBB, DL, TII->get(X86::GetCondBranchFromCond(X86::COND_AE))) 11492 .addMBB(overflowMBB); 11493 } 11494 11495 // In offsetMBB, emit code to use the reg_save_area. 11496 if (offsetMBB) { 11497 assert(OffsetReg != 0); 11498 11499 // Read the reg_save_area address. 11500 unsigned RegSaveReg = MRI.createVirtualRegister(AddrRegClass); 11501 BuildMI(offsetMBB, DL, TII->get(X86::MOV64rm), RegSaveReg) 11502 .addOperand(Base) 11503 .addOperand(Scale) 11504 .addOperand(Index) 11505 .addDisp(Disp, 16) 11506 .addOperand(Segment) 11507 .setMemRefs(MMOBegin, MMOEnd); 11508 11509 // Zero-extend the offset 11510 unsigned OffsetReg64 = MRI.createVirtualRegister(AddrRegClass); 11511 BuildMI(offsetMBB, DL, TII->get(X86::SUBREG_TO_REG), OffsetReg64) 11512 .addImm(0) 11513 .addReg(OffsetReg) 11514 .addImm(X86::sub_32bit); 11515 11516 // Add the offset to the reg_save_area to get the final address. 11517 BuildMI(offsetMBB, DL, TII->get(X86::ADD64rr), OffsetDestReg) 11518 .addReg(OffsetReg64) 11519 .addReg(RegSaveReg); 11520 11521 // Compute the offset for the next argument 11522 unsigned NextOffsetReg = MRI.createVirtualRegister(OffsetRegClass); 11523 BuildMI(offsetMBB, DL, TII->get(X86::ADD32ri), NextOffsetReg) 11524 .addReg(OffsetReg) 11525 .addImm(UseFPOffset ? 16 : 8); 11526 11527 // Store it back into the va_list. 11528 BuildMI(offsetMBB, DL, TII->get(X86::MOV32mr)) 11529 .addOperand(Base) 11530 .addOperand(Scale) 11531 .addOperand(Index) 11532 .addDisp(Disp, UseFPOffset ? 4 : 0) 11533 .addOperand(Segment) 11534 .addReg(NextOffsetReg) 11535 .setMemRefs(MMOBegin, MMOEnd); 11536 11537 // Jump to endMBB 11538 BuildMI(offsetMBB, DL, TII->get(X86::JMP_4)) 11539 .addMBB(endMBB); 11540 } 11541 11542 // 11543 // Emit code to use overflow area 11544 // 11545 11546 // Load the overflow_area address into a register. 11547 unsigned OverflowAddrReg = MRI.createVirtualRegister(AddrRegClass); 11548 BuildMI(overflowMBB, DL, TII->get(X86::MOV64rm), OverflowAddrReg) 11549 .addOperand(Base) 11550 .addOperand(Scale) 11551 .addOperand(Index) 11552 .addDisp(Disp, 8) 11553 .addOperand(Segment) 11554 .setMemRefs(MMOBegin, MMOEnd); 11555 11556 // If we need to align it, do so. Otherwise, just copy the address 11557 // to OverflowDestReg. 11558 if (NeedsAlign) { 11559 // Align the overflow address 11560 assert((Align & (Align-1)) == 0 && "Alignment must be a power of 2"); 11561 unsigned TmpReg = MRI.createVirtualRegister(AddrRegClass); 11562 11563 // aligned_addr = (addr + (align-1)) & ~(align-1) 11564 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), TmpReg) 11565 .addReg(OverflowAddrReg) 11566 .addImm(Align-1); 11567 11568 BuildMI(overflowMBB, DL, TII->get(X86::AND64ri32), OverflowDestReg) 11569 .addReg(TmpReg) 11570 .addImm(~(uint64_t)(Align-1)); 11571 } else { 11572 BuildMI(overflowMBB, DL, TII->get(TargetOpcode::COPY), OverflowDestReg) 11573 .addReg(OverflowAddrReg); 11574 } 11575 11576 // Compute the next overflow address after this argument. 11577 // (the overflow address should be kept 8-byte aligned) 11578 unsigned NextAddrReg = MRI.createVirtualRegister(AddrRegClass); 11579 BuildMI(overflowMBB, DL, TII->get(X86::ADD64ri32), NextAddrReg) 11580 .addReg(OverflowDestReg) 11581 .addImm(ArgSizeA8); 11582 11583 // Store the new overflow address. 11584 BuildMI(overflowMBB, DL, TII->get(X86::MOV64mr)) 11585 .addOperand(Base) 11586 .addOperand(Scale) 11587 .addOperand(Index) 11588 .addDisp(Disp, 8) 11589 .addOperand(Segment) 11590 .addReg(NextAddrReg) 11591 .setMemRefs(MMOBegin, MMOEnd); 11592 11593 // If we branched, emit the PHI to the front of endMBB. 11594 if (offsetMBB) { 11595 BuildMI(*endMBB, endMBB->begin(), DL, 11596 TII->get(X86::PHI), DestReg) 11597 .addReg(OffsetDestReg).addMBB(offsetMBB) 11598 .addReg(OverflowDestReg).addMBB(overflowMBB); 11599 } 11600 11601 // Erase the pseudo instruction 11602 MI->eraseFromParent(); 11603 11604 return endMBB; 11605 } 11606 11607 MachineBasicBlock * 11608 X86TargetLowering::EmitVAStartSaveXMMRegsWithCustomInserter( 11609 MachineInstr *MI, 11610 MachineBasicBlock *MBB) const { 11611 // Emit code to save XMM registers to the stack. The ABI says that the 11612 // number of registers to save is given in %al, so it's theoretically 11613 // possible to do an indirect jump trick to avoid saving all of them, 11614 // however this code takes a simpler approach and just executes all 11615 // of the stores if %al is non-zero. It's less code, and it's probably 11616 // easier on the hardware branch predictor, and stores aren't all that 11617 // expensive anyway. 11618 11619 // Create the new basic blocks. One block contains all the XMM stores, 11620 // and one block is the final destination regardless of whether any 11621 // stores were performed. 11622 const BasicBlock *LLVM_BB = MBB->getBasicBlock(); 11623 MachineFunction *F = MBB->getParent(); 11624 MachineFunction::iterator MBBIter = MBB; 11625 ++MBBIter; 11626 MachineBasicBlock *XMMSaveMBB = F->CreateMachineBasicBlock(LLVM_BB); 11627 MachineBasicBlock *EndMBB = F->CreateMachineBasicBlock(LLVM_BB); 11628 F->insert(MBBIter, XMMSaveMBB); 11629 F->insert(MBBIter, EndMBB); 11630 11631 // Transfer the remainder of MBB and its successor edges to EndMBB. 11632 EndMBB->splice(EndMBB->begin(), MBB, 11633 llvm::next(MachineBasicBlock::iterator(MI)), 11634 MBB->end()); 11635 EndMBB->transferSuccessorsAndUpdatePHIs(MBB); 11636 11637 // The original block will now fall through to the XMM save block. 11638 MBB->addSuccessor(XMMSaveMBB); 11639 // The XMMSaveMBB will fall through to the end block. 11640 XMMSaveMBB->addSuccessor(EndMBB); 11641 11642 // Now add the instructions. 11643 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11644 DebugLoc DL = MI->getDebugLoc(); 11645 11646 unsigned CountReg = MI->getOperand(0).getReg(); 11647 int64_t RegSaveFrameIndex = MI->getOperand(1).getImm(); 11648 int64_t VarArgsFPOffset = MI->getOperand(2).getImm(); 11649 11650 if (!Subtarget->isTargetWin64()) { 11651 // If %al is 0, branch around the XMM save block. 11652 BuildMI(MBB, DL, TII->get(X86::TEST8rr)).addReg(CountReg).addReg(CountReg); 11653 BuildMI(MBB, DL, TII->get(X86::JE_4)).addMBB(EndMBB); 11654 MBB->addSuccessor(EndMBB); 11655 } 11656 11657 unsigned MOVOpc = Subtarget->hasAVX() ? X86::VMOVAPSmr : X86::MOVAPSmr; 11658 // In the XMM save block, save all the XMM argument registers. 11659 for (int i = 3, e = MI->getNumOperands(); i != e; ++i) { 11660 int64_t Offset = (i - 3) * 16 + VarArgsFPOffset; 11661 MachineMemOperand *MMO = 11662 F->getMachineMemOperand( 11663 MachinePointerInfo::getFixedStack(RegSaveFrameIndex, Offset), 11664 MachineMemOperand::MOStore, 11665 /*Size=*/16, /*Align=*/16); 11666 BuildMI(XMMSaveMBB, DL, TII->get(MOVOpc)) 11667 .addFrameIndex(RegSaveFrameIndex) 11668 .addImm(/*Scale=*/1) 11669 .addReg(/*IndexReg=*/0) 11670 .addImm(/*Disp=*/Offset) 11671 .addReg(/*Segment=*/0) 11672 .addReg(MI->getOperand(i).getReg()) 11673 .addMemOperand(MMO); 11674 } 11675 11676 MI->eraseFromParent(); // The pseudo instruction is gone now. 11677 11678 return EndMBB; 11679 } 11680 11681 MachineBasicBlock * 11682 X86TargetLowering::EmitLoweredSelect(MachineInstr *MI, 11683 MachineBasicBlock *BB) const { 11684 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11685 DebugLoc DL = MI->getDebugLoc(); 11686 11687 // To "insert" a SELECT_CC instruction, we actually have to insert the 11688 // diamond control-flow pattern. The incoming instruction knows the 11689 // destination vreg to set, the condition code register to branch on, the 11690 // true/false values to select between, and a branch opcode to use. 11691 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11692 MachineFunction::iterator It = BB; 11693 ++It; 11694 11695 // thisMBB: 11696 // ... 11697 // TrueVal = ... 11698 // cmpTY ccX, r1, r2 11699 // bCC copy1MBB 11700 // fallthrough --> copy0MBB 11701 MachineBasicBlock *thisMBB = BB; 11702 MachineFunction *F = BB->getParent(); 11703 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB); 11704 MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB); 11705 F->insert(It, copy0MBB); 11706 F->insert(It, sinkMBB); 11707 11708 // If the EFLAGS register isn't dead in the terminator, then claim that it's 11709 // live into the sink and copy blocks. 11710 if (!MI->killsRegister(X86::EFLAGS)) { 11711 copy0MBB->addLiveIn(X86::EFLAGS); 11712 sinkMBB->addLiveIn(X86::EFLAGS); 11713 } 11714 11715 // Transfer the remainder of BB and its successor edges to sinkMBB. 11716 sinkMBB->splice(sinkMBB->begin(), BB, 11717 llvm::next(MachineBasicBlock::iterator(MI)), 11718 BB->end()); 11719 sinkMBB->transferSuccessorsAndUpdatePHIs(BB); 11720 11721 // Add the true and fallthrough blocks as its successors. 11722 BB->addSuccessor(copy0MBB); 11723 BB->addSuccessor(sinkMBB); 11724 11725 // Create the conditional branch instruction. 11726 unsigned Opc = 11727 X86::GetCondBranchFromCond((X86::CondCode)MI->getOperand(3).getImm()); 11728 BuildMI(BB, DL, TII->get(Opc)).addMBB(sinkMBB); 11729 11730 // copy0MBB: 11731 // %FalseValue = ... 11732 // # fallthrough to sinkMBB 11733 copy0MBB->addSuccessor(sinkMBB); 11734 11735 // sinkMBB: 11736 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ] 11737 // ... 11738 BuildMI(*sinkMBB, sinkMBB->begin(), DL, 11739 TII->get(X86::PHI), MI->getOperand(0).getReg()) 11740 .addReg(MI->getOperand(1).getReg()).addMBB(copy0MBB) 11741 .addReg(MI->getOperand(2).getReg()).addMBB(thisMBB); 11742 11743 MI->eraseFromParent(); // The pseudo instruction is gone now. 11744 return sinkMBB; 11745 } 11746 11747 MachineBasicBlock * 11748 X86TargetLowering::EmitLoweredSegAlloca(MachineInstr *MI, MachineBasicBlock *BB, 11749 bool Is64Bit) const { 11750 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11751 DebugLoc DL = MI->getDebugLoc(); 11752 MachineFunction *MF = BB->getParent(); 11753 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 11754 11755 assert(EnableSegmentedStacks); 11756 11757 unsigned TlsReg = Is64Bit ? X86::FS : X86::GS; 11758 unsigned TlsOffset = Is64Bit ? 0x70 : 0x30; 11759 11760 // BB: 11761 // ... [Till the alloca] 11762 // If stacklet is not large enough, jump to mallocMBB 11763 // 11764 // bumpMBB: 11765 // Allocate by subtracting from RSP 11766 // Jump to continueMBB 11767 // 11768 // mallocMBB: 11769 // Allocate by call to runtime 11770 // 11771 // continueMBB: 11772 // ... 11773 // [rest of original BB] 11774 // 11775 11776 MachineBasicBlock *mallocMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11777 MachineBasicBlock *bumpMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11778 MachineBasicBlock *continueMBB = MF->CreateMachineBasicBlock(LLVM_BB); 11779 11780 MachineRegisterInfo &MRI = MF->getRegInfo(); 11781 const TargetRegisterClass *AddrRegClass = 11782 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); 11783 11784 unsigned mallocPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11785 bumpSPPtrVReg = MRI.createVirtualRegister(AddrRegClass), 11786 tmpSPVReg = MRI.createVirtualRegister(AddrRegClass), 11787 sizeVReg = MI->getOperand(1).getReg(), 11788 physSPReg = Is64Bit ? X86::RSP : X86::ESP; 11789 11790 MachineFunction::iterator MBBIter = BB; 11791 ++MBBIter; 11792 11793 MF->insert(MBBIter, bumpMBB); 11794 MF->insert(MBBIter, mallocMBB); 11795 MF->insert(MBBIter, continueMBB); 11796 11797 continueMBB->splice(continueMBB->begin(), BB, llvm::next 11798 (MachineBasicBlock::iterator(MI)), BB->end()); 11799 continueMBB->transferSuccessorsAndUpdatePHIs(BB); 11800 11801 // Add code to the main basic block to check if the stack limit has been hit, 11802 // and if so, jump to mallocMBB otherwise to bumpMBB. 11803 BuildMI(BB, DL, TII->get(TargetOpcode::COPY), tmpSPVReg).addReg(physSPReg); 11804 BuildMI(BB, DL, TII->get(Is64Bit ? X86::SUB64rr:X86::SUB32rr), tmpSPVReg) 11805 .addReg(tmpSPVReg).addReg(sizeVReg); 11806 BuildMI(BB, DL, TII->get(Is64Bit ? X86::CMP64mr:X86::CMP32mr)) 11807 .addReg(0).addImm(0).addReg(0).addImm(TlsOffset).addReg(TlsReg) 11808 .addReg(tmpSPVReg); 11809 BuildMI(BB, DL, TII->get(X86::JG_4)).addMBB(mallocMBB); 11810 11811 // bumpMBB simply decreases the stack pointer, since we know the current 11812 // stacklet has enough space. 11813 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), physSPReg) 11814 .addReg(tmpSPVReg); 11815 BuildMI(bumpMBB, DL, TII->get(TargetOpcode::COPY), bumpSPPtrVReg) 11816 .addReg(tmpSPVReg); 11817 BuildMI(bumpMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11818 11819 // Calls into a routine in libgcc to allocate more space from the heap. 11820 if (Is64Bit) { 11821 BuildMI(mallocMBB, DL, TII->get(X86::MOV64rr), X86::RDI) 11822 .addReg(sizeVReg); 11823 BuildMI(mallocMBB, DL, TII->get(X86::CALL64pcrel32)) 11824 .addExternalSymbol("__morestack_allocate_stack_space").addReg(X86::RDI); 11825 } else { 11826 BuildMI(mallocMBB, DL, TII->get(X86::SUB32ri), physSPReg).addReg(physSPReg) 11827 .addImm(12); 11828 BuildMI(mallocMBB, DL, TII->get(X86::PUSH32r)).addReg(sizeVReg); 11829 BuildMI(mallocMBB, DL, TII->get(X86::CALLpcrel32)) 11830 .addExternalSymbol("__morestack_allocate_stack_space"); 11831 } 11832 11833 if (!Is64Bit) 11834 BuildMI(mallocMBB, DL, TII->get(X86::ADD32ri), physSPReg).addReg(physSPReg) 11835 .addImm(16); 11836 11837 BuildMI(mallocMBB, DL, TII->get(TargetOpcode::COPY), mallocPtrVReg) 11838 .addReg(Is64Bit ? X86::RAX : X86::EAX); 11839 BuildMI(mallocMBB, DL, TII->get(X86::JMP_4)).addMBB(continueMBB); 11840 11841 // Set up the CFG correctly. 11842 BB->addSuccessor(bumpMBB); 11843 BB->addSuccessor(mallocMBB); 11844 mallocMBB->addSuccessor(continueMBB); 11845 bumpMBB->addSuccessor(continueMBB); 11846 11847 // Take care of the PHI nodes. 11848 BuildMI(*continueMBB, continueMBB->begin(), DL, TII->get(X86::PHI), 11849 MI->getOperand(0).getReg()) 11850 .addReg(mallocPtrVReg).addMBB(mallocMBB) 11851 .addReg(bumpSPPtrVReg).addMBB(bumpMBB); 11852 11853 // Delete the original pseudo instruction. 11854 MI->eraseFromParent(); 11855 11856 // And we're done. 11857 return continueMBB; 11858 } 11859 11860 MachineBasicBlock * 11861 X86TargetLowering::EmitLoweredWinAlloca(MachineInstr *MI, 11862 MachineBasicBlock *BB) const { 11863 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 11864 DebugLoc DL = MI->getDebugLoc(); 11865 11866 assert(!Subtarget->isTargetEnvMacho()); 11867 11868 // The lowering is pretty easy: we're just emitting the call to _alloca. The 11869 // non-trivial part is impdef of ESP. 11870 11871 if (Subtarget->isTargetWin64()) { 11872 if (Subtarget->isTargetCygMing()) { 11873 // ___chkstk(Mingw64): 11874 // Clobbers R10, R11, RAX and EFLAGS. 11875 // Updates RSP. 11876 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11877 .addExternalSymbol("___chkstk") 11878 .addReg(X86::RAX, RegState::Implicit) 11879 .addReg(X86::RSP, RegState::Implicit) 11880 .addReg(X86::RAX, RegState::Define | RegState::Implicit) 11881 .addReg(X86::RSP, RegState::Define | RegState::Implicit) 11882 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11883 } else { 11884 // __chkstk(MSVCRT): does not update stack pointer. 11885 // Clobbers R10, R11 and EFLAGS. 11886 // FIXME: RAX(allocated size) might be reused and not killed. 11887 BuildMI(*BB, MI, DL, TII->get(X86::W64ALLOCA)) 11888 .addExternalSymbol("__chkstk") 11889 .addReg(X86::RAX, RegState::Implicit) 11890 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11891 // RAX has the offset to subtracted from RSP. 11892 BuildMI(*BB, MI, DL, TII->get(X86::SUB64rr), X86::RSP) 11893 .addReg(X86::RSP) 11894 .addReg(X86::RAX); 11895 } 11896 } else { 11897 const char *StackProbeSymbol = 11898 Subtarget->isTargetWindows() ? "_chkstk" : "_alloca"; 11899 11900 BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) 11901 .addExternalSymbol(StackProbeSymbol) 11902 .addReg(X86::EAX, RegState::Implicit) 11903 .addReg(X86::ESP, RegState::Implicit) 11904 .addReg(X86::EAX, RegState::Define | RegState::Implicit) 11905 .addReg(X86::ESP, RegState::Define | RegState::Implicit) 11906 .addReg(X86::EFLAGS, RegState::Define | RegState::Implicit); 11907 } 11908 11909 MI->eraseFromParent(); // The pseudo instruction is gone now. 11910 return BB; 11911 } 11912 11913 MachineBasicBlock * 11914 X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, 11915 MachineBasicBlock *BB) const { 11916 // This is pretty easy. We're taking the value that we received from 11917 // our load from the relocation, sticking it in either RDI (x86-64) 11918 // or EAX and doing an indirect call. The return value will then 11919 // be in the normal return register. 11920 const X86InstrInfo *TII 11921 = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); 11922 DebugLoc DL = MI->getDebugLoc(); 11923 MachineFunction *F = BB->getParent(); 11924 11925 assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?"); 11926 assert(MI->getOperand(3).isGlobal() && "This should be a global"); 11927 11928 if (Subtarget->is64Bit()) { 11929 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11930 TII->get(X86::MOV64rm), X86::RDI) 11931 .addReg(X86::RIP) 11932 .addImm(0).addReg(0) 11933 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11934 MI->getOperand(3).getTargetFlags()) 11935 .addReg(0); 11936 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m)); 11937 addDirectMem(MIB, X86::RDI); 11938 } else if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { 11939 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11940 TII->get(X86::MOV32rm), X86::EAX) 11941 .addReg(0) 11942 .addImm(0).addReg(0) 11943 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11944 MI->getOperand(3).getTargetFlags()) 11945 .addReg(0); 11946 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11947 addDirectMem(MIB, X86::EAX); 11948 } else { 11949 MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, 11950 TII->get(X86::MOV32rm), X86::EAX) 11951 .addReg(TII->getGlobalBaseReg(F)) 11952 .addImm(0).addReg(0) 11953 .addGlobalAddress(MI->getOperand(3).getGlobal(), 0, 11954 MI->getOperand(3).getTargetFlags()) 11955 .addReg(0); 11956 MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m)); 11957 addDirectMem(MIB, X86::EAX); 11958 } 11959 11960 MI->eraseFromParent(); // The pseudo instruction is gone now. 11961 return BB; 11962 } 11963 11964 MachineBasicBlock * 11965 X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 11966 MachineBasicBlock *BB) const { 11967 switch (MI->getOpcode()) { 11968 default: assert(0 && "Unexpected instr type to insert"); 11969 case X86::TAILJMPd64: 11970 case X86::TAILJMPr64: 11971 case X86::TAILJMPm64: 11972 assert(0 && "TAILJMP64 would not be touched here."); 11973 case X86::TCRETURNdi64: 11974 case X86::TCRETURNri64: 11975 case X86::TCRETURNmi64: 11976 // Defs of TCRETURNxx64 has Win64's callee-saved registers, as subset. 11977 // On AMD64, additional defs should be added before register allocation. 11978 if (!Subtarget->isTargetWin64()) { 11979 MI->addRegisterDefined(X86::RSI); 11980 MI->addRegisterDefined(X86::RDI); 11981 MI->addRegisterDefined(X86::XMM6); 11982 MI->addRegisterDefined(X86::XMM7); 11983 MI->addRegisterDefined(X86::XMM8); 11984 MI->addRegisterDefined(X86::XMM9); 11985 MI->addRegisterDefined(X86::XMM10); 11986 MI->addRegisterDefined(X86::XMM11); 11987 MI->addRegisterDefined(X86::XMM12); 11988 MI->addRegisterDefined(X86::XMM13); 11989 MI->addRegisterDefined(X86::XMM14); 11990 MI->addRegisterDefined(X86::XMM15); 11991 } 11992 return BB; 11993 case X86::WIN_ALLOCA: 11994 return EmitLoweredWinAlloca(MI, BB); 11995 case X86::SEG_ALLOCA_32: 11996 return EmitLoweredSegAlloca(MI, BB, false); 11997 case X86::SEG_ALLOCA_64: 11998 return EmitLoweredSegAlloca(MI, BB, true); 11999 case X86::TLSCall_32: 12000 case X86::TLSCall_64: 12001 return EmitLoweredTLSCall(MI, BB); 12002 case X86::CMOV_GR8: 12003 case X86::CMOV_FR32: 12004 case X86::CMOV_FR64: 12005 case X86::CMOV_V4F32: 12006 case X86::CMOV_V2F64: 12007 case X86::CMOV_V2I64: 12008 case X86::CMOV_V8F32: 12009 case X86::CMOV_V4F64: 12010 case X86::CMOV_V4I64: 12011 case X86::CMOV_GR16: 12012 case X86::CMOV_GR32: 12013 case X86::CMOV_RFP32: 12014 case X86::CMOV_RFP64: 12015 case X86::CMOV_RFP80: 12016 return EmitLoweredSelect(MI, BB); 12017 12018 case X86::FP32_TO_INT16_IN_MEM: 12019 case X86::FP32_TO_INT32_IN_MEM: 12020 case X86::FP32_TO_INT64_IN_MEM: 12021 case X86::FP64_TO_INT16_IN_MEM: 12022 case X86::FP64_TO_INT32_IN_MEM: 12023 case X86::FP64_TO_INT64_IN_MEM: 12024 case X86::FP80_TO_INT16_IN_MEM: 12025 case X86::FP80_TO_INT32_IN_MEM: 12026 case X86::FP80_TO_INT64_IN_MEM: { 12027 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 12028 DebugLoc DL = MI->getDebugLoc(); 12029 12030 // Change the floating point control register to use "round towards zero" 12031 // mode when truncating to an integer value. 12032 MachineFunction *F = BB->getParent(); 12033 int CWFrameIdx = F->getFrameInfo()->CreateStackObject(2, 2, false); 12034 addFrameReference(BuildMI(*BB, MI, DL, 12035 TII->get(X86::FNSTCW16m)), CWFrameIdx); 12036 12037 // Load the old value of the high byte of the control word... 12038 unsigned OldCW = 12039 F->getRegInfo().createVirtualRegister(X86::GR16RegisterClass); 12040 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16rm), OldCW), 12041 CWFrameIdx); 12042 12043 // Set the high part to be round to zero... 12044 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mi)), CWFrameIdx) 12045 .addImm(0xC7F); 12046 12047 // Reload the modified control word now... 12048 addFrameReference(BuildMI(*BB, MI, DL, 12049 TII->get(X86::FLDCW16m)), CWFrameIdx); 12050 12051 // Restore the memory image of control word to original value 12052 addFrameReference(BuildMI(*BB, MI, DL, TII->get(X86::MOV16mr)), CWFrameIdx) 12053 .addReg(OldCW); 12054 12055 // Get the X86 opcode to use. 12056 unsigned Opc; 12057 switch (MI->getOpcode()) { 12058 default: llvm_unreachable("illegal opcode!"); 12059 case X86::FP32_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m32; break; 12060 case X86::FP32_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m32; break; 12061 case X86::FP32_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m32; break; 12062 case X86::FP64_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m64; break; 12063 case X86::FP64_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m64; break; 12064 case X86::FP64_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m64; break; 12065 case X86::FP80_TO_INT16_IN_MEM: Opc = X86::IST_Fp16m80; break; 12066 case X86::FP80_TO_INT32_IN_MEM: Opc = X86::IST_Fp32m80; break; 12067 case X86::FP80_TO_INT64_IN_MEM: Opc = X86::IST_Fp64m80; break; 12068 } 12069 12070 X86AddressMode AM; 12071 MachineOperand &Op = MI->getOperand(0); 12072 if (Op.isReg()) { 12073 AM.BaseType = X86AddressMode::RegBase; 12074 AM.Base.Reg = Op.getReg(); 12075 } else { 12076 AM.BaseType = X86AddressMode::FrameIndexBase; 12077 AM.Base.FrameIndex = Op.getIndex(); 12078 } 12079 Op = MI->getOperand(1); 12080 if (Op.isImm()) 12081 AM.Scale = Op.getImm(); 12082 Op = MI->getOperand(2); 12083 if (Op.isImm()) 12084 AM.IndexReg = Op.getImm(); 12085 Op = MI->getOperand(3); 12086 if (Op.isGlobal()) { 12087 AM.GV = Op.getGlobal(); 12088 } else { 12089 AM.Disp = Op.getImm(); 12090 } 12091 addFullAddress(BuildMI(*BB, MI, DL, TII->get(Opc)), AM) 12092 .addReg(MI->getOperand(X86::AddrNumOperands).getReg()); 12093 12094 // Reload the original control word now. 12095 addFrameReference(BuildMI(*BB, MI, DL, 12096 TII->get(X86::FLDCW16m)), CWFrameIdx); 12097 12098 MI->eraseFromParent(); // The pseudo instruction is gone now. 12099 return BB; 12100 } 12101 // String/text processing lowering. 12102 case X86::PCMPISTRM128REG: 12103 case X86::VPCMPISTRM128REG: 12104 return EmitPCMP(MI, BB, 3, false /* in-mem */); 12105 case X86::PCMPISTRM128MEM: 12106 case X86::VPCMPISTRM128MEM: 12107 return EmitPCMP(MI, BB, 3, true /* in-mem */); 12108 case X86::PCMPESTRM128REG: 12109 case X86::VPCMPESTRM128REG: 12110 return EmitPCMP(MI, BB, 5, false /* in mem */); 12111 case X86::PCMPESTRM128MEM: 12112 case X86::VPCMPESTRM128MEM: 12113 return EmitPCMP(MI, BB, 5, true /* in mem */); 12114 12115 // Thread synchronization. 12116 case X86::MONITOR: 12117 return EmitMonitor(MI, BB); 12118 case X86::MWAIT: 12119 return EmitMwait(MI, BB); 12120 12121 // Atomic Lowering. 12122 case X86::ATOMAND32: 12123 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12124 X86::AND32ri, X86::MOV32rm, 12125 X86::LCMPXCHG32, 12126 X86::NOT32r, X86::EAX, 12127 X86::GR32RegisterClass); 12128 case X86::ATOMOR32: 12129 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR32rr, 12130 X86::OR32ri, X86::MOV32rm, 12131 X86::LCMPXCHG32, 12132 X86::NOT32r, X86::EAX, 12133 X86::GR32RegisterClass); 12134 case X86::ATOMXOR32: 12135 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR32rr, 12136 X86::XOR32ri, X86::MOV32rm, 12137 X86::LCMPXCHG32, 12138 X86::NOT32r, X86::EAX, 12139 X86::GR32RegisterClass); 12140 case X86::ATOMNAND32: 12141 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND32rr, 12142 X86::AND32ri, X86::MOV32rm, 12143 X86::LCMPXCHG32, 12144 X86::NOT32r, X86::EAX, 12145 X86::GR32RegisterClass, true); 12146 case X86::ATOMMIN32: 12147 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL32rr); 12148 case X86::ATOMMAX32: 12149 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG32rr); 12150 case X86::ATOMUMIN32: 12151 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB32rr); 12152 case X86::ATOMUMAX32: 12153 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA32rr); 12154 12155 case X86::ATOMAND16: 12156 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12157 X86::AND16ri, X86::MOV16rm, 12158 X86::LCMPXCHG16, 12159 X86::NOT16r, X86::AX, 12160 X86::GR16RegisterClass); 12161 case X86::ATOMOR16: 12162 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR16rr, 12163 X86::OR16ri, X86::MOV16rm, 12164 X86::LCMPXCHG16, 12165 X86::NOT16r, X86::AX, 12166 X86::GR16RegisterClass); 12167 case X86::ATOMXOR16: 12168 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR16rr, 12169 X86::XOR16ri, X86::MOV16rm, 12170 X86::LCMPXCHG16, 12171 X86::NOT16r, X86::AX, 12172 X86::GR16RegisterClass); 12173 case X86::ATOMNAND16: 12174 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND16rr, 12175 X86::AND16ri, X86::MOV16rm, 12176 X86::LCMPXCHG16, 12177 X86::NOT16r, X86::AX, 12178 X86::GR16RegisterClass, true); 12179 case X86::ATOMMIN16: 12180 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL16rr); 12181 case X86::ATOMMAX16: 12182 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG16rr); 12183 case X86::ATOMUMIN16: 12184 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB16rr); 12185 case X86::ATOMUMAX16: 12186 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA16rr); 12187 12188 case X86::ATOMAND8: 12189 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12190 X86::AND8ri, X86::MOV8rm, 12191 X86::LCMPXCHG8, 12192 X86::NOT8r, X86::AL, 12193 X86::GR8RegisterClass); 12194 case X86::ATOMOR8: 12195 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR8rr, 12196 X86::OR8ri, X86::MOV8rm, 12197 X86::LCMPXCHG8, 12198 X86::NOT8r, X86::AL, 12199 X86::GR8RegisterClass); 12200 case X86::ATOMXOR8: 12201 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR8rr, 12202 X86::XOR8ri, X86::MOV8rm, 12203 X86::LCMPXCHG8, 12204 X86::NOT8r, X86::AL, 12205 X86::GR8RegisterClass); 12206 case X86::ATOMNAND8: 12207 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND8rr, 12208 X86::AND8ri, X86::MOV8rm, 12209 X86::LCMPXCHG8, 12210 X86::NOT8r, X86::AL, 12211 X86::GR8RegisterClass, true); 12212 // FIXME: There are no CMOV8 instructions; MIN/MAX need some other way. 12213 // This group is for 64-bit host. 12214 case X86::ATOMAND64: 12215 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12216 X86::AND64ri32, X86::MOV64rm, 12217 X86::LCMPXCHG64, 12218 X86::NOT64r, X86::RAX, 12219 X86::GR64RegisterClass); 12220 case X86::ATOMOR64: 12221 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::OR64rr, 12222 X86::OR64ri32, X86::MOV64rm, 12223 X86::LCMPXCHG64, 12224 X86::NOT64r, X86::RAX, 12225 X86::GR64RegisterClass); 12226 case X86::ATOMXOR64: 12227 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::XOR64rr, 12228 X86::XOR64ri32, X86::MOV64rm, 12229 X86::LCMPXCHG64, 12230 X86::NOT64r, X86::RAX, 12231 X86::GR64RegisterClass); 12232 case X86::ATOMNAND64: 12233 return EmitAtomicBitwiseWithCustomInserter(MI, BB, X86::AND64rr, 12234 X86::AND64ri32, X86::MOV64rm, 12235 X86::LCMPXCHG64, 12236 X86::NOT64r, X86::RAX, 12237 X86::GR64RegisterClass, true); 12238 case X86::ATOMMIN64: 12239 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVL64rr); 12240 case X86::ATOMMAX64: 12241 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVG64rr); 12242 case X86::ATOMUMIN64: 12243 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVB64rr); 12244 case X86::ATOMUMAX64: 12245 return EmitAtomicMinMaxWithCustomInserter(MI, BB, X86::CMOVA64rr); 12246 12247 // This group does 64-bit operations on a 32-bit host. 12248 case X86::ATOMAND6432: 12249 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12250 X86::AND32rr, X86::AND32rr, 12251 X86::AND32ri, X86::AND32ri, 12252 false); 12253 case X86::ATOMOR6432: 12254 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12255 X86::OR32rr, X86::OR32rr, 12256 X86::OR32ri, X86::OR32ri, 12257 false); 12258 case X86::ATOMXOR6432: 12259 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12260 X86::XOR32rr, X86::XOR32rr, 12261 X86::XOR32ri, X86::XOR32ri, 12262 false); 12263 case X86::ATOMNAND6432: 12264 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12265 X86::AND32rr, X86::AND32rr, 12266 X86::AND32ri, X86::AND32ri, 12267 true); 12268 case X86::ATOMADD6432: 12269 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12270 X86::ADD32rr, X86::ADC32rr, 12271 X86::ADD32ri, X86::ADC32ri, 12272 false); 12273 case X86::ATOMSUB6432: 12274 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12275 X86::SUB32rr, X86::SBB32rr, 12276 X86::SUB32ri, X86::SBB32ri, 12277 false); 12278 case X86::ATOMSWAP6432: 12279 return EmitAtomicBit6432WithCustomInserter(MI, BB, 12280 X86::MOV32rr, X86::MOV32rr, 12281 X86::MOV32ri, X86::MOV32ri, 12282 false); 12283 case X86::VASTART_SAVE_XMM_REGS: 12284 return EmitVAStartSaveXMMRegsWithCustomInserter(MI, BB); 12285 12286 case X86::VAARG_64: 12287 return EmitVAARG64WithCustomInserter(MI, BB); 12288 } 12289 } 12290 12291 //===----------------------------------------------------------------------===// 12292 // X86 Optimization Hooks 12293 //===----------------------------------------------------------------------===// 12294 12295 void X86TargetLowering::computeMaskedBitsForTargetNode(const SDValue Op, 12296 const APInt &Mask, 12297 APInt &KnownZero, 12298 APInt &KnownOne, 12299 const SelectionDAG &DAG, 12300 unsigned Depth) const { 12301 unsigned Opc = Op.getOpcode(); 12302 assert((Opc >= ISD::BUILTIN_OP_END || 12303 Opc == ISD::INTRINSIC_WO_CHAIN || 12304 Opc == ISD::INTRINSIC_W_CHAIN || 12305 Opc == ISD::INTRINSIC_VOID) && 12306 "Should use MaskedValueIsZero if you don't know whether Op" 12307 " is a target node!"); 12308 12309 KnownZero = KnownOne = APInt(Mask.getBitWidth(), 0); // Don't know anything. 12310 switch (Opc) { 12311 default: break; 12312 case X86ISD::ADD: 12313 case X86ISD::SUB: 12314 case X86ISD::ADC: 12315 case X86ISD::SBB: 12316 case X86ISD::SMUL: 12317 case X86ISD::UMUL: 12318 case X86ISD::INC: 12319 case X86ISD::DEC: 12320 case X86ISD::OR: 12321 case X86ISD::XOR: 12322 case X86ISD::AND: 12323 // These nodes' second result is a boolean. 12324 if (Op.getResNo() == 0) 12325 break; 12326 // Fallthrough 12327 case X86ISD::SETCC: 12328 KnownZero |= APInt::getHighBitsSet(Mask.getBitWidth(), 12329 Mask.getBitWidth() - 1); 12330 break; 12331 case ISD::INTRINSIC_WO_CHAIN: { 12332 unsigned IntId = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue(); 12333 unsigned NumLoBits = 0; 12334 switch (IntId) { 12335 default: break; 12336 case Intrinsic::x86_sse_movmsk_ps: 12337 case Intrinsic::x86_avx_movmsk_ps_256: 12338 case Intrinsic::x86_sse2_movmsk_pd: 12339 case Intrinsic::x86_avx_movmsk_pd_256: 12340 case Intrinsic::x86_mmx_pmovmskb: 12341 case Intrinsic::x86_sse2_pmovmskb_128: { 12342 // High bits of movmskp{s|d}, pmovmskb are known zero. 12343 switch (IntId) { 12344 case Intrinsic::x86_sse_movmsk_ps: NumLoBits = 4; break; 12345 case Intrinsic::x86_avx_movmsk_ps_256: NumLoBits = 8; break; 12346 case Intrinsic::x86_sse2_movmsk_pd: NumLoBits = 2; break; 12347 case Intrinsic::x86_avx_movmsk_pd_256: NumLoBits = 4; break; 12348 case Intrinsic::x86_mmx_pmovmskb: NumLoBits = 8; break; 12349 case Intrinsic::x86_sse2_pmovmskb_128: NumLoBits = 16; break; 12350 } 12351 KnownZero = APInt::getHighBitsSet(Mask.getBitWidth(), 12352 Mask.getBitWidth() - NumLoBits); 12353 break; 12354 } 12355 } 12356 break; 12357 } 12358 } 12359 } 12360 12361 unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op, 12362 unsigned Depth) const { 12363 // SETCC_CARRY sets the dest to ~0 for true or 0 for false. 12364 if (Op.getOpcode() == X86ISD::SETCC_CARRY) 12365 return Op.getValueType().getScalarType().getSizeInBits(); 12366 12367 // Fallback case. 12368 return 1; 12369 } 12370 12371 /// isGAPlusOffset - Returns true (and the GlobalValue and the offset) if the 12372 /// node is a GlobalAddress + offset. 12373 bool X86TargetLowering::isGAPlusOffset(SDNode *N, 12374 const GlobalValue* &GA, 12375 int64_t &Offset) const { 12376 if (N->getOpcode() == X86ISD::Wrapper) { 12377 if (isa<GlobalAddressSDNode>(N->getOperand(0))) { 12378 GA = cast<GlobalAddressSDNode>(N->getOperand(0))->getGlobal(); 12379 Offset = cast<GlobalAddressSDNode>(N->getOperand(0))->getOffset(); 12380 return true; 12381 } 12382 } 12383 return TargetLowering::isGAPlusOffset(N, GA, Offset); 12384 } 12385 12386 /// isShuffleHigh128VectorInsertLow - Checks whether the shuffle node is the 12387 /// same as extracting the high 128-bit part of 256-bit vector and then 12388 /// inserting the result into the low part of a new 256-bit vector 12389 static bool isShuffleHigh128VectorInsertLow(ShuffleVectorSDNode *SVOp) { 12390 EVT VT = SVOp->getValueType(0); 12391 int NumElems = VT.getVectorNumElements(); 12392 12393 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12394 for (int i = 0, j = NumElems/2; i < NumElems/2; ++i, ++j) 12395 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12396 SVOp->getMaskElt(j) >= 0) 12397 return false; 12398 12399 return true; 12400 } 12401 12402 /// isShuffleLow128VectorInsertHigh - Checks whether the shuffle node is the 12403 /// same as extracting the low 128-bit part of 256-bit vector and then 12404 /// inserting the result into the high part of a new 256-bit vector 12405 static bool isShuffleLow128VectorInsertHigh(ShuffleVectorSDNode *SVOp) { 12406 EVT VT = SVOp->getValueType(0); 12407 int NumElems = VT.getVectorNumElements(); 12408 12409 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12410 for (int i = NumElems/2, j = 0; i < NumElems; ++i, ++j) 12411 if (!isUndefOrEqual(SVOp->getMaskElt(i), j) || 12412 SVOp->getMaskElt(j) >= 0) 12413 return false; 12414 12415 return true; 12416 } 12417 12418 /// PerformShuffleCombine256 - Performs shuffle combines for 256-bit vectors. 12419 static SDValue PerformShuffleCombine256(SDNode *N, SelectionDAG &DAG, 12420 TargetLowering::DAGCombinerInfo &DCI) { 12421 DebugLoc dl = N->getDebugLoc(); 12422 ShuffleVectorSDNode *SVOp = cast<ShuffleVectorSDNode>(N); 12423 SDValue V1 = SVOp->getOperand(0); 12424 SDValue V2 = SVOp->getOperand(1); 12425 EVT VT = SVOp->getValueType(0); 12426 int NumElems = VT.getVectorNumElements(); 12427 12428 if (V1.getOpcode() == ISD::CONCAT_VECTORS && 12429 V2.getOpcode() == ISD::CONCAT_VECTORS) { 12430 // 12431 // 0,0,0,... 12432 // | 12433 // V UNDEF BUILD_VECTOR UNDEF 12434 // \ / \ / 12435 // CONCAT_VECTOR CONCAT_VECTOR 12436 // \ / 12437 // \ / 12438 // RESULT: V + zero extended 12439 // 12440 if (V2.getOperand(0).getOpcode() != ISD::BUILD_VECTOR || 12441 V2.getOperand(1).getOpcode() != ISD::UNDEF || 12442 V1.getOperand(1).getOpcode() != ISD::UNDEF) 12443 return SDValue(); 12444 12445 if (!ISD::isBuildVectorAllZeros(V2.getOperand(0).getNode())) 12446 return SDValue(); 12447 12448 // To match the shuffle mask, the first half of the mask should 12449 // be exactly the first vector, and all the rest a splat with the 12450 // first element of the second one. 12451 for (int i = 0; i < NumElems/2; ++i) 12452 if (!isUndefOrEqual(SVOp->getMaskElt(i), i) || 12453 !isUndefOrEqual(SVOp->getMaskElt(i+NumElems/2), NumElems)) 12454 return SDValue(); 12455 12456 // Emit a zeroed vector and insert the desired subvector on its 12457 // first half. 12458 SDValue Zeros = getZeroVector(VT, true /* HasXMMInt */, DAG, dl); 12459 SDValue InsV = Insert128BitVector(Zeros, V1.getOperand(0), 12460 DAG.getConstant(0, MVT::i32), DAG, dl); 12461 return DCI.CombineTo(N, InsV); 12462 } 12463 12464 //===--------------------------------------------------------------------===// 12465 // Combine some shuffles into subvector extracts and inserts: 12466 // 12467 12468 // vector_shuffle <4, 5, 6, 7, u, u, u, u> or <2, 3, u, u> 12469 if (isShuffleHigh128VectorInsertLow(SVOp)) { 12470 SDValue V = Extract128BitVector(V1, DAG.getConstant(NumElems/2, MVT::i32), 12471 DAG, dl); 12472 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12473 V, DAG.getConstant(0, MVT::i32), DAG, dl); 12474 return DCI.CombineTo(N, InsV); 12475 } 12476 12477 // vector_shuffle <u, u, u, u, 0, 1, 2, 3> or <u, u, 0, 1> 12478 if (isShuffleLow128VectorInsertHigh(SVOp)) { 12479 SDValue V = Extract128BitVector(V1, DAG.getConstant(0, MVT::i32), DAG, dl); 12480 SDValue InsV = Insert128BitVector(DAG.getNode(ISD::UNDEF, dl, VT), 12481 V, DAG.getConstant(NumElems/2, MVT::i32), DAG, dl); 12482 return DCI.CombineTo(N, InsV); 12483 } 12484 12485 return SDValue(); 12486 } 12487 12488 /// PerformShuffleCombine - Performs several different shuffle combines. 12489 static SDValue PerformShuffleCombine(SDNode *N, SelectionDAG &DAG, 12490 TargetLowering::DAGCombinerInfo &DCI, 12491 const X86Subtarget *Subtarget) { 12492 DebugLoc dl = N->getDebugLoc(); 12493 EVT VT = N->getValueType(0); 12494 12495 // Don't create instructions with illegal types after legalize types has run. 12496 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 12497 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) 12498 return SDValue(); 12499 12500 // Combine 256-bit vector shuffles. This is only profitable when in AVX mode 12501 if (Subtarget->hasAVX() && VT.getSizeInBits() == 256 && 12502 N->getOpcode() == ISD::VECTOR_SHUFFLE) 12503 return PerformShuffleCombine256(N, DAG, DCI); 12504 12505 // Only handle 128 wide vector from here on. 12506 if (VT.getSizeInBits() != 128) 12507 return SDValue(); 12508 12509 // Combine a vector_shuffle that is equal to build_vector load1, load2, load3, 12510 // load4, <0, 1, 2, 3> into a 128-bit load if the load addresses are 12511 // consecutive, non-overlapping, and in the right order. 12512 SmallVector<SDValue, 16> Elts; 12513 for (unsigned i = 0, e = VT.getVectorNumElements(); i != e; ++i) 12514 Elts.push_back(getShuffleScalarElt(N, i, DAG, 0)); 12515 12516 return EltsFromConsecutiveLoads(VT, Elts, dl, DAG); 12517 } 12518 12519 /// PerformEXTRACT_VECTOR_ELTCombine - Detect vector gather/scatter index 12520 /// generation and convert it from being a bunch of shuffles and extracts 12521 /// to a simple store and scalar loads to extract the elements. 12522 static SDValue PerformEXTRACT_VECTOR_ELTCombine(SDNode *N, SelectionDAG &DAG, 12523 const TargetLowering &TLI) { 12524 SDValue InputVector = N->getOperand(0); 12525 12526 // Only operate on vectors of 4 elements, where the alternative shuffling 12527 // gets to be more expensive. 12528 if (InputVector.getValueType() != MVT::v4i32) 12529 return SDValue(); 12530 12531 // Check whether every use of InputVector is an EXTRACT_VECTOR_ELT with a 12532 // single use which is a sign-extend or zero-extend, and all elements are 12533 // used. 12534 SmallVector<SDNode *, 4> Uses; 12535 unsigned ExtractedElements = 0; 12536 for (SDNode::use_iterator UI = InputVector.getNode()->use_begin(), 12537 UE = InputVector.getNode()->use_end(); UI != UE; ++UI) { 12538 if (UI.getUse().getResNo() != InputVector.getResNo()) 12539 return SDValue(); 12540 12541 SDNode *Extract = *UI; 12542 if (Extract->getOpcode() != ISD::EXTRACT_VECTOR_ELT) 12543 return SDValue(); 12544 12545 if (Extract->getValueType(0) != MVT::i32) 12546 return SDValue(); 12547 if (!Extract->hasOneUse()) 12548 return SDValue(); 12549 if (Extract->use_begin()->getOpcode() != ISD::SIGN_EXTEND && 12550 Extract->use_begin()->getOpcode() != ISD::ZERO_EXTEND) 12551 return SDValue(); 12552 if (!isa<ConstantSDNode>(Extract->getOperand(1))) 12553 return SDValue(); 12554 12555 // Record which element was extracted. 12556 ExtractedElements |= 12557 1 << cast<ConstantSDNode>(Extract->getOperand(1))->getZExtValue(); 12558 12559 Uses.push_back(Extract); 12560 } 12561 12562 // If not all the elements were used, this may not be worthwhile. 12563 if (ExtractedElements != 15) 12564 return SDValue(); 12565 12566 // Ok, we've now decided to do the transformation. 12567 DebugLoc dl = InputVector.getDebugLoc(); 12568 12569 // Store the value to a temporary stack slot. 12570 SDValue StackPtr = DAG.CreateStackTemporary(InputVector.getValueType()); 12571 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, InputVector, StackPtr, 12572 MachinePointerInfo(), false, false, 0); 12573 12574 // Replace each use (extract) with a load of the appropriate element. 12575 for (SmallVectorImpl<SDNode *>::iterator UI = Uses.begin(), 12576 UE = Uses.end(); UI != UE; ++UI) { 12577 SDNode *Extract = *UI; 12578 12579 // cOMpute the element's address. 12580 SDValue Idx = Extract->getOperand(1); 12581 unsigned EltSize = 12582 InputVector.getValueType().getVectorElementType().getSizeInBits()/8; 12583 uint64_t Offset = EltSize * cast<ConstantSDNode>(Idx)->getZExtValue(); 12584 SDValue OffsetVal = DAG.getConstant(Offset, TLI.getPointerTy()); 12585 12586 SDValue ScalarAddr = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 12587 StackPtr, OffsetVal); 12588 12589 // Load the scalar. 12590 SDValue LoadScalar = DAG.getLoad(Extract->getValueType(0), dl, Ch, 12591 ScalarAddr, MachinePointerInfo(), 12592 false, false, 0); 12593 12594 // Replace the exact with the load. 12595 DAG.ReplaceAllUsesOfValueWith(SDValue(Extract, 0), LoadScalar); 12596 } 12597 12598 // The replacement was made in place; don't return anything. 12599 return SDValue(); 12600 } 12601 12602 /// PerformSELECTCombine - Do target-specific dag combines on SELECT and VSELECT 12603 /// nodes. 12604 static SDValue PerformSELECTCombine(SDNode *N, SelectionDAG &DAG, 12605 const X86Subtarget *Subtarget) { 12606 DebugLoc DL = N->getDebugLoc(); 12607 SDValue Cond = N->getOperand(0); 12608 // Get the LHS/RHS of the select. 12609 SDValue LHS = N->getOperand(1); 12610 SDValue RHS = N->getOperand(2); 12611 EVT VT = LHS.getValueType(); 12612 12613 // If we have SSE[12] support, try to form min/max nodes. SSE min/max 12614 // instructions match the semantics of the common C idiom x<y?x:y but not 12615 // x<=y?x:y, because of how they handle negative zero (which can be 12616 // ignored in unsafe-math mode). 12617 if (Cond.getOpcode() == ISD::SETCC && VT.isFloatingPoint() && 12618 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && 12619 (Subtarget->hasXMMInt() || 12620 (Subtarget->hasSSE1() && VT.getScalarType() == MVT::f32))) { 12621 ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get(); 12622 12623 unsigned Opcode = 0; 12624 // Check for x CC y ? x : y. 12625 if (DAG.isEqualTo(LHS, Cond.getOperand(0)) && 12626 DAG.isEqualTo(RHS, Cond.getOperand(1))) { 12627 switch (CC) { 12628 default: break; 12629 case ISD::SETULT: 12630 // Converting this to a min would handle NaNs incorrectly, and swapping 12631 // the operands would cause it to handle comparisons between positive 12632 // and negative zero incorrectly. 12633 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12634 if (!UnsafeFPMath && 12635 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12636 break; 12637 std::swap(LHS, RHS); 12638 } 12639 Opcode = X86ISD::FMIN; 12640 break; 12641 case ISD::SETOLE: 12642 // Converting this to a min would handle comparisons between positive 12643 // and negative zero incorrectly. 12644 if (!UnsafeFPMath && 12645 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12646 break; 12647 Opcode = X86ISD::FMIN; 12648 break; 12649 case ISD::SETULE: 12650 // Converting this to a min would handle both negative zeros and NaNs 12651 // incorrectly, but we can swap the operands to fix both. 12652 std::swap(LHS, RHS); 12653 case ISD::SETOLT: 12654 case ISD::SETLT: 12655 case ISD::SETLE: 12656 Opcode = X86ISD::FMIN; 12657 break; 12658 12659 case ISD::SETOGE: 12660 // Converting this to a max would handle comparisons between positive 12661 // and negative zero incorrectly. 12662 if (!UnsafeFPMath && 12663 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) 12664 break; 12665 Opcode = X86ISD::FMAX; 12666 break; 12667 case ISD::SETUGT: 12668 // Converting this to a max would handle NaNs incorrectly, and swapping 12669 // the operands would cause it to handle comparisons between positive 12670 // and negative zero incorrectly. 12671 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) { 12672 if (!UnsafeFPMath && 12673 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) 12674 break; 12675 std::swap(LHS, RHS); 12676 } 12677 Opcode = X86ISD::FMAX; 12678 break; 12679 case ISD::SETUGE: 12680 // Converting this to a max would handle both negative zeros and NaNs 12681 // incorrectly, but we can swap the operands to fix both. 12682 std::swap(LHS, RHS); 12683 case ISD::SETOGT: 12684 case ISD::SETGT: 12685 case ISD::SETGE: 12686 Opcode = X86ISD::FMAX; 12687 break; 12688 } 12689 // Check for x CC y ? y : x -- a min/max with reversed arms. 12690 } else if (DAG.isEqualTo(LHS, Cond.getOperand(1)) && 12691 DAG.isEqualTo(RHS, Cond.getOperand(0))) { 12692 switch (CC) { 12693 default: break; 12694 case ISD::SETOGE: 12695 // Converting this to a min would handle comparisons between positive 12696 // and negative zero incorrectly, and swapping the operands would 12697 // cause it to handle NaNs incorrectly. 12698 if (!UnsafeFPMath && 12699 !(DAG.isKnownNeverZero(LHS) || DAG.isKnownNeverZero(RHS))) { 12700 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12701 break; 12702 std::swap(LHS, RHS); 12703 } 12704 Opcode = X86ISD::FMIN; 12705 break; 12706 case ISD::SETUGT: 12707 // Converting this to a min would handle NaNs incorrectly. 12708 if (!UnsafeFPMath && 12709 (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS))) 12710 break; 12711 Opcode = X86ISD::FMIN; 12712 break; 12713 case ISD::SETUGE: 12714 // Converting this to a min would handle both negative zeros and NaNs 12715 // incorrectly, but we can swap the operands to fix both. 12716 std::swap(LHS, RHS); 12717 case ISD::SETOGT: 12718 case ISD::SETGT: 12719 case ISD::SETGE: 12720 Opcode = X86ISD::FMIN; 12721 break; 12722 12723 case ISD::SETULT: 12724 // Converting this to a max would handle NaNs incorrectly. 12725 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12726 break; 12727 Opcode = X86ISD::FMAX; 12728 break; 12729 case ISD::SETOLE: 12730 // Converting this to a max would handle comparisons between positive 12731 // and negative zero incorrectly, and swapping the operands would 12732 // cause it to handle NaNs incorrectly. 12733 if (!UnsafeFPMath && 12734 !DAG.isKnownNeverZero(LHS) && !DAG.isKnownNeverZero(RHS)) { 12735 if (!DAG.isKnownNeverNaN(LHS) || !DAG.isKnownNeverNaN(RHS)) 12736 break; 12737 std::swap(LHS, RHS); 12738 } 12739 Opcode = X86ISD::FMAX; 12740 break; 12741 case ISD::SETULE: 12742 // Converting this to a max would handle both negative zeros and NaNs 12743 // incorrectly, but we can swap the operands to fix both. 12744 std::swap(LHS, RHS); 12745 case ISD::SETOLT: 12746 case ISD::SETLT: 12747 case ISD::SETLE: 12748 Opcode = X86ISD::FMAX; 12749 break; 12750 } 12751 } 12752 12753 if (Opcode) 12754 return DAG.getNode(Opcode, DL, N->getValueType(0), LHS, RHS); 12755 } 12756 12757 // If this is a select between two integer constants, try to do some 12758 // optimizations. 12759 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(LHS)) { 12760 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(RHS)) 12761 // Don't do this for crazy integer types. 12762 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { 12763 // If this is efficiently invertible, canonicalize the LHSC/RHSC values 12764 // so that TrueC (the true value) is larger than FalseC. 12765 bool NeedsCondInvert = false; 12766 12767 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue()) && 12768 // Efficiently invertible. 12769 (Cond.getOpcode() == ISD::SETCC || // setcc -> invertible. 12770 (Cond.getOpcode() == ISD::XOR && // xor(X, C) -> invertible. 12771 isa<ConstantSDNode>(Cond.getOperand(1))))) { 12772 NeedsCondInvert = true; 12773 std::swap(TrueC, FalseC); 12774 } 12775 12776 // Optimize C ? 8 : 0 -> zext(C) << 3. Likewise for any pow2/0. 12777 if (FalseC->getAPIntValue() == 0 && 12778 TrueC->getAPIntValue().isPowerOf2()) { 12779 if (NeedsCondInvert) // Invert the condition if needed. 12780 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12781 DAG.getConstant(1, Cond.getValueType())); 12782 12783 // Zero extend the condition if needed. 12784 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, LHS.getValueType(), Cond); 12785 12786 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12787 return DAG.getNode(ISD::SHL, DL, LHS.getValueType(), Cond, 12788 DAG.getConstant(ShAmt, MVT::i8)); 12789 } 12790 12791 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. 12792 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12793 if (NeedsCondInvert) // Invert the condition if needed. 12794 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12795 DAG.getConstant(1, Cond.getValueType())); 12796 12797 // Zero extend the condition if needed. 12798 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12799 FalseC->getValueType(0), Cond); 12800 return DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12801 SDValue(FalseC, 0)); 12802 } 12803 12804 // Optimize cases that will turn into an LEA instruction. This requires 12805 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12806 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12807 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12808 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12809 12810 bool isFastMultiplier = false; 12811 if (Diff < 10) { 12812 switch ((unsigned char)Diff) { 12813 default: break; 12814 case 1: // result = add base, cond 12815 case 2: // result = lea base( , cond*2) 12816 case 3: // result = lea base(cond, cond*2) 12817 case 4: // result = lea base( , cond*4) 12818 case 5: // result = lea base(cond, cond*4) 12819 case 8: // result = lea base( , cond*8) 12820 case 9: // result = lea base(cond, cond*8) 12821 isFastMultiplier = true; 12822 break; 12823 } 12824 } 12825 12826 if (isFastMultiplier) { 12827 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12828 if (NeedsCondInvert) // Invert the condition if needed. 12829 Cond = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond, 12830 DAG.getConstant(1, Cond.getValueType())); 12831 12832 // Zero extend the condition if needed. 12833 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12834 Cond); 12835 // Scale the condition by the difference. 12836 if (Diff != 1) 12837 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12838 DAG.getConstant(Diff, Cond.getValueType())); 12839 12840 // Add the base if non-zero. 12841 if (FalseC->getAPIntValue() != 0) 12842 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12843 SDValue(FalseC, 0)); 12844 return Cond; 12845 } 12846 } 12847 } 12848 } 12849 12850 return SDValue(); 12851 } 12852 12853 /// Optimize X86ISD::CMOV [LHS, RHS, CONDCODE (e.g. X86::COND_NE), CONDVAL] 12854 static SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG, 12855 TargetLowering::DAGCombinerInfo &DCI) { 12856 DebugLoc DL = N->getDebugLoc(); 12857 12858 // If the flag operand isn't dead, don't touch this CMOV. 12859 if (N->getNumValues() == 2 && !SDValue(N, 1).use_empty()) 12860 return SDValue(); 12861 12862 SDValue FalseOp = N->getOperand(0); 12863 SDValue TrueOp = N->getOperand(1); 12864 X86::CondCode CC = (X86::CondCode)N->getConstantOperandVal(2); 12865 SDValue Cond = N->getOperand(3); 12866 if (CC == X86::COND_E || CC == X86::COND_NE) { 12867 switch (Cond.getOpcode()) { 12868 default: break; 12869 case X86ISD::BSR: 12870 case X86ISD::BSF: 12871 // If operand of BSR / BSF are proven never zero, then ZF cannot be set. 12872 if (DAG.isKnownNeverZero(Cond.getOperand(0))) 12873 return (CC == X86::COND_E) ? FalseOp : TrueOp; 12874 } 12875 } 12876 12877 // If this is a select between two integer constants, try to do some 12878 // optimizations. Note that the operands are ordered the opposite of SELECT 12879 // operands. 12880 if (ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp)) { 12881 if (ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp)) { 12882 // Canonicalize the TrueC/FalseC values so that TrueC (the true value) is 12883 // larger than FalseC (the false value). 12884 if (TrueC->getAPIntValue().ult(FalseC->getAPIntValue())) { 12885 CC = X86::GetOppositeBranchCondition(CC); 12886 std::swap(TrueC, FalseC); 12887 } 12888 12889 // Optimize C ? 8 : 0 -> zext(setcc(C)) << 3. Likewise for any pow2/0. 12890 // This is efficient for any integer data type (including i8/i16) and 12891 // shift amount. 12892 if (FalseC->getAPIntValue() == 0 && TrueC->getAPIntValue().isPowerOf2()) { 12893 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12894 DAG.getConstant(CC, MVT::i8), Cond); 12895 12896 // Zero extend the condition if needed. 12897 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, TrueC->getValueType(0), Cond); 12898 12899 unsigned ShAmt = TrueC->getAPIntValue().logBase2(); 12900 Cond = DAG.getNode(ISD::SHL, DL, Cond.getValueType(), Cond, 12901 DAG.getConstant(ShAmt, MVT::i8)); 12902 if (N->getNumValues() == 2) // Dead flag value? 12903 return DCI.CombineTo(N, Cond, SDValue()); 12904 return Cond; 12905 } 12906 12907 // Optimize Cond ? cst+1 : cst -> zext(setcc(C)+cst. This is efficient 12908 // for any integer data type, including i8/i16. 12909 if (FalseC->getAPIntValue()+1 == TrueC->getAPIntValue()) { 12910 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12911 DAG.getConstant(CC, MVT::i8), Cond); 12912 12913 // Zero extend the condition if needed. 12914 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, 12915 FalseC->getValueType(0), Cond); 12916 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12917 SDValue(FalseC, 0)); 12918 12919 if (N->getNumValues() == 2) // Dead flag value? 12920 return DCI.CombineTo(N, Cond, SDValue()); 12921 return Cond; 12922 } 12923 12924 // Optimize cases that will turn into an LEA instruction. This requires 12925 // an i32 or i64 and an efficient multiplier (1, 2, 3, 4, 5, 8, 9). 12926 if (N->getValueType(0) == MVT::i32 || N->getValueType(0) == MVT::i64) { 12927 uint64_t Diff = TrueC->getZExtValue()-FalseC->getZExtValue(); 12928 if (N->getValueType(0) == MVT::i32) Diff = (unsigned)Diff; 12929 12930 bool isFastMultiplier = false; 12931 if (Diff < 10) { 12932 switch ((unsigned char)Diff) { 12933 default: break; 12934 case 1: // result = add base, cond 12935 case 2: // result = lea base( , cond*2) 12936 case 3: // result = lea base(cond, cond*2) 12937 case 4: // result = lea base( , cond*4) 12938 case 5: // result = lea base(cond, cond*4) 12939 case 8: // result = lea base( , cond*8) 12940 case 9: // result = lea base(cond, cond*8) 12941 isFastMultiplier = true; 12942 break; 12943 } 12944 } 12945 12946 if (isFastMultiplier) { 12947 APInt Diff = TrueC->getAPIntValue()-FalseC->getAPIntValue(); 12948 Cond = DAG.getNode(X86ISD::SETCC, DL, MVT::i8, 12949 DAG.getConstant(CC, MVT::i8), Cond); 12950 // Zero extend the condition if needed. 12951 Cond = DAG.getNode(ISD::ZERO_EXTEND, DL, FalseC->getValueType(0), 12952 Cond); 12953 // Scale the condition by the difference. 12954 if (Diff != 1) 12955 Cond = DAG.getNode(ISD::MUL, DL, Cond.getValueType(), Cond, 12956 DAG.getConstant(Diff, Cond.getValueType())); 12957 12958 // Add the base if non-zero. 12959 if (FalseC->getAPIntValue() != 0) 12960 Cond = DAG.getNode(ISD::ADD, DL, Cond.getValueType(), Cond, 12961 SDValue(FalseC, 0)); 12962 if (N->getNumValues() == 2) // Dead flag value? 12963 return DCI.CombineTo(N, Cond, SDValue()); 12964 return Cond; 12965 } 12966 } 12967 } 12968 } 12969 return SDValue(); 12970 } 12971 12972 12973 /// PerformMulCombine - Optimize a single multiply with constant into two 12974 /// in order to implement it with two cheaper instructions, e.g. 12975 /// LEA + SHL, LEA + LEA. 12976 static SDValue PerformMulCombine(SDNode *N, SelectionDAG &DAG, 12977 TargetLowering::DAGCombinerInfo &DCI) { 12978 if (DCI.isBeforeLegalize() || DCI.isCalledByLegalizer()) 12979 return SDValue(); 12980 12981 EVT VT = N->getValueType(0); 12982 if (VT != MVT::i64) 12983 return SDValue(); 12984 12985 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)); 12986 if (!C) 12987 return SDValue(); 12988 uint64_t MulAmt = C->getZExtValue(); 12989 if (isPowerOf2_64(MulAmt) || MulAmt == 3 || MulAmt == 5 || MulAmt == 9) 12990 return SDValue(); 12991 12992 uint64_t MulAmt1 = 0; 12993 uint64_t MulAmt2 = 0; 12994 if ((MulAmt % 9) == 0) { 12995 MulAmt1 = 9; 12996 MulAmt2 = MulAmt / 9; 12997 } else if ((MulAmt % 5) == 0) { 12998 MulAmt1 = 5; 12999 MulAmt2 = MulAmt / 5; 13000 } else if ((MulAmt % 3) == 0) { 13001 MulAmt1 = 3; 13002 MulAmt2 = MulAmt / 3; 13003 } 13004 if (MulAmt2 && 13005 (isPowerOf2_64(MulAmt2) || MulAmt2 == 3 || MulAmt2 == 5 || MulAmt2 == 9)){ 13006 DebugLoc DL = N->getDebugLoc(); 13007 13008 if (isPowerOf2_64(MulAmt2) && 13009 !(N->hasOneUse() && N->use_begin()->getOpcode() == ISD::ADD)) 13010 // If second multiplifer is pow2, issue it first. We want the multiply by 13011 // 3, 5, or 9 to be folded into the addressing mode unless the lone use 13012 // is an add. 13013 std::swap(MulAmt1, MulAmt2); 13014 13015 SDValue NewMul; 13016 if (isPowerOf2_64(MulAmt1)) 13017 NewMul = DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), 13018 DAG.getConstant(Log2_64(MulAmt1), MVT::i8)); 13019 else 13020 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, N->getOperand(0), 13021 DAG.getConstant(MulAmt1, VT)); 13022 13023 if (isPowerOf2_64(MulAmt2)) 13024 NewMul = DAG.getNode(ISD::SHL, DL, VT, NewMul, 13025 DAG.getConstant(Log2_64(MulAmt2), MVT::i8)); 13026 else 13027 NewMul = DAG.getNode(X86ISD::MUL_IMM, DL, VT, NewMul, 13028 DAG.getConstant(MulAmt2, VT)); 13029 13030 // Do not add new nodes to DAG combiner worklist. 13031 DCI.CombineTo(N, NewMul, false); 13032 } 13033 return SDValue(); 13034 } 13035 13036 static SDValue PerformSHLCombine(SDNode *N, SelectionDAG &DAG) { 13037 SDValue N0 = N->getOperand(0); 13038 SDValue N1 = N->getOperand(1); 13039 ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1); 13040 EVT VT = N0.getValueType(); 13041 13042 // fold (shl (and (setcc_c), c1), c2) -> (and setcc_c, (c1 << c2)) 13043 // since the result of setcc_c is all zero's or all ones. 13044 if (N1C && N0.getOpcode() == ISD::AND && 13045 N0.getOperand(1).getOpcode() == ISD::Constant) { 13046 SDValue N00 = N0.getOperand(0); 13047 if (N00.getOpcode() == X86ISD::SETCC_CARRY || 13048 ((N00.getOpcode() == ISD::ANY_EXTEND || 13049 N00.getOpcode() == ISD::ZERO_EXTEND) && 13050 N00.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY)) { 13051 APInt Mask = cast<ConstantSDNode>(N0.getOperand(1))->getAPIntValue(); 13052 APInt ShAmt = N1C->getAPIntValue(); 13053 Mask = Mask.shl(ShAmt); 13054 if (Mask != 0) 13055 return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, 13056 N00, DAG.getConstant(Mask, VT)); 13057 } 13058 } 13059 13060 return SDValue(); 13061 } 13062 13063 /// PerformShiftCombine - Transforms vector shift nodes to use vector shifts 13064 /// when possible. 13065 static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG, 13066 const X86Subtarget *Subtarget) { 13067 EVT VT = N->getValueType(0); 13068 if (!VT.isVector() && VT.isInteger() && 13069 N->getOpcode() == ISD::SHL) 13070 return PerformSHLCombine(N, DAG); 13071 13072 // On X86 with SSE2 support, we can transform this to a vector shift if 13073 // all elements are shifted by the same amount. We can't do this in legalize 13074 // because the a constant vector is typically transformed to a constant pool 13075 // so we have no knowledge of the shift amount. 13076 if (!Subtarget->hasXMMInt()) 13077 return SDValue(); 13078 13079 if (VT != MVT::v2i64 && VT != MVT::v4i32 && VT != MVT::v8i16) 13080 return SDValue(); 13081 13082 SDValue ShAmtOp = N->getOperand(1); 13083 EVT EltVT = VT.getVectorElementType(); 13084 DebugLoc DL = N->getDebugLoc(); 13085 SDValue BaseShAmt = SDValue(); 13086 if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) { 13087 unsigned NumElts = VT.getVectorNumElements(); 13088 unsigned i = 0; 13089 for (; i != NumElts; ++i) { 13090 SDValue Arg = ShAmtOp.getOperand(i); 13091 if (Arg.getOpcode() == ISD::UNDEF) continue; 13092 BaseShAmt = Arg; 13093 break; 13094 } 13095 for (; i != NumElts; ++i) { 13096 SDValue Arg = ShAmtOp.getOperand(i); 13097 if (Arg.getOpcode() == ISD::UNDEF) continue; 13098 if (Arg != BaseShAmt) { 13099 return SDValue(); 13100 } 13101 } 13102 } else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE && 13103 cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) { 13104 SDValue InVec = ShAmtOp.getOperand(0); 13105 if (InVec.getOpcode() == ISD::BUILD_VECTOR) { 13106 unsigned NumElts = InVec.getValueType().getVectorNumElements(); 13107 unsigned i = 0; 13108 for (; i != NumElts; ++i) { 13109 SDValue Arg = InVec.getOperand(i); 13110 if (Arg.getOpcode() == ISD::UNDEF) continue; 13111 BaseShAmt = Arg; 13112 break; 13113 } 13114 } else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) { 13115 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) { 13116 unsigned SplatIdx= cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex(); 13117 if (C->getZExtValue() == SplatIdx) 13118 BaseShAmt = InVec.getOperand(1); 13119 } 13120 } 13121 if (BaseShAmt.getNode() == 0) 13122 BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp, 13123 DAG.getIntPtrConstant(0)); 13124 } else 13125 return SDValue(); 13126 13127 // The shift amount is an i32. 13128 if (EltVT.bitsGT(MVT::i32)) 13129 BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt); 13130 else if (EltVT.bitsLT(MVT::i32)) 13131 BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt); 13132 13133 // The shift amount is identical so we can do a vector shift. 13134 SDValue ValOp = N->getOperand(0); 13135 switch (N->getOpcode()) { 13136 default: 13137 llvm_unreachable("Unknown shift opcode!"); 13138 break; 13139 case ISD::SHL: 13140 if (VT == MVT::v2i64) 13141 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13142 DAG.getConstant(Intrinsic::x86_sse2_pslli_q, MVT::i32), 13143 ValOp, BaseShAmt); 13144 if (VT == MVT::v4i32) 13145 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13146 DAG.getConstant(Intrinsic::x86_sse2_pslli_d, MVT::i32), 13147 ValOp, BaseShAmt); 13148 if (VT == MVT::v8i16) 13149 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13150 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), 13151 ValOp, BaseShAmt); 13152 break; 13153 case ISD::SRA: 13154 if (VT == MVT::v4i32) 13155 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13156 DAG.getConstant(Intrinsic::x86_sse2_psrai_d, MVT::i32), 13157 ValOp, BaseShAmt); 13158 if (VT == MVT::v8i16) 13159 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13160 DAG.getConstant(Intrinsic::x86_sse2_psrai_w, MVT::i32), 13161 ValOp, BaseShAmt); 13162 break; 13163 case ISD::SRL: 13164 if (VT == MVT::v2i64) 13165 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13166 DAG.getConstant(Intrinsic::x86_sse2_psrli_q, MVT::i32), 13167 ValOp, BaseShAmt); 13168 if (VT == MVT::v4i32) 13169 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13170 DAG.getConstant(Intrinsic::x86_sse2_psrli_d, MVT::i32), 13171 ValOp, BaseShAmt); 13172 if (VT == MVT::v8i16) 13173 return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT, 13174 DAG.getConstant(Intrinsic::x86_sse2_psrli_w, MVT::i32), 13175 ValOp, BaseShAmt); 13176 break; 13177 } 13178 return SDValue(); 13179 } 13180 13181 13182 // CMPEQCombine - Recognize the distinctive (AND (setcc ...) (setcc ..)) 13183 // where both setccs reference the same FP CMP, and rewrite for CMPEQSS 13184 // and friends. Likewise for OR -> CMPNEQSS. 13185 static SDValue CMPEQCombine(SDNode *N, SelectionDAG &DAG, 13186 TargetLowering::DAGCombinerInfo &DCI, 13187 const X86Subtarget *Subtarget) { 13188 unsigned opcode; 13189 13190 // SSE1 supports CMP{eq|ne}SS, and SSE2 added CMP{eq|ne}SD, but 13191 // we're requiring SSE2 for both. 13192 if (Subtarget->hasXMMInt() && isAndOrOfSetCCs(SDValue(N, 0U), opcode)) { 13193 SDValue N0 = N->getOperand(0); 13194 SDValue N1 = N->getOperand(1); 13195 SDValue CMP0 = N0->getOperand(1); 13196 SDValue CMP1 = N1->getOperand(1); 13197 DebugLoc DL = N->getDebugLoc(); 13198 13199 // The SETCCs should both refer to the same CMP. 13200 if (CMP0.getOpcode() != X86ISD::CMP || CMP0 != CMP1) 13201 return SDValue(); 13202 13203 SDValue CMP00 = CMP0->getOperand(0); 13204 SDValue CMP01 = CMP0->getOperand(1); 13205 EVT VT = CMP00.getValueType(); 13206 13207 if (VT == MVT::f32 || VT == MVT::f64) { 13208 bool ExpectingFlags = false; 13209 // Check for any users that want flags: 13210 for (SDNode::use_iterator UI = N->use_begin(), 13211 UE = N->use_end(); 13212 !ExpectingFlags && UI != UE; ++UI) 13213 switch (UI->getOpcode()) { 13214 default: 13215 case ISD::BR_CC: 13216 case ISD::BRCOND: 13217 case ISD::SELECT: 13218 ExpectingFlags = true; 13219 break; 13220 case ISD::CopyToReg: 13221 case ISD::SIGN_EXTEND: 13222 case ISD::ZERO_EXTEND: 13223 case ISD::ANY_EXTEND: 13224 break; 13225 } 13226 13227 if (!ExpectingFlags) { 13228 enum X86::CondCode cc0 = (enum X86::CondCode)N0.getConstantOperandVal(0); 13229 enum X86::CondCode cc1 = (enum X86::CondCode)N1.getConstantOperandVal(0); 13230 13231 if (cc1 == X86::COND_E || cc1 == X86::COND_NE) { 13232 X86::CondCode tmp = cc0; 13233 cc0 = cc1; 13234 cc1 = tmp; 13235 } 13236 13237 if ((cc0 == X86::COND_E && cc1 == X86::COND_NP) || 13238 (cc0 == X86::COND_NE && cc1 == X86::COND_P)) { 13239 bool is64BitFP = (CMP00.getValueType() == MVT::f64); 13240 X86ISD::NodeType NTOperator = is64BitFP ? 13241 X86ISD::FSETCCsd : X86ISD::FSETCCss; 13242 // FIXME: need symbolic constants for these magic numbers. 13243 // See X86ATTInstPrinter.cpp:printSSECC(). 13244 unsigned x86cc = (cc0 == X86::COND_E) ? 0 : 4; 13245 SDValue OnesOrZeroesF = DAG.getNode(NTOperator, DL, MVT::f32, CMP00, CMP01, 13246 DAG.getConstant(x86cc, MVT::i8)); 13247 SDValue OnesOrZeroesI = DAG.getNode(ISD::BITCAST, DL, MVT::i32, 13248 OnesOrZeroesF); 13249 SDValue ANDed = DAG.getNode(ISD::AND, DL, MVT::i32, OnesOrZeroesI, 13250 DAG.getConstant(1, MVT::i32)); 13251 SDValue OneBitOfTruth = DAG.getNode(ISD::TRUNCATE, DL, MVT::i8, ANDed); 13252 return OneBitOfTruth; 13253 } 13254 } 13255 } 13256 } 13257 return SDValue(); 13258 } 13259 13260 /// CanFoldXORWithAllOnes - Test whether the XOR operand is a AllOnes vector 13261 /// so it can be folded inside ANDNP. 13262 static bool CanFoldXORWithAllOnes(const SDNode *N) { 13263 EVT VT = N->getValueType(0); 13264 13265 // Match direct AllOnes for 128 and 256-bit vectors 13266 if (ISD::isBuildVectorAllOnes(N)) 13267 return true; 13268 13269 // Look through a bit convert. 13270 if (N->getOpcode() == ISD::BITCAST) 13271 N = N->getOperand(0).getNode(); 13272 13273 // Sometimes the operand may come from a insert_subvector building a 256-bit 13274 // allones vector 13275 if (VT.getSizeInBits() == 256 && 13276 N->getOpcode() == ISD::INSERT_SUBVECTOR) { 13277 SDValue V1 = N->getOperand(0); 13278 SDValue V2 = N->getOperand(1); 13279 13280 if (V1.getOpcode() == ISD::INSERT_SUBVECTOR && 13281 V1.getOperand(0).getOpcode() == ISD::UNDEF && 13282 ISD::isBuildVectorAllOnes(V1.getOperand(1).getNode()) && 13283 ISD::isBuildVectorAllOnes(V2.getNode())) 13284 return true; 13285 } 13286 13287 return false; 13288 } 13289 13290 static SDValue PerformAndCombine(SDNode *N, SelectionDAG &DAG, 13291 TargetLowering::DAGCombinerInfo &DCI, 13292 const X86Subtarget *Subtarget) { 13293 if (DCI.isBeforeLegalizeOps()) 13294 return SDValue(); 13295 13296 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13297 if (R.getNode()) 13298 return R; 13299 13300 EVT VT = N->getValueType(0); 13301 13302 // Create ANDN instructions 13303 if (Subtarget->hasBMI() && (VT == MVT::i32 || VT == MVT::i64)) { 13304 SDValue N0 = N->getOperand(0); 13305 SDValue N1 = N->getOperand(1); 13306 DebugLoc DL = N->getDebugLoc(); 13307 13308 // Check LHS for not 13309 if (N0.getOpcode() == ISD::XOR && isAllOnes(N0.getOperand(1))) 13310 return DAG.getNode(X86ISD::ANDN, DL, VT, N0.getOperand(0), N1); 13311 // Check RHS for not 13312 if (N1.getOpcode() == ISD::XOR && isAllOnes(N1.getOperand(1))) 13313 return DAG.getNode(X86ISD::ANDN, DL, VT, N1.getOperand(0), N0); 13314 13315 return SDValue(); 13316 } 13317 13318 // Want to form ANDNP nodes: 13319 // 1) In the hopes of then easily combining them with OR and AND nodes 13320 // to form PBLEND/PSIGN. 13321 // 2) To match ANDN packed intrinsics 13322 if (VT != MVT::v2i64 && VT != MVT::v4i64) 13323 return SDValue(); 13324 13325 SDValue N0 = N->getOperand(0); 13326 SDValue N1 = N->getOperand(1); 13327 DebugLoc DL = N->getDebugLoc(); 13328 13329 // Check LHS for vnot 13330 if (N0.getOpcode() == ISD::XOR && 13331 //ISD::isBuildVectorAllOnes(N0.getOperand(1).getNode())) 13332 CanFoldXORWithAllOnes(N0.getOperand(1).getNode())) 13333 return DAG.getNode(X86ISD::ANDNP, DL, VT, N0.getOperand(0), N1); 13334 13335 // Check RHS for vnot 13336 if (N1.getOpcode() == ISD::XOR && 13337 //ISD::isBuildVectorAllOnes(N1.getOperand(1).getNode())) 13338 CanFoldXORWithAllOnes(N1.getOperand(1).getNode())) 13339 return DAG.getNode(X86ISD::ANDNP, DL, VT, N1.getOperand(0), N0); 13340 13341 return SDValue(); 13342 } 13343 13344 static SDValue PerformOrCombine(SDNode *N, SelectionDAG &DAG, 13345 TargetLowering::DAGCombinerInfo &DCI, 13346 const X86Subtarget *Subtarget) { 13347 if (DCI.isBeforeLegalizeOps()) 13348 return SDValue(); 13349 13350 SDValue R = CMPEQCombine(N, DAG, DCI, Subtarget); 13351 if (R.getNode()) 13352 return R; 13353 13354 EVT VT = N->getValueType(0); 13355 if (VT != MVT::i16 && VT != MVT::i32 && VT != MVT::i64 && VT != MVT::v2i64) 13356 return SDValue(); 13357 13358 SDValue N0 = N->getOperand(0); 13359 SDValue N1 = N->getOperand(1); 13360 13361 // look for psign/blend 13362 if (Subtarget->hasSSSE3() || Subtarget->hasAVX()) { 13363 if (VT == MVT::v2i64) { 13364 // Canonicalize pandn to RHS 13365 if (N0.getOpcode() == X86ISD::ANDNP) 13366 std::swap(N0, N1); 13367 // or (and (m, x), (pandn m, y)) 13368 if (N0.getOpcode() == ISD::AND && N1.getOpcode() == X86ISD::ANDNP) { 13369 SDValue Mask = N1.getOperand(0); 13370 SDValue X = N1.getOperand(1); 13371 SDValue Y; 13372 if (N0.getOperand(0) == Mask) 13373 Y = N0.getOperand(1); 13374 if (N0.getOperand(1) == Mask) 13375 Y = N0.getOperand(0); 13376 13377 // Check to see if the mask appeared in both the AND and ANDNP and 13378 if (!Y.getNode()) 13379 return SDValue(); 13380 13381 // Validate that X, Y, and Mask are BIT_CONVERTS, and see through them. 13382 if (Mask.getOpcode() != ISD::BITCAST || 13383 X.getOpcode() != ISD::BITCAST || 13384 Y.getOpcode() != ISD::BITCAST) 13385 return SDValue(); 13386 13387 // Look through mask bitcast. 13388 Mask = Mask.getOperand(0); 13389 EVT MaskVT = Mask.getValueType(); 13390 13391 // Validate that the Mask operand is a vector sra node. The sra node 13392 // will be an intrinsic. 13393 if (Mask.getOpcode() != ISD::INTRINSIC_WO_CHAIN) 13394 return SDValue(); 13395 13396 // FIXME: what to do for bytes, since there is a psignb/pblendvb, but 13397 // there is no psrai.b 13398 switch (cast<ConstantSDNode>(Mask.getOperand(0))->getZExtValue()) { 13399 case Intrinsic::x86_sse2_psrai_w: 13400 case Intrinsic::x86_sse2_psrai_d: 13401 break; 13402 default: return SDValue(); 13403 } 13404 13405 // Check that the SRA is all signbits. 13406 SDValue SraC = Mask.getOperand(2); 13407 unsigned SraAmt = cast<ConstantSDNode>(SraC)->getZExtValue(); 13408 unsigned EltBits = MaskVT.getVectorElementType().getSizeInBits(); 13409 if ((SraAmt + 1) != EltBits) 13410 return SDValue(); 13411 13412 DebugLoc DL = N->getDebugLoc(); 13413 13414 // Now we know we at least have a plendvb with the mask val. See if 13415 // we can form a psignb/w/d. 13416 // psign = x.type == y.type == mask.type && y = sub(0, x); 13417 X = X.getOperand(0); 13418 Y = Y.getOperand(0); 13419 if (Y.getOpcode() == ISD::SUB && Y.getOperand(1) == X && 13420 ISD::isBuildVectorAllZeros(Y.getOperand(0).getNode()) && 13421 X.getValueType() == MaskVT && X.getValueType() == Y.getValueType()){ 13422 unsigned Opc = 0; 13423 switch (EltBits) { 13424 case 8: Opc = X86ISD::PSIGNB; break; 13425 case 16: Opc = X86ISD::PSIGNW; break; 13426 case 32: Opc = X86ISD::PSIGND; break; 13427 default: break; 13428 } 13429 if (Opc) { 13430 SDValue Sign = DAG.getNode(Opc, DL, MaskVT, X, Mask.getOperand(1)); 13431 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Sign); 13432 } 13433 } 13434 // PBLENDVB only available on SSE 4.1 13435 if (!(Subtarget->hasSSE41() || Subtarget->hasAVX())) 13436 return SDValue(); 13437 13438 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X); 13439 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y); 13440 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask); 13441 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y); 13442 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask); 13443 } 13444 } 13445 } 13446 13447 // fold (or (x << c) | (y >> (64 - c))) ==> (shld64 x, y, c) 13448 if (N0.getOpcode() == ISD::SRL && N1.getOpcode() == ISD::SHL) 13449 std::swap(N0, N1); 13450 if (N0.getOpcode() != ISD::SHL || N1.getOpcode() != ISD::SRL) 13451 return SDValue(); 13452 if (!N0.hasOneUse() || !N1.hasOneUse()) 13453 return SDValue(); 13454 13455 SDValue ShAmt0 = N0.getOperand(1); 13456 if (ShAmt0.getValueType() != MVT::i8) 13457 return SDValue(); 13458 SDValue ShAmt1 = N1.getOperand(1); 13459 if (ShAmt1.getValueType() != MVT::i8) 13460 return SDValue(); 13461 if (ShAmt0.getOpcode() == ISD::TRUNCATE) 13462 ShAmt0 = ShAmt0.getOperand(0); 13463 if (ShAmt1.getOpcode() == ISD::TRUNCATE) 13464 ShAmt1 = ShAmt1.getOperand(0); 13465 13466 DebugLoc DL = N->getDebugLoc(); 13467 unsigned Opc = X86ISD::SHLD; 13468 SDValue Op0 = N0.getOperand(0); 13469 SDValue Op1 = N1.getOperand(0); 13470 if (ShAmt0.getOpcode() == ISD::SUB) { 13471 Opc = X86ISD::SHRD; 13472 std::swap(Op0, Op1); 13473 std::swap(ShAmt0, ShAmt1); 13474 } 13475 13476 unsigned Bits = VT.getSizeInBits(); 13477 if (ShAmt1.getOpcode() == ISD::SUB) { 13478 SDValue Sum = ShAmt1.getOperand(0); 13479 if (ConstantSDNode *SumC = dyn_cast<ConstantSDNode>(Sum)) { 13480 SDValue ShAmt1Op1 = ShAmt1.getOperand(1); 13481 if (ShAmt1Op1.getNode()->getOpcode() == ISD::TRUNCATE) 13482 ShAmt1Op1 = ShAmt1Op1.getOperand(0); 13483 if (SumC->getSExtValue() == Bits && ShAmt1Op1 == ShAmt0) 13484 return DAG.getNode(Opc, DL, VT, 13485 Op0, Op1, 13486 DAG.getNode(ISD::TRUNCATE, DL, 13487 MVT::i8, ShAmt0)); 13488 } 13489 } else if (ConstantSDNode *ShAmt1C = dyn_cast<ConstantSDNode>(ShAmt1)) { 13490 ConstantSDNode *ShAmt0C = dyn_cast<ConstantSDNode>(ShAmt0); 13491 if (ShAmt0C && 13492 ShAmt0C->getSExtValue() + ShAmt1C->getSExtValue() == Bits) 13493 return DAG.getNode(Opc, DL, VT, 13494 N0.getOperand(0), N1.getOperand(0), 13495 DAG.getNode(ISD::TRUNCATE, DL, 13496 MVT::i8, ShAmt0)); 13497 } 13498 13499 return SDValue(); 13500 } 13501 13502 /// PerformLOADCombine - Do target-specific dag combines on LOAD nodes. 13503 static SDValue PerformLOADCombine(SDNode *N, SelectionDAG &DAG, 13504 const X86Subtarget *Subtarget) { 13505 LoadSDNode *Ld = cast<LoadSDNode>(N); 13506 EVT RegVT = Ld->getValueType(0); 13507 EVT MemVT = Ld->getMemoryVT(); 13508 DebugLoc dl = Ld->getDebugLoc(); 13509 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13510 13511 ISD::LoadExtType Ext = Ld->getExtensionType(); 13512 13513 // If this is a vector EXT Load then attempt to optimize it using a 13514 // shuffle. We need SSE4 for the shuffles. 13515 // TODO: It is possible to support ZExt by zeroing the undef values 13516 // during the shuffle phase or after the shuffle. 13517 if (RegVT.isVector() && Ext == ISD::EXTLOAD && Subtarget->hasSSE41()) { 13518 assert(MemVT != RegVT && "Cannot extend to the same type"); 13519 assert(MemVT.isVector() && "Must load a vector from memory"); 13520 13521 unsigned NumElems = RegVT.getVectorNumElements(); 13522 unsigned RegSz = RegVT.getSizeInBits(); 13523 unsigned MemSz = MemVT.getSizeInBits(); 13524 assert(RegSz > MemSz && "Register size must be greater than the mem size"); 13525 // All sizes must be a power of two 13526 if (!isPowerOf2_32(RegSz * MemSz * NumElems)) return SDValue(); 13527 13528 // Attempt to load the original value using a single load op. 13529 // Find a scalar type which is equal to the loaded word size. 13530 MVT SclrLoadTy = MVT::i8; 13531 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13532 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13533 MVT Tp = (MVT::SimpleValueType)tp; 13534 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() == MemSz) { 13535 SclrLoadTy = Tp; 13536 break; 13537 } 13538 } 13539 13540 // Proceed if a load word is found. 13541 if (SclrLoadTy.getSizeInBits() != MemSz) return SDValue(); 13542 13543 EVT LoadUnitVecVT = EVT::getVectorVT(*DAG.getContext(), SclrLoadTy, 13544 RegSz/SclrLoadTy.getSizeInBits()); 13545 13546 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), MemVT.getScalarType(), 13547 RegSz/MemVT.getScalarType().getSizeInBits()); 13548 // Can't shuffle using an illegal type. 13549 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13550 13551 // Perform a single load. 13552 SDValue ScalarLoad = DAG.getLoad(SclrLoadTy, dl, Ld->getChain(), 13553 Ld->getBasePtr(), 13554 Ld->getPointerInfo(), Ld->isVolatile(), 13555 Ld->isNonTemporal(), Ld->getAlignment()); 13556 13557 // Insert the word loaded into a vector. 13558 SDValue ScalarInVector = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 13559 LoadUnitVecVT, ScalarLoad); 13560 13561 // Bitcast the loaded value to a vector of the original element type, in 13562 // the size of the target vector type. 13563 SDValue SlicedVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, ScalarInVector); 13564 unsigned SizeRatio = RegSz/MemSz; 13565 13566 // Redistribute the loaded elements into the different locations. 13567 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13568 for (unsigned i = 0; i < NumElems; i++) ShuffleVec[i*SizeRatio] = i; 13569 13570 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, SlicedVec, 13571 DAG.getUNDEF(SlicedVec.getValueType()), 13572 ShuffleVec.data()); 13573 13574 // Bitcast to the requested type. 13575 Shuff = DAG.getNode(ISD::BITCAST, dl, RegVT, Shuff); 13576 // Replace the original load with the new sequence 13577 // and return the new chain. 13578 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Shuff); 13579 return SDValue(ScalarLoad.getNode(), 1); 13580 } 13581 13582 return SDValue(); 13583 } 13584 13585 /// PerformSTORECombine - Do target-specific dag combines on STORE nodes. 13586 static SDValue PerformSTORECombine(SDNode *N, SelectionDAG &DAG, 13587 const X86Subtarget *Subtarget) { 13588 StoreSDNode *St = cast<StoreSDNode>(N); 13589 EVT VT = St->getValue().getValueType(); 13590 EVT StVT = St->getMemoryVT(); 13591 DebugLoc dl = St->getDebugLoc(); 13592 SDValue StoredVal = St->getOperand(1); 13593 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13594 13595 // If we are saving a concatination of two XMM registers, perform two stores. 13596 // This is better in Sandy Bridge cause one 256-bit mem op is done via two 13597 // 128-bit ones. If in the future the cost becomes only one memory access the 13598 // first version would be better. 13599 if (VT.getSizeInBits() == 256 && 13600 StoredVal.getNode()->getOpcode() == ISD::CONCAT_VECTORS && 13601 StoredVal.getNumOperands() == 2) { 13602 13603 SDValue Value0 = StoredVal.getOperand(0); 13604 SDValue Value1 = StoredVal.getOperand(1); 13605 13606 SDValue Stride = DAG.getConstant(16, TLI.getPointerTy()); 13607 SDValue Ptr0 = St->getBasePtr(); 13608 SDValue Ptr1 = DAG.getNode(ISD::ADD, dl, Ptr0.getValueType(), Ptr0, Stride); 13609 13610 SDValue Ch0 = DAG.getStore(St->getChain(), dl, Value0, Ptr0, 13611 St->getPointerInfo(), St->isVolatile(), 13612 St->isNonTemporal(), St->getAlignment()); 13613 SDValue Ch1 = DAG.getStore(St->getChain(), dl, Value1, Ptr1, 13614 St->getPointerInfo(), St->isVolatile(), 13615 St->isNonTemporal(), St->getAlignment()); 13616 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ch0, Ch1); 13617 } 13618 13619 // Optimize trunc store (of multiple scalars) to shuffle and store. 13620 // First, pack all of the elements in one place. Next, store to memory 13621 // in fewer chunks. 13622 if (St->isTruncatingStore() && VT.isVector()) { 13623 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13624 unsigned NumElems = VT.getVectorNumElements(); 13625 assert(StVT != VT && "Cannot truncate to the same type"); 13626 unsigned FromSz = VT.getVectorElementType().getSizeInBits(); 13627 unsigned ToSz = StVT.getVectorElementType().getSizeInBits(); 13628 13629 // From, To sizes and ElemCount must be pow of two 13630 if (!isPowerOf2_32(NumElems * FromSz * ToSz)) return SDValue(); 13631 // We are going to use the original vector elt for storing. 13632 // Accumulated smaller vector elements must be a multiple of the store size. 13633 if (0 != (NumElems * FromSz) % ToSz) return SDValue(); 13634 13635 unsigned SizeRatio = FromSz / ToSz; 13636 13637 assert(SizeRatio * NumElems * ToSz == VT.getSizeInBits()); 13638 13639 // Create a type on which we perform the shuffle 13640 EVT WideVecVT = EVT::getVectorVT(*DAG.getContext(), 13641 StVT.getScalarType(), NumElems*SizeRatio); 13642 13643 assert(WideVecVT.getSizeInBits() == VT.getSizeInBits()); 13644 13645 SDValue WideVec = DAG.getNode(ISD::BITCAST, dl, WideVecVT, St->getValue()); 13646 SmallVector<int, 8> ShuffleVec(NumElems * SizeRatio, -1); 13647 for (unsigned i = 0; i < NumElems; i++ ) ShuffleVec[i] = i * SizeRatio; 13648 13649 // Can't shuffle using an illegal type 13650 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); 13651 13652 SDValue Shuff = DAG.getVectorShuffle(WideVecVT, dl, WideVec, 13653 DAG.getUNDEF(WideVec.getValueType()), 13654 ShuffleVec.data()); 13655 // At this point all of the data is stored at the bottom of the 13656 // register. We now need to save it to mem. 13657 13658 // Find the largest store unit 13659 MVT StoreType = MVT::i8; 13660 for (unsigned tp = MVT::FIRST_INTEGER_VALUETYPE; 13661 tp < MVT::LAST_INTEGER_VALUETYPE; ++tp) { 13662 MVT Tp = (MVT::SimpleValueType)tp; 13663 if (TLI.isTypeLegal(Tp) && StoreType.getSizeInBits() < NumElems * ToSz) 13664 StoreType = Tp; 13665 } 13666 13667 // Bitcast the original vector into a vector of store-size units 13668 EVT StoreVecVT = EVT::getVectorVT(*DAG.getContext(), 13669 StoreType, VT.getSizeInBits()/EVT(StoreType).getSizeInBits()); 13670 assert(StoreVecVT.getSizeInBits() == VT.getSizeInBits()); 13671 SDValue ShuffWide = DAG.getNode(ISD::BITCAST, dl, StoreVecVT, Shuff); 13672 SmallVector<SDValue, 8> Chains; 13673 SDValue Increment = DAG.getConstant(StoreType.getSizeInBits()/8, 13674 TLI.getPointerTy()); 13675 SDValue Ptr = St->getBasePtr(); 13676 13677 // Perform one or more big stores into memory. 13678 for (unsigned i = 0; i < (ToSz*NumElems)/StoreType.getSizeInBits() ; i++) { 13679 SDValue SubVec = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 13680 StoreType, ShuffWide, 13681 DAG.getIntPtrConstant(i)); 13682 SDValue Ch = DAG.getStore(St->getChain(), dl, SubVec, Ptr, 13683 St->getPointerInfo(), St->isVolatile(), 13684 St->isNonTemporal(), St->getAlignment()); 13685 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 13686 Chains.push_back(Ch); 13687 } 13688 13689 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], 13690 Chains.size()); 13691 } 13692 13693 13694 // Turn load->store of MMX types into GPR load/stores. This avoids clobbering 13695 // the FP state in cases where an emms may be missing. 13696 // A preferable solution to the general problem is to figure out the right 13697 // places to insert EMMS. This qualifies as a quick hack. 13698 13699 // Similarly, turn load->store of i64 into double load/stores in 32-bit mode. 13700 if (VT.getSizeInBits() != 64) 13701 return SDValue(); 13702 13703 const Function *F = DAG.getMachineFunction().getFunction(); 13704 bool NoImplicitFloatOps = F->hasFnAttr(Attribute::NoImplicitFloat); 13705 bool F64IsLegal = !UseSoftFloat && !NoImplicitFloatOps 13706 && Subtarget->hasXMMInt(); 13707 if ((VT.isVector() || 13708 (VT == MVT::i64 && F64IsLegal && !Subtarget->is64Bit())) && 13709 isa<LoadSDNode>(St->getValue()) && 13710 !cast<LoadSDNode>(St->getValue())->isVolatile() && 13711 St->getChain().hasOneUse() && !St->isVolatile()) { 13712 SDNode* LdVal = St->getValue().getNode(); 13713 LoadSDNode *Ld = 0; 13714 int TokenFactorIndex = -1; 13715 SmallVector<SDValue, 8> Ops; 13716 SDNode* ChainVal = St->getChain().getNode(); 13717 // Must be a store of a load. We currently handle two cases: the load 13718 // is a direct child, and it's under an intervening TokenFactor. It is 13719 // possible to dig deeper under nested TokenFactors. 13720 if (ChainVal == LdVal) 13721 Ld = cast<LoadSDNode>(St->getChain()); 13722 else if (St->getValue().hasOneUse() && 13723 ChainVal->getOpcode() == ISD::TokenFactor) { 13724 for (unsigned i=0, e = ChainVal->getNumOperands(); i != e; ++i) { 13725 if (ChainVal->getOperand(i).getNode() == LdVal) { 13726 TokenFactorIndex = i; 13727 Ld = cast<LoadSDNode>(St->getValue()); 13728 } else 13729 Ops.push_back(ChainVal->getOperand(i)); 13730 } 13731 } 13732 13733 if (!Ld || !ISD::isNormalLoad(Ld)) 13734 return SDValue(); 13735 13736 // If this is not the MMX case, i.e. we are just turning i64 load/store 13737 // into f64 load/store, avoid the transformation if there are multiple 13738 // uses of the loaded value. 13739 if (!VT.isVector() && !Ld->hasNUsesOfValue(1, 0)) 13740 return SDValue(); 13741 13742 DebugLoc LdDL = Ld->getDebugLoc(); 13743 DebugLoc StDL = N->getDebugLoc(); 13744 // If we are a 64-bit capable x86, lower to a single movq load/store pair. 13745 // Otherwise, if it's legal to use f64 SSE instructions, use f64 load/store 13746 // pair instead. 13747 if (Subtarget->is64Bit() || F64IsLegal) { 13748 EVT LdVT = Subtarget->is64Bit() ? MVT::i64 : MVT::f64; 13749 SDValue NewLd = DAG.getLoad(LdVT, LdDL, Ld->getChain(), Ld->getBasePtr(), 13750 Ld->getPointerInfo(), Ld->isVolatile(), 13751 Ld->isNonTemporal(), Ld->getAlignment()); 13752 SDValue NewChain = NewLd.getValue(1); 13753 if (TokenFactorIndex != -1) { 13754 Ops.push_back(NewChain); 13755 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13756 Ops.size()); 13757 } 13758 return DAG.getStore(NewChain, StDL, NewLd, St->getBasePtr(), 13759 St->getPointerInfo(), 13760 St->isVolatile(), St->isNonTemporal(), 13761 St->getAlignment()); 13762 } 13763 13764 // Otherwise, lower to two pairs of 32-bit loads / stores. 13765 SDValue LoAddr = Ld->getBasePtr(); 13766 SDValue HiAddr = DAG.getNode(ISD::ADD, LdDL, MVT::i32, LoAddr, 13767 DAG.getConstant(4, MVT::i32)); 13768 13769 SDValue LoLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), LoAddr, 13770 Ld->getPointerInfo(), 13771 Ld->isVolatile(), Ld->isNonTemporal(), 13772 Ld->getAlignment()); 13773 SDValue HiLd = DAG.getLoad(MVT::i32, LdDL, Ld->getChain(), HiAddr, 13774 Ld->getPointerInfo().getWithOffset(4), 13775 Ld->isVolatile(), Ld->isNonTemporal(), 13776 MinAlign(Ld->getAlignment(), 4)); 13777 13778 SDValue NewChain = LoLd.getValue(1); 13779 if (TokenFactorIndex != -1) { 13780 Ops.push_back(LoLd); 13781 Ops.push_back(HiLd); 13782 NewChain = DAG.getNode(ISD::TokenFactor, LdDL, MVT::Other, &Ops[0], 13783 Ops.size()); 13784 } 13785 13786 LoAddr = St->getBasePtr(); 13787 HiAddr = DAG.getNode(ISD::ADD, StDL, MVT::i32, LoAddr, 13788 DAG.getConstant(4, MVT::i32)); 13789 13790 SDValue LoSt = DAG.getStore(NewChain, StDL, LoLd, LoAddr, 13791 St->getPointerInfo(), 13792 St->isVolatile(), St->isNonTemporal(), 13793 St->getAlignment()); 13794 SDValue HiSt = DAG.getStore(NewChain, StDL, HiLd, HiAddr, 13795 St->getPointerInfo().getWithOffset(4), 13796 St->isVolatile(), 13797 St->isNonTemporal(), 13798 MinAlign(St->getAlignment(), 4)); 13799 return DAG.getNode(ISD::TokenFactor, StDL, MVT::Other, LoSt, HiSt); 13800 } 13801 return SDValue(); 13802 } 13803 13804 /// isHorizontalBinOp - Return 'true' if this vector operation is "horizontal" 13805 /// and return the operands for the horizontal operation in LHS and RHS. A 13806 /// horizontal operation performs the binary operation on successive elements 13807 /// of its first operand, then on successive elements of its second operand, 13808 /// returning the resulting values in a vector. For example, if 13809 /// A = < float a0, float a1, float a2, float a3 > 13810 /// and 13811 /// B = < float b0, float b1, float b2, float b3 > 13812 /// then the result of doing a horizontal operation on A and B is 13813 /// A horizontal-op B = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 >. 13814 /// In short, LHS and RHS are inspected to see if LHS op RHS is of the form 13815 /// A horizontal-op B, for some already available A and B, and if so then LHS is 13816 /// set to A, RHS to B, and the routine returns 'true'. 13817 /// Note that the binary operation should have the property that if one of the 13818 /// operands is UNDEF then the result is UNDEF. 13819 static bool isHorizontalBinOp(SDValue &LHS, SDValue &RHS, bool isCommutative) { 13820 // Look for the following pattern: if 13821 // A = < float a0, float a1, float a2, float a3 > 13822 // B = < float b0, float b1, float b2, float b3 > 13823 // and 13824 // LHS = VECTOR_SHUFFLE A, B, <0, 2, 4, 6> 13825 // RHS = VECTOR_SHUFFLE A, B, <1, 3, 5, 7> 13826 // then LHS op RHS = < a0 op a1, a2 op a3, b0 op b1, b2 op b3 > 13827 // which is A horizontal-op B. 13828 13829 // At least one of the operands should be a vector shuffle. 13830 if (LHS.getOpcode() != ISD::VECTOR_SHUFFLE && 13831 RHS.getOpcode() != ISD::VECTOR_SHUFFLE) 13832 return false; 13833 13834 EVT VT = LHS.getValueType(); 13835 unsigned N = VT.getVectorNumElements(); 13836 13837 // View LHS in the form 13838 // LHS = VECTOR_SHUFFLE A, B, LMask 13839 // If LHS is not a shuffle then pretend it is the shuffle 13840 // LHS = VECTOR_SHUFFLE LHS, undef, <0, 1, ..., N-1> 13841 // NOTE: in what follows a default initialized SDValue represents an UNDEF of 13842 // type VT. 13843 SDValue A, B; 13844 SmallVector<int, 8> LMask(N); 13845 if (LHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 13846 if (LHS.getOperand(0).getOpcode() != ISD::UNDEF) 13847 A = LHS.getOperand(0); 13848 if (LHS.getOperand(1).getOpcode() != ISD::UNDEF) 13849 B = LHS.getOperand(1); 13850 cast<ShuffleVectorSDNode>(LHS.getNode())->getMask(LMask); 13851 } else { 13852 if (LHS.getOpcode() != ISD::UNDEF) 13853 A = LHS; 13854 for (unsigned i = 0; i != N; ++i) 13855 LMask[i] = i; 13856 } 13857 13858 // Likewise, view RHS in the form 13859 // RHS = VECTOR_SHUFFLE C, D, RMask 13860 SDValue C, D; 13861 SmallVector<int, 8> RMask(N); 13862 if (RHS.getOpcode() == ISD::VECTOR_SHUFFLE) { 13863 if (RHS.getOperand(0).getOpcode() != ISD::UNDEF) 13864 C = RHS.getOperand(0); 13865 if (RHS.getOperand(1).getOpcode() != ISD::UNDEF) 13866 D = RHS.getOperand(1); 13867 cast<ShuffleVectorSDNode>(RHS.getNode())->getMask(RMask); 13868 } else { 13869 if (RHS.getOpcode() != ISD::UNDEF) 13870 C = RHS; 13871 for (unsigned i = 0; i != N; ++i) 13872 RMask[i] = i; 13873 } 13874 13875 // Check that the shuffles are both shuffling the same vectors. 13876 if (!(A == C && B == D) && !(A == D && B == C)) 13877 return false; 13878 13879 // If everything is UNDEF then bail out: it would be better to fold to UNDEF. 13880 if (!A.getNode() && !B.getNode()) 13881 return false; 13882 13883 // If A and B occur in reverse order in RHS, then "swap" them (which means 13884 // rewriting the mask). 13885 if (A != C) 13886 for (unsigned i = 0; i != N; ++i) { 13887 unsigned Idx = RMask[i]; 13888 if (Idx < N) 13889 RMask[i] += N; 13890 else if (Idx < 2*N) 13891 RMask[i] -= N; 13892 } 13893 13894 // At this point LHS and RHS are equivalent to 13895 // LHS = VECTOR_SHUFFLE A, B, LMask 13896 // RHS = VECTOR_SHUFFLE A, B, RMask 13897 // Check that the masks correspond to performing a horizontal operation. 13898 for (unsigned i = 0; i != N; ++i) { 13899 unsigned LIdx = LMask[i], RIdx = RMask[i]; 13900 13901 // Ignore any UNDEF components. 13902 if (LIdx >= 2*N || RIdx >= 2*N || (!A.getNode() && (LIdx < N || RIdx < N)) 13903 || (!B.getNode() && (LIdx >= N || RIdx >= N))) 13904 continue; 13905 13906 // Check that successive elements are being operated on. If not, this is 13907 // not a horizontal operation. 13908 if (!(LIdx == 2*i && RIdx == 2*i + 1) && 13909 !(isCommutative && LIdx == 2*i + 1 && RIdx == 2*i)) 13910 return false; 13911 } 13912 13913 LHS = A.getNode() ? A : B; // If A is 'UNDEF', use B for it. 13914 RHS = B.getNode() ? B : A; // If B is 'UNDEF', use A for it. 13915 return true; 13916 } 13917 13918 /// PerformFADDCombine - Do target-specific dag combines on floating point adds. 13919 static SDValue PerformFADDCombine(SDNode *N, SelectionDAG &DAG, 13920 const X86Subtarget *Subtarget) { 13921 EVT VT = N->getValueType(0); 13922 SDValue LHS = N->getOperand(0); 13923 SDValue RHS = N->getOperand(1); 13924 13925 // Try to synthesize horizontal adds from adds of shuffles. 13926 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 13927 (VT == MVT::v4f32 || VT == MVT::v2f64) && 13928 isHorizontalBinOp(LHS, RHS, true)) 13929 return DAG.getNode(X86ISD::FHADD, N->getDebugLoc(), VT, LHS, RHS); 13930 return SDValue(); 13931 } 13932 13933 /// PerformFSUBCombine - Do target-specific dag combines on floating point subs. 13934 static SDValue PerformFSUBCombine(SDNode *N, SelectionDAG &DAG, 13935 const X86Subtarget *Subtarget) { 13936 EVT VT = N->getValueType(0); 13937 SDValue LHS = N->getOperand(0); 13938 SDValue RHS = N->getOperand(1); 13939 13940 // Try to synthesize horizontal subs from subs of shuffles. 13941 if ((Subtarget->hasSSE3() || Subtarget->hasAVX()) && 13942 (VT == MVT::v4f32 || VT == MVT::v2f64) && 13943 isHorizontalBinOp(LHS, RHS, false)) 13944 return DAG.getNode(X86ISD::FHSUB, N->getDebugLoc(), VT, LHS, RHS); 13945 return SDValue(); 13946 } 13947 13948 /// PerformFORCombine - Do target-specific dag combines on X86ISD::FOR and 13949 /// X86ISD::FXOR nodes. 13950 static SDValue PerformFORCombine(SDNode *N, SelectionDAG &DAG) { 13951 assert(N->getOpcode() == X86ISD::FOR || N->getOpcode() == X86ISD::FXOR); 13952 // F[X]OR(0.0, x) -> x 13953 // F[X]OR(x, 0.0) -> x 13954 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13955 if (C->getValueAPF().isPosZero()) 13956 return N->getOperand(1); 13957 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13958 if (C->getValueAPF().isPosZero()) 13959 return N->getOperand(0); 13960 return SDValue(); 13961 } 13962 13963 /// PerformFANDCombine - Do target-specific dag combines on X86ISD::FAND nodes. 13964 static SDValue PerformFANDCombine(SDNode *N, SelectionDAG &DAG) { 13965 // FAND(0.0, x) -> 0.0 13966 // FAND(x, 0.0) -> 0.0 13967 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(0))) 13968 if (C->getValueAPF().isPosZero()) 13969 return N->getOperand(0); 13970 if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(N->getOperand(1))) 13971 if (C->getValueAPF().isPosZero()) 13972 return N->getOperand(1); 13973 return SDValue(); 13974 } 13975 13976 static SDValue PerformBTCombine(SDNode *N, 13977 SelectionDAG &DAG, 13978 TargetLowering::DAGCombinerInfo &DCI) { 13979 // BT ignores high bits in the bit index operand. 13980 SDValue Op1 = N->getOperand(1); 13981 if (Op1.hasOneUse()) { 13982 unsigned BitWidth = Op1.getValueSizeInBits(); 13983 APInt DemandedMask = APInt::getLowBitsSet(BitWidth, Log2_32(BitWidth)); 13984 APInt KnownZero, KnownOne; 13985 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(), 13986 !DCI.isBeforeLegalizeOps()); 13987 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 13988 if (TLO.ShrinkDemandedConstant(Op1, DemandedMask) || 13989 TLI.SimplifyDemandedBits(Op1, DemandedMask, KnownZero, KnownOne, TLO)) 13990 DCI.CommitTargetLoweringOpt(TLO); 13991 } 13992 return SDValue(); 13993 } 13994 13995 static SDValue PerformVZEXT_MOVLCombine(SDNode *N, SelectionDAG &DAG) { 13996 SDValue Op = N->getOperand(0); 13997 if (Op.getOpcode() == ISD::BITCAST) 13998 Op = Op.getOperand(0); 13999 EVT VT = N->getValueType(0), OpVT = Op.getValueType(); 14000 if (Op.getOpcode() == X86ISD::VZEXT_LOAD && 14001 VT.getVectorElementType().getSizeInBits() == 14002 OpVT.getVectorElementType().getSizeInBits()) { 14003 return DAG.getNode(ISD::BITCAST, N->getDebugLoc(), VT, Op); 14004 } 14005 return SDValue(); 14006 } 14007 14008 static SDValue PerformZExtCombine(SDNode *N, SelectionDAG &DAG) { 14009 // (i32 zext (and (i8 x86isd::setcc_carry), 1)) -> 14010 // (and (i32 x86isd::setcc_carry), 1) 14011 // This eliminates the zext. This transformation is necessary because 14012 // ISD::SETCC is always legalized to i8. 14013 DebugLoc dl = N->getDebugLoc(); 14014 SDValue N0 = N->getOperand(0); 14015 EVT VT = N->getValueType(0); 14016 if (N0.getOpcode() == ISD::AND && 14017 N0.hasOneUse() && 14018 N0.getOperand(0).hasOneUse()) { 14019 SDValue N00 = N0.getOperand(0); 14020 if (N00.getOpcode() != X86ISD::SETCC_CARRY) 14021 return SDValue(); 14022 ConstantSDNode *C = dyn_cast<ConstantSDNode>(N0.getOperand(1)); 14023 if (!C || C->getZExtValue() != 1) 14024 return SDValue(); 14025 return DAG.getNode(ISD::AND, dl, VT, 14026 DAG.getNode(X86ISD::SETCC_CARRY, dl, VT, 14027 N00.getOperand(0), N00.getOperand(1)), 14028 DAG.getConstant(1, VT)); 14029 } 14030 14031 return SDValue(); 14032 } 14033 14034 // Optimize RES = X86ISD::SETCC CONDCODE, EFLAG_INPUT 14035 static SDValue PerformSETCCCombine(SDNode *N, SelectionDAG &DAG) { 14036 unsigned X86CC = N->getConstantOperandVal(0); 14037 SDValue EFLAG = N->getOperand(1); 14038 DebugLoc DL = N->getDebugLoc(); 14039 14040 // Materialize "setb reg" as "sbb reg,reg", since it can be extended without 14041 // a zext and produces an all-ones bit which is more useful than 0/1 in some 14042 // cases. 14043 if (X86CC == X86::COND_B) 14044 return DAG.getNode(ISD::AND, DL, MVT::i8, 14045 DAG.getNode(X86ISD::SETCC_CARRY, DL, MVT::i8, 14046 DAG.getConstant(X86CC, MVT::i8), EFLAG), 14047 DAG.getConstant(1, MVT::i8)); 14048 14049 return SDValue(); 14050 } 14051 14052 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, 14053 const X86TargetLowering *XTLI) { 14054 SDValue Op0 = N->getOperand(0); 14055 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have 14056 // a 32-bit target where SSE doesn't support i64->FP operations. 14057 if (Op0.getOpcode() == ISD::LOAD) { 14058 LoadSDNode *Ld = cast<LoadSDNode>(Op0.getNode()); 14059 EVT VT = Ld->getValueType(0); 14060 if (!Ld->isVolatile() && !N->getValueType(0).isVector() && 14061 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() && 14062 !XTLI->getSubtarget()->is64Bit() && 14063 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { 14064 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), 14065 Ld->getChain(), Op0, DAG); 14066 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1)); 14067 return FILDChain; 14068 } 14069 } 14070 return SDValue(); 14071 } 14072 14073 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS 14074 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG, 14075 X86TargetLowering::DAGCombinerInfo &DCI) { 14076 // If the LHS and RHS of the ADC node are zero, then it can't overflow and 14077 // the result is either zero or one (depending on the input carry bit). 14078 // Strength reduce this down to a "set on carry" aka SETCC_CARRY&1. 14079 if (X86::isZeroNode(N->getOperand(0)) && 14080 X86::isZeroNode(N->getOperand(1)) && 14081 // We don't have a good way to replace an EFLAGS use, so only do this when 14082 // dead right now. 14083 SDValue(N, 1).use_empty()) { 14084 DebugLoc DL = N->getDebugLoc(); 14085 EVT VT = N->getValueType(0); 14086 SDValue CarryOut = DAG.getConstant(0, N->getValueType(1)); 14087 SDValue Res1 = DAG.getNode(ISD::AND, DL, VT, 14088 DAG.getNode(X86ISD::SETCC_CARRY, DL, VT, 14089 DAG.getConstant(X86::COND_B,MVT::i8), 14090 N->getOperand(2)), 14091 DAG.getConstant(1, VT)); 14092 return DCI.CombineTo(N, Res1, CarryOut); 14093 } 14094 14095 return SDValue(); 14096 } 14097 14098 // fold (add Y, (sete X, 0)) -> adc 0, Y 14099 // (add Y, (setne X, 0)) -> sbb -1, Y 14100 // (sub (sete X, 0), Y) -> sbb 0, Y 14101 // (sub (setne X, 0), Y) -> adc -1, Y 14102 static SDValue OptimizeConditionalInDecrement(SDNode *N, SelectionDAG &DAG) { 14103 DebugLoc DL = N->getDebugLoc(); 14104 14105 // Look through ZExts. 14106 SDValue Ext = N->getOperand(N->getOpcode() == ISD::SUB ? 1 : 0); 14107 if (Ext.getOpcode() != ISD::ZERO_EXTEND || !Ext.hasOneUse()) 14108 return SDValue(); 14109 14110 SDValue SetCC = Ext.getOperand(0); 14111 if (SetCC.getOpcode() != X86ISD::SETCC || !SetCC.hasOneUse()) 14112 return SDValue(); 14113 14114 X86::CondCode CC = (X86::CondCode)SetCC.getConstantOperandVal(0); 14115 if (CC != X86::COND_E && CC != X86::COND_NE) 14116 return SDValue(); 14117 14118 SDValue Cmp = SetCC.getOperand(1); 14119 if (Cmp.getOpcode() != X86ISD::CMP || !Cmp.hasOneUse() || 14120 !X86::isZeroNode(Cmp.getOperand(1)) || 14121 !Cmp.getOperand(0).getValueType().isInteger()) 14122 return SDValue(); 14123 14124 SDValue CmpOp0 = Cmp.getOperand(0); 14125 SDValue NewCmp = DAG.getNode(X86ISD::CMP, DL, MVT::i32, CmpOp0, 14126 DAG.getConstant(1, CmpOp0.getValueType())); 14127 14128 SDValue OtherVal = N->getOperand(N->getOpcode() == ISD::SUB ? 0 : 1); 14129 if (CC == X86::COND_NE) 14130 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::ADC : X86ISD::SBB, 14131 DL, OtherVal.getValueType(), OtherVal, 14132 DAG.getConstant(-1ULL, OtherVal.getValueType()), NewCmp); 14133 return DAG.getNode(N->getOpcode() == ISD::SUB ? X86ISD::SBB : X86ISD::ADC, 14134 DL, OtherVal.getValueType(), OtherVal, 14135 DAG.getConstant(0, OtherVal.getValueType()), NewCmp); 14136 } 14137 14138 static SDValue PerformSubCombine(SDNode *N, SelectionDAG &DAG) { 14139 SDValue Op0 = N->getOperand(0); 14140 SDValue Op1 = N->getOperand(1); 14141 14142 // X86 can't encode an immediate LHS of a sub. See if we can push the 14143 // negation into a preceding instruction. 14144 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op0)) { 14145 // If the RHS of the sub is a XOR with one use and a constant, invert the 14146 // immediate. Then add one to the LHS of the sub so we can turn 14147 // X-Y -> X+~Y+1, saving one register. 14148 if (Op1->hasOneUse() && Op1.getOpcode() == ISD::XOR && 14149 isa<ConstantSDNode>(Op1.getOperand(1))) { 14150 APInt XorC = cast<ConstantSDNode>(Op1.getOperand(1))->getAPIntValue(); 14151 EVT VT = Op0.getValueType(); 14152 SDValue NewXor = DAG.getNode(ISD::XOR, Op1.getDebugLoc(), VT, 14153 Op1.getOperand(0), 14154 DAG.getConstant(~XorC, VT)); 14155 return DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, NewXor, 14156 DAG.getConstant(C->getAPIntValue()+1, VT)); 14157 } 14158 } 14159 14160 return OptimizeConditionalInDecrement(N, DAG); 14161 } 14162 14163 SDValue X86TargetLowering::PerformDAGCombine(SDNode *N, 14164 DAGCombinerInfo &DCI) const { 14165 SelectionDAG &DAG = DCI.DAG; 14166 switch (N->getOpcode()) { 14167 default: break; 14168 case ISD::EXTRACT_VECTOR_ELT: 14169 return PerformEXTRACT_VECTOR_ELTCombine(N, DAG, *this); 14170 case ISD::VSELECT: 14171 case ISD::SELECT: return PerformSELECTCombine(N, DAG, Subtarget); 14172 case X86ISD::CMOV: return PerformCMOVCombine(N, DAG, DCI); 14173 case ISD::ADD: return OptimizeConditionalInDecrement(N, DAG); 14174 case ISD::SUB: return PerformSubCombine(N, DAG); 14175 case X86ISD::ADC: return PerformADCCombine(N, DAG, DCI); 14176 case ISD::MUL: return PerformMulCombine(N, DAG, DCI); 14177 case ISD::SHL: 14178 case ISD::SRA: 14179 case ISD::SRL: return PerformShiftCombine(N, DAG, Subtarget); 14180 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget); 14181 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget); 14182 case ISD::LOAD: return PerformLOADCombine(N, DAG, Subtarget); 14183 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget); 14184 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this); 14185 case ISD::FADD: return PerformFADDCombine(N, DAG, Subtarget); 14186 case ISD::FSUB: return PerformFSUBCombine(N, DAG, Subtarget); 14187 case X86ISD::FXOR: 14188 case X86ISD::FOR: return PerformFORCombine(N, DAG); 14189 case X86ISD::FAND: return PerformFANDCombine(N, DAG); 14190 case X86ISD::BT: return PerformBTCombine(N, DAG, DCI); 14191 case X86ISD::VZEXT_MOVL: return PerformVZEXT_MOVLCombine(N, DAG); 14192 case ISD::ZERO_EXTEND: return PerformZExtCombine(N, DAG); 14193 case X86ISD::SETCC: return PerformSETCCCombine(N, DAG); 14194 case X86ISD::SHUFPS: // Handle all target specific shuffles 14195 case X86ISD::SHUFPD: 14196 case X86ISD::PALIGN: 14197 case X86ISD::PUNPCKHBW: 14198 case X86ISD::PUNPCKHWD: 14199 case X86ISD::PUNPCKHDQ: 14200 case X86ISD::PUNPCKHQDQ: 14201 case X86ISD::UNPCKHPS: 14202 case X86ISD::UNPCKHPD: 14203 case X86ISD::VUNPCKHPSY: 14204 case X86ISD::VUNPCKHPDY: 14205 case X86ISD::PUNPCKLBW: 14206 case X86ISD::PUNPCKLWD: 14207 case X86ISD::PUNPCKLDQ: 14208 case X86ISD::PUNPCKLQDQ: 14209 case X86ISD::UNPCKLPS: 14210 case X86ISD::UNPCKLPD: 14211 case X86ISD::VUNPCKLPSY: 14212 case X86ISD::VUNPCKLPDY: 14213 case X86ISD::MOVHLPS: 14214 case X86ISD::MOVLHPS: 14215 case X86ISD::PSHUFD: 14216 case X86ISD::PSHUFHW: 14217 case X86ISD::PSHUFLW: 14218 case X86ISD::MOVSS: 14219 case X86ISD::MOVSD: 14220 case X86ISD::VPERMILPS: 14221 case X86ISD::VPERMILPSY: 14222 case X86ISD::VPERMILPD: 14223 case X86ISD::VPERMILPDY: 14224 case X86ISD::VPERM2F128: 14225 case ISD::VECTOR_SHUFFLE: return PerformShuffleCombine(N, DAG, DCI,Subtarget); 14226 } 14227 14228 return SDValue(); 14229 } 14230 14231 /// isTypeDesirableForOp - Return true if the target has native support for 14232 /// the specified value type and it is 'desirable' to use the type for the 14233 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16 14234 /// instruction encodings are longer and some i16 instructions are slow. 14235 bool X86TargetLowering::isTypeDesirableForOp(unsigned Opc, EVT VT) const { 14236 if (!isTypeLegal(VT)) 14237 return false; 14238 if (VT != MVT::i16) 14239 return true; 14240 14241 switch (Opc) { 14242 default: 14243 return true; 14244 case ISD::LOAD: 14245 case ISD::SIGN_EXTEND: 14246 case ISD::ZERO_EXTEND: 14247 case ISD::ANY_EXTEND: 14248 case ISD::SHL: 14249 case ISD::SRL: 14250 case ISD::SUB: 14251 case ISD::ADD: 14252 case ISD::MUL: 14253 case ISD::AND: 14254 case ISD::OR: 14255 case ISD::XOR: 14256 return false; 14257 } 14258 } 14259 14260 /// IsDesirableToPromoteOp - This method query the target whether it is 14261 /// beneficial for dag combiner to promote the specified node. If true, it 14262 /// should return the desired promotion type by reference. 14263 bool X86TargetLowering::IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const { 14264 EVT VT = Op.getValueType(); 14265 if (VT != MVT::i16) 14266 return false; 14267 14268 bool Promote = false; 14269 bool Commute = false; 14270 switch (Op.getOpcode()) { 14271 default: break; 14272 case ISD::LOAD: { 14273 LoadSDNode *LD = cast<LoadSDNode>(Op); 14274 // If the non-extending load has a single use and it's not live out, then it 14275 // might be folded. 14276 if (LD->getExtensionType() == ISD::NON_EXTLOAD /*&& 14277 Op.hasOneUse()*/) { 14278 for (SDNode::use_iterator UI = Op.getNode()->use_begin(), 14279 UE = Op.getNode()->use_end(); UI != UE; ++UI) { 14280 // The only case where we'd want to promote LOAD (rather then it being 14281 // promoted as an operand is when it's only use is liveout. 14282 if (UI->getOpcode() != ISD::CopyToReg) 14283 return false; 14284 } 14285 } 14286 Promote = true; 14287 break; 14288 } 14289 case ISD::SIGN_EXTEND: 14290 case ISD::ZERO_EXTEND: 14291 case ISD::ANY_EXTEND: 14292 Promote = true; 14293 break; 14294 case ISD::SHL: 14295 case ISD::SRL: { 14296 SDValue N0 = Op.getOperand(0); 14297 // Look out for (store (shl (load), x)). 14298 if (MayFoldLoad(N0) && MayFoldIntoStore(Op)) 14299 return false; 14300 Promote = true; 14301 break; 14302 } 14303 case ISD::ADD: 14304 case ISD::MUL: 14305 case ISD::AND: 14306 case ISD::OR: 14307 case ISD::XOR: 14308 Commute = true; 14309 // fallthrough 14310 case ISD::SUB: { 14311 SDValue N0 = Op.getOperand(0); 14312 SDValue N1 = Op.getOperand(1); 14313 if (!Commute && MayFoldLoad(N1)) 14314 return false; 14315 // Avoid disabling potential load folding opportunities. 14316 if (MayFoldLoad(N0) && (!isa<ConstantSDNode>(N1) || MayFoldIntoStore(Op))) 14317 return false; 14318 if (MayFoldLoad(N1) && (!isa<ConstantSDNode>(N0) || MayFoldIntoStore(Op))) 14319 return false; 14320 Promote = true; 14321 } 14322 } 14323 14324 PVT = MVT::i32; 14325 return Promote; 14326 } 14327 14328 //===----------------------------------------------------------------------===// 14329 // X86 Inline Assembly Support 14330 //===----------------------------------------------------------------------===// 14331 14332 bool X86TargetLowering::ExpandInlineAsm(CallInst *CI) const { 14333 InlineAsm *IA = cast<InlineAsm>(CI->getCalledValue()); 14334 14335 std::string AsmStr = IA->getAsmString(); 14336 14337 // TODO: should remove alternatives from the asmstring: "foo {a|b}" -> "foo a" 14338 SmallVector<StringRef, 4> AsmPieces; 14339 SplitString(AsmStr, AsmPieces, ";\n"); 14340 14341 switch (AsmPieces.size()) { 14342 default: return false; 14343 case 1: 14344 AsmStr = AsmPieces[0]; 14345 AsmPieces.clear(); 14346 SplitString(AsmStr, AsmPieces, " \t"); // Split with whitespace. 14347 14348 // FIXME: this should verify that we are targeting a 486 or better. If not, 14349 // we will turn this bswap into something that will be lowered to logical ops 14350 // instead of emitting the bswap asm. For now, we don't support 486 or lower 14351 // so don't worry about this. 14352 // bswap $0 14353 if (AsmPieces.size() == 2 && 14354 (AsmPieces[0] == "bswap" || 14355 AsmPieces[0] == "bswapq" || 14356 AsmPieces[0] == "bswapl") && 14357 (AsmPieces[1] == "$0" || 14358 AsmPieces[1] == "${0:q}")) { 14359 // No need to check constraints, nothing other than the equivalent of 14360 // "=r,0" would be valid here. 14361 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14362 if (!Ty || Ty->getBitWidth() % 16 != 0) 14363 return false; 14364 return IntrinsicLowering::LowerToByteSwap(CI); 14365 } 14366 // rorw $$8, ${0:w} --> llvm.bswap.i16 14367 if (CI->getType()->isIntegerTy(16) && 14368 AsmPieces.size() == 3 && 14369 (AsmPieces[0] == "rorw" || AsmPieces[0] == "rolw") && 14370 AsmPieces[1] == "$$8," && 14371 AsmPieces[2] == "${0:w}" && 14372 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14373 AsmPieces.clear(); 14374 const std::string &ConstraintsStr = IA->getConstraintString(); 14375 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14376 std::sort(AsmPieces.begin(), AsmPieces.end()); 14377 if (AsmPieces.size() == 4 && 14378 AsmPieces[0] == "~{cc}" && 14379 AsmPieces[1] == "~{dirflag}" && 14380 AsmPieces[2] == "~{flags}" && 14381 AsmPieces[3] == "~{fpsr}") { 14382 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14383 if (!Ty || Ty->getBitWidth() % 16 != 0) 14384 return false; 14385 return IntrinsicLowering::LowerToByteSwap(CI); 14386 } 14387 } 14388 break; 14389 case 3: 14390 if (CI->getType()->isIntegerTy(32) && 14391 IA->getConstraintString().compare(0, 5, "=r,0,") == 0) { 14392 SmallVector<StringRef, 4> Words; 14393 SplitString(AsmPieces[0], Words, " \t,"); 14394 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14395 Words[2] == "${0:w}") { 14396 Words.clear(); 14397 SplitString(AsmPieces[1], Words, " \t,"); 14398 if (Words.size() == 3 && Words[0] == "rorl" && Words[1] == "$$16" && 14399 Words[2] == "$0") { 14400 Words.clear(); 14401 SplitString(AsmPieces[2], Words, " \t,"); 14402 if (Words.size() == 3 && Words[0] == "rorw" && Words[1] == "$$8" && 14403 Words[2] == "${0:w}") { 14404 AsmPieces.clear(); 14405 const std::string &ConstraintsStr = IA->getConstraintString(); 14406 SplitString(StringRef(ConstraintsStr).substr(5), AsmPieces, ","); 14407 std::sort(AsmPieces.begin(), AsmPieces.end()); 14408 if (AsmPieces.size() == 4 && 14409 AsmPieces[0] == "~{cc}" && 14410 AsmPieces[1] == "~{dirflag}" && 14411 AsmPieces[2] == "~{flags}" && 14412 AsmPieces[3] == "~{fpsr}") { 14413 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14414 if (!Ty || Ty->getBitWidth() % 16 != 0) 14415 return false; 14416 return IntrinsicLowering::LowerToByteSwap(CI); 14417 } 14418 } 14419 } 14420 } 14421 } 14422 14423 if (CI->getType()->isIntegerTy(64)) { 14424 InlineAsm::ConstraintInfoVector Constraints = IA->ParseConstraints(); 14425 if (Constraints.size() >= 2 && 14426 Constraints[0].Codes.size() == 1 && Constraints[0].Codes[0] == "A" && 14427 Constraints[1].Codes.size() == 1 && Constraints[1].Codes[0] == "0") { 14428 // bswap %eax / bswap %edx / xchgl %eax, %edx -> llvm.bswap.i64 14429 SmallVector<StringRef, 4> Words; 14430 SplitString(AsmPieces[0], Words, " \t"); 14431 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%eax") { 14432 Words.clear(); 14433 SplitString(AsmPieces[1], Words, " \t"); 14434 if (Words.size() == 2 && Words[0] == "bswap" && Words[1] == "%edx") { 14435 Words.clear(); 14436 SplitString(AsmPieces[2], Words, " \t,"); 14437 if (Words.size() == 3 && Words[0] == "xchgl" && Words[1] == "%eax" && 14438 Words[2] == "%edx") { 14439 IntegerType *Ty = dyn_cast<IntegerType>(CI->getType()); 14440 if (!Ty || Ty->getBitWidth() % 16 != 0) 14441 return false; 14442 return IntrinsicLowering::LowerToByteSwap(CI); 14443 } 14444 } 14445 } 14446 } 14447 } 14448 break; 14449 } 14450 return false; 14451 } 14452 14453 14454 14455 /// getConstraintType - Given a constraint letter, return the type of 14456 /// constraint it is for this target. 14457 X86TargetLowering::ConstraintType 14458 X86TargetLowering::getConstraintType(const std::string &Constraint) const { 14459 if (Constraint.size() == 1) { 14460 switch (Constraint[0]) { 14461 case 'R': 14462 case 'q': 14463 case 'Q': 14464 case 'f': 14465 case 't': 14466 case 'u': 14467 case 'y': 14468 case 'x': 14469 case 'Y': 14470 case 'l': 14471 return C_RegisterClass; 14472 case 'a': 14473 case 'b': 14474 case 'c': 14475 case 'd': 14476 case 'S': 14477 case 'D': 14478 case 'A': 14479 return C_Register; 14480 case 'I': 14481 case 'J': 14482 case 'K': 14483 case 'L': 14484 case 'M': 14485 case 'N': 14486 case 'G': 14487 case 'C': 14488 case 'e': 14489 case 'Z': 14490 return C_Other; 14491 default: 14492 break; 14493 } 14494 } 14495 return TargetLowering::getConstraintType(Constraint); 14496 } 14497 14498 /// Examine constraint type and operand type and determine a weight value. 14499 /// This object must already have been set up with the operand type 14500 /// and the current alternative constraint selected. 14501 TargetLowering::ConstraintWeight 14502 X86TargetLowering::getSingleConstraintMatchWeight( 14503 AsmOperandInfo &info, const char *constraint) const { 14504 ConstraintWeight weight = CW_Invalid; 14505 Value *CallOperandVal = info.CallOperandVal; 14506 // If we don't have a value, we can't do a match, 14507 // but allow it at the lowest weight. 14508 if (CallOperandVal == NULL) 14509 return CW_Default; 14510 Type *type = CallOperandVal->getType(); 14511 // Look at the constraint type. 14512 switch (*constraint) { 14513 default: 14514 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint); 14515 case 'R': 14516 case 'q': 14517 case 'Q': 14518 case 'a': 14519 case 'b': 14520 case 'c': 14521 case 'd': 14522 case 'S': 14523 case 'D': 14524 case 'A': 14525 if (CallOperandVal->getType()->isIntegerTy()) 14526 weight = CW_SpecificReg; 14527 break; 14528 case 'f': 14529 case 't': 14530 case 'u': 14531 if (type->isFloatingPointTy()) 14532 weight = CW_SpecificReg; 14533 break; 14534 case 'y': 14535 if (type->isX86_MMXTy() && Subtarget->hasMMX()) 14536 weight = CW_SpecificReg; 14537 break; 14538 case 'x': 14539 case 'Y': 14540 if ((type->getPrimitiveSizeInBits() == 128) && Subtarget->hasXMM()) 14541 weight = CW_Register; 14542 break; 14543 case 'I': 14544 if (ConstantInt *C = dyn_cast<ConstantInt>(info.CallOperandVal)) { 14545 if (C->getZExtValue() <= 31) 14546 weight = CW_Constant; 14547 } 14548 break; 14549 case 'J': 14550 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14551 if (C->getZExtValue() <= 63) 14552 weight = CW_Constant; 14553 } 14554 break; 14555 case 'K': 14556 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14557 if ((C->getSExtValue() >= -0x80) && (C->getSExtValue() <= 0x7f)) 14558 weight = CW_Constant; 14559 } 14560 break; 14561 case 'L': 14562 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14563 if ((C->getZExtValue() == 0xff) || (C->getZExtValue() == 0xffff)) 14564 weight = CW_Constant; 14565 } 14566 break; 14567 case 'M': 14568 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14569 if (C->getZExtValue() <= 3) 14570 weight = CW_Constant; 14571 } 14572 break; 14573 case 'N': 14574 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14575 if (C->getZExtValue() <= 0xff) 14576 weight = CW_Constant; 14577 } 14578 break; 14579 case 'G': 14580 case 'C': 14581 if (dyn_cast<ConstantFP>(CallOperandVal)) { 14582 weight = CW_Constant; 14583 } 14584 break; 14585 case 'e': 14586 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14587 if ((C->getSExtValue() >= -0x80000000LL) && 14588 (C->getSExtValue() <= 0x7fffffffLL)) 14589 weight = CW_Constant; 14590 } 14591 break; 14592 case 'Z': 14593 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal)) { 14594 if (C->getZExtValue() <= 0xffffffff) 14595 weight = CW_Constant; 14596 } 14597 break; 14598 } 14599 return weight; 14600 } 14601 14602 /// LowerXConstraint - try to replace an X constraint, which matches anything, 14603 /// with another that has more specific requirements based on the type of the 14604 /// corresponding operand. 14605 const char *X86TargetLowering:: 14606 LowerXConstraint(EVT ConstraintVT) const { 14607 // FP X constraints get lowered to SSE1/2 registers if available, otherwise 14608 // 'f' like normal targets. 14609 if (ConstraintVT.isFloatingPoint()) { 14610 if (Subtarget->hasXMMInt()) 14611 return "Y"; 14612 if (Subtarget->hasXMM()) 14613 return "x"; 14614 } 14615 14616 return TargetLowering::LowerXConstraint(ConstraintVT); 14617 } 14618 14619 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops 14620 /// vector. If it is invalid, don't add anything to Ops. 14621 void X86TargetLowering::LowerAsmOperandForConstraint(SDValue Op, 14622 std::string &Constraint, 14623 std::vector<SDValue>&Ops, 14624 SelectionDAG &DAG) const { 14625 SDValue Result(0, 0); 14626 14627 // Only support length 1 constraints for now. 14628 if (Constraint.length() > 1) return; 14629 14630 char ConstraintLetter = Constraint[0]; 14631 switch (ConstraintLetter) { 14632 default: break; 14633 case 'I': 14634 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14635 if (C->getZExtValue() <= 31) { 14636 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14637 break; 14638 } 14639 } 14640 return; 14641 case 'J': 14642 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14643 if (C->getZExtValue() <= 63) { 14644 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14645 break; 14646 } 14647 } 14648 return; 14649 case 'K': 14650 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14651 if ((int8_t)C->getSExtValue() == C->getSExtValue()) { 14652 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14653 break; 14654 } 14655 } 14656 return; 14657 case 'N': 14658 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14659 if (C->getZExtValue() <= 255) { 14660 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14661 break; 14662 } 14663 } 14664 return; 14665 case 'e': { 14666 // 32-bit signed value 14667 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14668 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14669 C->getSExtValue())) { 14670 // Widen to 64 bits here to get it sign extended. 14671 Result = DAG.getTargetConstant(C->getSExtValue(), MVT::i64); 14672 break; 14673 } 14674 // FIXME gcc accepts some relocatable values here too, but only in certain 14675 // memory models; it's complicated. 14676 } 14677 return; 14678 } 14679 case 'Z': { 14680 // 32-bit unsigned value 14681 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op)) { 14682 if (ConstantInt::isValueValidForType(Type::getInt32Ty(*DAG.getContext()), 14683 C->getZExtValue())) { 14684 Result = DAG.getTargetConstant(C->getZExtValue(), Op.getValueType()); 14685 break; 14686 } 14687 } 14688 // FIXME gcc accepts some relocatable values here too, but only in certain 14689 // memory models; it's complicated. 14690 return; 14691 } 14692 case 'i': { 14693 // Literal immediates are always ok. 14694 if (ConstantSDNode *CST = dyn_cast<ConstantSDNode>(Op)) { 14695 // Widen to 64 bits here to get it sign extended. 14696 Result = DAG.getTargetConstant(CST->getSExtValue(), MVT::i64); 14697 break; 14698 } 14699 14700 // In any sort of PIC mode addresses need to be computed at runtime by 14701 // adding in a register or some sort of table lookup. These can't 14702 // be used as immediates. 14703 if (Subtarget->isPICStyleGOT() || Subtarget->isPICStyleStubPIC()) 14704 return; 14705 14706 // If we are in non-pic codegen mode, we allow the address of a global (with 14707 // an optional displacement) to be used with 'i'. 14708 GlobalAddressSDNode *GA = 0; 14709 int64_t Offset = 0; 14710 14711 // Match either (GA), (GA+C), (GA+C1+C2), etc. 14712 while (1) { 14713 if ((GA = dyn_cast<GlobalAddressSDNode>(Op))) { 14714 Offset += GA->getOffset(); 14715 break; 14716 } else if (Op.getOpcode() == ISD::ADD) { 14717 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14718 Offset += C->getZExtValue(); 14719 Op = Op.getOperand(0); 14720 continue; 14721 } 14722 } else if (Op.getOpcode() == ISD::SUB) { 14723 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { 14724 Offset += -C->getZExtValue(); 14725 Op = Op.getOperand(0); 14726 continue; 14727 } 14728 } 14729 14730 // Otherwise, this isn't something we can handle, reject it. 14731 return; 14732 } 14733 14734 const GlobalValue *GV = GA->getGlobal(); 14735 // If we require an extra load to get this address, as in PIC mode, we 14736 // can't accept it. 14737 if (isGlobalStubReference(Subtarget->ClassifyGlobalReference(GV, 14738 getTargetMachine()))) 14739 return; 14740 14741 Result = DAG.getTargetGlobalAddress(GV, Op.getDebugLoc(), 14742 GA->getValueType(0), Offset); 14743 break; 14744 } 14745 } 14746 14747 if (Result.getNode()) { 14748 Ops.push_back(Result); 14749 return; 14750 } 14751 return TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG); 14752 } 14753 14754 std::pair<unsigned, const TargetRegisterClass*> 14755 X86TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint, 14756 EVT VT) const { 14757 // First, see if this is a constraint that directly corresponds to an LLVM 14758 // register class. 14759 if (Constraint.size() == 1) { 14760 // GCC Constraint Letters 14761 switch (Constraint[0]) { 14762 default: break; 14763 // TODO: Slight differences here in allocation order and leaving 14764 // RIP in the class. Do they matter any more here than they do 14765 // in the normal allocation? 14766 case 'q': // GENERAL_REGS in 64-bit mode, Q_REGS in 32-bit mode. 14767 if (Subtarget->is64Bit()) { 14768 if (VT == MVT::i32 || VT == MVT::f32) 14769 return std::make_pair(0U, X86::GR32RegisterClass); 14770 else if (VT == MVT::i16) 14771 return std::make_pair(0U, X86::GR16RegisterClass); 14772 else if (VT == MVT::i8 || VT == MVT::i1) 14773 return std::make_pair(0U, X86::GR8RegisterClass); 14774 else if (VT == MVT::i64 || VT == MVT::f64) 14775 return std::make_pair(0U, X86::GR64RegisterClass); 14776 break; 14777 } 14778 // 32-bit fallthrough 14779 case 'Q': // Q_REGS 14780 if (VT == MVT::i32 || VT == MVT::f32) 14781 return std::make_pair(0U, X86::GR32_ABCDRegisterClass); 14782 else if (VT == MVT::i16) 14783 return std::make_pair(0U, X86::GR16_ABCDRegisterClass); 14784 else if (VT == MVT::i8 || VT == MVT::i1) 14785 return std::make_pair(0U, X86::GR8_ABCD_LRegisterClass); 14786 else if (VT == MVT::i64) 14787 return std::make_pair(0U, X86::GR64_ABCDRegisterClass); 14788 break; 14789 case 'r': // GENERAL_REGS 14790 case 'l': // INDEX_REGS 14791 if (VT == MVT::i8 || VT == MVT::i1) 14792 return std::make_pair(0U, X86::GR8RegisterClass); 14793 if (VT == MVT::i16) 14794 return std::make_pair(0U, X86::GR16RegisterClass); 14795 if (VT == MVT::i32 || VT == MVT::f32 || !Subtarget->is64Bit()) 14796 return std::make_pair(0U, X86::GR32RegisterClass); 14797 return std::make_pair(0U, X86::GR64RegisterClass); 14798 case 'R': // LEGACY_REGS 14799 if (VT == MVT::i8 || VT == MVT::i1) 14800 return std::make_pair(0U, X86::GR8_NOREXRegisterClass); 14801 if (VT == MVT::i16) 14802 return std::make_pair(0U, X86::GR16_NOREXRegisterClass); 14803 if (VT == MVT::i32 || !Subtarget->is64Bit()) 14804 return std::make_pair(0U, X86::GR32_NOREXRegisterClass); 14805 return std::make_pair(0U, X86::GR64_NOREXRegisterClass); 14806 case 'f': // FP Stack registers. 14807 // If SSE is enabled for this VT, use f80 to ensure the isel moves the 14808 // value to the correct fpstack register class. 14809 if (VT == MVT::f32 && !isScalarFPTypeInSSEReg(VT)) 14810 return std::make_pair(0U, X86::RFP32RegisterClass); 14811 if (VT == MVT::f64 && !isScalarFPTypeInSSEReg(VT)) 14812 return std::make_pair(0U, X86::RFP64RegisterClass); 14813 return std::make_pair(0U, X86::RFP80RegisterClass); 14814 case 'y': // MMX_REGS if MMX allowed. 14815 if (!Subtarget->hasMMX()) break; 14816 return std::make_pair(0U, X86::VR64RegisterClass); 14817 case 'Y': // SSE_REGS if SSE2 allowed 14818 if (!Subtarget->hasXMMInt()) break; 14819 // FALL THROUGH. 14820 case 'x': // SSE_REGS if SSE1 allowed 14821 if (!Subtarget->hasXMM()) break; 14822 14823 switch (VT.getSimpleVT().SimpleTy) { 14824 default: break; 14825 // Scalar SSE types. 14826 case MVT::f32: 14827 case MVT::i32: 14828 return std::make_pair(0U, X86::FR32RegisterClass); 14829 case MVT::f64: 14830 case MVT::i64: 14831 return std::make_pair(0U, X86::FR64RegisterClass); 14832 // Vector types. 14833 case MVT::v16i8: 14834 case MVT::v8i16: 14835 case MVT::v4i32: 14836 case MVT::v2i64: 14837 case MVT::v4f32: 14838 case MVT::v2f64: 14839 return std::make_pair(0U, X86::VR128RegisterClass); 14840 } 14841 break; 14842 } 14843 } 14844 14845 // Use the default implementation in TargetLowering to convert the register 14846 // constraint into a member of a register class. 14847 std::pair<unsigned, const TargetRegisterClass*> Res; 14848 Res = TargetLowering::getRegForInlineAsmConstraint(Constraint, VT); 14849 14850 // Not found as a standard register? 14851 if (Res.second == 0) { 14852 // Map st(0) -> st(7) -> ST0 14853 if (Constraint.size() == 7 && Constraint[0] == '{' && 14854 tolower(Constraint[1]) == 's' && 14855 tolower(Constraint[2]) == 't' && 14856 Constraint[3] == '(' && 14857 (Constraint[4] >= '0' && Constraint[4] <= '7') && 14858 Constraint[5] == ')' && 14859 Constraint[6] == '}') { 14860 14861 Res.first = X86::ST0+Constraint[4]-'0'; 14862 Res.second = X86::RFP80RegisterClass; 14863 return Res; 14864 } 14865 14866 // GCC allows "st(0)" to be called just plain "st". 14867 if (StringRef("{st}").equals_lower(Constraint)) { 14868 Res.first = X86::ST0; 14869 Res.second = X86::RFP80RegisterClass; 14870 return Res; 14871 } 14872 14873 // flags -> EFLAGS 14874 if (StringRef("{flags}").equals_lower(Constraint)) { 14875 Res.first = X86::EFLAGS; 14876 Res.second = X86::CCRRegisterClass; 14877 return Res; 14878 } 14879 14880 // 'A' means EAX + EDX. 14881 if (Constraint == "A") { 14882 Res.first = X86::EAX; 14883 Res.second = X86::GR32_ADRegisterClass; 14884 return Res; 14885 } 14886 return Res; 14887 } 14888 14889 // Otherwise, check to see if this is a register class of the wrong value 14890 // type. For example, we want to map "{ax},i32" -> {eax}, we don't want it to 14891 // turn into {ax},{dx}. 14892 if (Res.second->hasType(VT)) 14893 return Res; // Correct type already, nothing to do. 14894 14895 // All of the single-register GCC register classes map their values onto 14896 // 16-bit register pieces "ax","dx","cx","bx","si","di","bp","sp". If we 14897 // really want an 8-bit or 32-bit register, map to the appropriate register 14898 // class and return the appropriate register. 14899 if (Res.second == X86::GR16RegisterClass) { 14900 if (VT == MVT::i8) { 14901 unsigned DestReg = 0; 14902 switch (Res.first) { 14903 default: break; 14904 case X86::AX: DestReg = X86::AL; break; 14905 case X86::DX: DestReg = X86::DL; break; 14906 case X86::CX: DestReg = X86::CL; break; 14907 case X86::BX: DestReg = X86::BL; break; 14908 } 14909 if (DestReg) { 14910 Res.first = DestReg; 14911 Res.second = X86::GR8RegisterClass; 14912 } 14913 } else if (VT == MVT::i32) { 14914 unsigned DestReg = 0; 14915 switch (Res.first) { 14916 default: break; 14917 case X86::AX: DestReg = X86::EAX; break; 14918 case X86::DX: DestReg = X86::EDX; break; 14919 case X86::CX: DestReg = X86::ECX; break; 14920 case X86::BX: DestReg = X86::EBX; break; 14921 case X86::SI: DestReg = X86::ESI; break; 14922 case X86::DI: DestReg = X86::EDI; break; 14923 case X86::BP: DestReg = X86::EBP; break; 14924 case X86::SP: DestReg = X86::ESP; break; 14925 } 14926 if (DestReg) { 14927 Res.first = DestReg; 14928 Res.second = X86::GR32RegisterClass; 14929 } 14930 } else if (VT == MVT::i64) { 14931 unsigned DestReg = 0; 14932 switch (Res.first) { 14933 default: break; 14934 case X86::AX: DestReg = X86::RAX; break; 14935 case X86::DX: DestReg = X86::RDX; break; 14936 case X86::CX: DestReg = X86::RCX; break; 14937 case X86::BX: DestReg = X86::RBX; break; 14938 case X86::SI: DestReg = X86::RSI; break; 14939 case X86::DI: DestReg = X86::RDI; break; 14940 case X86::BP: DestReg = X86::RBP; break; 14941 case X86::SP: DestReg = X86::RSP; break; 14942 } 14943 if (DestReg) { 14944 Res.first = DestReg; 14945 Res.second = X86::GR64RegisterClass; 14946 } 14947 } 14948 } else if (Res.second == X86::FR32RegisterClass || 14949 Res.second == X86::FR64RegisterClass || 14950 Res.second == X86::VR128RegisterClass) { 14951 // Handle references to XMM physical registers that got mapped into the 14952 // wrong class. This can happen with constraints like {xmm0} where the 14953 // target independent register mapper will just pick the first match it can 14954 // find, ignoring the required type. 14955 if (VT == MVT::f32) 14956 Res.second = X86::FR32RegisterClass; 14957 else if (VT == MVT::f64) 14958 Res.second = X86::FR64RegisterClass; 14959 else if (X86::VR128RegisterClass->hasType(VT)) 14960 Res.second = X86::VR128RegisterClass; 14961 } 14962 14963 return Res; 14964 } 14965