1 //===-- LegalizeDAG.cpp - Implement SelectionDAG::Legalize ----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the SelectionDAG::Legalize method. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "llvm/CallingConv.h" 15 #include "llvm/Constants.h" 16 #include "llvm/DebugInfo.h" 17 #include "llvm/DerivedTypes.h" 18 #include "llvm/LLVMContext.h" 19 #include "llvm/CodeGen/Analysis.h" 20 #include "llvm/CodeGen/MachineFunction.h" 21 #include "llvm/CodeGen/MachineJumpTableInfo.h" 22 #include "llvm/CodeGen/SelectionDAG.h" 23 #include "llvm/Target/TargetFrameLowering.h" 24 #include "llvm/Target/TargetLowering.h" 25 #include "llvm/Target/TargetData.h" 26 #include "llvm/Target/TargetMachine.h" 27 #include "llvm/Support/Debug.h" 28 #include "llvm/Support/ErrorHandling.h" 29 #include "llvm/Support/MathExtras.h" 30 #include "llvm/Support/raw_ostream.h" 31 #include "llvm/ADT/DenseMap.h" 32 #include "llvm/ADT/SmallVector.h" 33 #include "llvm/ADT/SmallPtrSet.h" 34 using namespace llvm; 35 36 //===----------------------------------------------------------------------===// 37 /// SelectionDAGLegalize - This takes an arbitrary SelectionDAG as input and 38 /// hacks on it until the target machine can handle it. This involves 39 /// eliminating value sizes the machine cannot handle (promoting small sizes to 40 /// large sizes or splitting up large values into small values) as well as 41 /// eliminating operations the machine cannot handle. 42 /// 43 /// This code also does a small amount of optimization and recognition of idioms 44 /// as part of its processing. For example, if a target does not support a 45 /// 'setcc' instruction efficiently, but does support 'brcc' instruction, this 46 /// will attempt merge setcc and brc instructions into brcc's. 47 /// 48 namespace { 49 class SelectionDAGLegalize : public SelectionDAG::DAGUpdateListener { 50 const TargetMachine &TM; 51 const TargetLowering &TLI; 52 SelectionDAG &DAG; 53 54 /// LegalizePosition - The iterator for walking through the node list. 55 SelectionDAG::allnodes_iterator LegalizePosition; 56 57 /// LegalizedNodes - The set of nodes which have already been legalized. 58 SmallPtrSet<SDNode *, 16> LegalizedNodes; 59 60 // Libcall insertion helpers. 61 62 public: 63 explicit SelectionDAGLegalize(SelectionDAG &DAG); 64 65 void LegalizeDAG(); 66 67 private: 68 /// LegalizeOp - Legalizes the given operation. 69 void LegalizeOp(SDNode *Node); 70 71 SDValue OptimizeFloatStore(StoreSDNode *ST); 72 73 void LegalizeLoadOps(SDNode *Node); 74 void LegalizeStoreOps(SDNode *Node); 75 76 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 77 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 78 /// is necessary to spill the vector being inserted into to memory, perform 79 /// the insert there, and then read the result back. 80 SDValue PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, 81 SDValue Idx, DebugLoc dl); 82 SDValue ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, 83 SDValue Idx, DebugLoc dl); 84 85 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 86 /// performs the same shuffe in terms of order or result bytes, but on a type 87 /// whose vector element type is narrower than the original shuffle type. 88 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 89 SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 90 SDValue N1, SDValue N2, 91 ArrayRef<int> Mask) const; 92 93 void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC, 94 DebugLoc dl); 95 96 SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned); 97 SDValue ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, const SDValue *Ops, 98 unsigned NumOps, bool isSigned, DebugLoc dl); 99 100 std::pair<SDValue, SDValue> ExpandChainLibCall(RTLIB::Libcall LC, 101 SDNode *Node, bool isSigned); 102 SDValue ExpandFPLibCall(SDNode *Node, RTLIB::Libcall Call_F32, 103 RTLIB::Libcall Call_F64, RTLIB::Libcall Call_F80, 104 RTLIB::Libcall Call_PPCF128); 105 SDValue ExpandIntLibCall(SDNode *Node, bool isSigned, 106 RTLIB::Libcall Call_I8, 107 RTLIB::Libcall Call_I16, 108 RTLIB::Libcall Call_I32, 109 RTLIB::Libcall Call_I64, 110 RTLIB::Libcall Call_I128); 111 void ExpandDivRemLibCall(SDNode *Node, SmallVectorImpl<SDValue> &Results); 112 113 SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl); 114 SDValue ExpandBUILD_VECTOR(SDNode *Node); 115 SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node); 116 void ExpandDYNAMIC_STACKALLOC(SDNode *Node, 117 SmallVectorImpl<SDValue> &Results); 118 SDValue ExpandFCOPYSIGN(SDNode *Node); 119 SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT, 120 DebugLoc dl); 121 SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned, 122 DebugLoc dl); 123 SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned, 124 DebugLoc dl); 125 126 SDValue ExpandBSWAP(SDValue Op, DebugLoc dl); 127 SDValue ExpandBitCount(unsigned Opc, SDValue Op, DebugLoc dl); 128 129 SDValue ExpandExtractFromVectorThroughStack(SDValue Op); 130 SDValue ExpandInsertToVectorThroughStack(SDValue Op); 131 SDValue ExpandVectorBuildThroughStack(SDNode* Node); 132 133 SDValue ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP); 134 135 std::pair<SDValue, SDValue> ExpandAtomic(SDNode *Node); 136 137 void ExpandNode(SDNode *Node); 138 void PromoteNode(SDNode *Node); 139 140 void ForgetNode(SDNode *N) { 141 LegalizedNodes.erase(N); 142 if (LegalizePosition == SelectionDAG::allnodes_iterator(N)) 143 ++LegalizePosition; 144 } 145 146 public: 147 // DAGUpdateListener implementation. 148 virtual void NodeDeleted(SDNode *N, SDNode *E) { 149 ForgetNode(N); 150 } 151 virtual void NodeUpdated(SDNode *N) {} 152 153 // Node replacement helpers 154 void ReplacedNode(SDNode *N) { 155 if (N->use_empty()) { 156 DAG.RemoveDeadNode(N); 157 } else { 158 ForgetNode(N); 159 } 160 } 161 void ReplaceNode(SDNode *Old, SDNode *New) { 162 DAG.ReplaceAllUsesWith(Old, New); 163 ReplacedNode(Old); 164 } 165 void ReplaceNode(SDValue Old, SDValue New) { 166 DAG.ReplaceAllUsesWith(Old, New); 167 ReplacedNode(Old.getNode()); 168 } 169 void ReplaceNode(SDNode *Old, const SDValue *New) { 170 DAG.ReplaceAllUsesWith(Old, New); 171 ReplacedNode(Old); 172 } 173 }; 174 } 175 176 /// ShuffleWithNarrowerEltType - Return a vector shuffle operation which 177 /// performs the same shuffe in terms of order or result bytes, but on a type 178 /// whose vector element type is narrower than the original shuffle type. 179 /// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3> 180 SDValue 181 SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl, 182 SDValue N1, SDValue N2, 183 ArrayRef<int> Mask) const { 184 unsigned NumMaskElts = VT.getVectorNumElements(); 185 unsigned NumDestElts = NVT.getVectorNumElements(); 186 unsigned NumEltsGrowth = NumDestElts / NumMaskElts; 187 188 assert(NumEltsGrowth && "Cannot promote to vector type with fewer elts!"); 189 190 if (NumEltsGrowth == 1) 191 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); 192 193 SmallVector<int, 8> NewMask; 194 for (unsigned i = 0; i != NumMaskElts; ++i) { 195 int Idx = Mask[i]; 196 for (unsigned j = 0; j != NumEltsGrowth; ++j) { 197 if (Idx < 0) 198 NewMask.push_back(-1); 199 else 200 NewMask.push_back(Idx * NumEltsGrowth + j); 201 } 202 } 203 assert(NewMask.size() == NumDestElts && "Non-integer NumEltsGrowth?"); 204 assert(TLI.isShuffleMaskLegal(NewMask, NVT) && "Shuffle not legal?"); 205 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); 206 } 207 208 SelectionDAGLegalize::SelectionDAGLegalize(SelectionDAG &dag) 209 : SelectionDAG::DAGUpdateListener(dag), 210 TM(dag.getTarget()), TLI(dag.getTargetLoweringInfo()), 211 DAG(dag) { 212 } 213 214 void SelectionDAGLegalize::LegalizeDAG() { 215 DAG.AssignTopologicalOrder(); 216 217 // Visit all the nodes. We start in topological order, so that we see 218 // nodes with their original operands intact. Legalization can produce 219 // new nodes which may themselves need to be legalized. Iterate until all 220 // nodes have been legalized. 221 for (;;) { 222 bool AnyLegalized = false; 223 for (LegalizePosition = DAG.allnodes_end(); 224 LegalizePosition != DAG.allnodes_begin(); ) { 225 --LegalizePosition; 226 227 SDNode *N = LegalizePosition; 228 if (LegalizedNodes.insert(N)) { 229 AnyLegalized = true; 230 LegalizeOp(N); 231 } 232 } 233 if (!AnyLegalized) 234 break; 235 236 } 237 238 // Remove dead nodes now. 239 DAG.RemoveDeadNodes(); 240 } 241 242 /// ExpandConstantFP - Expands the ConstantFP node to an integer constant or 243 /// a load from the constant pool. 244 SDValue 245 SelectionDAGLegalize::ExpandConstantFP(ConstantFPSDNode *CFP, bool UseCP) { 246 bool Extend = false; 247 DebugLoc dl = CFP->getDebugLoc(); 248 249 // If a FP immediate is precise when represented as a float and if the 250 // target can do an extending load from float to double, we put it into 251 // the constant pool as a float, even if it's is statically typed as a 252 // double. This shrinks FP constants and canonicalizes them for targets where 253 // an FP extending load is the same cost as a normal load (such as on the x87 254 // fp stack or PPC FP unit). 255 EVT VT = CFP->getValueType(0); 256 ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue()); 257 if (!UseCP) { 258 assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion"); 259 return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(), 260 (VT == MVT::f64) ? MVT::i64 : MVT::i32); 261 } 262 263 EVT OrigVT = VT; 264 EVT SVT = VT; 265 while (SVT != MVT::f32) { 266 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); 267 if (ConstantFPSDNode::isValueValidForType(SVT, CFP->getValueAPF()) && 268 // Only do this if the target has a native EXTLOAD instruction from 269 // smaller type. 270 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && 271 TLI.ShouldShrinkFPConstant(OrigVT)) { 272 Type *SType = SVT.getTypeForEVT(*DAG.getContext()); 273 LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType)); 274 VT = SVT; 275 Extend = true; 276 } 277 } 278 279 SDValue CPIdx = DAG.getConstantPool(LLVMC, TLI.getPointerTy()); 280 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 281 if (Extend) { 282 SDValue Result = 283 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, 284 DAG.getEntryNode(), 285 CPIdx, MachinePointerInfo::getConstantPool(), 286 VT, false, false, Alignment); 287 return Result; 288 } 289 SDValue Result = 290 DAG.getLoad(OrigVT, dl, DAG.getEntryNode(), CPIdx, 291 MachinePointerInfo::getConstantPool(), false, false, false, 292 Alignment); 293 return Result; 294 } 295 296 /// ExpandUnalignedStore - Expands an unaligned store to 2 half-size stores. 297 static void ExpandUnalignedStore(StoreSDNode *ST, SelectionDAG &DAG, 298 const TargetLowering &TLI, 299 SelectionDAGLegalize *DAGLegalize) { 300 assert(ST->getAddressingMode() == ISD::UNINDEXED && 301 "unaligned indexed stores not implemented!"); 302 SDValue Chain = ST->getChain(); 303 SDValue Ptr = ST->getBasePtr(); 304 SDValue Val = ST->getValue(); 305 EVT VT = Val.getValueType(); 306 int Alignment = ST->getAlignment(); 307 DebugLoc dl = ST->getDebugLoc(); 308 if (ST->getMemoryVT().isFloatingPoint() || 309 ST->getMemoryVT().isVector()) { 310 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); 311 if (TLI.isTypeLegal(intVT)) { 312 // Expand to a bitconvert of the value to the integer type of the 313 // same size, then a (misaligned) int store. 314 // FIXME: Does not handle truncating floating point stores! 315 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); 316 Result = DAG.getStore(Chain, dl, Result, Ptr, ST->getPointerInfo(), 317 ST->isVolatile(), ST->isNonTemporal(), Alignment); 318 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 319 return; 320 } 321 // Do a (aligned) store to a stack slot, then copy from the stack slot 322 // to the final destination using (unaligned) integer loads and stores. 323 EVT StoredVT = ST->getMemoryVT(); 324 EVT RegVT = 325 TLI.getRegisterType(*DAG.getContext(), 326 EVT::getIntegerVT(*DAG.getContext(), 327 StoredVT.getSizeInBits())); 328 unsigned StoredBytes = StoredVT.getSizeInBits() / 8; 329 unsigned RegBytes = RegVT.getSizeInBits() / 8; 330 unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes; 331 332 // Make sure the stack slot is also aligned for the register type. 333 SDValue StackPtr = DAG.CreateStackTemporary(StoredVT, RegVT); 334 335 // Perform the original store, only redirected to the stack slot. 336 SDValue Store = DAG.getTruncStore(Chain, dl, 337 Val, StackPtr, MachinePointerInfo(), 338 StoredVT, false, false, 0); 339 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 340 SmallVector<SDValue, 8> Stores; 341 unsigned Offset = 0; 342 343 // Do all but one copies using the full register width. 344 for (unsigned i = 1; i < NumRegs; i++) { 345 // Load one integer register's worth from the stack slot. 346 SDValue Load = DAG.getLoad(RegVT, dl, Store, StackPtr, 347 MachinePointerInfo(), 348 false, false, false, 0); 349 // Store it to the final location. Remember the store. 350 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, Ptr, 351 ST->getPointerInfo().getWithOffset(Offset), 352 ST->isVolatile(), ST->isNonTemporal(), 353 MinAlign(ST->getAlignment(), Offset))); 354 // Increment the pointers. 355 Offset += RegBytes; 356 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 357 Increment); 358 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 359 } 360 361 // The last store may be partial. Do a truncating store. On big-endian 362 // machines this requires an extending load from the stack slot to ensure 363 // that the bits are in the right place. 364 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 365 8 * (StoredBytes - Offset)); 366 367 // Load from the stack slot. 368 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, 369 MachinePointerInfo(), 370 MemVT, false, false, 0); 371 372 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, Ptr, 373 ST->getPointerInfo() 374 .getWithOffset(Offset), 375 MemVT, ST->isVolatile(), 376 ST->isNonTemporal(), 377 MinAlign(ST->getAlignment(), Offset))); 378 // The order of the stores doesn't matter - say it with a TokenFactor. 379 SDValue Result = 380 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 381 Stores.size()); 382 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 383 return; 384 } 385 assert(ST->getMemoryVT().isInteger() && 386 !ST->getMemoryVT().isVector() && 387 "Unaligned store of unknown type."); 388 // Get the half-size VT 389 EVT NewStoredVT = ST->getMemoryVT().getHalfSizedIntegerVT(*DAG.getContext()); 390 int NumBits = NewStoredVT.getSizeInBits(); 391 int IncrementSize = NumBits / 8; 392 393 // Divide the stored value in two parts. 394 SDValue ShiftAmount = DAG.getConstant(NumBits, 395 TLI.getShiftAmountTy(Val.getValueType())); 396 SDValue Lo = Val; 397 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); 398 399 // Store the two parts 400 SDValue Store1, Store2; 401 Store1 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Lo:Hi, Ptr, 402 ST->getPointerInfo(), NewStoredVT, 403 ST->isVolatile(), ST->isNonTemporal(), Alignment); 404 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 405 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 406 Alignment = MinAlign(Alignment, IncrementSize); 407 Store2 = DAG.getTruncStore(Chain, dl, TLI.isLittleEndian()?Hi:Lo, Ptr, 408 ST->getPointerInfo().getWithOffset(IncrementSize), 409 NewStoredVT, ST->isVolatile(), ST->isNonTemporal(), 410 Alignment); 411 412 SDValue Result = 413 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2); 414 DAGLegalize->ReplaceNode(SDValue(ST, 0), Result); 415 } 416 417 /// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads. 418 static void 419 ExpandUnalignedLoad(LoadSDNode *LD, SelectionDAG &DAG, 420 const TargetLowering &TLI, 421 SDValue &ValResult, SDValue &ChainResult) { 422 assert(LD->getAddressingMode() == ISD::UNINDEXED && 423 "unaligned indexed loads not implemented!"); 424 SDValue Chain = LD->getChain(); 425 SDValue Ptr = LD->getBasePtr(); 426 EVT VT = LD->getValueType(0); 427 EVT LoadedVT = LD->getMemoryVT(); 428 DebugLoc dl = LD->getDebugLoc(); 429 if (VT.isFloatingPoint() || VT.isVector()) { 430 EVT intVT = EVT::getIntegerVT(*DAG.getContext(), LoadedVT.getSizeInBits()); 431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) { 432 // Expand to a (misaligned) integer load of the same size, 433 // then bitconvert to floating point or vector. 434 SDValue newLoad = DAG.getLoad(intVT, dl, Chain, Ptr, LD->getPointerInfo(), 435 LD->isVolatile(), 436 LD->isNonTemporal(), 437 LD->isInvariant(), LD->getAlignment()); 438 SDValue Result = DAG.getNode(ISD::BITCAST, dl, LoadedVT, newLoad); 439 if (LoadedVT != VT) 440 Result = DAG.getNode(VT.isFloatingPoint() ? ISD::FP_EXTEND : 441 ISD::ANY_EXTEND, dl, VT, Result); 442 443 ValResult = Result; 444 ChainResult = Chain; 445 return; 446 } 447 448 // Copy the value to a (aligned) stack slot using (unaligned) integer 449 // loads and stores, then do a (aligned) load from the stack slot. 450 EVT RegVT = TLI.getRegisterType(*DAG.getContext(), intVT); 451 unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8; 452 unsigned RegBytes = RegVT.getSizeInBits() / 8; 453 unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes; 454 455 // Make sure the stack slot is also aligned for the register type. 456 SDValue StackBase = DAG.CreateStackTemporary(LoadedVT, RegVT); 457 458 SDValue Increment = DAG.getConstant(RegBytes, TLI.getPointerTy()); 459 SmallVector<SDValue, 8> Stores; 460 SDValue StackPtr = StackBase; 461 unsigned Offset = 0; 462 463 // Do all but one copies using the full register width. 464 for (unsigned i = 1; i < NumRegs; i++) { 465 // Load one integer register's worth from the original location. 466 SDValue Load = DAG.getLoad(RegVT, dl, Chain, Ptr, 467 LD->getPointerInfo().getWithOffset(Offset), 468 LD->isVolatile(), LD->isNonTemporal(), 469 LD->isInvariant(), 470 MinAlign(LD->getAlignment(), Offset)); 471 // Follow the load with a store to the stack slot. Remember the store. 472 Stores.push_back(DAG.getStore(Load.getValue(1), dl, Load, StackPtr, 473 MachinePointerInfo(), false, false, 0)); 474 // Increment the pointers. 475 Offset += RegBytes; 476 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); 477 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, 478 Increment); 479 } 480 481 // The last copy may be partial. Do an extending load. 482 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), 483 8 * (LoadedBytes - Offset)); 484 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr, 485 LD->getPointerInfo().getWithOffset(Offset), 486 MemVT, LD->isVolatile(), 487 LD->isNonTemporal(), 488 MinAlign(LD->getAlignment(), Offset)); 489 // Follow the load with a store to the stack slot. Remember the store. 490 // On big-endian machines this requires a truncating store to ensure 491 // that the bits end up in the right place. 492 Stores.push_back(DAG.getTruncStore(Load.getValue(1), dl, Load, StackPtr, 493 MachinePointerInfo(), MemVT, 494 false, false, 0)); 495 496 // The order of the stores doesn't matter - say it with a TokenFactor. 497 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], 498 Stores.size()); 499 500 // Finally, perform the original load only redirected to the stack slot. 501 Load = DAG.getExtLoad(LD->getExtensionType(), dl, VT, TF, StackBase, 502 MachinePointerInfo(), LoadedVT, false, false, 0); 503 504 // Callers expect a MERGE_VALUES node. 505 ValResult = Load; 506 ChainResult = TF; 507 return; 508 } 509 assert(LoadedVT.isInteger() && !LoadedVT.isVector() && 510 "Unaligned load of unsupported type."); 511 512 // Compute the new VT that is half the size of the old one. This is an 513 // integer MVT. 514 unsigned NumBits = LoadedVT.getSizeInBits(); 515 EVT NewLoadedVT; 516 NewLoadedVT = EVT::getIntegerVT(*DAG.getContext(), NumBits/2); 517 NumBits >>= 1; 518 519 unsigned Alignment = LD->getAlignment(); 520 unsigned IncrementSize = NumBits / 8; 521 ISD::LoadExtType HiExtType = LD->getExtensionType(); 522 523 // If the original load is NON_EXTLOAD, the hi part load must be ZEXTLOAD. 524 if (HiExtType == ISD::NON_EXTLOAD) 525 HiExtType = ISD::ZEXTLOAD; 526 527 // Load the value in two parts 528 SDValue Lo, Hi; 529 if (TLI.isLittleEndian()) { 530 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), 531 NewLoadedVT, LD->isVolatile(), 532 LD->isNonTemporal(), Alignment); 533 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 534 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 535 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, 536 LD->getPointerInfo().getWithOffset(IncrementSize), 537 NewLoadedVT, LD->isVolatile(), 538 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 539 } else { 540 Hi = DAG.getExtLoad(HiExtType, dl, VT, Chain, Ptr, LD->getPointerInfo(), 541 NewLoadedVT, LD->isVolatile(), 542 LD->isNonTemporal(), Alignment); 543 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 544 DAG.getConstant(IncrementSize, TLI.getPointerTy())); 545 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, 546 LD->getPointerInfo().getWithOffset(IncrementSize), 547 NewLoadedVT, LD->isVolatile(), 548 LD->isNonTemporal(), MinAlign(Alignment,IncrementSize)); 549 } 550 551 // aggregate the two parts 552 SDValue ShiftAmount = DAG.getConstant(NumBits, 553 TLI.getShiftAmountTy(Hi.getValueType())); 554 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount); 555 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); 556 557 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 558 Hi.getValue(1)); 559 560 ValResult = Result; 561 ChainResult = TF; 562 } 563 564 /// PerformInsertVectorEltInMemory - Some target cannot handle a variable 565 /// insertion index for the INSERT_VECTOR_ELT instruction. In this case, it 566 /// is necessary to spill the vector being inserted into to memory, perform 567 /// the insert there, and then read the result back. 568 SDValue SelectionDAGLegalize:: 569 PerformInsertVectorEltInMemory(SDValue Vec, SDValue Val, SDValue Idx, 570 DebugLoc dl) { 571 SDValue Tmp1 = Vec; 572 SDValue Tmp2 = Val; 573 SDValue Tmp3 = Idx; 574 575 // If the target doesn't support this, we have to spill the input vector 576 // to a temporary stack slot, update the element, then reload it. This is 577 // badness. We could also load the value into a vector register (either 578 // with a "move to register" or "extload into register" instruction, then 579 // permute it into place, if the idx is a constant and if the idx is 580 // supported by the target. 581 EVT VT = Tmp1.getValueType(); 582 EVT EltVT = VT.getVectorElementType(); 583 EVT IdxVT = Tmp3.getValueType(); 584 EVT PtrVT = TLI.getPointerTy(); 585 SDValue StackPtr = DAG.CreateStackTemporary(VT); 586 587 int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 588 589 // Store the vector. 590 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr, 591 MachinePointerInfo::getFixedStack(SPFI), 592 false, false, 0); 593 594 // Truncate or zero extend offset to target pointer type. 595 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; 596 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); 597 // Add the offset to the index. 598 unsigned EltSize = EltVT.getSizeInBits()/8; 599 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); 600 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); 601 // Store the scalar value. 602 Ch = DAG.getTruncStore(Ch, dl, Tmp2, StackPtr2, MachinePointerInfo(), EltVT, 603 false, false, 0); 604 // Load the updated vector. 605 return DAG.getLoad(VT, dl, Ch, StackPtr, 606 MachinePointerInfo::getFixedStack(SPFI), false, false, 607 false, 0); 608 } 609 610 611 SDValue SelectionDAGLegalize:: 612 ExpandINSERT_VECTOR_ELT(SDValue Vec, SDValue Val, SDValue Idx, DebugLoc dl) { 613 if (ConstantSDNode *InsertPos = dyn_cast<ConstantSDNode>(Idx)) { 614 // SCALAR_TO_VECTOR requires that the type of the value being inserted 615 // match the element type of the vector being created, except for 616 // integers in which case the inserted value can be over width. 617 EVT EltVT = Vec.getValueType().getVectorElementType(); 618 if (Val.getValueType() == EltVT || 619 (EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) { 620 SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, 621 Vec.getValueType(), Val); 622 623 unsigned NumElts = Vec.getValueType().getVectorNumElements(); 624 // We generate a shuffle of InVec and ScVec, so the shuffle mask 625 // should be 0,1,2,3,4,5... with the appropriate element replaced with 626 // elt 0 of the RHS. 627 SmallVector<int, 8> ShufOps; 628 for (unsigned i = 0; i != NumElts; ++i) 629 ShufOps.push_back(i != InsertPos->getZExtValue() ? i : NumElts); 630 631 return DAG.getVectorShuffle(Vec.getValueType(), dl, Vec, ScVec, 632 &ShufOps[0]); 633 } 634 } 635 return PerformInsertVectorEltInMemory(Vec, Val, Idx, dl); 636 } 637 638 SDValue SelectionDAGLegalize::OptimizeFloatStore(StoreSDNode* ST) { 639 // Turn 'store float 1.0, Ptr' -> 'store int 0x12345678, Ptr' 640 // FIXME: We shouldn't do this for TargetConstantFP's. 641 // FIXME: move this to the DAG Combiner! Note that we can't regress due 642 // to phase ordering between legalized code and the dag combiner. This 643 // probably means that we need to integrate dag combiner and legalizer 644 // together. 645 // We generally can't do this one for long doubles. 646 SDValue Chain = ST->getChain(); 647 SDValue Ptr = ST->getBasePtr(); 648 unsigned Alignment = ST->getAlignment(); 649 bool isVolatile = ST->isVolatile(); 650 bool isNonTemporal = ST->isNonTemporal(); 651 DebugLoc dl = ST->getDebugLoc(); 652 if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) { 653 if (CFP->getValueType(0) == MVT::f32 && 654 TLI.isTypeLegal(MVT::i32)) { 655 SDValue Con = DAG.getConstant(CFP->getValueAPF(). 656 bitcastToAPInt().zextOrTrunc(32), 657 MVT::i32); 658 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), 659 isVolatile, isNonTemporal, Alignment); 660 } 661 662 if (CFP->getValueType(0) == MVT::f64) { 663 // If this target supports 64-bit registers, do a single 64-bit store. 664 if (TLI.isTypeLegal(MVT::i64)) { 665 SDValue Con = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt(). 666 zextOrTrunc(64), MVT::i64); 667 return DAG.getStore(Chain, dl, Con, Ptr, ST->getPointerInfo(), 668 isVolatile, isNonTemporal, Alignment); 669 } 670 671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { 672 // Otherwise, if the target supports 32-bit registers, use 2 32-bit 673 // stores. If the target supports neither 32- nor 64-bits, this 674 // xform is certainly not worth it. 675 const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt(); 676 SDValue Lo = DAG.getConstant(IntVal.trunc(32), MVT::i32); 677 SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32); 678 if (TLI.isBigEndian()) std::swap(Lo, Hi); 679 680 Lo = DAG.getStore(Chain, dl, Lo, Ptr, ST->getPointerInfo(), isVolatile, 681 isNonTemporal, Alignment); 682 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 683 DAG.getIntPtrConstant(4)); 684 Hi = DAG.getStore(Chain, dl, Hi, Ptr, 685 ST->getPointerInfo().getWithOffset(4), 686 isVolatile, isNonTemporal, MinAlign(Alignment, 4U)); 687 688 return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 689 } 690 } 691 } 692 return SDValue(0, 0); 693 } 694 695 void SelectionDAGLegalize::LegalizeStoreOps(SDNode *Node) { 696 StoreSDNode *ST = cast<StoreSDNode>(Node); 697 SDValue Chain = ST->getChain(); 698 SDValue Ptr = ST->getBasePtr(); 699 DebugLoc dl = Node->getDebugLoc(); 700 701 unsigned Alignment = ST->getAlignment(); 702 bool isVolatile = ST->isVolatile(); 703 bool isNonTemporal = ST->isNonTemporal(); 704 705 if (!ST->isTruncatingStore()) { 706 if (SDNode *OptStore = OptimizeFloatStore(ST).getNode()) { 707 ReplaceNode(ST, OptStore); 708 return; 709 } 710 711 { 712 SDValue Value = ST->getValue(); 713 EVT VT = Value.getValueType(); 714 switch (TLI.getOperationAction(ISD::STORE, VT)) { 715 default: llvm_unreachable("This action is not supported yet!"); 716 case TargetLowering::Legal: 717 // If this is an unaligned store and the target doesn't support it, 718 // expand it. 719 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 720 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 721 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 722 if (ST->getAlignment() < ABIAlignment) 723 ExpandUnalignedStore(cast<StoreSDNode>(Node), 724 DAG, TLI, this); 725 } 726 break; 727 case TargetLowering::Custom: { 728 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 729 if (Res.getNode()) 730 ReplaceNode(SDValue(Node, 0), Res); 731 return; 732 } 733 case TargetLowering::Promote: { 734 assert(VT.isVector() && "Unknown legal promote case!"); 735 Value = DAG.getNode(ISD::BITCAST, dl, 736 TLI.getTypeToPromoteTo(ISD::STORE, VT), Value); 737 SDValue Result = 738 DAG.getStore(Chain, dl, Value, Ptr, 739 ST->getPointerInfo(), isVolatile, 740 isNonTemporal, Alignment); 741 ReplaceNode(SDValue(Node, 0), Result); 742 break; 743 } 744 } 745 return; 746 } 747 } else { 748 SDValue Value = ST->getValue(); 749 750 EVT StVT = ST->getMemoryVT(); 751 unsigned StWidth = StVT.getSizeInBits(); 752 753 if (StWidth != StVT.getStoreSizeInBits()) { 754 // Promote to a byte-sized store with upper bits zero if not 755 // storing an integral number of bytes. For example, promote 756 // TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1) 757 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), 758 StVT.getStoreSizeInBits()); 759 Value = DAG.getZeroExtendInReg(Value, dl, StVT); 760 SDValue Result = 761 DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 762 NVT, isVolatile, isNonTemporal, Alignment); 763 ReplaceNode(SDValue(Node, 0), Result); 764 } else if (StWidth & (StWidth - 1)) { 765 // If not storing a power-of-2 number of bits, expand as two stores. 766 assert(!StVT.isVector() && "Unsupported truncstore!"); 767 unsigned RoundWidth = 1 << Log2_32(StWidth); 768 assert(RoundWidth < StWidth); 769 unsigned ExtraWidth = StWidth - RoundWidth; 770 assert(ExtraWidth < RoundWidth); 771 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 772 "Store size not an integral number of bytes!"); 773 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 774 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 775 SDValue Lo, Hi; 776 unsigned IncrementSize; 777 778 if (TLI.isLittleEndian()) { 779 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 X, TRUNCSTORE@+2:i8 (srl X, 16) 780 // Store the bottom RoundWidth bits. 781 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 782 RoundVT, 783 isVolatile, isNonTemporal, Alignment); 784 785 // Store the remaining ExtraWidth bits. 786 IncrementSize = RoundWidth / 8; 787 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 788 DAG.getIntPtrConstant(IncrementSize)); 789 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 790 DAG.getConstant(RoundWidth, 791 TLI.getShiftAmountTy(Value.getValueType()))); 792 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, 793 ST->getPointerInfo().getWithOffset(IncrementSize), 794 ExtraVT, isVolatile, isNonTemporal, 795 MinAlign(Alignment, IncrementSize)); 796 } else { 797 // Big endian - avoid unaligned stores. 798 // TRUNCSTORE:i24 X -> TRUNCSTORE:i16 (srl X, 8), TRUNCSTORE@+2:i8 X 799 // Store the top RoundWidth bits. 800 Hi = DAG.getNode(ISD::SRL, dl, Value.getValueType(), Value, 801 DAG.getConstant(ExtraWidth, 802 TLI.getShiftAmountTy(Value.getValueType()))); 803 Hi = DAG.getTruncStore(Chain, dl, Hi, Ptr, ST->getPointerInfo(), 804 RoundVT, isVolatile, isNonTemporal, Alignment); 805 806 // Store the remaining ExtraWidth bits. 807 IncrementSize = RoundWidth / 8; 808 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 809 DAG.getIntPtrConstant(IncrementSize)); 810 Lo = DAG.getTruncStore(Chain, dl, Value, Ptr, 811 ST->getPointerInfo().getWithOffset(IncrementSize), 812 ExtraVT, isVolatile, isNonTemporal, 813 MinAlign(Alignment, IncrementSize)); 814 } 815 816 // The order of the stores doesn't matter. 817 SDValue Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi); 818 ReplaceNode(SDValue(Node, 0), Result); 819 } else { 820 switch (TLI.getTruncStoreAction(ST->getValue().getValueType(), StVT)) { 821 default: llvm_unreachable("This action is not supported yet!"); 822 case TargetLowering::Legal: 823 // If this is an unaligned store and the target doesn't support it, 824 // expand it. 825 if (!TLI.allowsUnalignedMemoryAccesses(ST->getMemoryVT())) { 826 Type *Ty = ST->getMemoryVT().getTypeForEVT(*DAG.getContext()); 827 unsigned ABIAlignment= TLI.getTargetData()->getABITypeAlignment(Ty); 828 if (ST->getAlignment() < ABIAlignment) 829 ExpandUnalignedStore(cast<StoreSDNode>(Node), DAG, TLI, this); 830 } 831 break; 832 case TargetLowering::Custom: { 833 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 834 if (Res.getNode()) 835 ReplaceNode(SDValue(Node, 0), Res); 836 return; 837 } 838 case TargetLowering::Expand: 839 assert(!StVT.isVector() && 840 "Vector Stores are handled in LegalizeVectorOps"); 841 842 // TRUNCSTORE:i16 i32 -> STORE i16 843 assert(TLI.isTypeLegal(StVT) && 844 "Do not know how to expand this store!"); 845 Value = DAG.getNode(ISD::TRUNCATE, dl, StVT, Value); 846 SDValue Result = 847 DAG.getStore(Chain, dl, Value, Ptr, ST->getPointerInfo(), 848 isVolatile, isNonTemporal, Alignment); 849 ReplaceNode(SDValue(Node, 0), Result); 850 break; 851 } 852 } 853 } 854 } 855 856 void SelectionDAGLegalize::LegalizeLoadOps(SDNode *Node) { 857 LoadSDNode *LD = cast<LoadSDNode>(Node); 858 SDValue Chain = LD->getChain(); // The chain. 859 SDValue Ptr = LD->getBasePtr(); // The base pointer. 860 SDValue Value; // The value returned by the load op. 861 DebugLoc dl = Node->getDebugLoc(); 862 863 ISD::LoadExtType ExtType = LD->getExtensionType(); 864 if (ExtType == ISD::NON_EXTLOAD) { 865 EVT VT = Node->getValueType(0); 866 SDValue RVal = SDValue(Node, 0); 867 SDValue RChain = SDValue(Node, 1); 868 869 switch (TLI.getOperationAction(Node->getOpcode(), VT)) { 870 default: llvm_unreachable("This action is not supported yet!"); 871 case TargetLowering::Legal: 872 // If this is an unaligned load and the target doesn't support it, 873 // expand it. 874 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 875 Type *Ty = LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 876 unsigned ABIAlignment = 877 TLI.getTargetData()->getABITypeAlignment(Ty); 878 if (LD->getAlignment() < ABIAlignment){ 879 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 880 DAG, TLI, RVal, RChain); 881 } 882 } 883 break; 884 case TargetLowering::Custom: { 885 SDValue Res = TLI.LowerOperation(RVal, DAG); 886 if (Res.getNode()) { 887 RVal = Res; 888 RChain = Res.getValue(1); 889 } 890 break; 891 } 892 case TargetLowering::Promote: { 893 // Only promote a load of vector type to another. 894 assert(VT.isVector() && "Cannot promote this load!"); 895 // Change base type to a different vector type. 896 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT); 897 898 SDValue Res = DAG.getLoad(NVT, dl, Chain, Ptr, LD->getPointerInfo(), 899 LD->isVolatile(), LD->isNonTemporal(), 900 LD->isInvariant(), LD->getAlignment()); 901 RVal = DAG.getNode(ISD::BITCAST, dl, VT, Res); 902 RChain = Res.getValue(1); 903 break; 904 } 905 } 906 if (RChain.getNode() != Node) { 907 assert(RVal.getNode() != Node && "Load must be completely replaced"); 908 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), RVal); 909 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), RChain); 910 ReplacedNode(Node); 911 } 912 return; 913 } 914 915 EVT SrcVT = LD->getMemoryVT(); 916 unsigned SrcWidth = SrcVT.getSizeInBits(); 917 unsigned Alignment = LD->getAlignment(); 918 bool isVolatile = LD->isVolatile(); 919 bool isNonTemporal = LD->isNonTemporal(); 920 921 if (SrcWidth != SrcVT.getStoreSizeInBits() && 922 // Some targets pretend to have an i1 loading operation, and actually 923 // load an i8. This trick is correct for ZEXTLOAD because the top 7 924 // bits are guaranteed to be zero; it helps the optimizers understand 925 // that these bits are zero. It is also useful for EXTLOAD, since it 926 // tells the optimizers that those bits are undefined. It would be 927 // nice to have an effective generic way of getting these benefits... 928 // Until such a way is found, don't insist on promoting i1 here. 929 (SrcVT != MVT::i1 || 930 TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) { 931 // Promote to a byte-sized load if not loading an integral number of 932 // bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24. 933 unsigned NewWidth = SrcVT.getStoreSizeInBits(); 934 EVT NVT = EVT::getIntegerVT(*DAG.getContext(), NewWidth); 935 SDValue Ch; 936 937 // The extra bits are guaranteed to be zero, since we stored them that 938 // way. A zext load from NVT thus automatically gives zext from SrcVT. 939 940 ISD::LoadExtType NewExtType = 941 ExtType == ISD::ZEXTLOAD ? ISD::ZEXTLOAD : ISD::EXTLOAD; 942 943 SDValue Result = 944 DAG.getExtLoad(NewExtType, dl, Node->getValueType(0), 945 Chain, Ptr, LD->getPointerInfo(), 946 NVT, isVolatile, isNonTemporal, Alignment); 947 948 Ch = Result.getValue(1); // The chain. 949 950 if (ExtType == ISD::SEXTLOAD) 951 // Having the top bits zero doesn't help when sign extending. 952 Result = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 953 Result.getValueType(), 954 Result, DAG.getValueType(SrcVT)); 955 else if (ExtType == ISD::ZEXTLOAD || NVT == Result.getValueType()) 956 // All the top bits are guaranteed to be zero - inform the optimizers. 957 Result = DAG.getNode(ISD::AssertZext, dl, 958 Result.getValueType(), Result, 959 DAG.getValueType(SrcVT)); 960 961 Value = Result; 962 Chain = Ch; 963 } else if (SrcWidth & (SrcWidth - 1)) { 964 // If not loading a power-of-2 number of bits, expand as two loads. 965 assert(!SrcVT.isVector() && "Unsupported extload!"); 966 unsigned RoundWidth = 1 << Log2_32(SrcWidth); 967 assert(RoundWidth < SrcWidth); 968 unsigned ExtraWidth = SrcWidth - RoundWidth; 969 assert(ExtraWidth < RoundWidth); 970 assert(!(RoundWidth % 8) && !(ExtraWidth % 8) && 971 "Load size not an integral number of bytes!"); 972 EVT RoundVT = EVT::getIntegerVT(*DAG.getContext(), RoundWidth); 973 EVT ExtraVT = EVT::getIntegerVT(*DAG.getContext(), ExtraWidth); 974 SDValue Lo, Hi, Ch; 975 unsigned IncrementSize; 976 977 if (TLI.isLittleEndian()) { 978 // EXTLOAD:i24 -> ZEXTLOAD:i16 | (shl EXTLOAD@+2:i8, 16) 979 // Load the bottom RoundWidth bits. 980 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, Node->getValueType(0), 981 Chain, Ptr, 982 LD->getPointerInfo(), RoundVT, isVolatile, 983 isNonTemporal, Alignment); 984 985 // Load the remaining ExtraWidth bits. 986 IncrementSize = RoundWidth / 8; 987 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 988 DAG.getIntPtrConstant(IncrementSize)); 989 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, 990 LD->getPointerInfo().getWithOffset(IncrementSize), 991 ExtraVT, isVolatile, isNonTemporal, 992 MinAlign(Alignment, IncrementSize)); 993 994 // Build a factor node to remember that this load is independent of 995 // the other one. 996 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 997 Hi.getValue(1)); 998 999 // Move the top bits to the right place. 1000 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1001 DAG.getConstant(RoundWidth, 1002 TLI.getShiftAmountTy(Hi.getValueType()))); 1003 1004 // Join the hi and lo parts. 1005 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1006 } else { 1007 // Big endian - avoid unaligned loads. 1008 // EXTLOAD:i24 -> (shl EXTLOAD:i16, 8) | ZEXTLOAD@+2:i8 1009 // Load the top RoundWidth bits. 1010 Hi = DAG.getExtLoad(ExtType, dl, Node->getValueType(0), Chain, Ptr, 1011 LD->getPointerInfo(), RoundVT, isVolatile, 1012 isNonTemporal, Alignment); 1013 1014 // Load the remaining ExtraWidth bits. 1015 IncrementSize = RoundWidth / 8; 1016 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, 1017 DAG.getIntPtrConstant(IncrementSize)); 1018 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, 1019 dl, Node->getValueType(0), Chain, Ptr, 1020 LD->getPointerInfo().getWithOffset(IncrementSize), 1021 ExtraVT, isVolatile, isNonTemporal, 1022 MinAlign(Alignment, IncrementSize)); 1023 1024 // Build a factor node to remember that this load is independent of 1025 // the other one. 1026 Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), 1027 Hi.getValue(1)); 1028 1029 // Move the top bits to the right place. 1030 Hi = DAG.getNode(ISD::SHL, dl, Hi.getValueType(), Hi, 1031 DAG.getConstant(ExtraWidth, 1032 TLI.getShiftAmountTy(Hi.getValueType()))); 1033 1034 // Join the hi and lo parts. 1035 Value = DAG.getNode(ISD::OR, dl, Node->getValueType(0), Lo, Hi); 1036 } 1037 1038 Chain = Ch; 1039 } else { 1040 bool isCustom = false; 1041 switch (TLI.getLoadExtAction(ExtType, SrcVT)) { 1042 default: llvm_unreachable("This action is not supported yet!"); 1043 case TargetLowering::Custom: 1044 isCustom = true; 1045 // FALLTHROUGH 1046 case TargetLowering::Legal: { 1047 Value = SDValue(Node, 0); 1048 Chain = SDValue(Node, 1); 1049 1050 if (isCustom) { 1051 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 1052 if (Res.getNode()) { 1053 Value = Res; 1054 Chain = Res.getValue(1); 1055 } 1056 } else { 1057 // If this is an unaligned load and the target doesn't support it, 1058 // expand it. 1059 if (!TLI.allowsUnalignedMemoryAccesses(LD->getMemoryVT())) { 1060 Type *Ty = 1061 LD->getMemoryVT().getTypeForEVT(*DAG.getContext()); 1062 unsigned ABIAlignment = 1063 TLI.getTargetData()->getABITypeAlignment(Ty); 1064 if (LD->getAlignment() < ABIAlignment){ 1065 ExpandUnalignedLoad(cast<LoadSDNode>(Node), 1066 DAG, TLI, Value, Chain); 1067 } 1068 } 1069 } 1070 break; 1071 } 1072 case TargetLowering::Expand: 1073 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { 1074 SDValue Load = DAG.getLoad(SrcVT, dl, Chain, Ptr, 1075 LD->getPointerInfo(), 1076 LD->isVolatile(), LD->isNonTemporal(), 1077 LD->isInvariant(), LD->getAlignment()); 1078 unsigned ExtendOp; 1079 switch (ExtType) { 1080 case ISD::EXTLOAD: 1081 ExtendOp = (SrcVT.isFloatingPoint() ? 1082 ISD::FP_EXTEND : ISD::ANY_EXTEND); 1083 break; 1084 case ISD::SEXTLOAD: ExtendOp = ISD::SIGN_EXTEND; break; 1085 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; 1086 default: llvm_unreachable("Unexpected extend load type!"); 1087 } 1088 Value = DAG.getNode(ExtendOp, dl, Node->getValueType(0), Load); 1089 Chain = Load.getValue(1); 1090 break; 1091 } 1092 1093 assert(!SrcVT.isVector() && 1094 "Vector Loads are handled in LegalizeVectorOps"); 1095 1096 // FIXME: This does not work for vectors on most targets. Sign- and 1097 // zero-extend operations are currently folded into extending loads, 1098 // whether they are legal or not, and then we end up here without any 1099 // support for legalizing them. 1100 assert(ExtType != ISD::EXTLOAD && 1101 "EXTLOAD should always be supported!"); 1102 // Turn the unsupported load into an EXTLOAD followed by an explicit 1103 // zero/sign extend inreg. 1104 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, dl, Node->getValueType(0), 1105 Chain, Ptr, LD->getPointerInfo(), SrcVT, 1106 LD->isVolatile(), LD->isNonTemporal(), 1107 LD->getAlignment()); 1108 SDValue ValRes; 1109 if (ExtType == ISD::SEXTLOAD) 1110 ValRes = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, 1111 Result.getValueType(), 1112 Result, DAG.getValueType(SrcVT)); 1113 else 1114 ValRes = DAG.getZeroExtendInReg(Result, dl, SrcVT.getScalarType()); 1115 Value = ValRes; 1116 Chain = Result.getValue(1); 1117 break; 1118 } 1119 } 1120 1121 // Since loads produce two values, make sure to remember that we legalized 1122 // both of them. 1123 if (Chain.getNode() != Node) { 1124 assert(Value.getNode() != Node && "Load must be completely replaced"); 1125 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Value); 1126 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 1127 ReplacedNode(Node); 1128 } 1129 } 1130 1131 /// LegalizeOp - Return a legal replacement for the given operation, with 1132 /// all legal operands. 1133 void SelectionDAGLegalize::LegalizeOp(SDNode *Node) { 1134 if (Node->getOpcode() == ISD::TargetConstant) // Allow illegal target nodes. 1135 return; 1136 1137 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1138 assert(TLI.getTypeAction(*DAG.getContext(), Node->getValueType(i)) == 1139 TargetLowering::TypeLegal && 1140 "Unexpected illegal type!"); 1141 1142 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) 1143 assert((TLI.getTypeAction(*DAG.getContext(), 1144 Node->getOperand(i).getValueType()) == 1145 TargetLowering::TypeLegal || 1146 Node->getOperand(i).getOpcode() == ISD::TargetConstant) && 1147 "Unexpected illegal type!"); 1148 1149 // Figure out the correct action; the way to query this varies by opcode 1150 TargetLowering::LegalizeAction Action = TargetLowering::Legal; 1151 bool SimpleFinishLegalizing = true; 1152 switch (Node->getOpcode()) { 1153 case ISD::INTRINSIC_W_CHAIN: 1154 case ISD::INTRINSIC_WO_CHAIN: 1155 case ISD::INTRINSIC_VOID: 1156 case ISD::STACKSAVE: 1157 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 1158 break; 1159 case ISD::VAARG: 1160 Action = TLI.getOperationAction(Node->getOpcode(), 1161 Node->getValueType(0)); 1162 if (Action != TargetLowering::Promote) 1163 Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other); 1164 break; 1165 case ISD::SINT_TO_FP: 1166 case ISD::UINT_TO_FP: 1167 case ISD::EXTRACT_VECTOR_ELT: 1168 Action = TLI.getOperationAction(Node->getOpcode(), 1169 Node->getOperand(0).getValueType()); 1170 break; 1171 case ISD::FP_ROUND_INREG: 1172 case ISD::SIGN_EXTEND_INREG: { 1173 EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT(); 1174 Action = TLI.getOperationAction(Node->getOpcode(), InnerType); 1175 break; 1176 } 1177 case ISD::ATOMIC_STORE: { 1178 Action = TLI.getOperationAction(Node->getOpcode(), 1179 Node->getOperand(2).getValueType()); 1180 break; 1181 } 1182 case ISD::SELECT_CC: 1183 case ISD::SETCC: 1184 case ISD::BR_CC: { 1185 unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 : 1186 Node->getOpcode() == ISD::SETCC ? 2 : 1; 1187 unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0; 1188 EVT OpVT = Node->getOperand(CompareOperand).getValueType(); 1189 ISD::CondCode CCCode = 1190 cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get(); 1191 Action = TLI.getCondCodeAction(CCCode, OpVT); 1192 if (Action == TargetLowering::Legal) { 1193 if (Node->getOpcode() == ISD::SELECT_CC) 1194 Action = TLI.getOperationAction(Node->getOpcode(), 1195 Node->getValueType(0)); 1196 else 1197 Action = TLI.getOperationAction(Node->getOpcode(), OpVT); 1198 } 1199 break; 1200 } 1201 case ISD::LOAD: 1202 case ISD::STORE: 1203 // FIXME: Model these properly. LOAD and STORE are complicated, and 1204 // STORE expects the unlegalized operand in some cases. 1205 SimpleFinishLegalizing = false; 1206 break; 1207 case ISD::CALLSEQ_START: 1208 case ISD::CALLSEQ_END: 1209 // FIXME: This shouldn't be necessary. These nodes have special properties 1210 // dealing with the recursive nature of legalization. Removing this 1211 // special case should be done as part of making LegalizeDAG non-recursive. 1212 SimpleFinishLegalizing = false; 1213 break; 1214 case ISD::EXTRACT_ELEMENT: 1215 case ISD::FLT_ROUNDS_: 1216 case ISD::SADDO: 1217 case ISD::SSUBO: 1218 case ISD::UADDO: 1219 case ISD::USUBO: 1220 case ISD::SMULO: 1221 case ISD::UMULO: 1222 case ISD::FPOWI: 1223 case ISD::MERGE_VALUES: 1224 case ISD::EH_RETURN: 1225 case ISD::FRAME_TO_ARGS_OFFSET: 1226 case ISD::EH_SJLJ_SETJMP: 1227 case ISD::EH_SJLJ_LONGJMP: 1228 // These operations lie about being legal: when they claim to be legal, 1229 // they should actually be expanded. 1230 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1231 if (Action == TargetLowering::Legal) 1232 Action = TargetLowering::Expand; 1233 break; 1234 case ISD::INIT_TRAMPOLINE: 1235 case ISD::ADJUST_TRAMPOLINE: 1236 case ISD::FRAMEADDR: 1237 case ISD::RETURNADDR: 1238 // These operations lie about being legal: when they claim to be legal, 1239 // they should actually be custom-lowered. 1240 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1241 if (Action == TargetLowering::Legal) 1242 Action = TargetLowering::Custom; 1243 break; 1244 default: 1245 if (Node->getOpcode() >= ISD::BUILTIN_OP_END) { 1246 Action = TargetLowering::Legal; 1247 } else { 1248 Action = TLI.getOperationAction(Node->getOpcode(), Node->getValueType(0)); 1249 } 1250 break; 1251 } 1252 1253 if (SimpleFinishLegalizing) { 1254 SDNode *NewNode = Node; 1255 switch (Node->getOpcode()) { 1256 default: break; 1257 case ISD::SHL: 1258 case ISD::SRL: 1259 case ISD::SRA: 1260 case ISD::ROTL: 1261 case ISD::ROTR: 1262 // Legalizing shifts/rotates requires adjusting the shift amount 1263 // to the appropriate width. 1264 if (!Node->getOperand(1).getValueType().isVector()) { 1265 SDValue SAO = 1266 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 1267 Node->getOperand(1)); 1268 HandleSDNode Handle(SAO); 1269 LegalizeOp(SAO.getNode()); 1270 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 1271 Handle.getValue()); 1272 } 1273 break; 1274 case ISD::SRL_PARTS: 1275 case ISD::SRA_PARTS: 1276 case ISD::SHL_PARTS: 1277 // Legalizing shifts/rotates requires adjusting the shift amount 1278 // to the appropriate width. 1279 if (!Node->getOperand(2).getValueType().isVector()) { 1280 SDValue SAO = 1281 DAG.getShiftAmountOperand(Node->getOperand(0).getValueType(), 1282 Node->getOperand(2)); 1283 HandleSDNode Handle(SAO); 1284 LegalizeOp(SAO.getNode()); 1285 NewNode = DAG.UpdateNodeOperands(Node, Node->getOperand(0), 1286 Node->getOperand(1), 1287 Handle.getValue()); 1288 } 1289 break; 1290 } 1291 1292 if (NewNode != Node) { 1293 DAG.ReplaceAllUsesWith(Node, NewNode); 1294 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1295 DAG.TransferDbgValues(SDValue(Node, i), SDValue(NewNode, i)); 1296 ReplacedNode(Node); 1297 Node = NewNode; 1298 } 1299 switch (Action) { 1300 case TargetLowering::Legal: 1301 return; 1302 case TargetLowering::Custom: { 1303 // FIXME: The handling for custom lowering with multiple results is 1304 // a complete mess. 1305 SDValue Res = TLI.LowerOperation(SDValue(Node, 0), DAG); 1306 if (Res.getNode()) { 1307 SmallVector<SDValue, 8> ResultVals; 1308 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) { 1309 if (e == 1) 1310 ResultVals.push_back(Res); 1311 else 1312 ResultVals.push_back(Res.getValue(i)); 1313 } 1314 if (Res.getNode() != Node || Res.getResNo() != 0) { 1315 DAG.ReplaceAllUsesWith(Node, ResultVals.data()); 1316 for (unsigned i = 0, e = Node->getNumValues(); i != e; ++i) 1317 DAG.TransferDbgValues(SDValue(Node, i), ResultVals[i]); 1318 ReplacedNode(Node); 1319 } 1320 return; 1321 } 1322 } 1323 // FALL THROUGH 1324 case TargetLowering::Expand: 1325 ExpandNode(Node); 1326 return; 1327 case TargetLowering::Promote: 1328 PromoteNode(Node); 1329 return; 1330 } 1331 } 1332 1333 switch (Node->getOpcode()) { 1334 default: 1335 #ifndef NDEBUG 1336 dbgs() << "NODE: "; 1337 Node->dump( &DAG); 1338 dbgs() << "\n"; 1339 #endif 1340 llvm_unreachable("Do not know how to legalize this operator!"); 1341 1342 case ISD::CALLSEQ_START: 1343 case ISD::CALLSEQ_END: 1344 break; 1345 case ISD::LOAD: { 1346 return LegalizeLoadOps(Node); 1347 } 1348 case ISD::STORE: { 1349 return LegalizeStoreOps(Node); 1350 } 1351 } 1352 } 1353 1354 SDValue SelectionDAGLegalize::ExpandExtractFromVectorThroughStack(SDValue Op) { 1355 SDValue Vec = Op.getOperand(0); 1356 SDValue Idx = Op.getOperand(1); 1357 DebugLoc dl = Op.getDebugLoc(); 1358 // Store the value to a temporary stack slot, then LOAD the returned part. 1359 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1360 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, 1361 MachinePointerInfo(), false, false, 0); 1362 1363 // Add the offset to the index. 1364 unsigned EltSize = 1365 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1366 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1367 DAG.getConstant(EltSize, Idx.getValueType())); 1368 1369 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1370 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1371 else 1372 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1373 1374 StackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, StackPtr); 1375 1376 if (Op.getValueType().isVector()) 1377 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr,MachinePointerInfo(), 1378 false, false, false, 0); 1379 return DAG.getExtLoad(ISD::EXTLOAD, dl, Op.getValueType(), Ch, StackPtr, 1380 MachinePointerInfo(), 1381 Vec.getValueType().getVectorElementType(), 1382 false, false, 0); 1383 } 1384 1385 SDValue SelectionDAGLegalize::ExpandInsertToVectorThroughStack(SDValue Op) { 1386 assert(Op.getValueType().isVector() && "Non-vector insert subvector!"); 1387 1388 SDValue Vec = Op.getOperand(0); 1389 SDValue Part = Op.getOperand(1); 1390 SDValue Idx = Op.getOperand(2); 1391 DebugLoc dl = Op.getDebugLoc(); 1392 1393 // Store the value to a temporary stack slot, then LOAD the returned part. 1394 1395 SDValue StackPtr = DAG.CreateStackTemporary(Vec.getValueType()); 1396 int FI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex(); 1397 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1398 1399 // First store the whole vector. 1400 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, PtrInfo, 1401 false, false, 0); 1402 1403 // Then store the inserted part. 1404 1405 // Add the offset to the index. 1406 unsigned EltSize = 1407 Vec.getValueType().getVectorElementType().getSizeInBits()/8; 1408 1409 Idx = DAG.getNode(ISD::MUL, dl, Idx.getValueType(), Idx, 1410 DAG.getConstant(EltSize, Idx.getValueType())); 1411 1412 if (Idx.getValueType().bitsGT(TLI.getPointerTy())) 1413 Idx = DAG.getNode(ISD::TRUNCATE, dl, TLI.getPointerTy(), Idx); 1414 else 1415 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); 1416 1417 SDValue SubStackPtr = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, 1418 StackPtr); 1419 1420 // Store the subvector. 1421 Ch = DAG.getStore(DAG.getEntryNode(), dl, Part, SubStackPtr, 1422 MachinePointerInfo(), false, false, 0); 1423 1424 // Finally, load the updated vector. 1425 return DAG.getLoad(Op.getValueType(), dl, Ch, StackPtr, PtrInfo, 1426 false, false, false, 0); 1427 } 1428 1429 SDValue SelectionDAGLegalize::ExpandVectorBuildThroughStack(SDNode* Node) { 1430 // We can't handle this case efficiently. Allocate a sufficiently 1431 // aligned object on the stack, store each element into it, then load 1432 // the result as a vector. 1433 // Create the stack frame object. 1434 EVT VT = Node->getValueType(0); 1435 EVT EltVT = VT.getVectorElementType(); 1436 DebugLoc dl = Node->getDebugLoc(); 1437 SDValue FIPtr = DAG.CreateStackTemporary(VT); 1438 int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex(); 1439 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(FI); 1440 1441 // Emit a store of each element to the stack slot. 1442 SmallVector<SDValue, 8> Stores; 1443 unsigned TypeByteSize = EltVT.getSizeInBits() / 8; 1444 // Store (in the right endianness) the elements to memory. 1445 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1446 // Ignore undef elements. 1447 if (Node->getOperand(i).getOpcode() == ISD::UNDEF) continue; 1448 1449 unsigned Offset = TypeByteSize*i; 1450 1451 SDValue Idx = DAG.getConstant(Offset, FIPtr.getValueType()); 1452 Idx = DAG.getNode(ISD::ADD, dl, FIPtr.getValueType(), FIPtr, Idx); 1453 1454 // If the destination vector element type is narrower than the source 1455 // element type, only store the bits necessary. 1456 if (EltVT.bitsLT(Node->getOperand(i).getValueType().getScalarType())) { 1457 Stores.push_back(DAG.getTruncStore(DAG.getEntryNode(), dl, 1458 Node->getOperand(i), Idx, 1459 PtrInfo.getWithOffset(Offset), 1460 EltVT, false, false, 0)); 1461 } else 1462 Stores.push_back(DAG.getStore(DAG.getEntryNode(), dl, 1463 Node->getOperand(i), Idx, 1464 PtrInfo.getWithOffset(Offset), 1465 false, false, 0)); 1466 } 1467 1468 SDValue StoreChain; 1469 if (!Stores.empty()) // Not all undef elements? 1470 StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, 1471 &Stores[0], Stores.size()); 1472 else 1473 StoreChain = DAG.getEntryNode(); 1474 1475 // Result is a load from the stack slot. 1476 return DAG.getLoad(VT, dl, StoreChain, FIPtr, PtrInfo, 1477 false, false, false, 0); 1478 } 1479 1480 SDValue SelectionDAGLegalize::ExpandFCOPYSIGN(SDNode* Node) { 1481 DebugLoc dl = Node->getDebugLoc(); 1482 SDValue Tmp1 = Node->getOperand(0); 1483 SDValue Tmp2 = Node->getOperand(1); 1484 1485 // Get the sign bit of the RHS. First obtain a value that has the same 1486 // sign as the sign bit, i.e. negative if and only if the sign bit is 1. 1487 SDValue SignBit; 1488 EVT FloatVT = Tmp2.getValueType(); 1489 EVT IVT = EVT::getIntegerVT(*DAG.getContext(), FloatVT.getSizeInBits()); 1490 if (TLI.isTypeLegal(IVT)) { 1491 // Convert to an integer with the same sign bit. 1492 SignBit = DAG.getNode(ISD::BITCAST, dl, IVT, Tmp2); 1493 } else { 1494 // Store the float to memory, then load the sign part out as an integer. 1495 MVT LoadTy = TLI.getPointerTy(); 1496 // First create a temporary that is aligned for both the load and store. 1497 SDValue StackPtr = DAG.CreateStackTemporary(FloatVT, LoadTy); 1498 // Then store the float to it. 1499 SDValue Ch = 1500 DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StackPtr, MachinePointerInfo(), 1501 false, false, 0); 1502 if (TLI.isBigEndian()) { 1503 assert(FloatVT.isByteSized() && "Unsupported floating point type!"); 1504 // Load out a legal integer with the same sign bit as the float. 1505 SignBit = DAG.getLoad(LoadTy, dl, Ch, StackPtr, MachinePointerInfo(), 1506 false, false, false, 0); 1507 } else { // Little endian 1508 SDValue LoadPtr = StackPtr; 1509 // The float may be wider than the integer we are going to load. Advance 1510 // the pointer so that the loaded integer will contain the sign bit. 1511 unsigned Strides = (FloatVT.getSizeInBits()-1)/LoadTy.getSizeInBits(); 1512 unsigned ByteOffset = (Strides * LoadTy.getSizeInBits()) / 8; 1513 LoadPtr = DAG.getNode(ISD::ADD, dl, LoadPtr.getValueType(), 1514 LoadPtr, DAG.getIntPtrConstant(ByteOffset)); 1515 // Load a legal integer containing the sign bit. 1516 SignBit = DAG.getLoad(LoadTy, dl, Ch, LoadPtr, MachinePointerInfo(), 1517 false, false, false, 0); 1518 // Move the sign bit to the top bit of the loaded integer. 1519 unsigned BitShift = LoadTy.getSizeInBits() - 1520 (FloatVT.getSizeInBits() - 8 * ByteOffset); 1521 assert(BitShift < LoadTy.getSizeInBits() && "Pointer advanced wrong?"); 1522 if (BitShift) 1523 SignBit = DAG.getNode(ISD::SHL, dl, LoadTy, SignBit, 1524 DAG.getConstant(BitShift, 1525 TLI.getShiftAmountTy(SignBit.getValueType()))); 1526 } 1527 } 1528 // Now get the sign bit proper, by seeing whether the value is negative. 1529 SignBit = DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()), 1530 SignBit, DAG.getConstant(0, SignBit.getValueType()), 1531 ISD::SETLT); 1532 // Get the absolute value of the result. 1533 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1); 1534 // Select between the nabs and abs value based on the sign bit of 1535 // the input. 1536 return DAG.getNode(ISD::SELECT, dl, AbsVal.getValueType(), SignBit, 1537 DAG.getNode(ISD::FNEG, dl, AbsVal.getValueType(), AbsVal), 1538 AbsVal); 1539 } 1540 1541 void SelectionDAGLegalize::ExpandDYNAMIC_STACKALLOC(SDNode* Node, 1542 SmallVectorImpl<SDValue> &Results) { 1543 unsigned SPReg = TLI.getStackPointerRegisterToSaveRestore(); 1544 assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and" 1545 " not tell us which reg is the stack pointer!"); 1546 DebugLoc dl = Node->getDebugLoc(); 1547 EVT VT = Node->getValueType(0); 1548 SDValue Tmp1 = SDValue(Node, 0); 1549 SDValue Tmp2 = SDValue(Node, 1); 1550 SDValue Tmp3 = Node->getOperand(2); 1551 SDValue Chain = Tmp1.getOperand(0); 1552 1553 // Chain the dynamic stack allocation so that it doesn't modify the stack 1554 // pointer when other instructions are using the stack. 1555 Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(0, true)); 1556 1557 SDValue Size = Tmp2.getOperand(1); 1558 SDValue SP = DAG.getCopyFromReg(Chain, dl, SPReg, VT); 1559 Chain = SP.getValue(1); 1560 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); 1561 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 1562 if (Align > StackAlign) 1563 SP = DAG.getNode(ISD::AND, dl, VT, SP, 1564 DAG.getConstant(-(uint64_t)Align, VT)); 1565 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value 1566 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Output chain 1567 1568 Tmp2 = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, true), 1569 DAG.getIntPtrConstant(0, true), SDValue()); 1570 1571 Results.push_back(Tmp1); 1572 Results.push_back(Tmp2); 1573 } 1574 1575 /// LegalizeSetCCCondCode - Legalize a SETCC with given LHS and RHS and 1576 /// condition code CC on the current target. This routine expands SETCC with 1577 /// illegal condition code into AND / OR of multiple SETCC values. 1578 void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT, 1579 SDValue &LHS, SDValue &RHS, 1580 SDValue &CC, 1581 DebugLoc dl) { 1582 EVT OpVT = LHS.getValueType(); 1583 ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get(); 1584 switch (TLI.getCondCodeAction(CCCode, OpVT)) { 1585 default: llvm_unreachable("Unknown condition code action!"); 1586 case TargetLowering::Legal: 1587 // Nothing to do. 1588 break; 1589 case TargetLowering::Expand: { 1590 ISD::CondCode CC1 = ISD::SETCC_INVALID, CC2 = ISD::SETCC_INVALID; 1591 unsigned Opc = 0; 1592 switch (CCCode) { 1593 default: llvm_unreachable("Don't know how to expand this condition!"); 1594 case ISD::SETOEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETO; Opc = ISD::AND; break; 1595 case ISD::SETOGT: CC1 = ISD::SETGT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1596 case ISD::SETOGE: CC1 = ISD::SETGE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1597 case ISD::SETOLT: CC1 = ISD::SETLT; CC2 = ISD::SETO; Opc = ISD::AND; break; 1598 case ISD::SETOLE: CC1 = ISD::SETLE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1599 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; 1600 case ISD::SETUEQ: CC1 = ISD::SETEQ; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1601 case ISD::SETUGT: CC1 = ISD::SETGT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1602 case ISD::SETUGE: CC1 = ISD::SETGE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1603 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1604 case ISD::SETULE: CC1 = ISD::SETLE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1605 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; 1606 // FIXME: Implement more expansions. 1607 } 1608 1609 SDValue SetCC1 = DAG.getSetCC(dl, VT, LHS, RHS, CC1); 1610 SDValue SetCC2 = DAG.getSetCC(dl, VT, LHS, RHS, CC2); 1611 LHS = DAG.getNode(Opc, dl, VT, SetCC1, SetCC2); 1612 RHS = SDValue(); 1613 CC = SDValue(); 1614 break; 1615 } 1616 } 1617 } 1618 1619 /// EmitStackConvert - Emit a store/load combination to the stack. This stores 1620 /// SrcOp to a stack slot of type SlotVT, truncating it if needed. It then does 1621 /// a load from the stack slot to DestVT, extending it if needed. 1622 /// The resultant code need not be legal. 1623 SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp, 1624 EVT SlotVT, 1625 EVT DestVT, 1626 DebugLoc dl) { 1627 // Create the stack frame object. 1628 unsigned SrcAlign = 1629 TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType(). 1630 getTypeForEVT(*DAG.getContext())); 1631 SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign); 1632 1633 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr); 1634 int SPFI = StackPtrFI->getIndex(); 1635 MachinePointerInfo PtrInfo = MachinePointerInfo::getFixedStack(SPFI); 1636 1637 unsigned SrcSize = SrcOp.getValueType().getSizeInBits(); 1638 unsigned SlotSize = SlotVT.getSizeInBits(); 1639 unsigned DestSize = DestVT.getSizeInBits(); 1640 Type *DestType = DestVT.getTypeForEVT(*DAG.getContext()); 1641 unsigned DestAlign = TLI.getTargetData()->getPrefTypeAlignment(DestType); 1642 1643 // Emit a store to the stack slot. Use a truncstore if the input value is 1644 // later than DestVT. 1645 SDValue Store; 1646 1647 if (SrcSize > SlotSize) 1648 Store = DAG.getTruncStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1649 PtrInfo, SlotVT, false, false, SrcAlign); 1650 else { 1651 assert(SrcSize == SlotSize && "Invalid store"); 1652 Store = DAG.getStore(DAG.getEntryNode(), dl, SrcOp, FIPtr, 1653 PtrInfo, false, false, SrcAlign); 1654 } 1655 1656 // Result is a load from the stack slot. 1657 if (SlotSize == DestSize) 1658 return DAG.getLoad(DestVT, dl, Store, FIPtr, PtrInfo, 1659 false, false, false, DestAlign); 1660 1661 assert(SlotSize < DestSize && "Unknown extension!"); 1662 return DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, Store, FIPtr, 1663 PtrInfo, SlotVT, false, false, DestAlign); 1664 } 1665 1666 SDValue SelectionDAGLegalize::ExpandSCALAR_TO_VECTOR(SDNode *Node) { 1667 DebugLoc dl = Node->getDebugLoc(); 1668 // Create a vector sized/aligned stack slot, store the value to element #0, 1669 // then load the whole vector back out. 1670 SDValue StackPtr = DAG.CreateStackTemporary(Node->getValueType(0)); 1671 1672 FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(StackPtr); 1673 int SPFI = StackPtrFI->getIndex(); 1674 1675 SDValue Ch = DAG.getTruncStore(DAG.getEntryNode(), dl, Node->getOperand(0), 1676 StackPtr, 1677 MachinePointerInfo::getFixedStack(SPFI), 1678 Node->getValueType(0).getVectorElementType(), 1679 false, false, 0); 1680 return DAG.getLoad(Node->getValueType(0), dl, Ch, StackPtr, 1681 MachinePointerInfo::getFixedStack(SPFI), 1682 false, false, false, 0); 1683 } 1684 1685 1686 /// ExpandBUILD_VECTOR - Expand a BUILD_VECTOR node on targets that don't 1687 /// support the operation, but do support the resultant vector type. 1688 SDValue SelectionDAGLegalize::ExpandBUILD_VECTOR(SDNode *Node) { 1689 unsigned NumElems = Node->getNumOperands(); 1690 SDValue Value1, Value2; 1691 DebugLoc dl = Node->getDebugLoc(); 1692 EVT VT = Node->getValueType(0); 1693 EVT OpVT = Node->getOperand(0).getValueType(); 1694 EVT EltVT = VT.getVectorElementType(); 1695 1696 // If the only non-undef value is the low element, turn this into a 1697 // SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X. 1698 bool isOnlyLowElement = true; 1699 bool MoreThanTwoValues = false; 1700 bool isConstant = true; 1701 for (unsigned i = 0; i < NumElems; ++i) { 1702 SDValue V = Node->getOperand(i); 1703 if (V.getOpcode() == ISD::UNDEF) 1704 continue; 1705 if (i > 0) 1706 isOnlyLowElement = false; 1707 if (!isa<ConstantFPSDNode>(V) && !isa<ConstantSDNode>(V)) 1708 isConstant = false; 1709 1710 if (!Value1.getNode()) { 1711 Value1 = V; 1712 } else if (!Value2.getNode()) { 1713 if (V != Value1) 1714 Value2 = V; 1715 } else if (V != Value1 && V != Value2) { 1716 MoreThanTwoValues = true; 1717 } 1718 } 1719 1720 if (!Value1.getNode()) 1721 return DAG.getUNDEF(VT); 1722 1723 if (isOnlyLowElement) 1724 return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Node->getOperand(0)); 1725 1726 // If all elements are constants, create a load from the constant pool. 1727 if (isConstant) { 1728 SmallVector<Constant*, 16> CV; 1729 for (unsigned i = 0, e = NumElems; i != e; ++i) { 1730 if (ConstantFPSDNode *V = 1731 dyn_cast<ConstantFPSDNode>(Node->getOperand(i))) { 1732 CV.push_back(const_cast<ConstantFP *>(V->getConstantFPValue())); 1733 } else if (ConstantSDNode *V = 1734 dyn_cast<ConstantSDNode>(Node->getOperand(i))) { 1735 if (OpVT==EltVT) 1736 CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue())); 1737 else { 1738 // If OpVT and EltVT don't match, EltVT is not legal and the 1739 // element values have been promoted/truncated earlier. Undo this; 1740 // we don't want a v16i8 to become a v16i32 for example. 1741 const ConstantInt *CI = V->getConstantIntValue(); 1742 CV.push_back(ConstantInt::get(EltVT.getTypeForEVT(*DAG.getContext()), 1743 CI->getZExtValue())); 1744 } 1745 } else { 1746 assert(Node->getOperand(i).getOpcode() == ISD::UNDEF); 1747 Type *OpNTy = EltVT.getTypeForEVT(*DAG.getContext()); 1748 CV.push_back(UndefValue::get(OpNTy)); 1749 } 1750 } 1751 Constant *CP = ConstantVector::get(CV); 1752 SDValue CPIdx = DAG.getConstantPool(CP, TLI.getPointerTy()); 1753 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 1754 return DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx, 1755 MachinePointerInfo::getConstantPool(), 1756 false, false, false, Alignment); 1757 } 1758 1759 if (!MoreThanTwoValues) { 1760 SmallVector<int, 8> ShuffleVec(NumElems, -1); 1761 for (unsigned i = 0; i < NumElems; ++i) { 1762 SDValue V = Node->getOperand(i); 1763 if (V.getOpcode() == ISD::UNDEF) 1764 continue; 1765 ShuffleVec[i] = V == Value1 ? 0 : NumElems; 1766 } 1767 if (TLI.isShuffleMaskLegal(ShuffleVec, Node->getValueType(0))) { 1768 // Get the splatted value into the low element of a vector register. 1769 SDValue Vec1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value1); 1770 SDValue Vec2; 1771 if (Value2.getNode()) 1772 Vec2 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Value2); 1773 else 1774 Vec2 = DAG.getUNDEF(VT); 1775 1776 // Return shuffle(LowValVec, undef, <0,0,0,0>) 1777 return DAG.getVectorShuffle(VT, dl, Vec1, Vec2, ShuffleVec.data()); 1778 } 1779 } 1780 1781 // Otherwise, we can't handle this case efficiently. 1782 return ExpandVectorBuildThroughStack(Node); 1783 } 1784 1785 // ExpandLibCall - Expand a node into a call to a libcall. If the result value 1786 // does not fit into a register, return the lo part and set the hi part to the 1787 // by-reg argument. If it does fit into a single register, return the result 1788 // and leave the Hi part unset. 1789 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, 1790 bool isSigned) { 1791 TargetLowering::ArgListTy Args; 1792 TargetLowering::ArgListEntry Entry; 1793 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 1794 EVT ArgVT = Node->getOperand(i).getValueType(); 1795 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1796 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 1797 Entry.isSExt = isSigned; 1798 Entry.isZExt = !isSigned; 1799 Args.push_back(Entry); 1800 } 1801 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1802 TLI.getPointerTy()); 1803 1804 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1805 1806 // By default, the input chain to this libcall is the entry node of the 1807 // function. If the libcall is going to be emitted as a tail call then 1808 // TLI.isUsedByReturnOnly will change it to the right chain if the return 1809 // node which is being folded has a non-entry input chain. 1810 SDValue InChain = DAG.getEntryNode(); 1811 1812 // isTailCall may be true since the callee does not reference caller stack 1813 // frame. Check if it's in the right position. 1814 SDValue TCChain = InChain; 1815 bool isTailCall = isInTailCallPosition(DAG, Node, TCChain, TLI); 1816 if (isTailCall) 1817 InChain = TCChain; 1818 1819 TargetLowering:: 1820 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 1821 0, TLI.getLibcallCallingConv(LC), isTailCall, 1822 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1823 Callee, Args, DAG, Node->getDebugLoc()); 1824 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 1825 1826 1827 if (!CallInfo.second.getNode()) 1828 // It's a tailcall, return the chain (which is the DAG root). 1829 return DAG.getRoot(); 1830 1831 return CallInfo.first; 1832 } 1833 1834 /// ExpandLibCall - Generate a libcall taking the given operands as arguments 1835 /// and returning a result of type RetVT. 1836 SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT, 1837 const SDValue *Ops, unsigned NumOps, 1838 bool isSigned, DebugLoc dl) { 1839 TargetLowering::ArgListTy Args; 1840 Args.reserve(NumOps); 1841 1842 TargetLowering::ArgListEntry Entry; 1843 for (unsigned i = 0; i != NumOps; ++i) { 1844 Entry.Node = Ops[i]; 1845 Entry.Ty = Entry.Node.getValueType().getTypeForEVT(*DAG.getContext()); 1846 Entry.isSExt = isSigned; 1847 Entry.isZExt = !isSigned; 1848 Args.push_back(Entry); 1849 } 1850 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1851 TLI.getPointerTy()); 1852 1853 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1854 TargetLowering:: 1855 CallLoweringInfo CLI(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false, 1856 false, 0, TLI.getLibcallCallingConv(LC), 1857 /*isTailCall=*/false, 1858 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1859 Callee, Args, DAG, dl); 1860 std::pair<SDValue,SDValue> CallInfo = TLI.LowerCallTo(CLI); 1861 1862 return CallInfo.first; 1863 } 1864 1865 // ExpandChainLibCall - Expand a node into a call to a libcall. Similar to 1866 // ExpandLibCall except that the first operand is the in-chain. 1867 std::pair<SDValue, SDValue> 1868 SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC, 1869 SDNode *Node, 1870 bool isSigned) { 1871 SDValue InChain = Node->getOperand(0); 1872 1873 TargetLowering::ArgListTy Args; 1874 TargetLowering::ArgListEntry Entry; 1875 for (unsigned i = 1, e = Node->getNumOperands(); i != e; ++i) { 1876 EVT ArgVT = Node->getOperand(i).getValueType(); 1877 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 1878 Entry.Node = Node->getOperand(i); 1879 Entry.Ty = ArgTy; 1880 Entry.isSExt = isSigned; 1881 Entry.isZExt = !isSigned; 1882 Args.push_back(Entry); 1883 } 1884 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 1885 TLI.getPointerTy()); 1886 1887 Type *RetTy = Node->getValueType(0).getTypeForEVT(*DAG.getContext()); 1888 TargetLowering:: 1889 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 1890 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 1891 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 1892 Callee, Args, DAG, Node->getDebugLoc()); 1893 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 1894 1895 return CallInfo; 1896 } 1897 1898 SDValue SelectionDAGLegalize::ExpandFPLibCall(SDNode* Node, 1899 RTLIB::Libcall Call_F32, 1900 RTLIB::Libcall Call_F64, 1901 RTLIB::Libcall Call_F80, 1902 RTLIB::Libcall Call_PPCF128) { 1903 RTLIB::Libcall LC; 1904 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1905 default: llvm_unreachable("Unexpected request for libcall!"); 1906 case MVT::f32: LC = Call_F32; break; 1907 case MVT::f64: LC = Call_F64; break; 1908 case MVT::f80: LC = Call_F80; break; 1909 case MVT::ppcf128: LC = Call_PPCF128; break; 1910 } 1911 return ExpandLibCall(LC, Node, false); 1912 } 1913 1914 SDValue SelectionDAGLegalize::ExpandIntLibCall(SDNode* Node, bool isSigned, 1915 RTLIB::Libcall Call_I8, 1916 RTLIB::Libcall Call_I16, 1917 RTLIB::Libcall Call_I32, 1918 RTLIB::Libcall Call_I64, 1919 RTLIB::Libcall Call_I128) { 1920 RTLIB::Libcall LC; 1921 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1922 default: llvm_unreachable("Unexpected request for libcall!"); 1923 case MVT::i8: LC = Call_I8; break; 1924 case MVT::i16: LC = Call_I16; break; 1925 case MVT::i32: LC = Call_I32; break; 1926 case MVT::i64: LC = Call_I64; break; 1927 case MVT::i128: LC = Call_I128; break; 1928 } 1929 return ExpandLibCall(LC, Node, isSigned); 1930 } 1931 1932 /// isDivRemLibcallAvailable - Return true if divmod libcall is available. 1933 static bool isDivRemLibcallAvailable(SDNode *Node, bool isSigned, 1934 const TargetLowering &TLI) { 1935 RTLIB::Libcall LC; 1936 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1937 default: llvm_unreachable("Unexpected request for libcall!"); 1938 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1939 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1940 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1941 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1942 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1943 } 1944 1945 return TLI.getLibcallName(LC) != 0; 1946 } 1947 1948 /// useDivRem - Only issue divrem libcall if both quotient and remainder are 1949 /// needed. 1950 static bool useDivRem(SDNode *Node, bool isSigned, bool isDIV) { 1951 // The other use might have been replaced with a divrem already. 1952 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 1953 unsigned OtherOpcode = 0; 1954 if (isSigned) 1955 OtherOpcode = isDIV ? ISD::SREM : ISD::SDIV; 1956 else 1957 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; 1958 1959 SDValue Op0 = Node->getOperand(0); 1960 SDValue Op1 = Node->getOperand(1); 1961 for (SDNode::use_iterator UI = Op0.getNode()->use_begin(), 1962 UE = Op0.getNode()->use_end(); UI != UE; ++UI) { 1963 SDNode *User = *UI; 1964 if (User == Node) 1965 continue; 1966 if ((User->getOpcode() == OtherOpcode || User->getOpcode() == DivRemOpc) && 1967 User->getOperand(0) == Op0 && 1968 User->getOperand(1) == Op1) 1969 return true; 1970 } 1971 return false; 1972 } 1973 1974 /// ExpandDivRemLibCall - Issue libcalls to __{u}divmod to compute div / rem 1975 /// pairs. 1976 void 1977 SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node, 1978 SmallVectorImpl<SDValue> &Results) { 1979 unsigned Opcode = Node->getOpcode(); 1980 bool isSigned = Opcode == ISD::SDIVREM; 1981 1982 RTLIB::Libcall LC; 1983 switch (Node->getValueType(0).getSimpleVT().SimpleTy) { 1984 default: llvm_unreachable("Unexpected request for libcall!"); 1985 case MVT::i8: LC= isSigned ? RTLIB::SDIVREM_I8 : RTLIB::UDIVREM_I8; break; 1986 case MVT::i16: LC= isSigned ? RTLIB::SDIVREM_I16 : RTLIB::UDIVREM_I16; break; 1987 case MVT::i32: LC= isSigned ? RTLIB::SDIVREM_I32 : RTLIB::UDIVREM_I32; break; 1988 case MVT::i64: LC= isSigned ? RTLIB::SDIVREM_I64 : RTLIB::UDIVREM_I64; break; 1989 case MVT::i128: LC= isSigned ? RTLIB::SDIVREM_I128:RTLIB::UDIVREM_I128; break; 1990 } 1991 1992 // The input chain to this libcall is the entry node of the function. 1993 // Legalizing the call will automatically add the previous call to the 1994 // dependence. 1995 SDValue InChain = DAG.getEntryNode(); 1996 1997 EVT RetVT = Node->getValueType(0); 1998 Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext()); 1999 2000 TargetLowering::ArgListTy Args; 2001 TargetLowering::ArgListEntry Entry; 2002 for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) { 2003 EVT ArgVT = Node->getOperand(i).getValueType(); 2004 Type *ArgTy = ArgVT.getTypeForEVT(*DAG.getContext()); 2005 Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy; 2006 Entry.isSExt = isSigned; 2007 Entry.isZExt = !isSigned; 2008 Args.push_back(Entry); 2009 } 2010 2011 // Also pass the return address of the remainder. 2012 SDValue FIPtr = DAG.CreateStackTemporary(RetVT); 2013 Entry.Node = FIPtr; 2014 Entry.Ty = RetTy->getPointerTo(); 2015 Entry.isSExt = isSigned; 2016 Entry.isZExt = !isSigned; 2017 Args.push_back(Entry); 2018 2019 SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC), 2020 TLI.getPointerTy()); 2021 2022 DebugLoc dl = Node->getDebugLoc(); 2023 TargetLowering:: 2024 CallLoweringInfo CLI(InChain, RetTy, isSigned, !isSigned, false, false, 2025 0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false, 2026 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2027 Callee, Args, DAG, dl); 2028 std::pair<SDValue, SDValue> CallInfo = TLI.LowerCallTo(CLI); 2029 2030 // Remainder is loaded back from the stack frame. 2031 SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr, 2032 MachinePointerInfo(), false, false, false, 0); 2033 Results.push_back(CallInfo.first); 2034 Results.push_back(Rem); 2035 } 2036 2037 /// ExpandLegalINT_TO_FP - This function is responsible for legalizing a 2038 /// INT_TO_FP operation of the specified operand when the target requests that 2039 /// we expand it. At this point, we know that the result and operand types are 2040 /// legal for the target. 2041 SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned, 2042 SDValue Op0, 2043 EVT DestVT, 2044 DebugLoc dl) { 2045 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) { 2046 // simple 32-bit [signed|unsigned] integer to float/double expansion 2047 2048 // Get the stack frame index of a 8 byte buffer. 2049 SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64); 2050 2051 // word offset constant for Hi/Lo address computation 2052 SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy()); 2053 // set up Hi and Lo (into buffer) address based on endian 2054 SDValue Hi = StackSlot; 2055 SDValue Lo = DAG.getNode(ISD::ADD, dl, 2056 TLI.getPointerTy(), StackSlot, WordOff); 2057 if (TLI.isLittleEndian()) 2058 std::swap(Hi, Lo); 2059 2060 // if signed map to unsigned space 2061 SDValue Op0Mapped; 2062 if (isSigned) { 2063 // constant used to invert sign bit (signed to unsigned mapping) 2064 SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32); 2065 Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit); 2066 } else { 2067 Op0Mapped = Op0; 2068 } 2069 // store the lo of the constructed double - based on integer input 2070 SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl, 2071 Op0Mapped, Lo, MachinePointerInfo(), 2072 false, false, 0); 2073 // initial hi portion of constructed double 2074 SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32); 2075 // store the hi of the constructed double - biased exponent 2076 SDValue Store2 = DAG.getStore(Store1, dl, InitialHi, Hi, 2077 MachinePointerInfo(), 2078 false, false, 0); 2079 // load the constructed double 2080 SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, 2081 MachinePointerInfo(), false, false, false, 0); 2082 // FP constant to bias correct the final result 2083 SDValue Bias = DAG.getConstantFP(isSigned ? 2084 BitsToDouble(0x4330000080000000ULL) : 2085 BitsToDouble(0x4330000000000000ULL), 2086 MVT::f64); 2087 // subtract the bias 2088 SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias); 2089 // final result 2090 SDValue Result; 2091 // handle final rounding 2092 if (DestVT == MVT::f64) { 2093 // do nothing 2094 Result = Sub; 2095 } else if (DestVT.bitsLT(MVT::f64)) { 2096 Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub, 2097 DAG.getIntPtrConstant(0)); 2098 } else if (DestVT.bitsGT(MVT::f64)) { 2099 Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub); 2100 } 2101 return Result; 2102 } 2103 assert(!isSigned && "Legalize cannot Expand SINT_TO_FP for i64 yet"); 2104 // Code below here assumes !isSigned without checking again. 2105 2106 // Implementation of unsigned i64 to f64 following the algorithm in 2107 // __floatundidf in compiler_rt. This implementation has the advantage 2108 // of performing rounding correctly, both in the default rounding mode 2109 // and in all alternate rounding modes. 2110 // TODO: Generalize this for use with other types. 2111 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f64) { 2112 SDValue TwoP52 = 2113 DAG.getConstant(UINT64_C(0x4330000000000000), MVT::i64); 2114 SDValue TwoP84PlusTwoP52 = 2115 DAG.getConstantFP(BitsToDouble(UINT64_C(0x4530000000100000)), MVT::f64); 2116 SDValue TwoP84 = 2117 DAG.getConstant(UINT64_C(0x4530000000000000), MVT::i64); 2118 2119 SDValue Lo = DAG.getZeroExtendInReg(Op0, dl, MVT::i32); 2120 SDValue Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, 2121 DAG.getConstant(32, MVT::i64)); 2122 SDValue LoOr = DAG.getNode(ISD::OR, dl, MVT::i64, Lo, TwoP52); 2123 SDValue HiOr = DAG.getNode(ISD::OR, dl, MVT::i64, Hi, TwoP84); 2124 SDValue LoFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, LoOr); 2125 SDValue HiFlt = DAG.getNode(ISD::BITCAST, dl, MVT::f64, HiOr); 2126 SDValue HiSub = DAG.getNode(ISD::FSUB, dl, MVT::f64, HiFlt, 2127 TwoP84PlusTwoP52); 2128 return DAG.getNode(ISD::FADD, dl, MVT::f64, LoFlt, HiSub); 2129 } 2130 2131 // Implementation of unsigned i64 to f32. 2132 // TODO: Generalize this for use with other types. 2133 if (Op0.getValueType() == MVT::i64 && DestVT == MVT::f32) { 2134 // For unsigned conversions, convert them to signed conversions using the 2135 // algorithm from the x86_64 __floatundidf in compiler_rt. 2136 if (!isSigned) { 2137 SDValue Fast = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Op0); 2138 2139 SDValue ShiftConst = 2140 DAG.getConstant(1, TLI.getShiftAmountTy(Op0.getValueType())); 2141 SDValue Shr = DAG.getNode(ISD::SRL, dl, MVT::i64, Op0, ShiftConst); 2142 SDValue AndConst = DAG.getConstant(1, MVT::i64); 2143 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, AndConst); 2144 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, Shr); 2145 2146 SDValue SignCvt = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, Or); 2147 SDValue Slow = DAG.getNode(ISD::FADD, dl, MVT::f32, SignCvt, SignCvt); 2148 2149 // TODO: This really should be implemented using a branch rather than a 2150 // select. We happen to get lucky and machinesink does the right 2151 // thing most of the time. This would be a good candidate for a 2152 //pseudo-op, or, even better, for whole-function isel. 2153 SDValue SignBitTest = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2154 Op0, DAG.getConstant(0, MVT::i64), ISD::SETLT); 2155 return DAG.getNode(ISD::SELECT, dl, MVT::f32, SignBitTest, Slow, Fast); 2156 } 2157 2158 // Otherwise, implement the fully general conversion. 2159 2160 SDValue And = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2161 DAG.getConstant(UINT64_C(0xfffffffffffff800), MVT::i64)); 2162 SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i64, And, 2163 DAG.getConstant(UINT64_C(0x800), MVT::i64)); 2164 SDValue And2 = DAG.getNode(ISD::AND, dl, MVT::i64, Op0, 2165 DAG.getConstant(UINT64_C(0x7ff), MVT::i64)); 2166 SDValue Ne = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2167 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); 2168 SDValue Sel = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ne, Or, Op0); 2169 SDValue Ge = DAG.getSetCC(dl, TLI.getSetCCResultType(MVT::i64), 2170 Op0, DAG.getConstant(UINT64_C(0x0020000000000000), MVT::i64), 2171 ISD::SETUGE); 2172 SDValue Sel2 = DAG.getNode(ISD::SELECT, dl, MVT::i64, Ge, Sel, Op0); 2173 EVT SHVT = TLI.getShiftAmountTy(Sel2.getValueType()); 2174 2175 SDValue Sh = DAG.getNode(ISD::SRL, dl, MVT::i64, Sel2, 2176 DAG.getConstant(32, SHVT)); 2177 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sh); 2178 SDValue Fcvt = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Trunc); 2179 SDValue TwoP32 = 2180 DAG.getConstantFP(BitsToDouble(UINT64_C(0x41f0000000000000)), MVT::f64); 2181 SDValue Fmul = DAG.getNode(ISD::FMUL, dl, MVT::f64, TwoP32, Fcvt); 2182 SDValue Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Sel2); 2183 SDValue Fcvt2 = DAG.getNode(ISD::UINT_TO_FP, dl, MVT::f64, Lo); 2184 SDValue Fadd = DAG.getNode(ISD::FADD, dl, MVT::f64, Fmul, Fcvt2); 2185 return DAG.getNode(ISD::FP_ROUND, dl, MVT::f32, Fadd, 2186 DAG.getIntPtrConstant(0)); 2187 } 2188 2189 SDValue Tmp1 = DAG.getNode(ISD::SINT_TO_FP, dl, DestVT, Op0); 2190 2191 SDValue SignSet = DAG.getSetCC(dl, TLI.getSetCCResultType(Op0.getValueType()), 2192 Op0, DAG.getConstant(0, Op0.getValueType()), 2193 ISD::SETLT); 2194 SDValue Zero = DAG.getIntPtrConstant(0), Four = DAG.getIntPtrConstant(4); 2195 SDValue CstOffset = DAG.getNode(ISD::SELECT, dl, Zero.getValueType(), 2196 SignSet, Four, Zero); 2197 2198 // If the sign bit of the integer is set, the large number will be treated 2199 // as a negative number. To counteract this, the dynamic code adds an 2200 // offset depending on the data type. 2201 uint64_t FF; 2202 switch (Op0.getValueType().getSimpleVT().SimpleTy) { 2203 default: llvm_unreachable("Unsupported integer type!"); 2204 case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float) 2205 case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float) 2206 case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float) 2207 case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float) 2208 } 2209 if (TLI.isLittleEndian()) FF <<= 32; 2210 Constant *FudgeFactor = ConstantInt::get( 2211 Type::getInt64Ty(*DAG.getContext()), FF); 2212 2213 SDValue CPIdx = DAG.getConstantPool(FudgeFactor, TLI.getPointerTy()); 2214 unsigned Alignment = cast<ConstantPoolSDNode>(CPIdx)->getAlignment(); 2215 CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset); 2216 Alignment = std::min(Alignment, 4u); 2217 SDValue FudgeInReg; 2218 if (DestVT == MVT::f32) 2219 FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx, 2220 MachinePointerInfo::getConstantPool(), 2221 false, false, false, Alignment); 2222 else { 2223 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT, 2224 DAG.getEntryNode(), CPIdx, 2225 MachinePointerInfo::getConstantPool(), 2226 MVT::f32, false, false, Alignment); 2227 HandleSDNode Handle(Load); 2228 LegalizeOp(Load.getNode()); 2229 FudgeInReg = Handle.getValue(); 2230 } 2231 2232 return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg); 2233 } 2234 2235 /// PromoteLegalINT_TO_FP - This function is responsible for legalizing a 2236 /// *INT_TO_FP operation of the specified operand when the target requests that 2237 /// we promote it. At this point, we know that the result and operand types are 2238 /// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP 2239 /// operation that takes a larger input. 2240 SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp, 2241 EVT DestVT, 2242 bool isSigned, 2243 DebugLoc dl) { 2244 // First step, figure out the appropriate *INT_TO_FP operation to use. 2245 EVT NewInTy = LegalOp.getValueType(); 2246 2247 unsigned OpToUse = 0; 2248 2249 // Scan for the appropriate larger type to use. 2250 while (1) { 2251 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); 2252 assert(NewInTy.isInteger() && "Ran out of possibilities!"); 2253 2254 // If the target supports SINT_TO_FP of this type, use it. 2255 if (TLI.isOperationLegalOrCustom(ISD::SINT_TO_FP, NewInTy)) { 2256 OpToUse = ISD::SINT_TO_FP; 2257 break; 2258 } 2259 if (isSigned) continue; 2260 2261 // If the target supports UINT_TO_FP of this type, use it. 2262 if (TLI.isOperationLegalOrCustom(ISD::UINT_TO_FP, NewInTy)) { 2263 OpToUse = ISD::UINT_TO_FP; 2264 break; 2265 } 2266 2267 // Otherwise, try a larger type. 2268 } 2269 2270 // Okay, we found the operation and type to use. Zero extend our input to the 2271 // desired type then run the operation on it. 2272 return DAG.getNode(OpToUse, dl, DestVT, 2273 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, 2274 dl, NewInTy, LegalOp)); 2275 } 2276 2277 /// PromoteLegalFP_TO_INT - This function is responsible for legalizing a 2278 /// FP_TO_*INT operation of the specified operand when the target requests that 2279 /// we promote it. At this point, we know that the result and operand types are 2280 /// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT 2281 /// operation that returns a larger result. 2282 SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp, 2283 EVT DestVT, 2284 bool isSigned, 2285 DebugLoc dl) { 2286 // First step, figure out the appropriate FP_TO*INT operation to use. 2287 EVT NewOutTy = DestVT; 2288 2289 unsigned OpToUse = 0; 2290 2291 // Scan for the appropriate larger type to use. 2292 while (1) { 2293 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); 2294 assert(NewOutTy.isInteger() && "Ran out of possibilities!"); 2295 2296 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) { 2297 OpToUse = ISD::FP_TO_SINT; 2298 break; 2299 } 2300 2301 if (TLI.isOperationLegalOrCustom(ISD::FP_TO_UINT, NewOutTy)) { 2302 OpToUse = ISD::FP_TO_UINT; 2303 break; 2304 } 2305 2306 // Otherwise, try a larger type. 2307 } 2308 2309 2310 // Okay, we found the operation and type to use. 2311 SDValue Operation = DAG.getNode(OpToUse, dl, NewOutTy, LegalOp); 2312 2313 // Truncate the result of the extended FP_TO_*INT operation to the desired 2314 // size. 2315 return DAG.getNode(ISD::TRUNCATE, dl, DestVT, Operation); 2316 } 2317 2318 /// ExpandBSWAP - Open code the operations for BSWAP of the specified operation. 2319 /// 2320 SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) { 2321 EVT VT = Op.getValueType(); 2322 EVT SHVT = TLI.getShiftAmountTy(VT); 2323 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; 2324 switch (VT.getSimpleVT().SimpleTy) { 2325 default: llvm_unreachable("Unhandled Expand type in BSWAP!"); 2326 case MVT::i16: 2327 Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2328 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2329 return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2); 2330 case MVT::i32: 2331 Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2332 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2333 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2334 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2335 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); 2336 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(0xFF00, VT)); 2337 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2338 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2339 return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2340 case MVT::i64: 2341 Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2342 Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2343 Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2344 Tmp5 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2345 Tmp4 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT)); 2346 Tmp3 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(24, SHVT)); 2347 Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(40, SHVT)); 2348 Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(56, SHVT)); 2349 Tmp7 = DAG.getNode(ISD::AND, dl, VT, Tmp7, DAG.getConstant(255ULL<<48, VT)); 2350 Tmp6 = DAG.getNode(ISD::AND, dl, VT, Tmp6, DAG.getConstant(255ULL<<40, VT)); 2351 Tmp5 = DAG.getNode(ISD::AND, dl, VT, Tmp5, DAG.getConstant(255ULL<<32, VT)); 2352 Tmp4 = DAG.getNode(ISD::AND, dl, VT, Tmp4, DAG.getConstant(255ULL<<24, VT)); 2353 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(255ULL<<16, VT)); 2354 Tmp2 = DAG.getNode(ISD::AND, dl, VT, Tmp2, DAG.getConstant(255ULL<<8 , VT)); 2355 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp7); 2356 Tmp6 = DAG.getNode(ISD::OR, dl, VT, Tmp6, Tmp5); 2357 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3); 2358 Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1); 2359 Tmp8 = DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp6); 2360 Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2); 2361 return DAG.getNode(ISD::OR, dl, VT, Tmp8, Tmp4); 2362 } 2363 } 2364 2365 /// SplatByte - Distribute ByteVal over NumBits bits. 2366 // FIXME: Move this helper to a common place. 2367 static APInt SplatByte(unsigned NumBits, uint8_t ByteVal) { 2368 APInt Val = APInt(NumBits, ByteVal); 2369 unsigned Shift = 8; 2370 for (unsigned i = NumBits; i > 8; i >>= 1) { 2371 Val = (Val << Shift) | Val; 2372 Shift <<= 1; 2373 } 2374 return Val; 2375 } 2376 2377 /// ExpandBitCount - Expand the specified bitcount instruction into operations. 2378 /// 2379 SDValue SelectionDAGLegalize::ExpandBitCount(unsigned Opc, SDValue Op, 2380 DebugLoc dl) { 2381 switch (Opc) { 2382 default: llvm_unreachable("Cannot expand this yet!"); 2383 case ISD::CTPOP: { 2384 EVT VT = Op.getValueType(); 2385 EVT ShVT = TLI.getShiftAmountTy(VT); 2386 unsigned Len = VT.getSizeInBits(); 2387 2388 assert(VT.isInteger() && Len <= 128 && Len % 8 == 0 && 2389 "CTPOP not implemented for this type."); 2390 2391 // This is the "best" algorithm from 2392 // http://graphics.stanford.edu/~seander/bithacks.html#CountBitsSetParallel 2393 2394 SDValue Mask55 = DAG.getConstant(SplatByte(Len, 0x55), VT); 2395 SDValue Mask33 = DAG.getConstant(SplatByte(Len, 0x33), VT); 2396 SDValue Mask0F = DAG.getConstant(SplatByte(Len, 0x0F), VT); 2397 SDValue Mask01 = DAG.getConstant(SplatByte(Len, 0x01), VT); 2398 2399 // v = v - ((v >> 1) & 0x55555555...) 2400 Op = DAG.getNode(ISD::SUB, dl, VT, Op, 2401 DAG.getNode(ISD::AND, dl, VT, 2402 DAG.getNode(ISD::SRL, dl, VT, Op, 2403 DAG.getConstant(1, ShVT)), 2404 Mask55)); 2405 // v = (v & 0x33333333...) + ((v >> 2) & 0x33333333...) 2406 Op = DAG.getNode(ISD::ADD, dl, VT, 2407 DAG.getNode(ISD::AND, dl, VT, Op, Mask33), 2408 DAG.getNode(ISD::AND, dl, VT, 2409 DAG.getNode(ISD::SRL, dl, VT, Op, 2410 DAG.getConstant(2, ShVT)), 2411 Mask33)); 2412 // v = (v + (v >> 4)) & 0x0F0F0F0F... 2413 Op = DAG.getNode(ISD::AND, dl, VT, 2414 DAG.getNode(ISD::ADD, dl, VT, Op, 2415 DAG.getNode(ISD::SRL, dl, VT, Op, 2416 DAG.getConstant(4, ShVT))), 2417 Mask0F); 2418 // v = (v * 0x01010101...) >> (Len - 8) 2419 Op = DAG.getNode(ISD::SRL, dl, VT, 2420 DAG.getNode(ISD::MUL, dl, VT, Op, Mask01), 2421 DAG.getConstant(Len - 8, ShVT)); 2422 2423 return Op; 2424 } 2425 case ISD::CTLZ_ZERO_UNDEF: 2426 // This trivially expands to CTLZ. 2427 return DAG.getNode(ISD::CTLZ, dl, Op.getValueType(), Op); 2428 case ISD::CTLZ: { 2429 // for now, we do this: 2430 // x = x | (x >> 1); 2431 // x = x | (x >> 2); 2432 // ... 2433 // x = x | (x >>16); 2434 // x = x | (x >>32); // for 64-bit input 2435 // return popcount(~x); 2436 // 2437 // but see also: http://www.hackersdelight.org/HDcode/nlz.cc 2438 EVT VT = Op.getValueType(); 2439 EVT ShVT = TLI.getShiftAmountTy(VT); 2440 unsigned len = VT.getSizeInBits(); 2441 for (unsigned i = 0; (1U << i) <= (len / 2); ++i) { 2442 SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT); 2443 Op = DAG.getNode(ISD::OR, dl, VT, Op, 2444 DAG.getNode(ISD::SRL, dl, VT, Op, Tmp3)); 2445 } 2446 Op = DAG.getNOT(dl, Op, VT); 2447 return DAG.getNode(ISD::CTPOP, dl, VT, Op); 2448 } 2449 case ISD::CTTZ_ZERO_UNDEF: 2450 // This trivially expands to CTTZ. 2451 return DAG.getNode(ISD::CTTZ, dl, Op.getValueType(), Op); 2452 case ISD::CTTZ: { 2453 // for now, we use: { return popcount(~x & (x - 1)); } 2454 // unless the target has ctlz but not ctpop, in which case we use: 2455 // { return 32 - nlz(~x & (x-1)); } 2456 // see also http://www.hackersdelight.org/HDcode/ntz.cc 2457 EVT VT = Op.getValueType(); 2458 SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT, 2459 DAG.getNOT(dl, Op, VT), 2460 DAG.getNode(ISD::SUB, dl, VT, Op, 2461 DAG.getConstant(1, VT))); 2462 // If ISD::CTLZ is legal and CTPOP isn't, then do that instead. 2463 if (!TLI.isOperationLegalOrCustom(ISD::CTPOP, VT) && 2464 TLI.isOperationLegalOrCustom(ISD::CTLZ, VT)) 2465 return DAG.getNode(ISD::SUB, dl, VT, 2466 DAG.getConstant(VT.getSizeInBits(), VT), 2467 DAG.getNode(ISD::CTLZ, dl, VT, Tmp3)); 2468 return DAG.getNode(ISD::CTPOP, dl, VT, Tmp3); 2469 } 2470 } 2471 } 2472 2473 std::pair <SDValue, SDValue> SelectionDAGLegalize::ExpandAtomic(SDNode *Node) { 2474 unsigned Opc = Node->getOpcode(); 2475 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); 2476 RTLIB::Libcall LC; 2477 2478 switch (Opc) { 2479 default: 2480 llvm_unreachable("Unhandled atomic intrinsic Expand!"); 2481 case ISD::ATOMIC_SWAP: 2482 switch (VT.SimpleTy) { 2483 default: llvm_unreachable("Unexpected value type for atomic!"); 2484 case MVT::i8: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_1; break; 2485 case MVT::i16: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_2; break; 2486 case MVT::i32: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_4; break; 2487 case MVT::i64: LC = RTLIB::SYNC_LOCK_TEST_AND_SET_8; break; 2488 } 2489 break; 2490 case ISD::ATOMIC_CMP_SWAP: 2491 switch (VT.SimpleTy) { 2492 default: llvm_unreachable("Unexpected value type for atomic!"); 2493 case MVT::i8: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1; break; 2494 case MVT::i16: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2; break; 2495 case MVT::i32: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4; break; 2496 case MVT::i64: LC = RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8; break; 2497 } 2498 break; 2499 case ISD::ATOMIC_LOAD_ADD: 2500 switch (VT.SimpleTy) { 2501 default: llvm_unreachable("Unexpected value type for atomic!"); 2502 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_ADD_1; break; 2503 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_ADD_2; break; 2504 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_ADD_4; break; 2505 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_ADD_8; break; 2506 } 2507 break; 2508 case ISD::ATOMIC_LOAD_SUB: 2509 switch (VT.SimpleTy) { 2510 default: llvm_unreachable("Unexpected value type for atomic!"); 2511 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_SUB_1; break; 2512 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_SUB_2; break; 2513 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_SUB_4; break; 2514 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_SUB_8; break; 2515 } 2516 break; 2517 case ISD::ATOMIC_LOAD_AND: 2518 switch (VT.SimpleTy) { 2519 default: llvm_unreachable("Unexpected value type for atomic!"); 2520 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_AND_1; break; 2521 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_AND_2; break; 2522 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_AND_4; break; 2523 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_AND_8; break; 2524 } 2525 break; 2526 case ISD::ATOMIC_LOAD_OR: 2527 switch (VT.SimpleTy) { 2528 default: llvm_unreachable("Unexpected value type for atomic!"); 2529 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_OR_1; break; 2530 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_OR_2; break; 2531 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_OR_4; break; 2532 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_OR_8; break; 2533 } 2534 break; 2535 case ISD::ATOMIC_LOAD_XOR: 2536 switch (VT.SimpleTy) { 2537 default: llvm_unreachable("Unexpected value type for atomic!"); 2538 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_XOR_1; break; 2539 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_XOR_2; break; 2540 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_XOR_4; break; 2541 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_XOR_8; break; 2542 } 2543 break; 2544 case ISD::ATOMIC_LOAD_NAND: 2545 switch (VT.SimpleTy) { 2546 default: llvm_unreachable("Unexpected value type for atomic!"); 2547 case MVT::i8: LC = RTLIB::SYNC_FETCH_AND_NAND_1; break; 2548 case MVT::i16: LC = RTLIB::SYNC_FETCH_AND_NAND_2; break; 2549 case MVT::i32: LC = RTLIB::SYNC_FETCH_AND_NAND_4; break; 2550 case MVT::i64: LC = RTLIB::SYNC_FETCH_AND_NAND_8; break; 2551 } 2552 break; 2553 } 2554 2555 return ExpandChainLibCall(LC, Node, false); 2556 } 2557 2558 void SelectionDAGLegalize::ExpandNode(SDNode *Node) { 2559 SmallVector<SDValue, 8> Results; 2560 DebugLoc dl = Node->getDebugLoc(); 2561 SDValue Tmp1, Tmp2, Tmp3, Tmp4; 2562 switch (Node->getOpcode()) { 2563 case ISD::CTPOP: 2564 case ISD::CTLZ: 2565 case ISD::CTLZ_ZERO_UNDEF: 2566 case ISD::CTTZ: 2567 case ISD::CTTZ_ZERO_UNDEF: 2568 Tmp1 = ExpandBitCount(Node->getOpcode(), Node->getOperand(0), dl); 2569 Results.push_back(Tmp1); 2570 break; 2571 case ISD::BSWAP: 2572 Results.push_back(ExpandBSWAP(Node->getOperand(0), dl)); 2573 break; 2574 case ISD::FRAMEADDR: 2575 case ISD::RETURNADDR: 2576 case ISD::FRAME_TO_ARGS_OFFSET: 2577 Results.push_back(DAG.getConstant(0, Node->getValueType(0))); 2578 break; 2579 case ISD::FLT_ROUNDS_: 2580 Results.push_back(DAG.getConstant(1, Node->getValueType(0))); 2581 break; 2582 case ISD::EH_RETURN: 2583 case ISD::EH_LABEL: 2584 case ISD::PREFETCH: 2585 case ISD::VAEND: 2586 case ISD::EH_SJLJ_LONGJMP: 2587 // If the target didn't expand these, there's nothing to do, so just 2588 // preserve the chain and be done. 2589 Results.push_back(Node->getOperand(0)); 2590 break; 2591 case ISD::EH_SJLJ_SETJMP: 2592 // If the target didn't expand this, just return 'zero' and preserve the 2593 // chain. 2594 Results.push_back(DAG.getConstant(0, MVT::i32)); 2595 Results.push_back(Node->getOperand(0)); 2596 break; 2597 case ISD::ATOMIC_FENCE: 2598 case ISD::MEMBARRIER: { 2599 // If the target didn't lower this, lower it to '__sync_synchronize()' call 2600 // FIXME: handle "fence singlethread" more efficiently. 2601 TargetLowering::ArgListTy Args; 2602 TargetLowering:: 2603 CallLoweringInfo CLI(Node->getOperand(0), 2604 Type::getVoidTy(*DAG.getContext()), 2605 false, false, false, false, 0, CallingConv::C, 2606 /*isTailCall=*/false, 2607 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2608 DAG.getExternalSymbol("__sync_synchronize", 2609 TLI.getPointerTy()), 2610 Args, DAG, dl); 2611 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 2612 2613 Results.push_back(CallResult.second); 2614 break; 2615 } 2616 case ISD::ATOMIC_LOAD: { 2617 // There is no libcall for atomic load; fake it with ATOMIC_CMP_SWAP. 2618 SDValue Zero = DAG.getConstant(0, Node->getValueType(0)); 2619 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 2620 cast<AtomicSDNode>(Node)->getMemoryVT(), 2621 Node->getOperand(0), 2622 Node->getOperand(1), Zero, Zero, 2623 cast<AtomicSDNode>(Node)->getMemOperand(), 2624 cast<AtomicSDNode>(Node)->getOrdering(), 2625 cast<AtomicSDNode>(Node)->getSynchScope()); 2626 Results.push_back(Swap.getValue(0)); 2627 Results.push_back(Swap.getValue(1)); 2628 break; 2629 } 2630 case ISD::ATOMIC_STORE: { 2631 // There is no libcall for atomic store; fake it with ATOMIC_SWAP. 2632 SDValue Swap = DAG.getAtomic(ISD::ATOMIC_SWAP, dl, 2633 cast<AtomicSDNode>(Node)->getMemoryVT(), 2634 Node->getOperand(0), 2635 Node->getOperand(1), Node->getOperand(2), 2636 cast<AtomicSDNode>(Node)->getMemOperand(), 2637 cast<AtomicSDNode>(Node)->getOrdering(), 2638 cast<AtomicSDNode>(Node)->getSynchScope()); 2639 Results.push_back(Swap.getValue(1)); 2640 break; 2641 } 2642 // By default, atomic intrinsics are marked Legal and lowered. Targets 2643 // which don't support them directly, however, may want libcalls, in which 2644 // case they mark them Expand, and we get here. 2645 case ISD::ATOMIC_SWAP: 2646 case ISD::ATOMIC_LOAD_ADD: 2647 case ISD::ATOMIC_LOAD_SUB: 2648 case ISD::ATOMIC_LOAD_AND: 2649 case ISD::ATOMIC_LOAD_OR: 2650 case ISD::ATOMIC_LOAD_XOR: 2651 case ISD::ATOMIC_LOAD_NAND: 2652 case ISD::ATOMIC_LOAD_MIN: 2653 case ISD::ATOMIC_LOAD_MAX: 2654 case ISD::ATOMIC_LOAD_UMIN: 2655 case ISD::ATOMIC_LOAD_UMAX: 2656 case ISD::ATOMIC_CMP_SWAP: { 2657 std::pair<SDValue, SDValue> Tmp = ExpandAtomic(Node); 2658 Results.push_back(Tmp.first); 2659 Results.push_back(Tmp.second); 2660 break; 2661 } 2662 case ISD::DYNAMIC_STACKALLOC: 2663 ExpandDYNAMIC_STACKALLOC(Node, Results); 2664 break; 2665 case ISD::MERGE_VALUES: 2666 for (unsigned i = 0; i < Node->getNumValues(); i++) 2667 Results.push_back(Node->getOperand(i)); 2668 break; 2669 case ISD::UNDEF: { 2670 EVT VT = Node->getValueType(0); 2671 if (VT.isInteger()) 2672 Results.push_back(DAG.getConstant(0, VT)); 2673 else { 2674 assert(VT.isFloatingPoint() && "Unknown value type!"); 2675 Results.push_back(DAG.getConstantFP(0, VT)); 2676 } 2677 break; 2678 } 2679 case ISD::TRAP: { 2680 // If this operation is not supported, lower it to 'abort()' call 2681 TargetLowering::ArgListTy Args; 2682 TargetLowering:: 2683 CallLoweringInfo CLI(Node->getOperand(0), 2684 Type::getVoidTy(*DAG.getContext()), 2685 false, false, false, false, 0, CallingConv::C, 2686 /*isTailCall=*/false, 2687 /*doesNotReturn=*/false, /*isReturnValueUsed=*/true, 2688 DAG.getExternalSymbol("abort", TLI.getPointerTy()), 2689 Args, DAG, dl); 2690 std::pair<SDValue, SDValue> CallResult = TLI.LowerCallTo(CLI); 2691 2692 Results.push_back(CallResult.second); 2693 break; 2694 } 2695 case ISD::FP_ROUND: 2696 case ISD::BITCAST: 2697 Tmp1 = EmitStackConvert(Node->getOperand(0), Node->getValueType(0), 2698 Node->getValueType(0), dl); 2699 Results.push_back(Tmp1); 2700 break; 2701 case ISD::FP_EXTEND: 2702 Tmp1 = EmitStackConvert(Node->getOperand(0), 2703 Node->getOperand(0).getValueType(), 2704 Node->getValueType(0), dl); 2705 Results.push_back(Tmp1); 2706 break; 2707 case ISD::SIGN_EXTEND_INREG: { 2708 // NOTE: we could fall back on load/store here too for targets without 2709 // SAR. However, it is doubtful that any exist. 2710 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2711 EVT VT = Node->getValueType(0); 2712 EVT ShiftAmountTy = TLI.getShiftAmountTy(VT); 2713 if (VT.isVector()) 2714 ShiftAmountTy = VT; 2715 unsigned BitsDiff = VT.getScalarType().getSizeInBits() - 2716 ExtraVT.getScalarType().getSizeInBits(); 2717 SDValue ShiftCst = DAG.getConstant(BitsDiff, ShiftAmountTy); 2718 Tmp1 = DAG.getNode(ISD::SHL, dl, Node->getValueType(0), 2719 Node->getOperand(0), ShiftCst); 2720 Tmp1 = DAG.getNode(ISD::SRA, dl, Node->getValueType(0), Tmp1, ShiftCst); 2721 Results.push_back(Tmp1); 2722 break; 2723 } 2724 case ISD::FP_ROUND_INREG: { 2725 // The only way we can lower this is to turn it into a TRUNCSTORE, 2726 // EXTLOAD pair, targeting a temporary location (a stack slot). 2727 2728 // NOTE: there is a choice here between constantly creating new stack 2729 // slots and always reusing the same one. We currently always create 2730 // new ones, as reuse may inhibit scheduling. 2731 EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT(); 2732 Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT, 2733 Node->getValueType(0), dl); 2734 Results.push_back(Tmp1); 2735 break; 2736 } 2737 case ISD::SINT_TO_FP: 2738 case ISD::UINT_TO_FP: 2739 Tmp1 = ExpandLegalINT_TO_FP(Node->getOpcode() == ISD::SINT_TO_FP, 2740 Node->getOperand(0), Node->getValueType(0), dl); 2741 Results.push_back(Tmp1); 2742 break; 2743 case ISD::FP_TO_UINT: { 2744 SDValue True, False; 2745 EVT VT = Node->getOperand(0).getValueType(); 2746 EVT NVT = Node->getValueType(0); 2747 APFloat apf(APInt::getNullValue(VT.getSizeInBits())); 2748 APInt x = APInt::getSignBit(NVT.getSizeInBits()); 2749 (void)apf.convertFromAPInt(x, false, APFloat::rmNearestTiesToEven); 2750 Tmp1 = DAG.getConstantFP(apf, VT); 2751 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), 2752 Node->getOperand(0), 2753 Tmp1, ISD::SETLT); 2754 True = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, Node->getOperand(0)); 2755 False = DAG.getNode(ISD::FP_TO_SINT, dl, NVT, 2756 DAG.getNode(ISD::FSUB, dl, VT, 2757 Node->getOperand(0), Tmp1)); 2758 False = DAG.getNode(ISD::XOR, dl, NVT, False, 2759 DAG.getConstant(x, NVT)); 2760 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, True, False); 2761 Results.push_back(Tmp1); 2762 break; 2763 } 2764 case ISD::VAARG: { 2765 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue(); 2766 EVT VT = Node->getValueType(0); 2767 Tmp1 = Node->getOperand(0); 2768 Tmp2 = Node->getOperand(1); 2769 unsigned Align = Node->getConstantOperandVal(3); 2770 2771 SDValue VAListLoad = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, 2772 MachinePointerInfo(V), 2773 false, false, false, 0); 2774 SDValue VAList = VAListLoad; 2775 2776 if (Align > TLI.getMinStackArgumentAlignment()) { 2777 assert(((Align & (Align-1)) == 0) && "Expected Align to be a power of 2"); 2778 2779 VAList = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2780 DAG.getConstant(Align - 1, 2781 TLI.getPointerTy())); 2782 2783 VAList = DAG.getNode(ISD::AND, dl, TLI.getPointerTy(), VAList, 2784 DAG.getConstant(-(int64_t)Align, 2785 TLI.getPointerTy())); 2786 } 2787 2788 // Increment the pointer, VAList, to the next vaarg 2789 Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList, 2790 DAG.getConstant(TLI.getTargetData()-> 2791 getTypeAllocSize(VT.getTypeForEVT(*DAG.getContext())), 2792 TLI.getPointerTy())); 2793 // Store the incremented VAList to the legalized pointer 2794 Tmp3 = DAG.getStore(VAListLoad.getValue(1), dl, Tmp3, Tmp2, 2795 MachinePointerInfo(V), false, false, 0); 2796 // Load the actual argument out of the pointer VAList 2797 Results.push_back(DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), 2798 false, false, false, 0)); 2799 Results.push_back(Results[0].getValue(1)); 2800 break; 2801 } 2802 case ISD::VACOPY: { 2803 // This defaults to loading a pointer from the input and storing it to the 2804 // output, returning the chain. 2805 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue(); 2806 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue(); 2807 Tmp1 = DAG.getLoad(TLI.getPointerTy(), dl, Node->getOperand(0), 2808 Node->getOperand(2), MachinePointerInfo(VS), 2809 false, false, false, 0); 2810 Tmp1 = DAG.getStore(Tmp1.getValue(1), dl, Tmp1, Node->getOperand(1), 2811 MachinePointerInfo(VD), false, false, 0); 2812 Results.push_back(Tmp1); 2813 break; 2814 } 2815 case ISD::EXTRACT_VECTOR_ELT: 2816 if (Node->getOperand(0).getValueType().getVectorNumElements() == 1) 2817 // This must be an access of the only element. Return it. 2818 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), 2819 Node->getOperand(0)); 2820 else 2821 Tmp1 = ExpandExtractFromVectorThroughStack(SDValue(Node, 0)); 2822 Results.push_back(Tmp1); 2823 break; 2824 case ISD::EXTRACT_SUBVECTOR: 2825 Results.push_back(ExpandExtractFromVectorThroughStack(SDValue(Node, 0))); 2826 break; 2827 case ISD::INSERT_SUBVECTOR: 2828 Results.push_back(ExpandInsertToVectorThroughStack(SDValue(Node, 0))); 2829 break; 2830 case ISD::CONCAT_VECTORS: { 2831 Results.push_back(ExpandVectorBuildThroughStack(Node)); 2832 break; 2833 } 2834 case ISD::SCALAR_TO_VECTOR: 2835 Results.push_back(ExpandSCALAR_TO_VECTOR(Node)); 2836 break; 2837 case ISD::INSERT_VECTOR_ELT: 2838 Results.push_back(ExpandINSERT_VECTOR_ELT(Node->getOperand(0), 2839 Node->getOperand(1), 2840 Node->getOperand(2), dl)); 2841 break; 2842 case ISD::VECTOR_SHUFFLE: { 2843 SmallVector<int, 32> NewMask; 2844 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 2845 2846 EVT VT = Node->getValueType(0); 2847 EVT EltVT = VT.getVectorElementType(); 2848 SDValue Op0 = Node->getOperand(0); 2849 SDValue Op1 = Node->getOperand(1); 2850 if (!TLI.isTypeLegal(EltVT)) { 2851 2852 EVT NewEltVT = TLI.getTypeToTransformTo(*DAG.getContext(), EltVT); 2853 2854 // BUILD_VECTOR operands are allowed to be wider than the element type. 2855 // But if NewEltVT is smaller that EltVT the BUILD_VECTOR does not accept it 2856 if (NewEltVT.bitsLT(EltVT)) { 2857 2858 // Convert shuffle node. 2859 // If original node was v4i64 and the new EltVT is i32, 2860 // cast operands to v8i32 and re-build the mask. 2861 2862 // Calculate new VT, the size of the new VT should be equal to original. 2863 EVT NewVT = EVT::getVectorVT(*DAG.getContext(), NewEltVT, 2864 VT.getSizeInBits()/NewEltVT.getSizeInBits()); 2865 assert(NewVT.bitsEq(VT)); 2866 2867 // cast operands to new VT 2868 Op0 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op0); 2869 Op1 = DAG.getNode(ISD::BITCAST, dl, NewVT, Op1); 2870 2871 // Convert the shuffle mask 2872 unsigned int factor = NewVT.getVectorNumElements()/VT.getVectorNumElements(); 2873 2874 // EltVT gets smaller 2875 assert(factor > 0); 2876 2877 for (unsigned i = 0; i < VT.getVectorNumElements(); ++i) { 2878 if (Mask[i] < 0) { 2879 for (unsigned fi = 0; fi < factor; ++fi) 2880 NewMask.push_back(Mask[i]); 2881 } 2882 else { 2883 for (unsigned fi = 0; fi < factor; ++fi) 2884 NewMask.push_back(Mask[i]*factor+fi); 2885 } 2886 } 2887 Mask = NewMask; 2888 VT = NewVT; 2889 } 2890 EltVT = NewEltVT; 2891 } 2892 unsigned NumElems = VT.getVectorNumElements(); 2893 SmallVector<SDValue, 16> Ops; 2894 for (unsigned i = 0; i != NumElems; ++i) { 2895 if (Mask[i] < 0) { 2896 Ops.push_back(DAG.getUNDEF(EltVT)); 2897 continue; 2898 } 2899 unsigned Idx = Mask[i]; 2900 if (Idx < NumElems) 2901 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2902 Op0, 2903 DAG.getIntPtrConstant(Idx))); 2904 else 2905 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, 2906 Op1, 2907 DAG.getIntPtrConstant(Idx - NumElems))); 2908 } 2909 2910 Tmp1 = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &Ops[0], Ops.size()); 2911 // We may have changed the BUILD_VECTOR type. Cast it back to the Node type. 2912 Tmp1 = DAG.getNode(ISD::BITCAST, dl, Node->getValueType(0), Tmp1); 2913 Results.push_back(Tmp1); 2914 break; 2915 } 2916 case ISD::EXTRACT_ELEMENT: { 2917 EVT OpTy = Node->getOperand(0).getValueType(); 2918 if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) { 2919 // 1 -> Hi 2920 Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0), 2921 DAG.getConstant(OpTy.getSizeInBits()/2, 2922 TLI.getShiftAmountTy(Node->getOperand(0).getValueType()))); 2923 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), Tmp1); 2924 } else { 2925 // 0 -> Lo 2926 Tmp1 = DAG.getNode(ISD::TRUNCATE, dl, Node->getValueType(0), 2927 Node->getOperand(0)); 2928 } 2929 Results.push_back(Tmp1); 2930 break; 2931 } 2932 case ISD::STACKSAVE: 2933 // Expand to CopyFromReg if the target set 2934 // StackPointerRegisterToSaveRestore. 2935 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2936 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, SP, 2937 Node->getValueType(0))); 2938 Results.push_back(Results[0].getValue(1)); 2939 } else { 2940 Results.push_back(DAG.getUNDEF(Node->getValueType(0))); 2941 Results.push_back(Node->getOperand(0)); 2942 } 2943 break; 2944 case ISD::STACKRESTORE: 2945 // Expand to CopyToReg if the target set 2946 // StackPointerRegisterToSaveRestore. 2947 if (unsigned SP = TLI.getStackPointerRegisterToSaveRestore()) { 2948 Results.push_back(DAG.getCopyToReg(Node->getOperand(0), dl, SP, 2949 Node->getOperand(1))); 2950 } else { 2951 Results.push_back(Node->getOperand(0)); 2952 } 2953 break; 2954 case ISD::FCOPYSIGN: 2955 Results.push_back(ExpandFCOPYSIGN(Node)); 2956 break; 2957 case ISD::FNEG: 2958 // Expand Y = FNEG(X) -> Y = SUB -0.0, X 2959 Tmp1 = DAG.getConstantFP(-0.0, Node->getValueType(0)); 2960 Tmp1 = DAG.getNode(ISD::FSUB, dl, Node->getValueType(0), Tmp1, 2961 Node->getOperand(0)); 2962 Results.push_back(Tmp1); 2963 break; 2964 case ISD::FABS: { 2965 // Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X). 2966 EVT VT = Node->getValueType(0); 2967 Tmp1 = Node->getOperand(0); 2968 Tmp2 = DAG.getConstantFP(0.0, VT); 2969 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()), 2970 Tmp1, Tmp2, ISD::SETUGT); 2971 Tmp3 = DAG.getNode(ISD::FNEG, dl, VT, Tmp1); 2972 Tmp1 = DAG.getNode(ISD::SELECT, dl, VT, Tmp2, Tmp1, Tmp3); 2973 Results.push_back(Tmp1); 2974 break; 2975 } 2976 case ISD::FSQRT: 2977 Results.push_back(ExpandFPLibCall(Node, RTLIB::SQRT_F32, RTLIB::SQRT_F64, 2978 RTLIB::SQRT_F80, RTLIB::SQRT_PPCF128)); 2979 break; 2980 case ISD::FSIN: 2981 Results.push_back(ExpandFPLibCall(Node, RTLIB::SIN_F32, RTLIB::SIN_F64, 2982 RTLIB::SIN_F80, RTLIB::SIN_PPCF128)); 2983 break; 2984 case ISD::FCOS: 2985 Results.push_back(ExpandFPLibCall(Node, RTLIB::COS_F32, RTLIB::COS_F64, 2986 RTLIB::COS_F80, RTLIB::COS_PPCF128)); 2987 break; 2988 case ISD::FLOG: 2989 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG_F32, RTLIB::LOG_F64, 2990 RTLIB::LOG_F80, RTLIB::LOG_PPCF128)); 2991 break; 2992 case ISD::FLOG2: 2993 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG2_F32, RTLIB::LOG2_F64, 2994 RTLIB::LOG2_F80, RTLIB::LOG2_PPCF128)); 2995 break; 2996 case ISD::FLOG10: 2997 Results.push_back(ExpandFPLibCall(Node, RTLIB::LOG10_F32, RTLIB::LOG10_F64, 2998 RTLIB::LOG10_F80, RTLIB::LOG10_PPCF128)); 2999 break; 3000 case ISD::FEXP: 3001 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP_F32, RTLIB::EXP_F64, 3002 RTLIB::EXP_F80, RTLIB::EXP_PPCF128)); 3003 break; 3004 case ISD::FEXP2: 3005 Results.push_back(ExpandFPLibCall(Node, RTLIB::EXP2_F32, RTLIB::EXP2_F64, 3006 RTLIB::EXP2_F80, RTLIB::EXP2_PPCF128)); 3007 break; 3008 case ISD::FTRUNC: 3009 Results.push_back(ExpandFPLibCall(Node, RTLIB::TRUNC_F32, RTLIB::TRUNC_F64, 3010 RTLIB::TRUNC_F80, RTLIB::TRUNC_PPCF128)); 3011 break; 3012 case ISD::FFLOOR: 3013 Results.push_back(ExpandFPLibCall(Node, RTLIB::FLOOR_F32, RTLIB::FLOOR_F64, 3014 RTLIB::FLOOR_F80, RTLIB::FLOOR_PPCF128)); 3015 break; 3016 case ISD::FCEIL: 3017 Results.push_back(ExpandFPLibCall(Node, RTLIB::CEIL_F32, RTLIB::CEIL_F64, 3018 RTLIB::CEIL_F80, RTLIB::CEIL_PPCF128)); 3019 break; 3020 case ISD::FRINT: 3021 Results.push_back(ExpandFPLibCall(Node, RTLIB::RINT_F32, RTLIB::RINT_F64, 3022 RTLIB::RINT_F80, RTLIB::RINT_PPCF128)); 3023 break; 3024 case ISD::FNEARBYINT: 3025 Results.push_back(ExpandFPLibCall(Node, RTLIB::NEARBYINT_F32, 3026 RTLIB::NEARBYINT_F64, 3027 RTLIB::NEARBYINT_F80, 3028 RTLIB::NEARBYINT_PPCF128)); 3029 break; 3030 case ISD::FPOWI: 3031 Results.push_back(ExpandFPLibCall(Node, RTLIB::POWI_F32, RTLIB::POWI_F64, 3032 RTLIB::POWI_F80, RTLIB::POWI_PPCF128)); 3033 break; 3034 case ISD::FPOW: 3035 Results.push_back(ExpandFPLibCall(Node, RTLIB::POW_F32, RTLIB::POW_F64, 3036 RTLIB::POW_F80, RTLIB::POW_PPCF128)); 3037 break; 3038 case ISD::FDIV: 3039 Results.push_back(ExpandFPLibCall(Node, RTLIB::DIV_F32, RTLIB::DIV_F64, 3040 RTLIB::DIV_F80, RTLIB::DIV_PPCF128)); 3041 break; 3042 case ISD::FREM: 3043 Results.push_back(ExpandFPLibCall(Node, RTLIB::REM_F32, RTLIB::REM_F64, 3044 RTLIB::REM_F80, RTLIB::REM_PPCF128)); 3045 break; 3046 case ISD::FMA: 3047 Results.push_back(ExpandFPLibCall(Node, RTLIB::FMA_F32, RTLIB::FMA_F64, 3048 RTLIB::FMA_F80, RTLIB::FMA_PPCF128)); 3049 break; 3050 case ISD::FP16_TO_FP32: 3051 Results.push_back(ExpandLibCall(RTLIB::FPEXT_F16_F32, Node, false)); 3052 break; 3053 case ISD::FP32_TO_FP16: 3054 Results.push_back(ExpandLibCall(RTLIB::FPROUND_F32_F16, Node, false)); 3055 break; 3056 case ISD::ConstantFP: { 3057 ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Node); 3058 // Check to see if this FP immediate is already legal. 3059 // If this is a legal constant, turn it into a TargetConstantFP node. 3060 if (!TLI.isFPImmLegal(CFP->getValueAPF(), Node->getValueType(0))) 3061 Results.push_back(ExpandConstantFP(CFP, true)); 3062 break; 3063 } 3064 case ISD::EHSELECTION: { 3065 unsigned Reg = TLI.getExceptionSelectorRegister(); 3066 assert(Reg && "Can't expand to unknown register!"); 3067 Results.push_back(DAG.getCopyFromReg(Node->getOperand(1), dl, Reg, 3068 Node->getValueType(0))); 3069 Results.push_back(Results[0].getValue(1)); 3070 break; 3071 } 3072 case ISD::EXCEPTIONADDR: { 3073 unsigned Reg = TLI.getExceptionPointerRegister(); 3074 assert(Reg && "Can't expand to unknown register!"); 3075 Results.push_back(DAG.getCopyFromReg(Node->getOperand(0), dl, Reg, 3076 Node->getValueType(0))); 3077 Results.push_back(Results[0].getValue(1)); 3078 break; 3079 } 3080 case ISD::FSUB: { 3081 EVT VT = Node->getValueType(0); 3082 assert(TLI.isOperationLegalOrCustom(ISD::FADD, VT) && 3083 TLI.isOperationLegalOrCustom(ISD::FNEG, VT) && 3084 "Don't know how to expand this FP subtraction!"); 3085 Tmp1 = DAG.getNode(ISD::FNEG, dl, VT, Node->getOperand(1)); 3086 Tmp1 = DAG.getNode(ISD::FADD, dl, VT, Node->getOperand(0), Tmp1); 3087 Results.push_back(Tmp1); 3088 break; 3089 } 3090 case ISD::SUB: { 3091 EVT VT = Node->getValueType(0); 3092 assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) && 3093 TLI.isOperationLegalOrCustom(ISD::XOR, VT) && 3094 "Don't know how to expand this subtraction!"); 3095 Tmp1 = DAG.getNode(ISD::XOR, dl, VT, Node->getOperand(1), 3096 DAG.getConstant(APInt::getAllOnesValue(VT.getSizeInBits()), VT)); 3097 Tmp1 = DAG.getNode(ISD::ADD, dl, VT, Tmp1, DAG.getConstant(1, VT)); 3098 Results.push_back(DAG.getNode(ISD::ADD, dl, VT, Node->getOperand(0), Tmp1)); 3099 break; 3100 } 3101 case ISD::UREM: 3102 case ISD::SREM: { 3103 EVT VT = Node->getValueType(0); 3104 SDVTList VTs = DAG.getVTList(VT, VT); 3105 bool isSigned = Node->getOpcode() == ISD::SREM; 3106 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; 3107 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3108 Tmp2 = Node->getOperand(0); 3109 Tmp3 = Node->getOperand(1); 3110 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3111 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3112 useDivRem(Node, isSigned, false))) { 3113 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Tmp2, Tmp3).getValue(1); 3114 } else if (TLI.isOperationLegalOrCustom(DivOpc, VT)) { 3115 // X % Y -> X-X/Y*Y 3116 Tmp1 = DAG.getNode(DivOpc, dl, VT, Tmp2, Tmp3); 3117 Tmp1 = DAG.getNode(ISD::MUL, dl, VT, Tmp1, Tmp3); 3118 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, Tmp2, Tmp1); 3119 } else if (isSigned) 3120 Tmp1 = ExpandIntLibCall(Node, true, 3121 RTLIB::SREM_I8, 3122 RTLIB::SREM_I16, RTLIB::SREM_I32, 3123 RTLIB::SREM_I64, RTLIB::SREM_I128); 3124 else 3125 Tmp1 = ExpandIntLibCall(Node, false, 3126 RTLIB::UREM_I8, 3127 RTLIB::UREM_I16, RTLIB::UREM_I32, 3128 RTLIB::UREM_I64, RTLIB::UREM_I128); 3129 Results.push_back(Tmp1); 3130 break; 3131 } 3132 case ISD::UDIV: 3133 case ISD::SDIV: { 3134 bool isSigned = Node->getOpcode() == ISD::SDIV; 3135 unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM; 3136 EVT VT = Node->getValueType(0); 3137 SDVTList VTs = DAG.getVTList(VT, VT); 3138 if (TLI.isOperationLegalOrCustom(DivRemOpc, VT) || 3139 (isDivRemLibcallAvailable(Node, isSigned, TLI) && 3140 useDivRem(Node, isSigned, true))) 3141 Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0), 3142 Node->getOperand(1)); 3143 else if (isSigned) 3144 Tmp1 = ExpandIntLibCall(Node, true, 3145 RTLIB::SDIV_I8, 3146 RTLIB::SDIV_I16, RTLIB::SDIV_I32, 3147 RTLIB::SDIV_I64, RTLIB::SDIV_I128); 3148 else 3149 Tmp1 = ExpandIntLibCall(Node, false, 3150 RTLIB::UDIV_I8, 3151 RTLIB::UDIV_I16, RTLIB::UDIV_I32, 3152 RTLIB::UDIV_I64, RTLIB::UDIV_I128); 3153 Results.push_back(Tmp1); 3154 break; 3155 } 3156 case ISD::MULHU: 3157 case ISD::MULHS: { 3158 unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI : 3159 ISD::SMUL_LOHI; 3160 EVT VT = Node->getValueType(0); 3161 SDVTList VTs = DAG.getVTList(VT, VT); 3162 assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) && 3163 "If this wasn't legal, it shouldn't have been created!"); 3164 Tmp1 = DAG.getNode(ExpandOpcode, dl, VTs, Node->getOperand(0), 3165 Node->getOperand(1)); 3166 Results.push_back(Tmp1.getValue(1)); 3167 break; 3168 } 3169 case ISD::SDIVREM: 3170 case ISD::UDIVREM: 3171 // Expand into divrem libcall 3172 ExpandDivRemLibCall(Node, Results); 3173 break; 3174 case ISD::MUL: { 3175 EVT VT = Node->getValueType(0); 3176 SDVTList VTs = DAG.getVTList(VT, VT); 3177 // See if multiply or divide can be lowered using two-result operations. 3178 // We just need the low half of the multiply; try both the signed 3179 // and unsigned forms. If the target supports both SMUL_LOHI and 3180 // UMUL_LOHI, form a preference by checking which forms of plain 3181 // MULH it supports. 3182 bool HasSMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::SMUL_LOHI, VT); 3183 bool HasUMUL_LOHI = TLI.isOperationLegalOrCustom(ISD::UMUL_LOHI, VT); 3184 bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, VT); 3185 bool HasMULHU = TLI.isOperationLegalOrCustom(ISD::MULHU, VT); 3186 unsigned OpToUse = 0; 3187 if (HasSMUL_LOHI && !HasMULHS) { 3188 OpToUse = ISD::SMUL_LOHI; 3189 } else if (HasUMUL_LOHI && !HasMULHU) { 3190 OpToUse = ISD::UMUL_LOHI; 3191 } else if (HasSMUL_LOHI) { 3192 OpToUse = ISD::SMUL_LOHI; 3193 } else if (HasUMUL_LOHI) { 3194 OpToUse = ISD::UMUL_LOHI; 3195 } 3196 if (OpToUse) { 3197 Results.push_back(DAG.getNode(OpToUse, dl, VTs, Node->getOperand(0), 3198 Node->getOperand(1))); 3199 break; 3200 } 3201 Tmp1 = ExpandIntLibCall(Node, false, 3202 RTLIB::MUL_I8, 3203 RTLIB::MUL_I16, RTLIB::MUL_I32, 3204 RTLIB::MUL_I64, RTLIB::MUL_I128); 3205 Results.push_back(Tmp1); 3206 break; 3207 } 3208 case ISD::SADDO: 3209 case ISD::SSUBO: { 3210 SDValue LHS = Node->getOperand(0); 3211 SDValue RHS = Node->getOperand(1); 3212 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::SADDO ? 3213 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3214 LHS, RHS); 3215 Results.push_back(Sum); 3216 EVT OType = Node->getValueType(1); 3217 3218 SDValue Zero = DAG.getConstant(0, LHS.getValueType()); 3219 3220 // LHSSign -> LHS >= 0 3221 // RHSSign -> RHS >= 0 3222 // SumSign -> Sum >= 0 3223 // 3224 // Add: 3225 // Overflow -> (LHSSign == RHSSign) && (LHSSign != SumSign) 3226 // Sub: 3227 // Overflow -> (LHSSign != RHSSign) && (LHSSign != SumSign) 3228 // 3229 SDValue LHSSign = DAG.getSetCC(dl, OType, LHS, Zero, ISD::SETGE); 3230 SDValue RHSSign = DAG.getSetCC(dl, OType, RHS, Zero, ISD::SETGE); 3231 SDValue SignsMatch = DAG.getSetCC(dl, OType, LHSSign, RHSSign, 3232 Node->getOpcode() == ISD::SADDO ? 3233 ISD::SETEQ : ISD::SETNE); 3234 3235 SDValue SumSign = DAG.getSetCC(dl, OType, Sum, Zero, ISD::SETGE); 3236 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); 3237 3238 SDValue Cmp = DAG.getNode(ISD::AND, dl, OType, SignsMatch, SumSignNE); 3239 Results.push_back(Cmp); 3240 break; 3241 } 3242 case ISD::UADDO: 3243 case ISD::USUBO: { 3244 SDValue LHS = Node->getOperand(0); 3245 SDValue RHS = Node->getOperand(1); 3246 SDValue Sum = DAG.getNode(Node->getOpcode() == ISD::UADDO ? 3247 ISD::ADD : ISD::SUB, dl, LHS.getValueType(), 3248 LHS, RHS); 3249 Results.push_back(Sum); 3250 Results.push_back(DAG.getSetCC(dl, Node->getValueType(1), Sum, LHS, 3251 Node->getOpcode () == ISD::UADDO ? 3252 ISD::SETULT : ISD::SETUGT)); 3253 break; 3254 } 3255 case ISD::UMULO: 3256 case ISD::SMULO: { 3257 EVT VT = Node->getValueType(0); 3258 EVT WideVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits() * 2); 3259 SDValue LHS = Node->getOperand(0); 3260 SDValue RHS = Node->getOperand(1); 3261 SDValue BottomHalf; 3262 SDValue TopHalf; 3263 static const unsigned Ops[2][3] = 3264 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, 3265 { ISD::MULHS, ISD::SMUL_LOHI, ISD::SIGN_EXTEND }}; 3266 bool isSigned = Node->getOpcode() == ISD::SMULO; 3267 if (TLI.isOperationLegalOrCustom(Ops[isSigned][0], VT)) { 3268 BottomHalf = DAG.getNode(ISD::MUL, dl, VT, LHS, RHS); 3269 TopHalf = DAG.getNode(Ops[isSigned][0], dl, VT, LHS, RHS); 3270 } else if (TLI.isOperationLegalOrCustom(Ops[isSigned][1], VT)) { 3271 BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS, 3272 RHS); 3273 TopHalf = BottomHalf.getValue(1); 3274 } else if (TLI.isTypeLegal(EVT::getIntegerVT(*DAG.getContext(), 3275 VT.getSizeInBits() * 2))) { 3276 LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS); 3277 RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS); 3278 Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS); 3279 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3280 DAG.getIntPtrConstant(0)); 3281 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Tmp1, 3282 DAG.getIntPtrConstant(1)); 3283 } else { 3284 // We can fall back to a libcall with an illegal type for the MUL if we 3285 // have a libcall big enough. 3286 // Also, we can fall back to a division in some cases, but that's a big 3287 // performance hit in the general case. 3288 RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL; 3289 if (WideVT == MVT::i16) 3290 LC = RTLIB::MUL_I16; 3291 else if (WideVT == MVT::i32) 3292 LC = RTLIB::MUL_I32; 3293 else if (WideVT == MVT::i64) 3294 LC = RTLIB::MUL_I64; 3295 else if (WideVT == MVT::i128) 3296 LC = RTLIB::MUL_I128; 3297 assert(LC != RTLIB::UNKNOWN_LIBCALL && "Cannot expand this operation!"); 3298 3299 // The high part is obtained by SRA'ing all but one of the bits of low 3300 // part. 3301 unsigned LoSize = VT.getSizeInBits(); 3302 SDValue HiLHS = DAG.getNode(ISD::SRA, dl, VT, RHS, 3303 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3304 SDValue HiRHS = DAG.getNode(ISD::SRA, dl, VT, LHS, 3305 DAG.getConstant(LoSize-1, TLI.getPointerTy())); 3306 3307 // Here we're passing the 2 arguments explicitly as 4 arguments that are 3308 // pre-lowered to the correct types. This all depends upon WideVT not 3309 // being a legal type for the architecture and thus has to be split to 3310 // two arguments. 3311 SDValue Args[] = { LHS, HiLHS, RHS, HiRHS }; 3312 SDValue Ret = ExpandLibCall(LC, WideVT, Args, 4, isSigned, dl); 3313 BottomHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3314 DAG.getIntPtrConstant(0)); 3315 TopHalf = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, VT, Ret, 3316 DAG.getIntPtrConstant(1)); 3317 // Ret is a node with an illegal type. Because such things are not 3318 // generally permitted during this phase of legalization, delete the 3319 // node. The above EXTRACT_ELEMENT nodes should have been folded. 3320 DAG.DeleteNode(Ret.getNode()); 3321 } 3322 3323 if (isSigned) { 3324 Tmp1 = DAG.getConstant(VT.getSizeInBits() - 1, 3325 TLI.getShiftAmountTy(BottomHalf.getValueType())); 3326 Tmp1 = DAG.getNode(ISD::SRA, dl, VT, BottomHalf, Tmp1); 3327 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, Tmp1, 3328 ISD::SETNE); 3329 } else { 3330 TopHalf = DAG.getSetCC(dl, TLI.getSetCCResultType(VT), TopHalf, 3331 DAG.getConstant(0, VT), ISD::SETNE); 3332 } 3333 Results.push_back(BottomHalf); 3334 Results.push_back(TopHalf); 3335 break; 3336 } 3337 case ISD::BUILD_PAIR: { 3338 EVT PairTy = Node->getValueType(0); 3339 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); 3340 Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1)); 3341 Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2, 3342 DAG.getConstant(PairTy.getSizeInBits()/2, 3343 TLI.getShiftAmountTy(PairTy))); 3344 Results.push_back(DAG.getNode(ISD::OR, dl, PairTy, Tmp1, Tmp2)); 3345 break; 3346 } 3347 case ISD::SELECT: 3348 Tmp1 = Node->getOperand(0); 3349 Tmp2 = Node->getOperand(1); 3350 Tmp3 = Node->getOperand(2); 3351 if (Tmp1.getOpcode() == ISD::SETCC) { 3352 Tmp1 = DAG.getSelectCC(dl, Tmp1.getOperand(0), Tmp1.getOperand(1), 3353 Tmp2, Tmp3, 3354 cast<CondCodeSDNode>(Tmp1.getOperand(2))->get()); 3355 } else { 3356 Tmp1 = DAG.getSelectCC(dl, Tmp1, 3357 DAG.getConstant(0, Tmp1.getValueType()), 3358 Tmp2, Tmp3, ISD::SETNE); 3359 } 3360 Results.push_back(Tmp1); 3361 break; 3362 case ISD::BR_JT: { 3363 SDValue Chain = Node->getOperand(0); 3364 SDValue Table = Node->getOperand(1); 3365 SDValue Index = Node->getOperand(2); 3366 3367 EVT PTy = TLI.getPointerTy(); 3368 3369 const TargetData &TD = *TLI.getTargetData(); 3370 unsigned EntrySize = 3371 DAG.getMachineFunction().getJumpTableInfo()->getEntrySize(TD); 3372 3373 Index = DAG.getNode(ISD::MUL, dl, PTy, 3374 Index, DAG.getConstant(EntrySize, PTy)); 3375 SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table); 3376 3377 EVT MemVT = EVT::getIntegerVT(*DAG.getContext(), EntrySize * 8); 3378 SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr, 3379 MachinePointerInfo::getJumpTable(), MemVT, 3380 false, false, 0); 3381 Addr = LD; 3382 if (TM.getRelocationModel() == Reloc::PIC_) { 3383 // For PIC, the sequence is: 3384 // BRIND(load(Jumptable + index) + RelocBase) 3385 // RelocBase can be JumpTable, GOT or some sort of global base. 3386 Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr, 3387 TLI.getPICJumpTableRelocBase(Table, DAG)); 3388 } 3389 Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr); 3390 Results.push_back(Tmp1); 3391 break; 3392 } 3393 case ISD::BRCOND: 3394 // Expand brcond's setcc into its constituent parts and create a BR_CC 3395 // Node. 3396 Tmp1 = Node->getOperand(0); 3397 Tmp2 = Node->getOperand(1); 3398 if (Tmp2.getOpcode() == ISD::SETCC) { 3399 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, 3400 Tmp1, Tmp2.getOperand(2), 3401 Tmp2.getOperand(0), Tmp2.getOperand(1), 3402 Node->getOperand(2)); 3403 } else { 3404 // We test only the i1 bit. Skip the AND if UNDEF. 3405 Tmp3 = (Tmp2.getOpcode() == ISD::UNDEF) ? Tmp2 : 3406 DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2, 3407 DAG.getConstant(1, Tmp2.getValueType())); 3408 Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1, 3409 DAG.getCondCode(ISD::SETNE), Tmp3, 3410 DAG.getConstant(0, Tmp3.getValueType()), 3411 Node->getOperand(2)); 3412 } 3413 Results.push_back(Tmp1); 3414 break; 3415 case ISD::SETCC: { 3416 Tmp1 = Node->getOperand(0); 3417 Tmp2 = Node->getOperand(1); 3418 Tmp3 = Node->getOperand(2); 3419 LegalizeSetCCCondCode(Node->getValueType(0), Tmp1, Tmp2, Tmp3, dl); 3420 3421 // If we expanded the SETCC into an AND/OR, return the new node 3422 if (Tmp2.getNode() == 0) { 3423 Results.push_back(Tmp1); 3424 break; 3425 } 3426 3427 // Otherwise, SETCC for the given comparison type must be completely 3428 // illegal; expand it into a SELECT_CC. 3429 EVT VT = Node->getValueType(0); 3430 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2, 3431 DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3); 3432 Results.push_back(Tmp1); 3433 break; 3434 } 3435 case ISD::SELECT_CC: { 3436 Tmp1 = Node->getOperand(0); // LHS 3437 Tmp2 = Node->getOperand(1); // RHS 3438 Tmp3 = Node->getOperand(2); // True 3439 Tmp4 = Node->getOperand(3); // False 3440 SDValue CC = Node->getOperand(4); 3441 3442 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp1.getValueType()), 3443 Tmp1, Tmp2, CC, dl); 3444 3445 assert(!Tmp2.getNode() && "Can't legalize SELECT_CC with legal condition!"); 3446 Tmp2 = DAG.getConstant(0, Tmp1.getValueType()); 3447 CC = DAG.getCondCode(ISD::SETNE); 3448 Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, Node->getValueType(0), Tmp1, Tmp2, 3449 Tmp3, Tmp4, CC); 3450 Results.push_back(Tmp1); 3451 break; 3452 } 3453 case ISD::BR_CC: { 3454 Tmp1 = Node->getOperand(0); // Chain 3455 Tmp2 = Node->getOperand(2); // LHS 3456 Tmp3 = Node->getOperand(3); // RHS 3457 Tmp4 = Node->getOperand(1); // CC 3458 3459 LegalizeSetCCCondCode(TLI.getSetCCResultType(Tmp2.getValueType()), 3460 Tmp2, Tmp3, Tmp4, dl); 3461 3462 assert(!Tmp3.getNode() && "Can't legalize BR_CC with legal condition!"); 3463 Tmp3 = DAG.getConstant(0, Tmp2.getValueType()); 3464 Tmp4 = DAG.getCondCode(ISD::SETNE); 3465 Tmp1 = DAG.getNode(ISD::BR_CC, dl, Node->getValueType(0), Tmp1, Tmp4, Tmp2, 3466 Tmp3, Node->getOperand(4)); 3467 Results.push_back(Tmp1); 3468 break; 3469 } 3470 case ISD::BUILD_VECTOR: 3471 Results.push_back(ExpandBUILD_VECTOR(Node)); 3472 break; 3473 case ISD::SRA: 3474 case ISD::SRL: 3475 case ISD::SHL: { 3476 // Scalarize vector SRA/SRL/SHL. 3477 EVT VT = Node->getValueType(0); 3478 assert(VT.isVector() && "Unable to legalize non-vector shift"); 3479 assert(TLI.isTypeLegal(VT.getScalarType())&& "Element type must be legal"); 3480 unsigned NumElem = VT.getVectorNumElements(); 3481 3482 SmallVector<SDValue, 8> Scalars; 3483 for (unsigned Idx = 0; Idx < NumElem; Idx++) { 3484 SDValue Ex = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3485 VT.getScalarType(), 3486 Node->getOperand(0), DAG.getIntPtrConstant(Idx)); 3487 SDValue Sh = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, 3488 VT.getScalarType(), 3489 Node->getOperand(1), DAG.getIntPtrConstant(Idx)); 3490 Scalars.push_back(DAG.getNode(Node->getOpcode(), dl, 3491 VT.getScalarType(), Ex, Sh)); 3492 } 3493 SDValue Result = 3494 DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), 3495 &Scalars[0], Scalars.size()); 3496 ReplaceNode(SDValue(Node, 0), Result); 3497 break; 3498 } 3499 case ISD::GLOBAL_OFFSET_TABLE: 3500 case ISD::GlobalAddress: 3501 case ISD::GlobalTLSAddress: 3502 case ISD::ExternalSymbol: 3503 case ISD::ConstantPool: 3504 case ISD::JumpTable: 3505 case ISD::INTRINSIC_W_CHAIN: 3506 case ISD::INTRINSIC_WO_CHAIN: 3507 case ISD::INTRINSIC_VOID: 3508 // FIXME: Custom lowering for these operations shouldn't return null! 3509 break; 3510 } 3511 3512 // Replace the original node with the legalized result. 3513 if (!Results.empty()) 3514 ReplaceNode(Node, Results.data()); 3515 } 3516 3517 void SelectionDAGLegalize::PromoteNode(SDNode *Node) { 3518 SmallVector<SDValue, 8> Results; 3519 EVT OVT = Node->getValueType(0); 3520 if (Node->getOpcode() == ISD::UINT_TO_FP || 3521 Node->getOpcode() == ISD::SINT_TO_FP || 3522 Node->getOpcode() == ISD::SETCC) { 3523 OVT = Node->getOperand(0).getValueType(); 3524 } 3525 EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT); 3526 DebugLoc dl = Node->getDebugLoc(); 3527 SDValue Tmp1, Tmp2, Tmp3; 3528 switch (Node->getOpcode()) { 3529 case ISD::CTTZ: 3530 case ISD::CTTZ_ZERO_UNDEF: 3531 case ISD::CTLZ: 3532 case ISD::CTLZ_ZERO_UNDEF: 3533 case ISD::CTPOP: 3534 // Zero extend the argument. 3535 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3536 // Perform the larger operation. For CTPOP and CTTZ_ZERO_UNDEF, this is 3537 // already the correct result. 3538 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3539 if (Node->getOpcode() == ISD::CTTZ) { 3540 // FIXME: This should set a bit in the zero extended value instead. 3541 Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), 3542 Tmp1, DAG.getConstant(NVT.getSizeInBits(), NVT), 3543 ISD::SETEQ); 3544 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp2, 3545 DAG.getConstant(OVT.getSizeInBits(), NVT), Tmp1); 3546 } else if (Node->getOpcode() == ISD::CTLZ || 3547 Node->getOpcode() == ISD::CTLZ_ZERO_UNDEF) { 3548 // Tmp1 = Tmp1 - (sizeinbits(NVT) - sizeinbits(Old VT)) 3549 Tmp1 = DAG.getNode(ISD::SUB, dl, NVT, Tmp1, 3550 DAG.getConstant(NVT.getSizeInBits() - 3551 OVT.getSizeInBits(), NVT)); 3552 } 3553 Results.push_back(DAG.getNode(ISD::TRUNCATE, dl, OVT, Tmp1)); 3554 break; 3555 case ISD::BSWAP: { 3556 unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits(); 3557 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); 3558 Tmp1 = DAG.getNode(ISD::BSWAP, dl, NVT, Tmp1); 3559 Tmp1 = DAG.getNode(ISD::SRL, dl, NVT, Tmp1, 3560 DAG.getConstant(DiffBits, TLI.getShiftAmountTy(NVT))); 3561 Results.push_back(Tmp1); 3562 break; 3563 } 3564 case ISD::FP_TO_UINT: 3565 case ISD::FP_TO_SINT: 3566 Tmp1 = PromoteLegalFP_TO_INT(Node->getOperand(0), Node->getValueType(0), 3567 Node->getOpcode() == ISD::FP_TO_SINT, dl); 3568 Results.push_back(Tmp1); 3569 break; 3570 case ISD::UINT_TO_FP: 3571 case ISD::SINT_TO_FP: 3572 Tmp1 = PromoteLegalINT_TO_FP(Node->getOperand(0), Node->getValueType(0), 3573 Node->getOpcode() == ISD::SINT_TO_FP, dl); 3574 Results.push_back(Tmp1); 3575 break; 3576 case ISD::VAARG: { 3577 SDValue Chain = Node->getOperand(0); // Get the chain. 3578 SDValue Ptr = Node->getOperand(1); // Get the pointer. 3579 3580 unsigned TruncOp; 3581 if (OVT.isVector()) { 3582 TruncOp = ISD::BITCAST; 3583 } else { 3584 assert(OVT.isInteger() 3585 && "VAARG promotion is supported only for vectors or integer types"); 3586 TruncOp = ISD::TRUNCATE; 3587 } 3588 3589 // Perform the larger operation, then convert back 3590 Tmp1 = DAG.getVAArg(NVT, dl, Chain, Ptr, Node->getOperand(2), 3591 Node->getConstantOperandVal(3)); 3592 Chain = Tmp1.getValue(1); 3593 3594 Tmp2 = DAG.getNode(TruncOp, dl, OVT, Tmp1); 3595 3596 // Modified the chain result - switch anything that used the old chain to 3597 // use the new one. 3598 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 0), Tmp2); 3599 DAG.ReplaceAllUsesOfValueWith(SDValue(Node, 1), Chain); 3600 ReplacedNode(Node); 3601 break; 3602 } 3603 case ISD::AND: 3604 case ISD::OR: 3605 case ISD::XOR: { 3606 unsigned ExtOp, TruncOp; 3607 if (OVT.isVector()) { 3608 ExtOp = ISD::BITCAST; 3609 TruncOp = ISD::BITCAST; 3610 } else { 3611 assert(OVT.isInteger() && "Cannot promote logic operation"); 3612 ExtOp = ISD::ANY_EXTEND; 3613 TruncOp = ISD::TRUNCATE; 3614 } 3615 // Promote each of the values to the new type. 3616 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3617 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3618 // Perform the larger operation, then convert back 3619 Tmp1 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3620 Results.push_back(DAG.getNode(TruncOp, dl, OVT, Tmp1)); 3621 break; 3622 } 3623 case ISD::SELECT: { 3624 unsigned ExtOp, TruncOp; 3625 if (Node->getValueType(0).isVector()) { 3626 ExtOp = ISD::BITCAST; 3627 TruncOp = ISD::BITCAST; 3628 } else if (Node->getValueType(0).isInteger()) { 3629 ExtOp = ISD::ANY_EXTEND; 3630 TruncOp = ISD::TRUNCATE; 3631 } else { 3632 ExtOp = ISD::FP_EXTEND; 3633 TruncOp = ISD::FP_ROUND; 3634 } 3635 Tmp1 = Node->getOperand(0); 3636 // Promote each of the values to the new type. 3637 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3638 Tmp3 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(2)); 3639 // Perform the larger operation, then round down. 3640 Tmp1 = DAG.getNode(ISD::SELECT, dl, NVT, Tmp1, Tmp2, Tmp3); 3641 if (TruncOp != ISD::FP_ROUND) 3642 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1); 3643 else 3644 Tmp1 = DAG.getNode(TruncOp, dl, Node->getValueType(0), Tmp1, 3645 DAG.getIntPtrConstant(0)); 3646 Results.push_back(Tmp1); 3647 break; 3648 } 3649 case ISD::VECTOR_SHUFFLE: { 3650 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(Node)->getMask(); 3651 3652 // Cast the two input vectors. 3653 Tmp1 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(0)); 3654 Tmp2 = DAG.getNode(ISD::BITCAST, dl, NVT, Node->getOperand(1)); 3655 3656 // Convert the shuffle mask to the right # elements. 3657 Tmp1 = ShuffleWithNarrowerEltType(NVT, OVT, dl, Tmp1, Tmp2, Mask); 3658 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OVT, Tmp1); 3659 Results.push_back(Tmp1); 3660 break; 3661 } 3662 case ISD::SETCC: { 3663 unsigned ExtOp = ISD::FP_EXTEND; 3664 if (NVT.isInteger()) { 3665 ISD::CondCode CCCode = 3666 cast<CondCodeSDNode>(Node->getOperand(2))->get(); 3667 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; 3668 } 3669 Tmp1 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(0)); 3670 Tmp2 = DAG.getNode(ExtOp, dl, NVT, Node->getOperand(1)); 3671 Results.push_back(DAG.getNode(ISD::SETCC, dl, Node->getValueType(0), 3672 Tmp1, Tmp2, Node->getOperand(2))); 3673 break; 3674 } 3675 case ISD::FDIV: 3676 case ISD::FREM: 3677 case ISD::FPOW: { 3678 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3679 Tmp2 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(1)); 3680 Tmp3 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1, Tmp2); 3681 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3682 Tmp3, DAG.getIntPtrConstant(0))); 3683 break; 3684 } 3685 case ISD::FLOG2: 3686 case ISD::FEXP2: 3687 case ISD::FLOG: 3688 case ISD::FEXP: { 3689 Tmp1 = DAG.getNode(ISD::FP_EXTEND, dl, NVT, Node->getOperand(0)); 3690 Tmp2 = DAG.getNode(Node->getOpcode(), dl, NVT, Tmp1); 3691 Results.push_back(DAG.getNode(ISD::FP_ROUND, dl, OVT, 3692 Tmp2, DAG.getIntPtrConstant(0))); 3693 break; 3694 } 3695 } 3696 3697 // Replace the original node with the legalized result. 3698 if (!Results.empty()) 3699 ReplaceNode(Node, Results.data()); 3700 } 3701 3702 // SelectionDAG::Legalize - This is the entry point for the file. 3703 // 3704 void SelectionDAG::Legalize() { 3705 /// run - This is the main entry point to this class. 3706 /// 3707 SelectionDAGLegalize(*this).LegalizeDAG(); 3708 } 3709