1 // Copyright 2017, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright 10 // notice, this list of conditions and the following disclaimer in the 11 // documentation and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may 13 // be used to endorse or promote products derived from this software 14 // without specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 // IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 // ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 // LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 // CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 // SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 // INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 // CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 // POSSIBILITY OF SUCH DAMAGE. 27 28 #ifndef VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 29 #define VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 30 31 #include "code-generation-scopes-vixl.h" 32 #include "macro-assembler-interface.h" 33 #include "pool-manager-impl.h" 34 #include "pool-manager.h" 35 #include "utils-vixl.h" 36 37 #include "aarch32/assembler-aarch32.h" 38 #include "aarch32/instructions-aarch32.h" 39 #include "aarch32/operands-aarch32.h" 40 41 namespace vixl { 42 43 namespace aarch32 { 44 45 class UseScratchRegisterScope; 46 47 enum FlagsUpdate { LeaveFlags = 0, SetFlags = 1, DontCare = 2 }; 48 49 // We use a subclass to access the protected `ExactAssemblyScope` constructor 50 // giving us control over the pools, and make the constructor private to limit 51 // usage to code paths emitting pools. 52 class ExactAssemblyScopeWithoutPoolsCheck : public ExactAssemblyScope { 53 private: 54 ExactAssemblyScopeWithoutPoolsCheck(MacroAssembler* masm, 55 size_t size, 56 SizePolicy size_policy = kExactSize); 57 58 friend class MacroAssembler; 59 friend class Label; 60 }; 61 // Macro assembler for aarch32 instruction set. 62 class MacroAssembler : public Assembler, public MacroAssemblerInterface { 63 public: 64 enum FinalizeOption { 65 kFallThrough, // There may be more code to execute after calling Finalize. 66 kUnreachable // Anything generated after calling Finalize is unreachable. 67 }; 68 69 virtual internal::AssemblerBase* AsAssemblerBase() VIXL_OVERRIDE { 70 return this; 71 } 72 73 virtual bool ArePoolsBlocked() const VIXL_OVERRIDE { 74 return pool_manager_.IsBlocked(); 75 } 76 77 virtual void EmitPoolHeader() VIXL_OVERRIDE { 78 // Check that we have the correct alignment. 79 if (IsUsingT32()) { 80 VIXL_ASSERT(GetBuffer()->Is16bitAligned()); 81 } else { 82 VIXL_ASSERT(GetBuffer()->Is32bitAligned()); 83 } 84 VIXL_ASSERT(pool_end_ == NULL); 85 pool_end_ = new Label(); 86 ExactAssemblyScopeWithoutPoolsCheck guard(this, 87 kMaxInstructionSizeInBytes, 88 ExactAssemblyScope::kMaximumSize); 89 b(pool_end_); 90 } 91 virtual void EmitPoolFooter() VIXL_OVERRIDE { 92 // Align buffer to 4 bytes. 93 GetBuffer()->Align(); 94 if (pool_end_ != NULL) { 95 Bind(pool_end_); 96 delete pool_end_; 97 pool_end_ = NULL; 98 } 99 } 100 virtual void EmitPaddingBytes(int n) VIXL_OVERRIDE { 101 GetBuffer()->EmitZeroedBytes(n); 102 } 103 virtual void EmitNopBytes(int n) VIXL_OVERRIDE { 104 int nops = 0; 105 int nop_size = IsUsingT32() ? k16BitT32InstructionSizeInBytes 106 : kA32InstructionSizeInBytes; 107 VIXL_ASSERT(n % nop_size == 0); 108 nops = n / nop_size; 109 ExactAssemblyScopeWithoutPoolsCheck guard(this, 110 n, 111 ExactAssemblyScope::kExactSize); 112 for (int i = 0; i < nops; ++i) { 113 nop(); 114 } 115 } 116 117 118 private: 119 class MacroEmissionCheckScope : public EmissionCheckScope { 120 public: 121 explicit MacroEmissionCheckScope(MacroAssemblerInterface* masm, 122 PoolPolicy pool_policy = kBlockPools) 123 : EmissionCheckScope(masm, 124 kTypicalMacroInstructionMaxSize, 125 kMaximumSize, 126 pool_policy) {} 127 128 private: 129 static const size_t kTypicalMacroInstructionMaxSize = 130 8 * kMaxInstructionSizeInBytes; 131 }; 132 133 class MacroAssemblerContext { 134 public: 135 MacroAssemblerContext() : count_(0) {} 136 ~MacroAssemblerContext() {} 137 unsigned GetRecursiveCount() const { return count_; } 138 void Up(const char* loc) { 139 location_stack_[count_] = loc; 140 count_++; 141 if (count_ >= kMaxRecursion) { 142 printf( 143 "Recursion limit reached; unable to resolve macro assembler " 144 "call.\n"); 145 printf("Macro assembler context stack:\n"); 146 for (unsigned i = 0; i < kMaxRecursion; i++) { 147 printf("%10s %s\n", (i == 0) ? "oldest -> " : "", location_stack_[i]); 148 } 149 VIXL_ABORT(); 150 } 151 } 152 void Down() { 153 VIXL_ASSERT((count_ > 0) && (count_ < kMaxRecursion)); 154 count_--; 155 } 156 157 private: 158 unsigned count_; 159 static const uint32_t kMaxRecursion = 6; 160 const char* location_stack_[kMaxRecursion]; 161 }; 162 163 // This scope is used at each Delegate entry to avoid infinite recursion of 164 // Delegate calls. The limit is defined by 165 // MacroAssemblerContext::kMaxRecursion. 166 class ContextScope { 167 public: 168 explicit ContextScope(MacroAssembler* const masm, const char* loc) 169 : masm_(masm) { 170 VIXL_ASSERT(masm_->AllowMacroInstructions()); 171 masm_->GetContext()->Up(loc); 172 } 173 ~ContextScope() { masm_->GetContext()->Down(); } 174 175 private: 176 MacroAssembler* const masm_; 177 }; 178 179 MacroAssemblerContext* GetContext() { return &context_; } 180 181 class ITScope { 182 public: 183 ITScope(MacroAssembler* masm, 184 Condition* cond, 185 const MacroEmissionCheckScope& scope, 186 bool can_use_it = false) 187 : masm_(masm), cond_(*cond), can_use_it_(can_use_it) { 188 // The 'scope' argument is used to remind us to only use this scope inside 189 // a MacroEmissionCheckScope. This way, we do not need to check whether 190 // we need to emit the pools or grow the code buffer when emitting the 191 // IT or B instructions. 192 USE(scope); 193 if (!cond_.Is(al) && masm->IsUsingT32()) { 194 if (can_use_it_) { 195 // IT is not deprecated (that implies a 16 bit T32 instruction). 196 // We generate an IT instruction and a conditional instruction. 197 masm->it(cond_); 198 } else { 199 // The usage of IT is deprecated for the instruction. 200 // We generate a conditional branch and an unconditional instruction. 201 // Generate the branch. 202 masm_->b(cond_.Negate(), Narrow, &label_); 203 // Tell the macro-assembler to generate unconditional instructions. 204 *cond = al; 205 } 206 } 207 #ifdef VIXL_DEBUG 208 initial_cursor_offset_ = masm->GetCursorOffset(); 209 #else 210 USE(initial_cursor_offset_); 211 #endif 212 } 213 ~ITScope() { 214 if (label_.IsReferenced()) { 215 // We only use the label for conditional T32 instructions for which we 216 // cannot use IT. 217 VIXL_ASSERT(!cond_.Is(al)); 218 VIXL_ASSERT(masm_->IsUsingT32()); 219 VIXL_ASSERT(!can_use_it_); 220 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= 221 kMaxT32MacroInstructionSizeInBytes); 222 masm_->BindHelper(&label_); 223 } else if (masm_->IsUsingT32() && !cond_.Is(al)) { 224 // If we've generated a conditional T32 instruction but haven't used the 225 // label, we must have used IT. Check that we did not generate a 226 // deprecated sequence. 227 VIXL_ASSERT(can_use_it_); 228 VIXL_ASSERT(masm_->GetCursorOffset() - initial_cursor_offset_ <= 229 k16BitT32InstructionSizeInBytes); 230 } 231 } 232 233 private: 234 MacroAssembler* masm_; 235 Condition cond_; 236 Label label_; 237 bool can_use_it_; 238 uint32_t initial_cursor_offset_; 239 }; 240 241 protected: 242 virtual void BlockPools() VIXL_OVERRIDE { pool_manager_.Block(); } 243 virtual void ReleasePools() VIXL_OVERRIDE { 244 pool_manager_.Release(GetCursorOffset()); 245 } 246 virtual void EnsureEmitPoolsFor(size_t size) VIXL_OVERRIDE; 247 248 // Tell whether any of the macro instruction can be used. When false the 249 // MacroAssembler will assert if a method which can emit a variable number 250 // of instructions is called. 251 virtual void SetAllowMacroInstructions(bool value) VIXL_OVERRIDE { 252 allow_macro_instructions_ = value; 253 } 254 255 void HandleOutOfBoundsImmediate(Condition cond, Register tmp, uint32_t imm); 256 257 public: 258 // TODO: If we change the MacroAssembler to disallow setting a different ISA, 259 // we can change the alignment of the pool in the pool manager constructor to 260 // be 2 bytes for T32. 261 explicit MacroAssembler(InstructionSet isa = kDefaultISA) 262 : Assembler(isa), 263 available_(r12), 264 current_scratch_scope_(NULL), 265 pool_manager_(4 /*header_size*/, 266 4 /*alignment*/, 267 4 /*buffer_alignment*/), 268 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE), 269 pool_end_(NULL) { 270 #ifdef VIXL_DEBUG 271 SetAllowMacroInstructions(true); 272 #else 273 USE(allow_macro_instructions_); 274 #endif 275 } 276 explicit MacroAssembler(size_t size, InstructionSet isa = kDefaultISA) 277 : Assembler(size, isa), 278 available_(r12), 279 current_scratch_scope_(NULL), 280 pool_manager_(4 /*header_size*/, 281 4 /*alignment*/, 282 4 /*buffer_alignment*/), 283 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE), 284 pool_end_(NULL) { 285 #ifdef VIXL_DEBUG 286 SetAllowMacroInstructions(true); 287 #endif 288 } 289 MacroAssembler(byte* buffer, size_t size, InstructionSet isa = kDefaultISA) 290 : Assembler(buffer, size, isa), 291 available_(r12), 292 current_scratch_scope_(NULL), 293 pool_manager_(4 /*header_size*/, 294 4 /*alignment*/, 295 4 /*buffer_alignment*/), 296 generate_simulator_code_(VIXL_AARCH32_GENERATE_SIMULATOR_CODE), 297 pool_end_(NULL) { 298 #ifdef VIXL_DEBUG 299 SetAllowMacroInstructions(true); 300 #endif 301 } 302 303 bool GenerateSimulatorCode() const { return generate_simulator_code_; } 304 305 virtual bool AllowMacroInstructions() const VIXL_OVERRIDE { 306 return allow_macro_instructions_; 307 } 308 309 void FinalizeCode(FinalizeOption option = kUnreachable) { 310 EmitLiteralPool(option == kUnreachable 311 ? PoolManager<int32_t>::kNoBranchRequired 312 : PoolManager<int32_t>::kBranchRequired); 313 Assembler::FinalizeCode(); 314 } 315 316 RegisterList* GetScratchRegisterList() { return &available_; } 317 VRegisterList* GetScratchVRegisterList() { return &available_vfp_; } 318 319 // Get or set the current (most-deeply-nested) UseScratchRegisterScope. 320 void SetCurrentScratchRegisterScope(UseScratchRegisterScope* scope) { 321 current_scratch_scope_ = scope; 322 } 323 UseScratchRegisterScope* GetCurrentScratchRegisterScope() { 324 return current_scratch_scope_; 325 } 326 327 // Given an address calculation (Register + immediate), generate code to 328 // partially compute the address. The returned MemOperand will perform any 329 // remaining computation in a subsequent load or store instruction. 330 // 331 // The offset provided should be the offset that would be used in a load or 332 // store instruction (if it had sufficient range). This only matters where 333 // base.Is(pc), since load and store instructions align the pc before 334 // dereferencing it. 335 // 336 // TODO: Improve the handling of negative offsets. They are not implemented 337 // precisely for now because they only have a marginal benefit for the 338 // existing uses (in delegates). 339 MemOperand MemOperandComputationHelper(Condition cond, 340 Register scratch, 341 Register base, 342 uint32_t offset, 343 uint32_t extra_offset_mask = 0); 344 345 MemOperand MemOperandComputationHelper(Register scratch, 346 Register base, 347 uint32_t offset, 348 uint32_t extra_offset_mask = 0) { 349 return MemOperandComputationHelper(al, 350 scratch, 351 base, 352 offset, 353 extra_offset_mask); 354 } 355 MemOperand MemOperandComputationHelper(Condition cond, 356 Register scratch, 357 Location* location, 358 uint32_t extra_offset_mask = 0) { 359 // Check for buffer space _before_ calculating the offset, in case we 360 // generate a pool that affects the offset calculation. 361 CodeBufferCheckScope scope(this, 4 * kMaxInstructionSizeInBytes); 362 Label::Offset offset = 363 location->GetLocation() - 364 AlignDown(GetCursorOffset() + GetArchitectureStatePCOffset(), 4); 365 return MemOperandComputationHelper(cond, 366 scratch, 367 pc, 368 offset, 369 extra_offset_mask); 370 } 371 MemOperand MemOperandComputationHelper(Register scratch, 372 Location* location, 373 uint32_t extra_offset_mask = 0) { 374 return MemOperandComputationHelper(al, 375 scratch, 376 location, 377 extra_offset_mask); 378 } 379 380 // Determine the appropriate mask to pass into MemOperandComputationHelper. 381 uint32_t GetOffsetMask(InstructionType type, AddrMode addrmode); 382 383 // State and type helpers. 384 bool IsModifiedImmediate(uint32_t imm) { 385 return IsUsingT32() ? ImmediateT32::IsImmediateT32(imm) 386 : ImmediateA32::IsImmediateA32(imm); 387 } 388 389 void Bind(Label* label) { 390 VIXL_ASSERT(allow_macro_instructions_); 391 BindHelper(label); 392 } 393 394 virtual void BindHelper(Label* label) VIXL_OVERRIDE { 395 // Assert that we have the correct buffer alignment. 396 if (IsUsingT32()) { 397 VIXL_ASSERT(GetBuffer()->Is16bitAligned()); 398 } else { 399 VIXL_ASSERT(GetBuffer()->Is32bitAligned()); 400 } 401 // If we need to add padding, check if we have to emit the pool. 402 const int32_t pc = GetCursorOffset(); 403 if (label->Needs16BitPadding(pc)) { 404 const int kPaddingBytes = 2; 405 if (pool_manager_.MustEmit(pc, kPaddingBytes)) { 406 int32_t new_pc = pool_manager_.Emit(this, pc, kPaddingBytes); 407 USE(new_pc); 408 VIXL_ASSERT(new_pc == GetCursorOffset()); 409 } 410 } 411 pool_manager_.Bind(this, label, GetCursorOffset()); 412 } 413 414 void RegisterLiteralReference(RawLiteral* literal) { 415 if (literal->IsManuallyPlaced()) return; 416 RegisterForwardReference(literal); 417 } 418 419 void RegisterForwardReference(Location* location) { 420 if (location->IsBound()) return; 421 VIXL_ASSERT(location->HasForwardReferences()); 422 const Location::ForwardRef& reference = location->GetLastForwardReference(); 423 pool_manager_.AddObjectReference(&reference, location); 424 } 425 426 void CheckEmitPoolForInstruction(const ReferenceInfo* info, 427 Location* location, 428 Condition* cond = NULL) { 429 int size = info->size; 430 int32_t pc = GetCursorOffset(); 431 // If we need to emit a branch over the instruction, take this into account. 432 if ((cond != NULL) && NeedBranch(cond)) { 433 size += kBranchSize; 434 pc += kBranchSize; 435 } 436 int32_t from = pc; 437 from += IsUsingT32() ? kT32PcDelta : kA32PcDelta; 438 if (info->pc_needs_aligning) from = AlignDown(from, 4); 439 int32_t min = from + info->min_offset; 440 int32_t max = from + info->max_offset; 441 ForwardReference<int32_t> temp_ref(pc, 442 info->size, 443 min, 444 max, 445 info->alignment); 446 if (pool_manager_.MustEmit(GetCursorOffset(), size, &temp_ref, location)) { 447 int32_t new_pc = pool_manager_.Emit(this, 448 GetCursorOffset(), 449 info->size, 450 &temp_ref, 451 location); 452 USE(new_pc); 453 VIXL_ASSERT(new_pc == GetCursorOffset()); 454 } 455 } 456 457 void Place(RawLiteral* literal) { 458 VIXL_ASSERT(allow_macro_instructions_); 459 VIXL_ASSERT(literal->IsManuallyPlaced()); 460 // Check if we need to emit the pools. Take the alignment of the literal 461 // into account, as well as potential 16-bit padding needed to reach the 462 // minimum accessible location. 463 int alignment = literal->GetMaxAlignment(); 464 int32_t pc = GetCursorOffset(); 465 int total_size = AlignUp(pc, alignment) - pc + literal->GetSize(); 466 if (literal->Needs16BitPadding(pc)) total_size += 2; 467 if (pool_manager_.MustEmit(pc, total_size)) { 468 int32_t new_pc = pool_manager_.Emit(this, pc, total_size); 469 USE(new_pc); 470 VIXL_ASSERT(new_pc == GetCursorOffset()); 471 } 472 pool_manager_.Bind(this, literal, GetCursorOffset()); 473 literal->EmitPoolObject(this); 474 // Align the buffer, to be ready to generate instructions right after 475 // this. 476 GetBuffer()->Align(); 477 } 478 479 void EmitLiteralPool(PoolManager<int32_t>::EmitOption option = 480 PoolManager<int32_t>::kBranchRequired) { 481 VIXL_ASSERT(!ArePoolsBlocked()); 482 int32_t new_pc = 483 pool_manager_.Emit(this, GetCursorOffset(), 0, NULL, NULL, option); 484 VIXL_ASSERT(new_pc == GetCursorOffset()); 485 USE(new_pc); 486 } 487 488 void EnsureEmitFor(uint32_t size) { 489 EnsureEmitPoolsFor(size); 490 VIXL_ASSERT(GetBuffer()->HasSpaceFor(size) || GetBuffer()->IsManaged()); 491 GetBuffer()->EnsureSpaceFor(size); 492 } 493 494 bool AliasesAvailableScratchRegister(Register reg) { 495 return GetScratchRegisterList()->Includes(reg); 496 } 497 498 bool AliasesAvailableScratchRegister(RegisterOrAPSR_nzcv reg) { 499 if (reg.IsAPSR_nzcv()) return false; 500 return GetScratchRegisterList()->Includes(reg.AsRegister()); 501 } 502 503 bool AliasesAvailableScratchRegister(VRegister reg) { 504 return GetScratchVRegisterList()->IncludesAliasOf(reg); 505 } 506 507 bool AliasesAvailableScratchRegister(const Operand& operand) { 508 if (operand.IsImmediate()) return false; 509 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) || 510 (operand.IsRegisterShiftedRegister() && 511 AliasesAvailableScratchRegister(operand.GetShiftRegister())); 512 } 513 514 bool AliasesAvailableScratchRegister(const NeonOperand& operand) { 515 if (operand.IsImmediate()) return false; 516 return AliasesAvailableScratchRegister(operand.GetRegister()); 517 } 518 519 bool AliasesAvailableScratchRegister(SRegisterList list) { 520 for (int n = 0; n < list.GetLength(); n++) { 521 if (AliasesAvailableScratchRegister(list.GetSRegister(n))) return true; 522 } 523 return false; 524 } 525 526 bool AliasesAvailableScratchRegister(DRegisterList list) { 527 for (int n = 0; n < list.GetLength(); n++) { 528 if (AliasesAvailableScratchRegister(list.GetDRegister(n))) return true; 529 } 530 return false; 531 } 532 533 bool AliasesAvailableScratchRegister(NeonRegisterList list) { 534 for (int n = 0; n < list.GetLength(); n++) { 535 if (AliasesAvailableScratchRegister(list.GetDRegister(n))) return true; 536 } 537 return false; 538 } 539 540 bool AliasesAvailableScratchRegister(RegisterList list) { 541 return GetScratchRegisterList()->Overlaps(list); 542 } 543 544 bool AliasesAvailableScratchRegister(const MemOperand& operand) { 545 return AliasesAvailableScratchRegister(operand.GetBaseRegister()) || 546 (operand.IsShiftedRegister() && 547 AliasesAvailableScratchRegister(operand.GetOffsetRegister())); 548 } 549 550 // Adr with a literal already constructed. Add the literal to the pool if it 551 // is not already done. 552 void Adr(Condition cond, Register rd, RawLiteral* literal) { 553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 554 VIXL_ASSERT(allow_macro_instructions_); 555 VIXL_ASSERT(OutsideITBlock()); 556 MacroEmissionCheckScope::PoolPolicy pool_policy = 557 MacroEmissionCheckScope::kBlockPools; 558 if (!literal->IsBound()) { 559 const ReferenceInfo* info; 560 bool can_encode = adr_info(cond, Best, rd, literal, &info); 561 VIXL_CHECK(can_encode); 562 CheckEmitPoolForInstruction(info, literal, &cond); 563 // We have already checked for pool emission. 564 pool_policy = MacroEmissionCheckScope::kIgnorePools; 565 } 566 MacroEmissionCheckScope guard(this, pool_policy); 567 ITScope it_scope(this, &cond, guard); 568 adr(cond, Best, rd, literal); 569 RegisterLiteralReference(literal); 570 } 571 void Adr(Register rd, RawLiteral* literal) { Adr(al, rd, literal); } 572 573 // Loads with literals already constructed. Add the literal to the pool 574 // if it is not already done. 575 void Ldr(Condition cond, Register rt, RawLiteral* literal) { 576 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 577 VIXL_ASSERT(allow_macro_instructions_); 578 VIXL_ASSERT(OutsideITBlock()); 579 MacroEmissionCheckScope::PoolPolicy pool_policy = 580 MacroEmissionCheckScope::kBlockPools; 581 if (!literal->IsBound()) { 582 const ReferenceInfo* info; 583 bool can_encode = ldr_info(cond, Best, rt, literal, &info); 584 VIXL_CHECK(can_encode); 585 CheckEmitPoolForInstruction(info, literal, &cond); 586 // We have already checked for pool emission. 587 pool_policy = MacroEmissionCheckScope::kIgnorePools; 588 } 589 MacroEmissionCheckScope guard(this, pool_policy); 590 ITScope it_scope(this, &cond, guard); 591 ldr(cond, rt, literal); 592 RegisterLiteralReference(literal); 593 } 594 void Ldr(Register rt, RawLiteral* literal) { Ldr(al, rt, literal); } 595 596 void Ldrb(Condition cond, Register rt, RawLiteral* literal) { 597 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 598 VIXL_ASSERT(allow_macro_instructions_); 599 VIXL_ASSERT(OutsideITBlock()); 600 MacroEmissionCheckScope::PoolPolicy pool_policy = 601 MacroEmissionCheckScope::kBlockPools; 602 if (!literal->IsBound()) { 603 const ReferenceInfo* info; 604 bool can_encode = ldrb_info(cond, rt, literal, &info); 605 VIXL_CHECK(can_encode); 606 CheckEmitPoolForInstruction(info, literal, &cond); 607 // We have already checked for pool emission. 608 pool_policy = MacroEmissionCheckScope::kIgnorePools; 609 } 610 MacroEmissionCheckScope guard(this, pool_policy); 611 ITScope it_scope(this, &cond, guard); 612 ldrb(cond, rt, literal); 613 RegisterLiteralReference(literal); 614 } 615 void Ldrb(Register rt, RawLiteral* literal) { Ldrb(al, rt, literal); } 616 617 void Ldrd(Condition cond, Register rt, Register rt2, RawLiteral* literal) { 618 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 619 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 620 VIXL_ASSERT(allow_macro_instructions_); 621 VIXL_ASSERT(OutsideITBlock()); 622 MacroEmissionCheckScope::PoolPolicy pool_policy = 623 MacroEmissionCheckScope::kBlockPools; 624 if (!literal->IsBound()) { 625 const ReferenceInfo* info; 626 bool can_encode = ldrd_info(cond, rt, rt2, literal, &info); 627 VIXL_CHECK(can_encode); 628 CheckEmitPoolForInstruction(info, literal, &cond); 629 // We have already checked for pool emission. 630 pool_policy = MacroEmissionCheckScope::kIgnorePools; 631 } 632 MacroEmissionCheckScope guard(this, pool_policy); 633 ITScope it_scope(this, &cond, guard); 634 ldrd(cond, rt, rt2, literal); 635 RegisterLiteralReference(literal); 636 } 637 void Ldrd(Register rt, Register rt2, RawLiteral* literal) { 638 Ldrd(al, rt, rt2, literal); 639 } 640 641 void Ldrh(Condition cond, Register rt, RawLiteral* literal) { 642 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 643 VIXL_ASSERT(allow_macro_instructions_); 644 VIXL_ASSERT(OutsideITBlock()); 645 MacroEmissionCheckScope::PoolPolicy pool_policy = 646 MacroEmissionCheckScope::kBlockPools; 647 if (!literal->IsBound()) { 648 const ReferenceInfo* info; 649 bool can_encode = ldrh_info(cond, rt, literal, &info); 650 VIXL_CHECK(can_encode); 651 CheckEmitPoolForInstruction(info, literal, &cond); 652 // We have already checked for pool emission. 653 pool_policy = MacroEmissionCheckScope::kIgnorePools; 654 } 655 MacroEmissionCheckScope guard(this, pool_policy); 656 ITScope it_scope(this, &cond, guard); 657 ldrh(cond, rt, literal); 658 RegisterLiteralReference(literal); 659 } 660 void Ldrh(Register rt, RawLiteral* literal) { Ldrh(al, rt, literal); } 661 662 void Ldrsb(Condition cond, Register rt, RawLiteral* literal) { 663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 664 VIXL_ASSERT(allow_macro_instructions_); 665 VIXL_ASSERT(OutsideITBlock()); 666 MacroEmissionCheckScope::PoolPolicy pool_policy = 667 MacroEmissionCheckScope::kBlockPools; 668 if (!literal->IsBound()) { 669 const ReferenceInfo* info; 670 bool can_encode = ldrsb_info(cond, rt, literal, &info); 671 VIXL_CHECK(can_encode); 672 CheckEmitPoolForInstruction(info, literal, &cond); 673 // We have already checked for pool emission. 674 pool_policy = MacroEmissionCheckScope::kIgnorePools; 675 } 676 MacroEmissionCheckScope guard(this, pool_policy); 677 ITScope it_scope(this, &cond, guard); 678 ldrsb(cond, rt, literal); 679 RegisterLiteralReference(literal); 680 } 681 void Ldrsb(Register rt, RawLiteral* literal) { Ldrsb(al, rt, literal); } 682 683 void Ldrsh(Condition cond, Register rt, RawLiteral* literal) { 684 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 685 VIXL_ASSERT(allow_macro_instructions_); 686 VIXL_ASSERT(OutsideITBlock()); 687 MacroEmissionCheckScope::PoolPolicy pool_policy = 688 MacroEmissionCheckScope::kBlockPools; 689 if (!literal->IsBound()) { 690 const ReferenceInfo* info; 691 bool can_encode = ldrsh_info(cond, rt, literal, &info); 692 VIXL_CHECK(can_encode); 693 CheckEmitPoolForInstruction(info, literal, &cond); 694 // We have already checked for pool emission. 695 pool_policy = MacroEmissionCheckScope::kIgnorePools; 696 } 697 MacroEmissionCheckScope guard(this, pool_policy); 698 ITScope it_scope(this, &cond, guard); 699 ldrsh(cond, rt, literal); 700 RegisterLiteralReference(literal); 701 } 702 void Ldrsh(Register rt, RawLiteral* literal) { Ldrsh(al, rt, literal); } 703 704 void Vldr(Condition cond, DataType dt, DRegister rd, RawLiteral* literal) { 705 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 706 VIXL_ASSERT(allow_macro_instructions_); 707 VIXL_ASSERT(OutsideITBlock()); 708 MacroEmissionCheckScope::PoolPolicy pool_policy = 709 MacroEmissionCheckScope::kBlockPools; 710 if (!literal->IsBound()) { 711 const ReferenceInfo* info; 712 bool can_encode = vldr_info(cond, dt, rd, literal, &info); 713 VIXL_CHECK(can_encode); 714 CheckEmitPoolForInstruction(info, literal, &cond); 715 // We have already checked for pool emission. 716 pool_policy = MacroEmissionCheckScope::kIgnorePools; 717 } 718 MacroEmissionCheckScope guard(this, pool_policy); 719 ITScope it_scope(this, &cond, guard); 720 vldr(cond, dt, rd, literal); 721 RegisterLiteralReference(literal); 722 } 723 void Vldr(DataType dt, DRegister rd, RawLiteral* literal) { 724 Vldr(al, dt, rd, literal); 725 } 726 void Vldr(Condition cond, DRegister rd, RawLiteral* literal) { 727 Vldr(cond, Untyped64, rd, literal); 728 } 729 void Vldr(DRegister rd, RawLiteral* literal) { 730 Vldr(al, Untyped64, rd, literal); 731 } 732 733 void Vldr(Condition cond, DataType dt, SRegister rd, RawLiteral* literal) { 734 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 735 VIXL_ASSERT(allow_macro_instructions_); 736 VIXL_ASSERT(OutsideITBlock()); 737 MacroEmissionCheckScope::PoolPolicy pool_policy = 738 MacroEmissionCheckScope::kBlockPools; 739 if (!literal->IsBound()) { 740 const ReferenceInfo* info; 741 bool can_encode = vldr_info(cond, dt, rd, literal, &info); 742 VIXL_CHECK(can_encode); 743 CheckEmitPoolForInstruction(info, literal, &cond); 744 // We have already checked for pool emission. 745 pool_policy = MacroEmissionCheckScope::kIgnorePools; 746 } 747 MacroEmissionCheckScope guard(this, pool_policy); 748 ITScope it_scope(this, &cond, guard); 749 vldr(cond, dt, rd, literal); 750 RegisterLiteralReference(literal); 751 } 752 void Vldr(DataType dt, SRegister rd, RawLiteral* literal) { 753 Vldr(al, dt, rd, literal); 754 } 755 void Vldr(Condition cond, SRegister rd, RawLiteral* literal) { 756 Vldr(cond, Untyped32, rd, literal); 757 } 758 void Vldr(SRegister rd, RawLiteral* literal) { 759 Vldr(al, Untyped32, rd, literal); 760 } 761 762 // Generic Ldr(register, data) 763 void Ldr(Condition cond, Register rt, uint32_t v) { 764 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 765 VIXL_ASSERT(allow_macro_instructions_); 766 VIXL_ASSERT(OutsideITBlock()); 767 RawLiteral* literal = 768 new Literal<uint32_t>(v, RawLiteral::kDeletedOnPlacementByPool); 769 Ldr(cond, rt, literal); 770 } 771 template <typename T> 772 void Ldr(Register rt, T v) { 773 Ldr(al, rt, v); 774 } 775 776 // Generic Ldrd(rt, rt2, data) 777 void Ldrd(Condition cond, Register rt, Register rt2, uint64_t v) { 778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 779 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 780 VIXL_ASSERT(allow_macro_instructions_); 781 VIXL_ASSERT(OutsideITBlock()); 782 RawLiteral* literal = 783 new Literal<uint64_t>(v, RawLiteral::kDeletedOnPlacementByPool); 784 Ldrd(cond, rt, rt2, literal); 785 } 786 template <typename T> 787 void Ldrd(Register rt, Register rt2, T v) { 788 Ldrd(al, rt, rt2, v); 789 } 790 791 void Vldr(Condition cond, SRegister rd, float v) { 792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 793 VIXL_ASSERT(allow_macro_instructions_); 794 VIXL_ASSERT(OutsideITBlock()); 795 RawLiteral* literal = 796 new Literal<float>(v, RawLiteral::kDeletedOnPlacementByPool); 797 Vldr(cond, rd, literal); 798 } 799 void Vldr(SRegister rd, float v) { Vldr(al, rd, v); } 800 801 void Vldr(Condition cond, DRegister rd, double v) { 802 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 803 VIXL_ASSERT(allow_macro_instructions_); 804 VIXL_ASSERT(OutsideITBlock()); 805 RawLiteral* literal = 806 new Literal<double>(v, RawLiteral::kDeletedOnPlacementByPool); 807 Vldr(cond, rd, literal); 808 } 809 void Vldr(DRegister rd, double v) { Vldr(al, rd, v); } 810 811 void Vmov(Condition cond, DRegister rt, double v) { Vmov(cond, F64, rt, v); } 812 void Vmov(DRegister rt, double v) { Vmov(al, F64, rt, v); } 813 void Vmov(Condition cond, SRegister rt, float v) { Vmov(cond, F32, rt, v); } 814 void Vmov(SRegister rt, float v) { Vmov(al, F32, rt, v); } 815 816 // Claim memory on the stack. 817 // Note that the Claim, Drop, and Peek helpers below ensure that offsets used 818 // are multiples of 32 bits to help maintain 32-bit SP alignment. 819 // We could `Align{Up,Down}(size, 4)`, but that's potentially problematic: 820 // Claim(3) 821 // Claim(1) 822 // Drop(4) 823 // would seem correct, when in fact: 824 // Claim(3) -> sp = sp - 4 825 // Claim(1) -> sp = sp - 4 826 // Drop(4) -> sp = sp + 4 827 // 828 void Claim(int32_t size) { 829 if (size == 0) return; 830 // The stack must be kept 32bit aligned. 831 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 832 Sub(sp, sp, size); 833 } 834 // Release memory on the stack 835 void Drop(int32_t size) { 836 if (size == 0) return; 837 // The stack must be kept 32bit aligned. 838 VIXL_ASSERT((size > 0) && ((size % 4) == 0)); 839 Add(sp, sp, size); 840 } 841 void Peek(Register dst, int32_t offset) { 842 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 843 Ldr(dst, MemOperand(sp, offset)); 844 } 845 void Poke(Register src, int32_t offset) { 846 VIXL_ASSERT((offset >= 0) && ((offset % 4) == 0)); 847 Str(src, MemOperand(sp, offset)); 848 } 849 void Printf(const char* format, 850 CPURegister reg1 = NoReg, 851 CPURegister reg2 = NoReg, 852 CPURegister reg3 = NoReg, 853 CPURegister reg4 = NoReg); 854 // Functions used by Printf for generation. 855 void PushRegister(CPURegister reg); 856 void PreparePrintfArgument(CPURegister reg, 857 int* core_count, 858 int* vfp_count, 859 uint32_t* printf_type); 860 // Handlers for cases not handled by the assembler. 861 // ADD, MOVT, MOVW, SUB, SXTB16, TEQ, UXTB16 862 virtual void Delegate(InstructionType type, 863 InstructionCondROp instruction, 864 Condition cond, 865 Register rn, 866 const Operand& operand) VIXL_OVERRIDE; 867 // CMN, CMP, MOV, MOVS, MVN, MVNS, SXTB, SXTH, TST, UXTB, UXTH 868 virtual void Delegate(InstructionType type, 869 InstructionCondSizeROp instruction, 870 Condition cond, 871 EncodingSize size, 872 Register rn, 873 const Operand& operand) VIXL_OVERRIDE; 874 // ADDW, ORN, ORNS, PKHBT, PKHTB, RSC, RSCS, SUBW, SXTAB, SXTAB16, SXTAH, 875 // UXTAB, UXTAB16, UXTAH 876 virtual void Delegate(InstructionType type, 877 InstructionCondRROp instruction, 878 Condition cond, 879 Register rd, 880 Register rn, 881 const Operand& operand) VIXL_OVERRIDE; 882 // ADC, ADCS, ADD, ADDS, AND, ANDS, ASR, ASRS, BIC, BICS, EOR, EORS, LSL, 883 // LSLS, LSR, LSRS, ORR, ORRS, ROR, RORS, RSB, RSBS, SBC, SBCS, SUB, SUBS 884 virtual void Delegate(InstructionType type, 885 InstructionCondSizeRL instruction, 886 Condition cond, 887 EncodingSize size, 888 Register rd, 889 Location* location) VIXL_OVERRIDE; 890 bool GenerateSplitInstruction(InstructionCondSizeRROp instruction, 891 Condition cond, 892 Register rd, 893 Register rn, 894 uint32_t imm, 895 uint32_t mask); 896 virtual void Delegate(InstructionType type, 897 InstructionCondSizeRROp instruction, 898 Condition cond, 899 EncodingSize size, 900 Register rd, 901 Register rn, 902 const Operand& operand) VIXL_OVERRIDE; 903 // CBNZ, CBZ 904 virtual void Delegate(InstructionType type, 905 InstructionRL instruction, 906 Register rn, 907 Location* location) VIXL_OVERRIDE; 908 // VMOV 909 virtual void Delegate(InstructionType type, 910 InstructionCondDtSSop instruction, 911 Condition cond, 912 DataType dt, 913 SRegister rd, 914 const SOperand& operand) VIXL_OVERRIDE; 915 // VMOV, VMVN 916 virtual void Delegate(InstructionType type, 917 InstructionCondDtDDop instruction, 918 Condition cond, 919 DataType dt, 920 DRegister rd, 921 const DOperand& operand) VIXL_OVERRIDE; 922 // VMOV, VMVN 923 virtual void Delegate(InstructionType type, 924 InstructionCondDtQQop instruction, 925 Condition cond, 926 DataType dt, 927 QRegister rd, 928 const QOperand& operand) VIXL_OVERRIDE; 929 // LDR, LDRB, LDRH, LDRSB, LDRSH, STR, STRB, STRH 930 virtual void Delegate(InstructionType type, 931 InstructionCondSizeRMop instruction, 932 Condition cond, 933 EncodingSize size, 934 Register rd, 935 const MemOperand& operand) VIXL_OVERRIDE; 936 // LDAEXD, LDRD, LDREXD, STLEX, STLEXB, STLEXH, STRD, STREX, STREXB, STREXH 937 virtual void Delegate(InstructionType type, 938 InstructionCondRL instruction, 939 Condition cond, 940 Register rt, 941 Location* location) VIXL_OVERRIDE; 942 virtual void Delegate(InstructionType type, 943 InstructionCondRRL instruction, 944 Condition cond, 945 Register rt, 946 Register rt2, 947 Location* location) VIXL_OVERRIDE; 948 virtual void Delegate(InstructionType type, 949 InstructionCondRRMop instruction, 950 Condition cond, 951 Register rt, 952 Register rt2, 953 const MemOperand& operand) VIXL_OVERRIDE; 954 // VLDR, VSTR 955 virtual void Delegate(InstructionType type, 956 InstructionCondDtSMop instruction, 957 Condition cond, 958 DataType dt, 959 SRegister rd, 960 const MemOperand& operand) VIXL_OVERRIDE; 961 // VLDR, VSTR 962 virtual void Delegate(InstructionType type, 963 InstructionCondDtDMop instruction, 964 Condition cond, 965 DataType dt, 966 DRegister rd, 967 const MemOperand& operand) VIXL_OVERRIDE; 968 // MSR 969 virtual void Delegate(InstructionType type, 970 InstructionCondMsrOp instruction, 971 Condition cond, 972 MaskedSpecialRegister spec_reg, 973 const Operand& operand) VIXL_OVERRIDE; 974 virtual void Delegate(InstructionType type, 975 InstructionCondDtDL instruction, 976 Condition cond, 977 DataType dt, 978 DRegister rd, 979 Location* location) VIXL_OVERRIDE; 980 virtual void Delegate(InstructionType type, 981 InstructionCondDtSL instruction, 982 Condition cond, 983 DataType dt, 984 SRegister rd, 985 Location* location) VIXL_OVERRIDE; 986 987 // Start of generated code. 988 989 void Adc(Condition cond, Register rd, Register rn, const Operand& operand) { 990 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 992 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 993 VIXL_ASSERT(allow_macro_instructions_); 994 VIXL_ASSERT(OutsideITBlock()); 995 MacroEmissionCheckScope guard(this); 996 bool can_use_it = 997 // ADC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 998 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 999 operand.GetBaseRegister().IsLow(); 1000 ITScope it_scope(this, &cond, guard, can_use_it); 1001 adc(cond, rd, rn, operand); 1002 } 1003 void Adc(Register rd, Register rn, const Operand& operand) { 1004 Adc(al, rd, rn, operand); 1005 } 1006 void Adc(FlagsUpdate flags, 1007 Condition cond, 1008 Register rd, 1009 Register rn, 1010 const Operand& operand) { 1011 switch (flags) { 1012 case LeaveFlags: 1013 Adc(cond, rd, rn, operand); 1014 break; 1015 case SetFlags: 1016 Adcs(cond, rd, rn, operand); 1017 break; 1018 case DontCare: 1019 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1020 rn.Is(rd) && operand.IsPlainRegister() && 1021 operand.GetBaseRegister().IsLow(); 1022 if (setflags_is_smaller) { 1023 Adcs(cond, rd, rn, operand); 1024 } else { 1025 Adc(cond, rd, rn, operand); 1026 } 1027 break; 1028 } 1029 } 1030 void Adc(FlagsUpdate flags, 1031 Register rd, 1032 Register rn, 1033 const Operand& operand) { 1034 Adc(flags, al, rd, rn, operand); 1035 } 1036 1037 void Adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 1038 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1040 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1041 VIXL_ASSERT(allow_macro_instructions_); 1042 VIXL_ASSERT(OutsideITBlock()); 1043 MacroEmissionCheckScope guard(this); 1044 ITScope it_scope(this, &cond, guard); 1045 adcs(cond, rd, rn, operand); 1046 } 1047 void Adcs(Register rd, Register rn, const Operand& operand) { 1048 Adcs(al, rd, rn, operand); 1049 } 1050 1051 void Add(Condition cond, Register rd, Register rn, const Operand& operand) { 1052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1053 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1054 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1055 VIXL_ASSERT(allow_macro_instructions_); 1056 VIXL_ASSERT(OutsideITBlock()); 1057 MacroEmissionCheckScope guard(this); 1058 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 1059 uint32_t immediate = operand.GetImmediate(); 1060 if (immediate == 0) { 1061 return; 1062 } 1063 } 1064 bool can_use_it = 1065 // ADD<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 1066 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 1067 rd.IsLow()) || 1068 // ADD<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 1069 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 1070 rd.IsLow() && rn.Is(rd)) || 1071 // ADD{<c>}{<q>} <Rd>, SP, #<imm8> ; T1 1072 (operand.IsImmediate() && (operand.GetImmediate() <= 1020) && 1073 ((operand.GetImmediate() & 0x3) == 0) && rd.IsLow() && rn.IsSP()) || 1074 // ADD<c>{<q>} <Rd>, <Rn>, <Rm> 1075 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 1076 operand.GetBaseRegister().IsLow()) || 1077 // ADD<c>{<q>} <Rdn>, <Rm> ; T2 1078 (operand.IsPlainRegister() && !rd.IsPC() && rn.Is(rd) && 1079 !operand.GetBaseRegister().IsSP() && 1080 !operand.GetBaseRegister().IsPC()) || 1081 // ADD{<c>}{<q>} {<Rdm>,} SP, <Rdm> ; T1 1082 (operand.IsPlainRegister() && !rd.IsPC() && rn.IsSP() && 1083 operand.GetBaseRegister().Is(rd)); 1084 ITScope it_scope(this, &cond, guard, can_use_it); 1085 add(cond, rd, rn, operand); 1086 } 1087 void Add(Register rd, Register rn, const Operand& operand) { 1088 Add(al, rd, rn, operand); 1089 } 1090 void Add(FlagsUpdate flags, 1091 Condition cond, 1092 Register rd, 1093 Register rn, 1094 const Operand& operand) { 1095 switch (flags) { 1096 case LeaveFlags: 1097 Add(cond, rd, rn, operand); 1098 break; 1099 case SetFlags: 1100 Adds(cond, rd, rn, operand); 1101 break; 1102 case DontCare: 1103 bool setflags_is_smaller = 1104 IsUsingT32() && cond.Is(al) && 1105 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 1106 !rd.Is(rn) && operand.GetBaseRegister().IsLow()) || 1107 (operand.IsImmediate() && 1108 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 1109 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 1110 if (setflags_is_smaller) { 1111 Adds(cond, rd, rn, operand); 1112 } else { 1113 bool changed_op_is_smaller = 1114 operand.IsImmediate() && (operand.GetSignedImmediate() < 0) && 1115 ((rd.IsLow() && rn.IsLow() && 1116 (operand.GetSignedImmediate() >= -7)) || 1117 (rd.IsLow() && rn.Is(rd) && 1118 (operand.GetSignedImmediate() >= -255))); 1119 if (changed_op_is_smaller) { 1120 Subs(cond, rd, rn, -operand.GetSignedImmediate()); 1121 } else { 1122 Add(cond, rd, rn, operand); 1123 } 1124 } 1125 break; 1126 } 1127 } 1128 void Add(FlagsUpdate flags, 1129 Register rd, 1130 Register rn, 1131 const Operand& operand) { 1132 Add(flags, al, rd, rn, operand); 1133 } 1134 1135 void Adds(Condition cond, Register rd, Register rn, const Operand& operand) { 1136 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1137 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1138 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1139 VIXL_ASSERT(allow_macro_instructions_); 1140 VIXL_ASSERT(OutsideITBlock()); 1141 MacroEmissionCheckScope guard(this); 1142 ITScope it_scope(this, &cond, guard); 1143 adds(cond, rd, rn, operand); 1144 } 1145 void Adds(Register rd, Register rn, const Operand& operand) { 1146 Adds(al, rd, rn, operand); 1147 } 1148 1149 void And(Condition cond, Register rd, Register rn, const Operand& operand) { 1150 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1152 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1153 VIXL_ASSERT(allow_macro_instructions_); 1154 VIXL_ASSERT(OutsideITBlock()); 1155 MacroEmissionCheckScope guard(this); 1156 if (rd.Is(rn) && operand.IsPlainRegister() && 1157 rd.Is(operand.GetBaseRegister())) { 1158 return; 1159 } 1160 if (cond.Is(al) && operand.IsImmediate()) { 1161 uint32_t immediate = operand.GetImmediate(); 1162 if (immediate == 0) { 1163 mov(rd, 0); 1164 return; 1165 } 1166 if ((immediate == 0xffffffff) && rd.Is(rn)) { 1167 return; 1168 } 1169 } 1170 bool can_use_it = 1171 // AND<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1172 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1173 operand.GetBaseRegister().IsLow(); 1174 ITScope it_scope(this, &cond, guard, can_use_it); 1175 and_(cond, rd, rn, operand); 1176 } 1177 void And(Register rd, Register rn, const Operand& operand) { 1178 And(al, rd, rn, operand); 1179 } 1180 void And(FlagsUpdate flags, 1181 Condition cond, 1182 Register rd, 1183 Register rn, 1184 const Operand& operand) { 1185 switch (flags) { 1186 case LeaveFlags: 1187 And(cond, rd, rn, operand); 1188 break; 1189 case SetFlags: 1190 Ands(cond, rd, rn, operand); 1191 break; 1192 case DontCare: 1193 if (operand.IsPlainRegister() && rd.Is(rn) && 1194 rd.Is(operand.GetBaseRegister())) { 1195 return; 1196 } 1197 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1198 rn.Is(rd) && operand.IsPlainRegister() && 1199 operand.GetBaseRegister().IsLow(); 1200 if (setflags_is_smaller) { 1201 Ands(cond, rd, rn, operand); 1202 } else { 1203 And(cond, rd, rn, operand); 1204 } 1205 break; 1206 } 1207 } 1208 void And(FlagsUpdate flags, 1209 Register rd, 1210 Register rn, 1211 const Operand& operand) { 1212 And(flags, al, rd, rn, operand); 1213 } 1214 1215 void Ands(Condition cond, Register rd, Register rn, const Operand& operand) { 1216 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1217 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1218 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1219 VIXL_ASSERT(allow_macro_instructions_); 1220 VIXL_ASSERT(OutsideITBlock()); 1221 MacroEmissionCheckScope guard(this); 1222 ITScope it_scope(this, &cond, guard); 1223 ands(cond, rd, rn, operand); 1224 } 1225 void Ands(Register rd, Register rn, const Operand& operand) { 1226 Ands(al, rd, rn, operand); 1227 } 1228 1229 void Asr(Condition cond, Register rd, Register rm, const Operand& operand) { 1230 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1231 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1232 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1233 VIXL_ASSERT(allow_macro_instructions_); 1234 VIXL_ASSERT(OutsideITBlock()); 1235 MacroEmissionCheckScope guard(this); 1236 bool can_use_it = 1237 // ASR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 1238 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 1239 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 1240 // ASR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 1241 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 1242 operand.GetBaseRegister().IsLow()); 1243 ITScope it_scope(this, &cond, guard, can_use_it); 1244 asr(cond, rd, rm, operand); 1245 } 1246 void Asr(Register rd, Register rm, const Operand& operand) { 1247 Asr(al, rd, rm, operand); 1248 } 1249 void Asr(FlagsUpdate flags, 1250 Condition cond, 1251 Register rd, 1252 Register rm, 1253 const Operand& operand) { 1254 switch (flags) { 1255 case LeaveFlags: 1256 Asr(cond, rd, rm, operand); 1257 break; 1258 case SetFlags: 1259 Asrs(cond, rd, rm, operand); 1260 break; 1261 case DontCare: 1262 bool setflags_is_smaller = 1263 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() && 1264 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) && 1265 (operand.GetImmediate() <= 32)) || 1266 (operand.IsPlainRegister() && rd.Is(rm))); 1267 if (setflags_is_smaller) { 1268 Asrs(cond, rd, rm, operand); 1269 } else { 1270 Asr(cond, rd, rm, operand); 1271 } 1272 break; 1273 } 1274 } 1275 void Asr(FlagsUpdate flags, 1276 Register rd, 1277 Register rm, 1278 const Operand& operand) { 1279 Asr(flags, al, rd, rm, operand); 1280 } 1281 1282 void Asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 1283 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1284 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1285 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1286 VIXL_ASSERT(allow_macro_instructions_); 1287 VIXL_ASSERT(OutsideITBlock()); 1288 MacroEmissionCheckScope guard(this); 1289 ITScope it_scope(this, &cond, guard); 1290 asrs(cond, rd, rm, operand); 1291 } 1292 void Asrs(Register rd, Register rm, const Operand& operand) { 1293 Asrs(al, rd, rm, operand); 1294 } 1295 1296 void B(Condition cond, Label* label, BranchHint hint = kBranchWithoutHint) { 1297 VIXL_ASSERT(allow_macro_instructions_); 1298 VIXL_ASSERT(OutsideITBlock()); 1299 EncodingSize size = Best; 1300 MacroEmissionCheckScope::PoolPolicy pool_policy = 1301 MacroEmissionCheckScope::kBlockPools; 1302 if (!label->IsBound()) { 1303 if (hint == kNear) size = Narrow; 1304 const ReferenceInfo* info; 1305 bool can_encode = b_info(cond, size, label, &info); 1306 VIXL_CHECK(can_encode); 1307 CheckEmitPoolForInstruction(info, label, &cond); 1308 // We have already checked for pool emission. 1309 pool_policy = MacroEmissionCheckScope::kIgnorePools; 1310 } 1311 MacroEmissionCheckScope guard(this, pool_policy); 1312 b(cond, size, label); 1313 RegisterForwardReference(label); 1314 } 1315 void B(Label* label, BranchHint hint = kBranchWithoutHint) { 1316 B(al, label, hint); 1317 } 1318 void BPreferNear(Condition cond, Label* label) { B(cond, label, kNear); } 1319 void BPreferNear(Label* label) { B(al, label, kNear); } 1320 1321 void Bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width) { 1322 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1323 VIXL_ASSERT(allow_macro_instructions_); 1324 VIXL_ASSERT(OutsideITBlock()); 1325 MacroEmissionCheckScope guard(this); 1326 ITScope it_scope(this, &cond, guard); 1327 bfc(cond, rd, lsb, width); 1328 } 1329 void Bfc(Register rd, uint32_t lsb, uint32_t width) { 1330 Bfc(al, rd, lsb, width); 1331 } 1332 1333 void Bfi( 1334 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { 1335 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1336 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1337 VIXL_ASSERT(allow_macro_instructions_); 1338 VIXL_ASSERT(OutsideITBlock()); 1339 MacroEmissionCheckScope guard(this); 1340 ITScope it_scope(this, &cond, guard); 1341 bfi(cond, rd, rn, lsb, width); 1342 } 1343 void Bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) { 1344 Bfi(al, rd, rn, lsb, width); 1345 } 1346 1347 void Bic(Condition cond, Register rd, Register rn, const Operand& operand) { 1348 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1349 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1350 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1351 VIXL_ASSERT(allow_macro_instructions_); 1352 VIXL_ASSERT(OutsideITBlock()); 1353 MacroEmissionCheckScope guard(this); 1354 if (cond.Is(al) && operand.IsImmediate()) { 1355 uint32_t immediate = operand.GetImmediate(); 1356 if ((immediate == 0) && rd.Is(rn)) { 1357 return; 1358 } 1359 if (immediate == 0xffffffff) { 1360 mov(rd, 0); 1361 return; 1362 } 1363 } 1364 bool can_use_it = 1365 // BIC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1366 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1367 operand.GetBaseRegister().IsLow(); 1368 ITScope it_scope(this, &cond, guard, can_use_it); 1369 bic(cond, rd, rn, operand); 1370 } 1371 void Bic(Register rd, Register rn, const Operand& operand) { 1372 Bic(al, rd, rn, operand); 1373 } 1374 void Bic(FlagsUpdate flags, 1375 Condition cond, 1376 Register rd, 1377 Register rn, 1378 const Operand& operand) { 1379 switch (flags) { 1380 case LeaveFlags: 1381 Bic(cond, rd, rn, operand); 1382 break; 1383 case SetFlags: 1384 Bics(cond, rd, rn, operand); 1385 break; 1386 case DontCare: 1387 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1388 rn.Is(rd) && operand.IsPlainRegister() && 1389 operand.GetBaseRegister().IsLow(); 1390 if (setflags_is_smaller) { 1391 Bics(cond, rd, rn, operand); 1392 } else { 1393 Bic(cond, rd, rn, operand); 1394 } 1395 break; 1396 } 1397 } 1398 void Bic(FlagsUpdate flags, 1399 Register rd, 1400 Register rn, 1401 const Operand& operand) { 1402 Bic(flags, al, rd, rn, operand); 1403 } 1404 1405 void Bics(Condition cond, Register rd, Register rn, const Operand& operand) { 1406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1407 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1408 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1409 VIXL_ASSERT(allow_macro_instructions_); 1410 VIXL_ASSERT(OutsideITBlock()); 1411 MacroEmissionCheckScope guard(this); 1412 ITScope it_scope(this, &cond, guard); 1413 bics(cond, rd, rn, operand); 1414 } 1415 void Bics(Register rd, Register rn, const Operand& operand) { 1416 Bics(al, rd, rn, operand); 1417 } 1418 1419 void Bkpt(Condition cond, uint32_t imm) { 1420 VIXL_ASSERT(allow_macro_instructions_); 1421 VIXL_ASSERT(OutsideITBlock()); 1422 MacroEmissionCheckScope guard(this); 1423 ITScope it_scope(this, &cond, guard); 1424 bkpt(cond, imm); 1425 } 1426 void Bkpt(uint32_t imm) { Bkpt(al, imm); } 1427 1428 void Bl(Condition cond, Label* label) { 1429 VIXL_ASSERT(allow_macro_instructions_); 1430 VIXL_ASSERT(OutsideITBlock()); 1431 MacroEmissionCheckScope::PoolPolicy pool_policy = 1432 MacroEmissionCheckScope::kBlockPools; 1433 if (!label->IsBound()) { 1434 const ReferenceInfo* info; 1435 bool can_encode = bl_info(cond, label, &info); 1436 VIXL_CHECK(can_encode); 1437 CheckEmitPoolForInstruction(info, label, &cond); 1438 // We have already checked for pool emission. 1439 pool_policy = MacroEmissionCheckScope::kIgnorePools; 1440 } 1441 MacroEmissionCheckScope guard(this, pool_policy); 1442 ITScope it_scope(this, &cond, guard); 1443 bl(cond, label); 1444 RegisterForwardReference(label); 1445 } 1446 void Bl(Label* label) { Bl(al, label); } 1447 1448 void Blx(Condition cond, Label* label) { 1449 VIXL_ASSERT(allow_macro_instructions_); 1450 VIXL_ASSERT(OutsideITBlock()); 1451 MacroEmissionCheckScope::PoolPolicy pool_policy = 1452 MacroEmissionCheckScope::kBlockPools; 1453 if (!label->IsBound()) { 1454 const ReferenceInfo* info; 1455 bool can_encode = blx_info(cond, label, &info); 1456 VIXL_CHECK(can_encode); 1457 CheckEmitPoolForInstruction(info, label, &cond); 1458 // We have already checked for pool emission. 1459 pool_policy = MacroEmissionCheckScope::kIgnorePools; 1460 } 1461 MacroEmissionCheckScope guard(this, pool_policy); 1462 ITScope it_scope(this, &cond, guard); 1463 blx(cond, label); 1464 RegisterForwardReference(label); 1465 } 1466 void Blx(Label* label) { Blx(al, label); } 1467 1468 void Blx(Condition cond, Register rm) { 1469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1470 VIXL_ASSERT(allow_macro_instructions_); 1471 VIXL_ASSERT(OutsideITBlock()); 1472 MacroEmissionCheckScope guard(this); 1473 bool can_use_it = 1474 // BLX{<c>}{<q>} <Rm> ; T1 1475 !rm.IsPC(); 1476 ITScope it_scope(this, &cond, guard, can_use_it); 1477 blx(cond, rm); 1478 } 1479 void Blx(Register rm) { Blx(al, rm); } 1480 1481 void Bx(Condition cond, Register rm) { 1482 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1483 VIXL_ASSERT(allow_macro_instructions_); 1484 VIXL_ASSERT(OutsideITBlock()); 1485 MacroEmissionCheckScope guard(this); 1486 bool can_use_it = 1487 // BX{<c>}{<q>} <Rm> ; T1 1488 !rm.IsPC(); 1489 ITScope it_scope(this, &cond, guard, can_use_it); 1490 bx(cond, rm); 1491 } 1492 void Bx(Register rm) { Bx(al, rm); } 1493 1494 void Bxj(Condition cond, Register rm) { 1495 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1496 VIXL_ASSERT(allow_macro_instructions_); 1497 VIXL_ASSERT(OutsideITBlock()); 1498 MacroEmissionCheckScope guard(this); 1499 ITScope it_scope(this, &cond, guard); 1500 bxj(cond, rm); 1501 } 1502 void Bxj(Register rm) { Bxj(al, rm); } 1503 1504 void Cbnz(Register rn, Label* label) { 1505 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1506 VIXL_ASSERT(allow_macro_instructions_); 1507 VIXL_ASSERT(OutsideITBlock()); 1508 MacroEmissionCheckScope::PoolPolicy pool_policy = 1509 MacroEmissionCheckScope::kBlockPools; 1510 if (!label->IsBound()) { 1511 const ReferenceInfo* info; 1512 bool can_encode = cbnz_info(rn, label, &info); 1513 VIXL_CHECK(can_encode); 1514 CheckEmitPoolForInstruction(info, label); 1515 // We have already checked for pool emission. 1516 pool_policy = MacroEmissionCheckScope::kIgnorePools; 1517 } 1518 MacroEmissionCheckScope guard(this, pool_policy); 1519 cbnz(rn, label); 1520 RegisterForwardReference(label); 1521 } 1522 1523 void Cbz(Register rn, Label* label) { 1524 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1525 VIXL_ASSERT(allow_macro_instructions_); 1526 VIXL_ASSERT(OutsideITBlock()); 1527 MacroEmissionCheckScope::PoolPolicy pool_policy = 1528 MacroEmissionCheckScope::kBlockPools; 1529 if (!label->IsBound()) { 1530 const ReferenceInfo* info; 1531 bool can_encode = cbz_info(rn, label, &info); 1532 VIXL_CHECK(can_encode); 1533 CheckEmitPoolForInstruction(info, label); 1534 // We have already checked for pool emission. 1535 pool_policy = MacroEmissionCheckScope::kIgnorePools; 1536 } 1537 MacroEmissionCheckScope guard(this, pool_policy); 1538 cbz(rn, label); 1539 RegisterForwardReference(label); 1540 } 1541 1542 void Clrex(Condition cond) { 1543 VIXL_ASSERT(allow_macro_instructions_); 1544 VIXL_ASSERT(OutsideITBlock()); 1545 MacroEmissionCheckScope guard(this); 1546 ITScope it_scope(this, &cond, guard); 1547 clrex(cond); 1548 } 1549 void Clrex() { Clrex(al); } 1550 1551 void Clz(Condition cond, Register rd, Register rm) { 1552 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1554 VIXL_ASSERT(allow_macro_instructions_); 1555 VIXL_ASSERT(OutsideITBlock()); 1556 MacroEmissionCheckScope guard(this); 1557 ITScope it_scope(this, &cond, guard); 1558 clz(cond, rd, rm); 1559 } 1560 void Clz(Register rd, Register rm) { Clz(al, rd, rm); } 1561 1562 void Cmn(Condition cond, Register rn, const Operand& operand) { 1563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1564 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1565 VIXL_ASSERT(allow_macro_instructions_); 1566 VIXL_ASSERT(OutsideITBlock()); 1567 MacroEmissionCheckScope guard(this); 1568 bool can_use_it = 1569 // CMN{<c>}{<q>} <Rn>, <Rm> ; T1 1570 operand.IsPlainRegister() && rn.IsLow() && 1571 operand.GetBaseRegister().IsLow(); 1572 ITScope it_scope(this, &cond, guard, can_use_it); 1573 cmn(cond, rn, operand); 1574 } 1575 void Cmn(Register rn, const Operand& operand) { Cmn(al, rn, operand); } 1576 1577 void Cmp(Condition cond, Register rn, const Operand& operand) { 1578 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1579 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1580 VIXL_ASSERT(allow_macro_instructions_); 1581 VIXL_ASSERT(OutsideITBlock()); 1582 MacroEmissionCheckScope guard(this); 1583 bool can_use_it = 1584 // CMP{<c>}{<q>} <Rn>, #<imm8> ; T1 1585 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 1586 rn.IsLow()) || 1587 // CMP{<c>}{<q>} <Rn>, <Rm> ; T1 T2 1588 (operand.IsPlainRegister() && !rn.IsPC() && 1589 !operand.GetBaseRegister().IsPC()); 1590 ITScope it_scope(this, &cond, guard, can_use_it); 1591 cmp(cond, rn, operand); 1592 } 1593 void Cmp(Register rn, const Operand& operand) { Cmp(al, rn, operand); } 1594 1595 void Crc32b(Condition cond, Register rd, Register rn, Register rm) { 1596 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1597 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1598 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1599 VIXL_ASSERT(allow_macro_instructions_); 1600 VIXL_ASSERT(OutsideITBlock()); 1601 MacroEmissionCheckScope guard(this); 1602 ITScope it_scope(this, &cond, guard); 1603 crc32b(cond, rd, rn, rm); 1604 } 1605 void Crc32b(Register rd, Register rn, Register rm) { Crc32b(al, rd, rn, rm); } 1606 1607 void Crc32cb(Condition cond, Register rd, Register rn, Register rm) { 1608 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1609 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1610 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1611 VIXL_ASSERT(allow_macro_instructions_); 1612 VIXL_ASSERT(OutsideITBlock()); 1613 MacroEmissionCheckScope guard(this); 1614 ITScope it_scope(this, &cond, guard); 1615 crc32cb(cond, rd, rn, rm); 1616 } 1617 void Crc32cb(Register rd, Register rn, Register rm) { 1618 Crc32cb(al, rd, rn, rm); 1619 } 1620 1621 void Crc32ch(Condition cond, Register rd, Register rn, Register rm) { 1622 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1623 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1624 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1625 VIXL_ASSERT(allow_macro_instructions_); 1626 VIXL_ASSERT(OutsideITBlock()); 1627 MacroEmissionCheckScope guard(this); 1628 ITScope it_scope(this, &cond, guard); 1629 crc32ch(cond, rd, rn, rm); 1630 } 1631 void Crc32ch(Register rd, Register rn, Register rm) { 1632 Crc32ch(al, rd, rn, rm); 1633 } 1634 1635 void Crc32cw(Condition cond, Register rd, Register rn, Register rm) { 1636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1638 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1639 VIXL_ASSERT(allow_macro_instructions_); 1640 VIXL_ASSERT(OutsideITBlock()); 1641 MacroEmissionCheckScope guard(this); 1642 ITScope it_scope(this, &cond, guard); 1643 crc32cw(cond, rd, rn, rm); 1644 } 1645 void Crc32cw(Register rd, Register rn, Register rm) { 1646 Crc32cw(al, rd, rn, rm); 1647 } 1648 1649 void Crc32h(Condition cond, Register rd, Register rn, Register rm) { 1650 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1651 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1652 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1653 VIXL_ASSERT(allow_macro_instructions_); 1654 VIXL_ASSERT(OutsideITBlock()); 1655 MacroEmissionCheckScope guard(this); 1656 ITScope it_scope(this, &cond, guard); 1657 crc32h(cond, rd, rn, rm); 1658 } 1659 void Crc32h(Register rd, Register rn, Register rm) { Crc32h(al, rd, rn, rm); } 1660 1661 void Crc32w(Condition cond, Register rd, Register rn, Register rm) { 1662 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1664 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 1665 VIXL_ASSERT(allow_macro_instructions_); 1666 VIXL_ASSERT(OutsideITBlock()); 1667 MacroEmissionCheckScope guard(this); 1668 ITScope it_scope(this, &cond, guard); 1669 crc32w(cond, rd, rn, rm); 1670 } 1671 void Crc32w(Register rd, Register rn, Register rm) { Crc32w(al, rd, rn, rm); } 1672 1673 void Dmb(Condition cond, MemoryBarrier option) { 1674 VIXL_ASSERT(allow_macro_instructions_); 1675 VIXL_ASSERT(OutsideITBlock()); 1676 MacroEmissionCheckScope guard(this); 1677 ITScope it_scope(this, &cond, guard); 1678 dmb(cond, option); 1679 } 1680 void Dmb(MemoryBarrier option) { Dmb(al, option); } 1681 1682 void Dsb(Condition cond, MemoryBarrier option) { 1683 VIXL_ASSERT(allow_macro_instructions_); 1684 VIXL_ASSERT(OutsideITBlock()); 1685 MacroEmissionCheckScope guard(this); 1686 ITScope it_scope(this, &cond, guard); 1687 dsb(cond, option); 1688 } 1689 void Dsb(MemoryBarrier option) { Dsb(al, option); } 1690 1691 void Eor(Condition cond, Register rd, Register rn, const Operand& operand) { 1692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1693 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1694 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1695 VIXL_ASSERT(allow_macro_instructions_); 1696 VIXL_ASSERT(OutsideITBlock()); 1697 MacroEmissionCheckScope guard(this); 1698 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 1699 uint32_t immediate = operand.GetImmediate(); 1700 if (immediate == 0) { 1701 return; 1702 } 1703 if (immediate == 0xffffffff) { 1704 mvn(rd, rn); 1705 return; 1706 } 1707 } 1708 bool can_use_it = 1709 // EOR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 1710 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 1711 operand.GetBaseRegister().IsLow(); 1712 ITScope it_scope(this, &cond, guard, can_use_it); 1713 eor(cond, rd, rn, operand); 1714 } 1715 void Eor(Register rd, Register rn, const Operand& operand) { 1716 Eor(al, rd, rn, operand); 1717 } 1718 void Eor(FlagsUpdate flags, 1719 Condition cond, 1720 Register rd, 1721 Register rn, 1722 const Operand& operand) { 1723 switch (flags) { 1724 case LeaveFlags: 1725 Eor(cond, rd, rn, operand); 1726 break; 1727 case SetFlags: 1728 Eors(cond, rd, rn, operand); 1729 break; 1730 case DontCare: 1731 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 1732 rn.Is(rd) && operand.IsPlainRegister() && 1733 operand.GetBaseRegister().IsLow(); 1734 if (setflags_is_smaller) { 1735 Eors(cond, rd, rn, operand); 1736 } else { 1737 Eor(cond, rd, rn, operand); 1738 } 1739 break; 1740 } 1741 } 1742 void Eor(FlagsUpdate flags, 1743 Register rd, 1744 Register rn, 1745 const Operand& operand) { 1746 Eor(flags, al, rd, rn, operand); 1747 } 1748 1749 void Eors(Condition cond, Register rd, Register rn, const Operand& operand) { 1750 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 1751 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1752 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1753 VIXL_ASSERT(allow_macro_instructions_); 1754 VIXL_ASSERT(OutsideITBlock()); 1755 MacroEmissionCheckScope guard(this); 1756 ITScope it_scope(this, &cond, guard); 1757 eors(cond, rd, rn, operand); 1758 } 1759 void Eors(Register rd, Register rn, const Operand& operand) { 1760 Eors(al, rd, rn, operand); 1761 } 1762 1763 void Fldmdbx(Condition cond, 1764 Register rn, 1765 WriteBack write_back, 1766 DRegisterList dreglist) { 1767 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1768 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1769 VIXL_ASSERT(allow_macro_instructions_); 1770 VIXL_ASSERT(OutsideITBlock()); 1771 MacroEmissionCheckScope guard(this); 1772 ITScope it_scope(this, &cond, guard); 1773 fldmdbx(cond, rn, write_back, dreglist); 1774 } 1775 void Fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1776 Fldmdbx(al, rn, write_back, dreglist); 1777 } 1778 1779 void Fldmiax(Condition cond, 1780 Register rn, 1781 WriteBack write_back, 1782 DRegisterList dreglist) { 1783 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1784 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1785 VIXL_ASSERT(allow_macro_instructions_); 1786 VIXL_ASSERT(OutsideITBlock()); 1787 MacroEmissionCheckScope guard(this); 1788 ITScope it_scope(this, &cond, guard); 1789 fldmiax(cond, rn, write_back, dreglist); 1790 } 1791 void Fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1792 Fldmiax(al, rn, write_back, dreglist); 1793 } 1794 1795 void Fstmdbx(Condition cond, 1796 Register rn, 1797 WriteBack write_back, 1798 DRegisterList dreglist) { 1799 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1800 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1801 VIXL_ASSERT(allow_macro_instructions_); 1802 VIXL_ASSERT(OutsideITBlock()); 1803 MacroEmissionCheckScope guard(this); 1804 ITScope it_scope(this, &cond, guard); 1805 fstmdbx(cond, rn, write_back, dreglist); 1806 } 1807 void Fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 1808 Fstmdbx(al, rn, write_back, dreglist); 1809 } 1810 1811 void Fstmiax(Condition cond, 1812 Register rn, 1813 WriteBack write_back, 1814 DRegisterList dreglist) { 1815 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1816 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 1817 VIXL_ASSERT(allow_macro_instructions_); 1818 VIXL_ASSERT(OutsideITBlock()); 1819 MacroEmissionCheckScope guard(this); 1820 ITScope it_scope(this, &cond, guard); 1821 fstmiax(cond, rn, write_back, dreglist); 1822 } 1823 void Fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 1824 Fstmiax(al, rn, write_back, dreglist); 1825 } 1826 1827 void Hlt(Condition cond, uint32_t imm) { 1828 VIXL_ASSERT(allow_macro_instructions_); 1829 VIXL_ASSERT(OutsideITBlock()); 1830 MacroEmissionCheckScope guard(this); 1831 ITScope it_scope(this, &cond, guard); 1832 hlt(cond, imm); 1833 } 1834 void Hlt(uint32_t imm) { Hlt(al, imm); } 1835 1836 void Hvc(Condition cond, uint32_t imm) { 1837 VIXL_ASSERT(allow_macro_instructions_); 1838 VIXL_ASSERT(OutsideITBlock()); 1839 MacroEmissionCheckScope guard(this); 1840 ITScope it_scope(this, &cond, guard); 1841 hvc(cond, imm); 1842 } 1843 void Hvc(uint32_t imm) { Hvc(al, imm); } 1844 1845 void Isb(Condition cond, MemoryBarrier option) { 1846 VIXL_ASSERT(allow_macro_instructions_); 1847 VIXL_ASSERT(OutsideITBlock()); 1848 MacroEmissionCheckScope guard(this); 1849 ITScope it_scope(this, &cond, guard); 1850 isb(cond, option); 1851 } 1852 void Isb(MemoryBarrier option) { Isb(al, option); } 1853 1854 void Lda(Condition cond, Register rt, const MemOperand& operand) { 1855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1856 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1857 VIXL_ASSERT(allow_macro_instructions_); 1858 VIXL_ASSERT(OutsideITBlock()); 1859 MacroEmissionCheckScope guard(this); 1860 ITScope it_scope(this, &cond, guard); 1861 lda(cond, rt, operand); 1862 } 1863 void Lda(Register rt, const MemOperand& operand) { Lda(al, rt, operand); } 1864 1865 void Ldab(Condition cond, Register rt, const MemOperand& operand) { 1866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1867 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1868 VIXL_ASSERT(allow_macro_instructions_); 1869 VIXL_ASSERT(OutsideITBlock()); 1870 MacroEmissionCheckScope guard(this); 1871 ITScope it_scope(this, &cond, guard); 1872 ldab(cond, rt, operand); 1873 } 1874 void Ldab(Register rt, const MemOperand& operand) { Ldab(al, rt, operand); } 1875 1876 void Ldaex(Condition cond, Register rt, const MemOperand& operand) { 1877 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1878 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1879 VIXL_ASSERT(allow_macro_instructions_); 1880 VIXL_ASSERT(OutsideITBlock()); 1881 MacroEmissionCheckScope guard(this); 1882 ITScope it_scope(this, &cond, guard); 1883 ldaex(cond, rt, operand); 1884 } 1885 void Ldaex(Register rt, const MemOperand& operand) { Ldaex(al, rt, operand); } 1886 1887 void Ldaexb(Condition cond, Register rt, const MemOperand& operand) { 1888 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1889 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1890 VIXL_ASSERT(allow_macro_instructions_); 1891 VIXL_ASSERT(OutsideITBlock()); 1892 MacroEmissionCheckScope guard(this); 1893 ITScope it_scope(this, &cond, guard); 1894 ldaexb(cond, rt, operand); 1895 } 1896 void Ldaexb(Register rt, const MemOperand& operand) { 1897 Ldaexb(al, rt, operand); 1898 } 1899 1900 void Ldaexd(Condition cond, 1901 Register rt, 1902 Register rt2, 1903 const MemOperand& operand) { 1904 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 1906 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1907 VIXL_ASSERT(allow_macro_instructions_); 1908 VIXL_ASSERT(OutsideITBlock()); 1909 MacroEmissionCheckScope guard(this); 1910 ITScope it_scope(this, &cond, guard); 1911 ldaexd(cond, rt, rt2, operand); 1912 } 1913 void Ldaexd(Register rt, Register rt2, const MemOperand& operand) { 1914 Ldaexd(al, rt, rt2, operand); 1915 } 1916 1917 void Ldaexh(Condition cond, Register rt, const MemOperand& operand) { 1918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1919 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1920 VIXL_ASSERT(allow_macro_instructions_); 1921 VIXL_ASSERT(OutsideITBlock()); 1922 MacroEmissionCheckScope guard(this); 1923 ITScope it_scope(this, &cond, guard); 1924 ldaexh(cond, rt, operand); 1925 } 1926 void Ldaexh(Register rt, const MemOperand& operand) { 1927 Ldaexh(al, rt, operand); 1928 } 1929 1930 void Ldah(Condition cond, Register rt, const MemOperand& operand) { 1931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 1932 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 1933 VIXL_ASSERT(allow_macro_instructions_); 1934 VIXL_ASSERT(OutsideITBlock()); 1935 MacroEmissionCheckScope guard(this); 1936 ITScope it_scope(this, &cond, guard); 1937 ldah(cond, rt, operand); 1938 } 1939 void Ldah(Register rt, const MemOperand& operand) { Ldah(al, rt, operand); } 1940 1941 void Ldm(Condition cond, 1942 Register rn, 1943 WriteBack write_back, 1944 RegisterList registers) { 1945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1946 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1947 VIXL_ASSERT(allow_macro_instructions_); 1948 VIXL_ASSERT(OutsideITBlock()); 1949 MacroEmissionCheckScope guard(this); 1950 ITScope it_scope(this, &cond, guard); 1951 ldm(cond, rn, write_back, registers); 1952 } 1953 void Ldm(Register rn, WriteBack write_back, RegisterList registers) { 1954 Ldm(al, rn, write_back, registers); 1955 } 1956 1957 void Ldmda(Condition cond, 1958 Register rn, 1959 WriteBack write_back, 1960 RegisterList registers) { 1961 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1962 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1963 VIXL_ASSERT(allow_macro_instructions_); 1964 VIXL_ASSERT(OutsideITBlock()); 1965 MacroEmissionCheckScope guard(this); 1966 ITScope it_scope(this, &cond, guard); 1967 ldmda(cond, rn, write_back, registers); 1968 } 1969 void Ldmda(Register rn, WriteBack write_back, RegisterList registers) { 1970 Ldmda(al, rn, write_back, registers); 1971 } 1972 1973 void Ldmdb(Condition cond, 1974 Register rn, 1975 WriteBack write_back, 1976 RegisterList registers) { 1977 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1978 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1979 VIXL_ASSERT(allow_macro_instructions_); 1980 VIXL_ASSERT(OutsideITBlock()); 1981 MacroEmissionCheckScope guard(this); 1982 ITScope it_scope(this, &cond, guard); 1983 ldmdb(cond, rn, write_back, registers); 1984 } 1985 void Ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 1986 Ldmdb(al, rn, write_back, registers); 1987 } 1988 1989 void Ldmea(Condition cond, 1990 Register rn, 1991 WriteBack write_back, 1992 RegisterList registers) { 1993 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 1994 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 1995 VIXL_ASSERT(allow_macro_instructions_); 1996 VIXL_ASSERT(OutsideITBlock()); 1997 MacroEmissionCheckScope guard(this); 1998 ITScope it_scope(this, &cond, guard); 1999 ldmea(cond, rn, write_back, registers); 2000 } 2001 void Ldmea(Register rn, WriteBack write_back, RegisterList registers) { 2002 Ldmea(al, rn, write_back, registers); 2003 } 2004 2005 void Ldmed(Condition cond, 2006 Register rn, 2007 WriteBack write_back, 2008 RegisterList registers) { 2009 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2010 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2011 VIXL_ASSERT(allow_macro_instructions_); 2012 VIXL_ASSERT(OutsideITBlock()); 2013 MacroEmissionCheckScope guard(this); 2014 ITScope it_scope(this, &cond, guard); 2015 ldmed(cond, rn, write_back, registers); 2016 } 2017 void Ldmed(Register rn, WriteBack write_back, RegisterList registers) { 2018 Ldmed(al, rn, write_back, registers); 2019 } 2020 2021 void Ldmfa(Condition cond, 2022 Register rn, 2023 WriteBack write_back, 2024 RegisterList registers) { 2025 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2026 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2027 VIXL_ASSERT(allow_macro_instructions_); 2028 VIXL_ASSERT(OutsideITBlock()); 2029 MacroEmissionCheckScope guard(this); 2030 ITScope it_scope(this, &cond, guard); 2031 ldmfa(cond, rn, write_back, registers); 2032 } 2033 void Ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 2034 Ldmfa(al, rn, write_back, registers); 2035 } 2036 2037 void Ldmfd(Condition cond, 2038 Register rn, 2039 WriteBack write_back, 2040 RegisterList registers) { 2041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2042 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2043 VIXL_ASSERT(allow_macro_instructions_); 2044 VIXL_ASSERT(OutsideITBlock()); 2045 MacroEmissionCheckScope guard(this); 2046 ITScope it_scope(this, &cond, guard); 2047 ldmfd(cond, rn, write_back, registers); 2048 } 2049 void Ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 2050 Ldmfd(al, rn, write_back, registers); 2051 } 2052 2053 void Ldmib(Condition cond, 2054 Register rn, 2055 WriteBack write_back, 2056 RegisterList registers) { 2057 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2058 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2059 VIXL_ASSERT(allow_macro_instructions_); 2060 VIXL_ASSERT(OutsideITBlock()); 2061 MacroEmissionCheckScope guard(this); 2062 ITScope it_scope(this, &cond, guard); 2063 ldmib(cond, rn, write_back, registers); 2064 } 2065 void Ldmib(Register rn, WriteBack write_back, RegisterList registers) { 2066 Ldmib(al, rn, write_back, registers); 2067 } 2068 2069 void Ldr(Condition cond, Register rt, const MemOperand& operand) { 2070 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2071 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2072 VIXL_ASSERT(allow_macro_instructions_); 2073 VIXL_ASSERT(OutsideITBlock()); 2074 MacroEmissionCheckScope guard(this); 2075 bool can_use_it = 2076 // LDR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 2077 (operand.IsImmediate() && rt.IsLow() && 2078 operand.GetBaseRegister().IsLow() && 2079 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 2080 (operand.GetAddrMode() == Offset)) || 2081 // LDR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 2082 (operand.IsImmediate() && rt.IsLow() && 2083 operand.GetBaseRegister().IsSP() && 2084 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 2085 (operand.GetAddrMode() == Offset)) || 2086 // LDR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2087 (operand.IsPlainRegister() && rt.IsLow() && 2088 operand.GetBaseRegister().IsLow() && 2089 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2090 (operand.GetAddrMode() == Offset)); 2091 ITScope it_scope(this, &cond, guard, can_use_it); 2092 ldr(cond, rt, operand); 2093 } 2094 void Ldr(Register rt, const MemOperand& operand) { Ldr(al, rt, operand); } 2095 2096 2097 void Ldrb(Condition cond, Register rt, const MemOperand& operand) { 2098 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2099 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2100 VIXL_ASSERT(allow_macro_instructions_); 2101 VIXL_ASSERT(OutsideITBlock()); 2102 MacroEmissionCheckScope guard(this); 2103 bool can_use_it = 2104 // LDRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 2105 (operand.IsImmediate() && rt.IsLow() && 2106 operand.GetBaseRegister().IsLow() && 2107 operand.IsOffsetImmediateWithinRange(0, 31) && 2108 (operand.GetAddrMode() == Offset)) || 2109 // LDRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2110 (operand.IsPlainRegister() && rt.IsLow() && 2111 operand.GetBaseRegister().IsLow() && 2112 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2113 (operand.GetAddrMode() == Offset)); 2114 ITScope it_scope(this, &cond, guard, can_use_it); 2115 ldrb(cond, rt, operand); 2116 } 2117 void Ldrb(Register rt, const MemOperand& operand) { Ldrb(al, rt, operand); } 2118 2119 2120 void Ldrd(Condition cond, 2121 Register rt, 2122 Register rt2, 2123 const MemOperand& operand) { 2124 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2125 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 2126 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2127 VIXL_ASSERT(allow_macro_instructions_); 2128 VIXL_ASSERT(OutsideITBlock()); 2129 MacroEmissionCheckScope guard(this); 2130 ITScope it_scope(this, &cond, guard); 2131 ldrd(cond, rt, rt2, operand); 2132 } 2133 void Ldrd(Register rt, Register rt2, const MemOperand& operand) { 2134 Ldrd(al, rt, rt2, operand); 2135 } 2136 2137 2138 void Ldrex(Condition cond, Register rt, const MemOperand& operand) { 2139 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2140 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2141 VIXL_ASSERT(allow_macro_instructions_); 2142 VIXL_ASSERT(OutsideITBlock()); 2143 MacroEmissionCheckScope guard(this); 2144 ITScope it_scope(this, &cond, guard); 2145 ldrex(cond, rt, operand); 2146 } 2147 void Ldrex(Register rt, const MemOperand& operand) { Ldrex(al, rt, operand); } 2148 2149 void Ldrexb(Condition cond, Register rt, const MemOperand& operand) { 2150 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2151 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2152 VIXL_ASSERT(allow_macro_instructions_); 2153 VIXL_ASSERT(OutsideITBlock()); 2154 MacroEmissionCheckScope guard(this); 2155 ITScope it_scope(this, &cond, guard); 2156 ldrexb(cond, rt, operand); 2157 } 2158 void Ldrexb(Register rt, const MemOperand& operand) { 2159 Ldrexb(al, rt, operand); 2160 } 2161 2162 void Ldrexd(Condition cond, 2163 Register rt, 2164 Register rt2, 2165 const MemOperand& operand) { 2166 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2167 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 2168 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2169 VIXL_ASSERT(allow_macro_instructions_); 2170 VIXL_ASSERT(OutsideITBlock()); 2171 MacroEmissionCheckScope guard(this); 2172 ITScope it_scope(this, &cond, guard); 2173 ldrexd(cond, rt, rt2, operand); 2174 } 2175 void Ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2176 Ldrexd(al, rt, rt2, operand); 2177 } 2178 2179 void Ldrexh(Condition cond, Register rt, const MemOperand& operand) { 2180 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2181 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2182 VIXL_ASSERT(allow_macro_instructions_); 2183 VIXL_ASSERT(OutsideITBlock()); 2184 MacroEmissionCheckScope guard(this); 2185 ITScope it_scope(this, &cond, guard); 2186 ldrexh(cond, rt, operand); 2187 } 2188 void Ldrexh(Register rt, const MemOperand& operand) { 2189 Ldrexh(al, rt, operand); 2190 } 2191 2192 void Ldrh(Condition cond, Register rt, const MemOperand& operand) { 2193 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2194 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2195 VIXL_ASSERT(allow_macro_instructions_); 2196 VIXL_ASSERT(OutsideITBlock()); 2197 MacroEmissionCheckScope guard(this); 2198 bool can_use_it = 2199 // LDRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 2200 (operand.IsImmediate() && rt.IsLow() && 2201 operand.GetBaseRegister().IsLow() && 2202 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 2203 (operand.GetAddrMode() == Offset)) || 2204 // LDRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2205 (operand.IsPlainRegister() && rt.IsLow() && 2206 operand.GetBaseRegister().IsLow() && 2207 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2208 (operand.GetAddrMode() == Offset)); 2209 ITScope it_scope(this, &cond, guard, can_use_it); 2210 ldrh(cond, rt, operand); 2211 } 2212 void Ldrh(Register rt, const MemOperand& operand) { Ldrh(al, rt, operand); } 2213 2214 2215 void Ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2216 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2217 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2218 VIXL_ASSERT(allow_macro_instructions_); 2219 VIXL_ASSERT(OutsideITBlock()); 2220 MacroEmissionCheckScope guard(this); 2221 bool can_use_it = 2222 // LDRSB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2223 operand.IsPlainRegister() && rt.IsLow() && 2224 operand.GetBaseRegister().IsLow() && 2225 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2226 (operand.GetAddrMode() == Offset); 2227 ITScope it_scope(this, &cond, guard, can_use_it); 2228 ldrsb(cond, rt, operand); 2229 } 2230 void Ldrsb(Register rt, const MemOperand& operand) { Ldrsb(al, rt, operand); } 2231 2232 2233 void Ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2234 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2235 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2236 VIXL_ASSERT(allow_macro_instructions_); 2237 VIXL_ASSERT(OutsideITBlock()); 2238 MacroEmissionCheckScope guard(this); 2239 bool can_use_it = 2240 // LDRSH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 2241 operand.IsPlainRegister() && rt.IsLow() && 2242 operand.GetBaseRegister().IsLow() && 2243 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 2244 (operand.GetAddrMode() == Offset); 2245 ITScope it_scope(this, &cond, guard, can_use_it); 2246 ldrsh(cond, rt, operand); 2247 } 2248 void Ldrsh(Register rt, const MemOperand& operand) { Ldrsh(al, rt, operand); } 2249 2250 2251 void Lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2252 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2253 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2254 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2255 VIXL_ASSERT(allow_macro_instructions_); 2256 VIXL_ASSERT(OutsideITBlock()); 2257 MacroEmissionCheckScope guard(this); 2258 bool can_use_it = 2259 // LSL<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 2260 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2261 (operand.GetImmediate() <= 31) && rd.IsLow() && rm.IsLow()) || 2262 // LSL<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2263 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2264 operand.GetBaseRegister().IsLow()); 2265 ITScope it_scope(this, &cond, guard, can_use_it); 2266 lsl(cond, rd, rm, operand); 2267 } 2268 void Lsl(Register rd, Register rm, const Operand& operand) { 2269 Lsl(al, rd, rm, operand); 2270 } 2271 void Lsl(FlagsUpdate flags, 2272 Condition cond, 2273 Register rd, 2274 Register rm, 2275 const Operand& operand) { 2276 switch (flags) { 2277 case LeaveFlags: 2278 Lsl(cond, rd, rm, operand); 2279 break; 2280 case SetFlags: 2281 Lsls(cond, rd, rm, operand); 2282 break; 2283 case DontCare: 2284 bool setflags_is_smaller = 2285 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() && 2286 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2287 (operand.GetImmediate() < 32)) || 2288 (operand.IsPlainRegister() && rd.Is(rm))); 2289 if (setflags_is_smaller) { 2290 Lsls(cond, rd, rm, operand); 2291 } else { 2292 Lsl(cond, rd, rm, operand); 2293 } 2294 break; 2295 } 2296 } 2297 void Lsl(FlagsUpdate flags, 2298 Register rd, 2299 Register rm, 2300 const Operand& operand) { 2301 Lsl(flags, al, rd, rm, operand); 2302 } 2303 2304 void Lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2305 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2306 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2307 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2308 VIXL_ASSERT(allow_macro_instructions_); 2309 VIXL_ASSERT(OutsideITBlock()); 2310 MacroEmissionCheckScope guard(this); 2311 ITScope it_scope(this, &cond, guard); 2312 lsls(cond, rd, rm, operand); 2313 } 2314 void Lsls(Register rd, Register rm, const Operand& operand) { 2315 Lsls(al, rd, rm, operand); 2316 } 2317 2318 void Lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2319 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2320 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2321 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2322 VIXL_ASSERT(allow_macro_instructions_); 2323 VIXL_ASSERT(OutsideITBlock()); 2324 MacroEmissionCheckScope guard(this); 2325 bool can_use_it = 2326 // LSR<c>{<q>} {<Rd>,} <Rm>, #<imm> ; T2 2327 (operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2328 (operand.GetImmediate() <= 32) && rd.IsLow() && rm.IsLow()) || 2329 // LSR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 2330 (operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 2331 operand.GetBaseRegister().IsLow()); 2332 ITScope it_scope(this, &cond, guard, can_use_it); 2333 lsr(cond, rd, rm, operand); 2334 } 2335 void Lsr(Register rd, Register rm, const Operand& operand) { 2336 Lsr(al, rd, rm, operand); 2337 } 2338 void Lsr(FlagsUpdate flags, 2339 Condition cond, 2340 Register rd, 2341 Register rm, 2342 const Operand& operand) { 2343 switch (flags) { 2344 case LeaveFlags: 2345 Lsr(cond, rd, rm, operand); 2346 break; 2347 case SetFlags: 2348 Lsrs(cond, rd, rm, operand); 2349 break; 2350 case DontCare: 2351 bool setflags_is_smaller = 2352 IsUsingT32() && cond.Is(al) && rd.IsLow() && rm.IsLow() && 2353 ((operand.IsImmediate() && (operand.GetImmediate() >= 1) && 2354 (operand.GetImmediate() <= 32)) || 2355 (operand.IsPlainRegister() && rd.Is(rm))); 2356 if (setflags_is_smaller) { 2357 Lsrs(cond, rd, rm, operand); 2358 } else { 2359 Lsr(cond, rd, rm, operand); 2360 } 2361 break; 2362 } 2363 } 2364 void Lsr(FlagsUpdate flags, 2365 Register rd, 2366 Register rm, 2367 const Operand& operand) { 2368 Lsr(flags, al, rd, rm, operand); 2369 } 2370 2371 void Lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2373 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2374 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2375 VIXL_ASSERT(allow_macro_instructions_); 2376 VIXL_ASSERT(OutsideITBlock()); 2377 MacroEmissionCheckScope guard(this); 2378 ITScope it_scope(this, &cond, guard); 2379 lsrs(cond, rd, rm, operand); 2380 } 2381 void Lsrs(Register rd, Register rm, const Operand& operand) { 2382 Lsrs(al, rd, rm, operand); 2383 } 2384 2385 void Mla(Condition cond, Register rd, Register rn, Register rm, Register ra) { 2386 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2387 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2388 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2389 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2390 VIXL_ASSERT(allow_macro_instructions_); 2391 VIXL_ASSERT(OutsideITBlock()); 2392 MacroEmissionCheckScope guard(this); 2393 ITScope it_scope(this, &cond, guard); 2394 mla(cond, rd, rn, rm, ra); 2395 } 2396 void Mla(Register rd, Register rn, Register rm, Register ra) { 2397 Mla(al, rd, rn, rm, ra); 2398 } 2399 void Mla(FlagsUpdate flags, 2400 Condition cond, 2401 Register rd, 2402 Register rn, 2403 Register rm, 2404 Register ra) { 2405 switch (flags) { 2406 case LeaveFlags: 2407 Mla(cond, rd, rn, rm, ra); 2408 break; 2409 case SetFlags: 2410 Mlas(cond, rd, rn, rm, ra); 2411 break; 2412 case DontCare: 2413 Mla(cond, rd, rn, rm, ra); 2414 break; 2415 } 2416 } 2417 void Mla( 2418 FlagsUpdate flags, Register rd, Register rn, Register rm, Register ra) { 2419 Mla(flags, al, rd, rn, rm, ra); 2420 } 2421 2422 void Mlas( 2423 Condition cond, Register rd, Register rn, Register rm, Register ra) { 2424 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2425 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2426 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2427 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2428 VIXL_ASSERT(allow_macro_instructions_); 2429 VIXL_ASSERT(OutsideITBlock()); 2430 MacroEmissionCheckScope guard(this); 2431 ITScope it_scope(this, &cond, guard); 2432 mlas(cond, rd, rn, rm, ra); 2433 } 2434 void Mlas(Register rd, Register rn, Register rm, Register ra) { 2435 Mlas(al, rd, rn, rm, ra); 2436 } 2437 2438 void Mls(Condition cond, Register rd, Register rn, Register rm, Register ra) { 2439 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2440 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2441 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2442 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 2443 VIXL_ASSERT(allow_macro_instructions_); 2444 VIXL_ASSERT(OutsideITBlock()); 2445 MacroEmissionCheckScope guard(this); 2446 ITScope it_scope(this, &cond, guard); 2447 mls(cond, rd, rn, rm, ra); 2448 } 2449 void Mls(Register rd, Register rn, Register rm, Register ra) { 2450 Mls(al, rd, rn, rm, ra); 2451 } 2452 2453 void Mov(Condition cond, Register rd, const Operand& operand) { 2454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2455 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2456 VIXL_ASSERT(allow_macro_instructions_); 2457 VIXL_ASSERT(OutsideITBlock()); 2458 MacroEmissionCheckScope guard(this); 2459 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) { 2460 return; 2461 } 2462 bool can_use_it = 2463 // MOV<c>{<q>} <Rd>, #<imm8> ; T1 2464 (operand.IsImmediate() && rd.IsLow() && 2465 (operand.GetImmediate() <= 255)) || 2466 // MOV{<c>}{<q>} <Rd>, <Rm> ; T1 2467 (operand.IsPlainRegister() && !rd.IsPC() && 2468 !operand.GetBaseRegister().IsPC()) || 2469 // MOV<c>{<q>} <Rd>, <Rm> {, <shift> #<amount>} ; T2 2470 (operand.IsImmediateShiftedRegister() && rd.IsLow() && 2471 operand.GetBaseRegister().IsLow() && 2472 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2473 operand.GetShift().Is(ASR))) || 2474 // MOV<c>{<q>} <Rdm>, <Rdm>, LSL <Rs> ; T1 2475 // MOV<c>{<q>} <Rdm>, <Rdm>, LSR <Rs> ; T1 2476 // MOV<c>{<q>} <Rdm>, <Rdm>, ASR <Rs> ; T1 2477 // MOV<c>{<q>} <Rdm>, <Rdm>, ROR <Rs> ; T1 2478 (operand.IsRegisterShiftedRegister() && 2479 rd.Is(operand.GetBaseRegister()) && rd.IsLow() && 2480 (operand.GetShift().Is(LSL) || operand.GetShift().Is(LSR) || 2481 operand.GetShift().Is(ASR) || operand.GetShift().Is(ROR)) && 2482 operand.GetShiftRegister().IsLow()); 2483 ITScope it_scope(this, &cond, guard, can_use_it); 2484 mov(cond, rd, operand); 2485 } 2486 void Mov(Register rd, const Operand& operand) { Mov(al, rd, operand); } 2487 void Mov(FlagsUpdate flags, 2488 Condition cond, 2489 Register rd, 2490 const Operand& operand) { 2491 switch (flags) { 2492 case LeaveFlags: 2493 Mov(cond, rd, operand); 2494 break; 2495 case SetFlags: 2496 Movs(cond, rd, operand); 2497 break; 2498 case DontCare: 2499 if (operand.IsPlainRegister() && rd.Is(operand.GetBaseRegister())) { 2500 return; 2501 } 2502 bool setflags_is_smaller = 2503 IsUsingT32() && cond.Is(al) && 2504 ((operand.IsImmediateShiftedRegister() && rd.IsLow() && 2505 operand.GetBaseRegister().IsLow() && 2506 (operand.GetShiftAmount() >= 1) && 2507 (((operand.GetShiftAmount() <= 32) && 2508 ((operand.GetShift().IsLSR() || operand.GetShift().IsASR()))) || 2509 ((operand.GetShiftAmount() < 32) && 2510 operand.GetShift().IsLSL()))) || 2511 (operand.IsRegisterShiftedRegister() && rd.IsLow() && 2512 operand.GetBaseRegister().Is(rd) && 2513 operand.GetShiftRegister().IsLow() && 2514 (operand.GetShift().IsLSL() || operand.GetShift().IsLSR() || 2515 operand.GetShift().IsASR() || operand.GetShift().IsROR())) || 2516 (operand.IsImmediate() && rd.IsLow() && 2517 (operand.GetImmediate() < 256))); 2518 if (setflags_is_smaller) { 2519 Movs(cond, rd, operand); 2520 } else { 2521 Mov(cond, rd, operand); 2522 } 2523 break; 2524 } 2525 } 2526 void Mov(FlagsUpdate flags, Register rd, const Operand& operand) { 2527 Mov(flags, al, rd, operand); 2528 } 2529 2530 void Movs(Condition cond, Register rd, const Operand& operand) { 2531 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2532 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2533 VIXL_ASSERT(allow_macro_instructions_); 2534 VIXL_ASSERT(OutsideITBlock()); 2535 MacroEmissionCheckScope guard(this); 2536 ITScope it_scope(this, &cond, guard); 2537 movs(cond, rd, operand); 2538 } 2539 void Movs(Register rd, const Operand& operand) { Movs(al, rd, operand); } 2540 2541 void Movt(Condition cond, Register rd, const Operand& operand) { 2542 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2543 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2544 VIXL_ASSERT(allow_macro_instructions_); 2545 VIXL_ASSERT(OutsideITBlock()); 2546 MacroEmissionCheckScope guard(this); 2547 ITScope it_scope(this, &cond, guard); 2548 movt(cond, rd, operand); 2549 } 2550 void Movt(Register rd, const Operand& operand) { Movt(al, rd, operand); } 2551 2552 void Mrs(Condition cond, Register rd, SpecialRegister spec_reg) { 2553 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2554 VIXL_ASSERT(allow_macro_instructions_); 2555 VIXL_ASSERT(OutsideITBlock()); 2556 MacroEmissionCheckScope guard(this); 2557 ITScope it_scope(this, &cond, guard); 2558 mrs(cond, rd, spec_reg); 2559 } 2560 void Mrs(Register rd, SpecialRegister spec_reg) { Mrs(al, rd, spec_reg); } 2561 2562 void Msr(Condition cond, 2563 MaskedSpecialRegister spec_reg, 2564 const Operand& operand) { 2565 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2566 VIXL_ASSERT(allow_macro_instructions_); 2567 VIXL_ASSERT(OutsideITBlock()); 2568 MacroEmissionCheckScope guard(this); 2569 ITScope it_scope(this, &cond, guard); 2570 msr(cond, spec_reg, operand); 2571 } 2572 void Msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2573 Msr(al, spec_reg, operand); 2574 } 2575 2576 void Mul(Condition cond, Register rd, Register rn, Register rm) { 2577 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2578 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2579 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2580 VIXL_ASSERT(allow_macro_instructions_); 2581 VIXL_ASSERT(OutsideITBlock()); 2582 MacroEmissionCheckScope guard(this); 2583 bool can_use_it = 2584 // MUL<c>{<q>} <Rdm>, <Rn>{, <Rdm>} ; T1 2585 rd.Is(rm) && rn.IsLow() && rm.IsLow(); 2586 ITScope it_scope(this, &cond, guard, can_use_it); 2587 mul(cond, rd, rn, rm); 2588 } 2589 void Mul(Register rd, Register rn, Register rm) { Mul(al, rd, rn, rm); } 2590 void Mul(FlagsUpdate flags, 2591 Condition cond, 2592 Register rd, 2593 Register rn, 2594 Register rm) { 2595 switch (flags) { 2596 case LeaveFlags: 2597 Mul(cond, rd, rn, rm); 2598 break; 2599 case SetFlags: 2600 Muls(cond, rd, rn, rm); 2601 break; 2602 case DontCare: 2603 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2604 rn.IsLow() && rm.Is(rd); 2605 if (setflags_is_smaller) { 2606 Muls(cond, rd, rn, rm); 2607 } else { 2608 Mul(cond, rd, rn, rm); 2609 } 2610 break; 2611 } 2612 } 2613 void Mul(FlagsUpdate flags, Register rd, Register rn, Register rm) { 2614 Mul(flags, al, rd, rn, rm); 2615 } 2616 2617 void Muls(Condition cond, Register rd, Register rn, Register rm) { 2618 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2619 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2620 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2621 VIXL_ASSERT(allow_macro_instructions_); 2622 VIXL_ASSERT(OutsideITBlock()); 2623 MacroEmissionCheckScope guard(this); 2624 ITScope it_scope(this, &cond, guard); 2625 muls(cond, rd, rn, rm); 2626 } 2627 void Muls(Register rd, Register rn, Register rm) { Muls(al, rd, rn, rm); } 2628 2629 void Mvn(Condition cond, Register rd, const Operand& operand) { 2630 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2631 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2632 VIXL_ASSERT(allow_macro_instructions_); 2633 VIXL_ASSERT(OutsideITBlock()); 2634 MacroEmissionCheckScope guard(this); 2635 bool can_use_it = 2636 // MVN<c>{<q>} <Rd>, <Rm> ; T1 2637 operand.IsPlainRegister() && rd.IsLow() && 2638 operand.GetBaseRegister().IsLow(); 2639 ITScope it_scope(this, &cond, guard, can_use_it); 2640 mvn(cond, rd, operand); 2641 } 2642 void Mvn(Register rd, const Operand& operand) { Mvn(al, rd, operand); } 2643 void Mvn(FlagsUpdate flags, 2644 Condition cond, 2645 Register rd, 2646 const Operand& operand) { 2647 switch (flags) { 2648 case LeaveFlags: 2649 Mvn(cond, rd, operand); 2650 break; 2651 case SetFlags: 2652 Mvns(cond, rd, operand); 2653 break; 2654 case DontCare: 2655 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2656 operand.IsPlainRegister() && 2657 operand.GetBaseRegister().IsLow(); 2658 if (setflags_is_smaller) { 2659 Mvns(cond, rd, operand); 2660 } else { 2661 Mvn(cond, rd, operand); 2662 } 2663 break; 2664 } 2665 } 2666 void Mvn(FlagsUpdate flags, Register rd, const Operand& operand) { 2667 Mvn(flags, al, rd, operand); 2668 } 2669 2670 void Mvns(Condition cond, Register rd, const Operand& operand) { 2671 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2672 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2673 VIXL_ASSERT(allow_macro_instructions_); 2674 VIXL_ASSERT(OutsideITBlock()); 2675 MacroEmissionCheckScope guard(this); 2676 ITScope it_scope(this, &cond, guard); 2677 mvns(cond, rd, operand); 2678 } 2679 void Mvns(Register rd, const Operand& operand) { Mvns(al, rd, operand); } 2680 2681 void Nop(Condition cond) { 2682 VIXL_ASSERT(allow_macro_instructions_); 2683 VIXL_ASSERT(OutsideITBlock()); 2684 MacroEmissionCheckScope guard(this); 2685 ITScope it_scope(this, &cond, guard); 2686 nop(cond); 2687 } 2688 void Nop() { Nop(al); } 2689 2690 void Orn(Condition cond, Register rd, Register rn, const Operand& operand) { 2691 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2693 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2694 VIXL_ASSERT(allow_macro_instructions_); 2695 VIXL_ASSERT(OutsideITBlock()); 2696 MacroEmissionCheckScope guard(this); 2697 if (cond.Is(al) && operand.IsImmediate()) { 2698 uint32_t immediate = operand.GetImmediate(); 2699 if (immediate == 0) { 2700 mvn(rd, 0); 2701 return; 2702 } 2703 if ((immediate == 0xffffffff) && rd.Is(rn)) { 2704 return; 2705 } 2706 } 2707 ITScope it_scope(this, &cond, guard); 2708 orn(cond, rd, rn, operand); 2709 } 2710 void Orn(Register rd, Register rn, const Operand& operand) { 2711 Orn(al, rd, rn, operand); 2712 } 2713 void Orn(FlagsUpdate flags, 2714 Condition cond, 2715 Register rd, 2716 Register rn, 2717 const Operand& operand) { 2718 switch (flags) { 2719 case LeaveFlags: 2720 Orn(cond, rd, rn, operand); 2721 break; 2722 case SetFlags: 2723 Orns(cond, rd, rn, operand); 2724 break; 2725 case DontCare: 2726 Orn(cond, rd, rn, operand); 2727 break; 2728 } 2729 } 2730 void Orn(FlagsUpdate flags, 2731 Register rd, 2732 Register rn, 2733 const Operand& operand) { 2734 Orn(flags, al, rd, rn, operand); 2735 } 2736 2737 void Orns(Condition cond, Register rd, Register rn, const Operand& operand) { 2738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2739 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2740 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2741 VIXL_ASSERT(allow_macro_instructions_); 2742 VIXL_ASSERT(OutsideITBlock()); 2743 MacroEmissionCheckScope guard(this); 2744 ITScope it_scope(this, &cond, guard); 2745 orns(cond, rd, rn, operand); 2746 } 2747 void Orns(Register rd, Register rn, const Operand& operand) { 2748 Orns(al, rd, rn, operand); 2749 } 2750 2751 void Orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2753 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2754 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2755 VIXL_ASSERT(allow_macro_instructions_); 2756 VIXL_ASSERT(OutsideITBlock()); 2757 MacroEmissionCheckScope guard(this); 2758 if (rd.Is(rn) && operand.IsPlainRegister() && 2759 rd.Is(operand.GetBaseRegister())) { 2760 return; 2761 } 2762 if (cond.Is(al) && operand.IsImmediate()) { 2763 uint32_t immediate = operand.GetImmediate(); 2764 if ((immediate == 0) && rd.Is(rn)) { 2765 return; 2766 } 2767 if (immediate == 0xffffffff) { 2768 mvn(rd, 0); 2769 return; 2770 } 2771 } 2772 bool can_use_it = 2773 // ORR<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 2774 operand.IsPlainRegister() && rd.Is(rn) && rn.IsLow() && 2775 operand.GetBaseRegister().IsLow(); 2776 ITScope it_scope(this, &cond, guard, can_use_it); 2777 orr(cond, rd, rn, operand); 2778 } 2779 void Orr(Register rd, Register rn, const Operand& operand) { 2780 Orr(al, rd, rn, operand); 2781 } 2782 void Orr(FlagsUpdate flags, 2783 Condition cond, 2784 Register rd, 2785 Register rn, 2786 const Operand& operand) { 2787 switch (flags) { 2788 case LeaveFlags: 2789 Orr(cond, rd, rn, operand); 2790 break; 2791 case SetFlags: 2792 Orrs(cond, rd, rn, operand); 2793 break; 2794 case DontCare: 2795 if (operand.IsPlainRegister() && rd.Is(rn) && 2796 rd.Is(operand.GetBaseRegister())) { 2797 return; 2798 } 2799 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 2800 rn.Is(rd) && operand.IsPlainRegister() && 2801 operand.GetBaseRegister().IsLow(); 2802 if (setflags_is_smaller) { 2803 Orrs(cond, rd, rn, operand); 2804 } else { 2805 Orr(cond, rd, rn, operand); 2806 } 2807 break; 2808 } 2809 } 2810 void Orr(FlagsUpdate flags, 2811 Register rd, 2812 Register rn, 2813 const Operand& operand) { 2814 Orr(flags, al, rd, rn, operand); 2815 } 2816 2817 void Orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2818 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2819 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2820 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2821 VIXL_ASSERT(allow_macro_instructions_); 2822 VIXL_ASSERT(OutsideITBlock()); 2823 MacroEmissionCheckScope guard(this); 2824 ITScope it_scope(this, &cond, guard); 2825 orrs(cond, rd, rn, operand); 2826 } 2827 void Orrs(Register rd, Register rn, const Operand& operand) { 2828 Orrs(al, rd, rn, operand); 2829 } 2830 2831 void Pkhbt(Condition cond, Register rd, Register rn, const Operand& operand) { 2832 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2833 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2834 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2835 VIXL_ASSERT(allow_macro_instructions_); 2836 VIXL_ASSERT(OutsideITBlock()); 2837 MacroEmissionCheckScope guard(this); 2838 ITScope it_scope(this, &cond, guard); 2839 pkhbt(cond, rd, rn, operand); 2840 } 2841 void Pkhbt(Register rd, Register rn, const Operand& operand) { 2842 Pkhbt(al, rd, rn, operand); 2843 } 2844 2845 void Pkhtb(Condition cond, Register rd, Register rn, const Operand& operand) { 2846 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2847 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2848 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2849 VIXL_ASSERT(allow_macro_instructions_); 2850 VIXL_ASSERT(OutsideITBlock()); 2851 MacroEmissionCheckScope guard(this); 2852 ITScope it_scope(this, &cond, guard); 2853 pkhtb(cond, rd, rn, operand); 2854 } 2855 void Pkhtb(Register rd, Register rn, const Operand& operand) { 2856 Pkhtb(al, rd, rn, operand); 2857 } 2858 2859 2860 void Pld(Condition cond, const MemOperand& operand) { 2861 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2862 VIXL_ASSERT(allow_macro_instructions_); 2863 VIXL_ASSERT(OutsideITBlock()); 2864 MacroEmissionCheckScope guard(this); 2865 ITScope it_scope(this, &cond, guard); 2866 pld(cond, operand); 2867 } 2868 void Pld(const MemOperand& operand) { Pld(al, operand); } 2869 2870 void Pldw(Condition cond, const MemOperand& operand) { 2871 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2872 VIXL_ASSERT(allow_macro_instructions_); 2873 VIXL_ASSERT(OutsideITBlock()); 2874 MacroEmissionCheckScope guard(this); 2875 ITScope it_scope(this, &cond, guard); 2876 pldw(cond, operand); 2877 } 2878 void Pldw(const MemOperand& operand) { Pldw(al, operand); } 2879 2880 void Pli(Condition cond, const MemOperand& operand) { 2881 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 2882 VIXL_ASSERT(allow_macro_instructions_); 2883 VIXL_ASSERT(OutsideITBlock()); 2884 MacroEmissionCheckScope guard(this); 2885 ITScope it_scope(this, &cond, guard); 2886 pli(cond, operand); 2887 } 2888 void Pli(const MemOperand& operand) { Pli(al, operand); } 2889 2890 2891 void Pop(Condition cond, RegisterList registers) { 2892 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2893 VIXL_ASSERT(allow_macro_instructions_); 2894 VIXL_ASSERT(OutsideITBlock()); 2895 MacroEmissionCheckScope guard(this); 2896 ITScope it_scope(this, &cond, guard); 2897 pop(cond, registers); 2898 } 2899 void Pop(RegisterList registers) { Pop(al, registers); } 2900 2901 void Pop(Condition cond, Register rt) { 2902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2903 VIXL_ASSERT(allow_macro_instructions_); 2904 VIXL_ASSERT(OutsideITBlock()); 2905 MacroEmissionCheckScope guard(this); 2906 ITScope it_scope(this, &cond, guard); 2907 pop(cond, rt); 2908 } 2909 void Pop(Register rt) { Pop(al, rt); } 2910 2911 void Push(Condition cond, RegisterList registers) { 2912 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 2913 VIXL_ASSERT(allow_macro_instructions_); 2914 VIXL_ASSERT(OutsideITBlock()); 2915 MacroEmissionCheckScope guard(this); 2916 ITScope it_scope(this, &cond, guard); 2917 push(cond, registers); 2918 } 2919 void Push(RegisterList registers) { Push(al, registers); } 2920 2921 void Push(Condition cond, Register rt) { 2922 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 2923 VIXL_ASSERT(allow_macro_instructions_); 2924 VIXL_ASSERT(OutsideITBlock()); 2925 MacroEmissionCheckScope guard(this); 2926 ITScope it_scope(this, &cond, guard); 2927 push(cond, rt); 2928 } 2929 void Push(Register rt) { Push(al, rt); } 2930 2931 void Qadd(Condition cond, Register rd, Register rm, Register rn) { 2932 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2933 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2934 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2935 VIXL_ASSERT(allow_macro_instructions_); 2936 VIXL_ASSERT(OutsideITBlock()); 2937 MacroEmissionCheckScope guard(this); 2938 ITScope it_scope(this, &cond, guard); 2939 qadd(cond, rd, rm, rn); 2940 } 2941 void Qadd(Register rd, Register rm, Register rn) { Qadd(al, rd, rm, rn); } 2942 2943 void Qadd16(Condition cond, Register rd, Register rn, Register rm) { 2944 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2947 VIXL_ASSERT(allow_macro_instructions_); 2948 VIXL_ASSERT(OutsideITBlock()); 2949 MacroEmissionCheckScope guard(this); 2950 ITScope it_scope(this, &cond, guard); 2951 qadd16(cond, rd, rn, rm); 2952 } 2953 void Qadd16(Register rd, Register rn, Register rm) { Qadd16(al, rd, rn, rm); } 2954 2955 void Qadd8(Condition cond, Register rd, Register rn, Register rm) { 2956 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2957 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2958 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2959 VIXL_ASSERT(allow_macro_instructions_); 2960 VIXL_ASSERT(OutsideITBlock()); 2961 MacroEmissionCheckScope guard(this); 2962 ITScope it_scope(this, &cond, guard); 2963 qadd8(cond, rd, rn, rm); 2964 } 2965 void Qadd8(Register rd, Register rn, Register rm) { Qadd8(al, rd, rn, rm); } 2966 2967 void Qasx(Condition cond, Register rd, Register rn, Register rm) { 2968 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2969 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2971 VIXL_ASSERT(allow_macro_instructions_); 2972 VIXL_ASSERT(OutsideITBlock()); 2973 MacroEmissionCheckScope guard(this); 2974 ITScope it_scope(this, &cond, guard); 2975 qasx(cond, rd, rn, rm); 2976 } 2977 void Qasx(Register rd, Register rn, Register rm) { Qasx(al, rd, rn, rm); } 2978 2979 void Qdadd(Condition cond, Register rd, Register rm, Register rn) { 2980 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2981 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2982 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2983 VIXL_ASSERT(allow_macro_instructions_); 2984 VIXL_ASSERT(OutsideITBlock()); 2985 MacroEmissionCheckScope guard(this); 2986 ITScope it_scope(this, &cond, guard); 2987 qdadd(cond, rd, rm, rn); 2988 } 2989 void Qdadd(Register rd, Register rm, Register rn) { Qdadd(al, rd, rm, rn); } 2990 2991 void Qdsub(Condition cond, Register rd, Register rm, Register rn) { 2992 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 2993 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 2994 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 2995 VIXL_ASSERT(allow_macro_instructions_); 2996 VIXL_ASSERT(OutsideITBlock()); 2997 MacroEmissionCheckScope guard(this); 2998 ITScope it_scope(this, &cond, guard); 2999 qdsub(cond, rd, rm, rn); 3000 } 3001 void Qdsub(Register rd, Register rm, Register rn) { Qdsub(al, rd, rm, rn); } 3002 3003 void Qsax(Condition cond, Register rd, Register rn, Register rm) { 3004 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3005 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3006 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3007 VIXL_ASSERT(allow_macro_instructions_); 3008 VIXL_ASSERT(OutsideITBlock()); 3009 MacroEmissionCheckScope guard(this); 3010 ITScope it_scope(this, &cond, guard); 3011 qsax(cond, rd, rn, rm); 3012 } 3013 void Qsax(Register rd, Register rn, Register rm) { Qsax(al, rd, rn, rm); } 3014 3015 void Qsub(Condition cond, Register rd, Register rm, Register rn) { 3016 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3017 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3018 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3019 VIXL_ASSERT(allow_macro_instructions_); 3020 VIXL_ASSERT(OutsideITBlock()); 3021 MacroEmissionCheckScope guard(this); 3022 ITScope it_scope(this, &cond, guard); 3023 qsub(cond, rd, rm, rn); 3024 } 3025 void Qsub(Register rd, Register rm, Register rn) { Qsub(al, rd, rm, rn); } 3026 3027 void Qsub16(Condition cond, Register rd, Register rn, Register rm) { 3028 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3029 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3030 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3031 VIXL_ASSERT(allow_macro_instructions_); 3032 VIXL_ASSERT(OutsideITBlock()); 3033 MacroEmissionCheckScope guard(this); 3034 ITScope it_scope(this, &cond, guard); 3035 qsub16(cond, rd, rn, rm); 3036 } 3037 void Qsub16(Register rd, Register rn, Register rm) { Qsub16(al, rd, rn, rm); } 3038 3039 void Qsub8(Condition cond, Register rd, Register rn, Register rm) { 3040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3042 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3043 VIXL_ASSERT(allow_macro_instructions_); 3044 VIXL_ASSERT(OutsideITBlock()); 3045 MacroEmissionCheckScope guard(this); 3046 ITScope it_scope(this, &cond, guard); 3047 qsub8(cond, rd, rn, rm); 3048 } 3049 void Qsub8(Register rd, Register rn, Register rm) { Qsub8(al, rd, rn, rm); } 3050 3051 void Rbit(Condition cond, Register rd, Register rm) { 3052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3053 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3054 VIXL_ASSERT(allow_macro_instructions_); 3055 VIXL_ASSERT(OutsideITBlock()); 3056 MacroEmissionCheckScope guard(this); 3057 ITScope it_scope(this, &cond, guard); 3058 rbit(cond, rd, rm); 3059 } 3060 void Rbit(Register rd, Register rm) { Rbit(al, rd, rm); } 3061 3062 void Rev(Condition cond, Register rd, Register rm) { 3063 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3064 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3065 VIXL_ASSERT(allow_macro_instructions_); 3066 VIXL_ASSERT(OutsideITBlock()); 3067 MacroEmissionCheckScope guard(this); 3068 ITScope it_scope(this, &cond, guard); 3069 rev(cond, rd, rm); 3070 } 3071 void Rev(Register rd, Register rm) { Rev(al, rd, rm); } 3072 3073 void Rev16(Condition cond, Register rd, Register rm) { 3074 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3075 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3076 VIXL_ASSERT(allow_macro_instructions_); 3077 VIXL_ASSERT(OutsideITBlock()); 3078 MacroEmissionCheckScope guard(this); 3079 ITScope it_scope(this, &cond, guard); 3080 rev16(cond, rd, rm); 3081 } 3082 void Rev16(Register rd, Register rm) { Rev16(al, rd, rm); } 3083 3084 void Revsh(Condition cond, Register rd, Register rm) { 3085 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3087 VIXL_ASSERT(allow_macro_instructions_); 3088 VIXL_ASSERT(OutsideITBlock()); 3089 MacroEmissionCheckScope guard(this); 3090 ITScope it_scope(this, &cond, guard); 3091 revsh(cond, rd, rm); 3092 } 3093 void Revsh(Register rd, Register rm) { Revsh(al, rd, rm); } 3094 3095 void Ror(Condition cond, Register rd, Register rm, const Operand& operand) { 3096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3097 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3098 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3099 VIXL_ASSERT(allow_macro_instructions_); 3100 VIXL_ASSERT(OutsideITBlock()); 3101 MacroEmissionCheckScope guard(this); 3102 bool can_use_it = 3103 // ROR<c>{<q>} {<Rdm>,} <Rdm>, <Rs> ; T1 3104 operand.IsPlainRegister() && rd.Is(rm) && rd.IsLow() && 3105 operand.GetBaseRegister().IsLow(); 3106 ITScope it_scope(this, &cond, guard, can_use_it); 3107 ror(cond, rd, rm, operand); 3108 } 3109 void Ror(Register rd, Register rm, const Operand& operand) { 3110 Ror(al, rd, rm, operand); 3111 } 3112 void Ror(FlagsUpdate flags, 3113 Condition cond, 3114 Register rd, 3115 Register rm, 3116 const Operand& operand) { 3117 switch (flags) { 3118 case LeaveFlags: 3119 Ror(cond, rd, rm, operand); 3120 break; 3121 case SetFlags: 3122 Rors(cond, rd, rm, operand); 3123 break; 3124 case DontCare: 3125 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 3126 rm.IsLow() && operand.IsPlainRegister() && 3127 rd.Is(rm); 3128 if (setflags_is_smaller) { 3129 Rors(cond, rd, rm, operand); 3130 } else { 3131 Ror(cond, rd, rm, operand); 3132 } 3133 break; 3134 } 3135 } 3136 void Ror(FlagsUpdate flags, 3137 Register rd, 3138 Register rm, 3139 const Operand& operand) { 3140 Ror(flags, al, rd, rm, operand); 3141 } 3142 3143 void Rors(Condition cond, Register rd, Register rm, const Operand& operand) { 3144 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3145 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3146 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3147 VIXL_ASSERT(allow_macro_instructions_); 3148 VIXL_ASSERT(OutsideITBlock()); 3149 MacroEmissionCheckScope guard(this); 3150 ITScope it_scope(this, &cond, guard); 3151 rors(cond, rd, rm, operand); 3152 } 3153 void Rors(Register rd, Register rm, const Operand& operand) { 3154 Rors(al, rd, rm, operand); 3155 } 3156 3157 void Rrx(Condition cond, Register rd, Register rm) { 3158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3159 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3160 VIXL_ASSERT(allow_macro_instructions_); 3161 VIXL_ASSERT(OutsideITBlock()); 3162 MacroEmissionCheckScope guard(this); 3163 ITScope it_scope(this, &cond, guard); 3164 rrx(cond, rd, rm); 3165 } 3166 void Rrx(Register rd, Register rm) { Rrx(al, rd, rm); } 3167 void Rrx(FlagsUpdate flags, Condition cond, Register rd, Register rm) { 3168 switch (flags) { 3169 case LeaveFlags: 3170 Rrx(cond, rd, rm); 3171 break; 3172 case SetFlags: 3173 Rrxs(cond, rd, rm); 3174 break; 3175 case DontCare: 3176 Rrx(cond, rd, rm); 3177 break; 3178 } 3179 } 3180 void Rrx(FlagsUpdate flags, Register rd, Register rm) { 3181 Rrx(flags, al, rd, rm); 3182 } 3183 3184 void Rrxs(Condition cond, Register rd, Register rm) { 3185 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3186 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3187 VIXL_ASSERT(allow_macro_instructions_); 3188 VIXL_ASSERT(OutsideITBlock()); 3189 MacroEmissionCheckScope guard(this); 3190 ITScope it_scope(this, &cond, guard); 3191 rrxs(cond, rd, rm); 3192 } 3193 void Rrxs(Register rd, Register rm) { Rrxs(al, rd, rm); } 3194 3195 void Rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 3196 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3197 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3198 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3199 VIXL_ASSERT(allow_macro_instructions_); 3200 VIXL_ASSERT(OutsideITBlock()); 3201 MacroEmissionCheckScope guard(this); 3202 bool can_use_it = 3203 // RSB<c>{<q>} {<Rd>, }<Rn>, #0 ; T1 3204 operand.IsImmediate() && rd.IsLow() && rn.IsLow() && 3205 (operand.GetImmediate() == 0); 3206 ITScope it_scope(this, &cond, guard, can_use_it); 3207 rsb(cond, rd, rn, operand); 3208 } 3209 void Rsb(Register rd, Register rn, const Operand& operand) { 3210 Rsb(al, rd, rn, operand); 3211 } 3212 void Rsb(FlagsUpdate flags, 3213 Condition cond, 3214 Register rd, 3215 Register rn, 3216 const Operand& operand) { 3217 switch (flags) { 3218 case LeaveFlags: 3219 Rsb(cond, rd, rn, operand); 3220 break; 3221 case SetFlags: 3222 Rsbs(cond, rd, rn, operand); 3223 break; 3224 case DontCare: 3225 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 3226 rn.IsLow() && operand.IsImmediate() && 3227 (operand.GetImmediate() == 0); 3228 if (setflags_is_smaller) { 3229 Rsbs(cond, rd, rn, operand); 3230 } else { 3231 Rsb(cond, rd, rn, operand); 3232 } 3233 break; 3234 } 3235 } 3236 void Rsb(FlagsUpdate flags, 3237 Register rd, 3238 Register rn, 3239 const Operand& operand) { 3240 Rsb(flags, al, rd, rn, operand); 3241 } 3242 3243 void Rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 3244 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3245 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3246 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3247 VIXL_ASSERT(allow_macro_instructions_); 3248 VIXL_ASSERT(OutsideITBlock()); 3249 MacroEmissionCheckScope guard(this); 3250 ITScope it_scope(this, &cond, guard); 3251 rsbs(cond, rd, rn, operand); 3252 } 3253 void Rsbs(Register rd, Register rn, const Operand& operand) { 3254 Rsbs(al, rd, rn, operand); 3255 } 3256 3257 void Rsc(Condition cond, Register rd, Register rn, const Operand& operand) { 3258 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3259 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3260 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3261 VIXL_ASSERT(allow_macro_instructions_); 3262 VIXL_ASSERT(OutsideITBlock()); 3263 MacroEmissionCheckScope guard(this); 3264 ITScope it_scope(this, &cond, guard); 3265 rsc(cond, rd, rn, operand); 3266 } 3267 void Rsc(Register rd, Register rn, const Operand& operand) { 3268 Rsc(al, rd, rn, operand); 3269 } 3270 void Rsc(FlagsUpdate flags, 3271 Condition cond, 3272 Register rd, 3273 Register rn, 3274 const Operand& operand) { 3275 switch (flags) { 3276 case LeaveFlags: 3277 Rsc(cond, rd, rn, operand); 3278 break; 3279 case SetFlags: 3280 Rscs(cond, rd, rn, operand); 3281 break; 3282 case DontCare: 3283 Rsc(cond, rd, rn, operand); 3284 break; 3285 } 3286 } 3287 void Rsc(FlagsUpdate flags, 3288 Register rd, 3289 Register rn, 3290 const Operand& operand) { 3291 Rsc(flags, al, rd, rn, operand); 3292 } 3293 3294 void Rscs(Condition cond, Register rd, Register rn, const Operand& operand) { 3295 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3296 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3297 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3298 VIXL_ASSERT(allow_macro_instructions_); 3299 VIXL_ASSERT(OutsideITBlock()); 3300 MacroEmissionCheckScope guard(this); 3301 ITScope it_scope(this, &cond, guard); 3302 rscs(cond, rd, rn, operand); 3303 } 3304 void Rscs(Register rd, Register rn, const Operand& operand) { 3305 Rscs(al, rd, rn, operand); 3306 } 3307 3308 void Sadd16(Condition cond, Register rd, Register rn, Register rm) { 3309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3310 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3311 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3312 VIXL_ASSERT(allow_macro_instructions_); 3313 VIXL_ASSERT(OutsideITBlock()); 3314 MacroEmissionCheckScope guard(this); 3315 ITScope it_scope(this, &cond, guard); 3316 sadd16(cond, rd, rn, rm); 3317 } 3318 void Sadd16(Register rd, Register rn, Register rm) { Sadd16(al, rd, rn, rm); } 3319 3320 void Sadd8(Condition cond, Register rd, Register rn, Register rm) { 3321 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3322 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3323 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3324 VIXL_ASSERT(allow_macro_instructions_); 3325 VIXL_ASSERT(OutsideITBlock()); 3326 MacroEmissionCheckScope guard(this); 3327 ITScope it_scope(this, &cond, guard); 3328 sadd8(cond, rd, rn, rm); 3329 } 3330 void Sadd8(Register rd, Register rn, Register rm) { Sadd8(al, rd, rn, rm); } 3331 3332 void Sasx(Condition cond, Register rd, Register rn, Register rm) { 3333 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3334 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3335 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3336 VIXL_ASSERT(allow_macro_instructions_); 3337 VIXL_ASSERT(OutsideITBlock()); 3338 MacroEmissionCheckScope guard(this); 3339 ITScope it_scope(this, &cond, guard); 3340 sasx(cond, rd, rn, rm); 3341 } 3342 void Sasx(Register rd, Register rn, Register rm) { Sasx(al, rd, rn, rm); } 3343 3344 void Sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 3345 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3346 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3347 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3348 VIXL_ASSERT(allow_macro_instructions_); 3349 VIXL_ASSERT(OutsideITBlock()); 3350 MacroEmissionCheckScope guard(this); 3351 bool can_use_it = 3352 // SBC<c>{<q>} {<Rdn>,} <Rdn>, <Rm> ; T1 3353 operand.IsPlainRegister() && rn.IsLow() && rd.Is(rn) && 3354 operand.GetBaseRegister().IsLow(); 3355 ITScope it_scope(this, &cond, guard, can_use_it); 3356 sbc(cond, rd, rn, operand); 3357 } 3358 void Sbc(Register rd, Register rn, const Operand& operand) { 3359 Sbc(al, rd, rn, operand); 3360 } 3361 void Sbc(FlagsUpdate flags, 3362 Condition cond, 3363 Register rd, 3364 Register rn, 3365 const Operand& operand) { 3366 switch (flags) { 3367 case LeaveFlags: 3368 Sbc(cond, rd, rn, operand); 3369 break; 3370 case SetFlags: 3371 Sbcs(cond, rd, rn, operand); 3372 break; 3373 case DontCare: 3374 bool setflags_is_smaller = IsUsingT32() && cond.Is(al) && rd.IsLow() && 3375 rn.Is(rd) && operand.IsPlainRegister() && 3376 operand.GetBaseRegister().IsLow(); 3377 if (setflags_is_smaller) { 3378 Sbcs(cond, rd, rn, operand); 3379 } else { 3380 Sbc(cond, rd, rn, operand); 3381 } 3382 break; 3383 } 3384 } 3385 void Sbc(FlagsUpdate flags, 3386 Register rd, 3387 Register rn, 3388 const Operand& operand) { 3389 Sbc(flags, al, rd, rn, operand); 3390 } 3391 3392 void Sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 3393 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3394 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3395 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 3396 VIXL_ASSERT(allow_macro_instructions_); 3397 VIXL_ASSERT(OutsideITBlock()); 3398 MacroEmissionCheckScope guard(this); 3399 ITScope it_scope(this, &cond, guard); 3400 sbcs(cond, rd, rn, operand); 3401 } 3402 void Sbcs(Register rd, Register rn, const Operand& operand) { 3403 Sbcs(al, rd, rn, operand); 3404 } 3405 3406 void Sbfx( 3407 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { 3408 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3409 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3410 VIXL_ASSERT(allow_macro_instructions_); 3411 VIXL_ASSERT(OutsideITBlock()); 3412 MacroEmissionCheckScope guard(this); 3413 ITScope it_scope(this, &cond, guard); 3414 sbfx(cond, rd, rn, lsb, width); 3415 } 3416 void Sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) { 3417 Sbfx(al, rd, rn, lsb, width); 3418 } 3419 3420 void Sdiv(Condition cond, Register rd, Register rn, Register rm) { 3421 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3422 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3423 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3424 VIXL_ASSERT(allow_macro_instructions_); 3425 VIXL_ASSERT(OutsideITBlock()); 3426 MacroEmissionCheckScope guard(this); 3427 ITScope it_scope(this, &cond, guard); 3428 sdiv(cond, rd, rn, rm); 3429 } 3430 void Sdiv(Register rd, Register rn, Register rm) { Sdiv(al, rd, rn, rm); } 3431 3432 void Sel(Condition cond, Register rd, Register rn, Register rm) { 3433 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3434 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3435 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3436 VIXL_ASSERT(allow_macro_instructions_); 3437 VIXL_ASSERT(OutsideITBlock()); 3438 MacroEmissionCheckScope guard(this); 3439 ITScope it_scope(this, &cond, guard); 3440 sel(cond, rd, rn, rm); 3441 } 3442 void Sel(Register rd, Register rn, Register rm) { Sel(al, rd, rn, rm); } 3443 3444 void Shadd16(Condition cond, Register rd, Register rn, Register rm) { 3445 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3446 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3447 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3448 VIXL_ASSERT(allow_macro_instructions_); 3449 VIXL_ASSERT(OutsideITBlock()); 3450 MacroEmissionCheckScope guard(this); 3451 ITScope it_scope(this, &cond, guard); 3452 shadd16(cond, rd, rn, rm); 3453 } 3454 void Shadd16(Register rd, Register rn, Register rm) { 3455 Shadd16(al, rd, rn, rm); 3456 } 3457 3458 void Shadd8(Condition cond, Register rd, Register rn, Register rm) { 3459 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3460 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3461 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3462 VIXL_ASSERT(allow_macro_instructions_); 3463 VIXL_ASSERT(OutsideITBlock()); 3464 MacroEmissionCheckScope guard(this); 3465 ITScope it_scope(this, &cond, guard); 3466 shadd8(cond, rd, rn, rm); 3467 } 3468 void Shadd8(Register rd, Register rn, Register rm) { Shadd8(al, rd, rn, rm); } 3469 3470 void Shasx(Condition cond, Register rd, Register rn, Register rm) { 3471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3473 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3474 VIXL_ASSERT(allow_macro_instructions_); 3475 VIXL_ASSERT(OutsideITBlock()); 3476 MacroEmissionCheckScope guard(this); 3477 ITScope it_scope(this, &cond, guard); 3478 shasx(cond, rd, rn, rm); 3479 } 3480 void Shasx(Register rd, Register rn, Register rm) { Shasx(al, rd, rn, rm); } 3481 3482 void Shsax(Condition cond, Register rd, Register rn, Register rm) { 3483 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3484 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3486 VIXL_ASSERT(allow_macro_instructions_); 3487 VIXL_ASSERT(OutsideITBlock()); 3488 MacroEmissionCheckScope guard(this); 3489 ITScope it_scope(this, &cond, guard); 3490 shsax(cond, rd, rn, rm); 3491 } 3492 void Shsax(Register rd, Register rn, Register rm) { Shsax(al, rd, rn, rm); } 3493 3494 void Shsub16(Condition cond, Register rd, Register rn, Register rm) { 3495 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3496 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3497 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3498 VIXL_ASSERT(allow_macro_instructions_); 3499 VIXL_ASSERT(OutsideITBlock()); 3500 MacroEmissionCheckScope guard(this); 3501 ITScope it_scope(this, &cond, guard); 3502 shsub16(cond, rd, rn, rm); 3503 } 3504 void Shsub16(Register rd, Register rn, Register rm) { 3505 Shsub16(al, rd, rn, rm); 3506 } 3507 3508 void Shsub8(Condition cond, Register rd, Register rn, Register rm) { 3509 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3510 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3511 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3512 VIXL_ASSERT(allow_macro_instructions_); 3513 VIXL_ASSERT(OutsideITBlock()); 3514 MacroEmissionCheckScope guard(this); 3515 ITScope it_scope(this, &cond, guard); 3516 shsub8(cond, rd, rn, rm); 3517 } 3518 void Shsub8(Register rd, Register rn, Register rm) { Shsub8(al, rd, rn, rm); } 3519 3520 void Smlabb( 3521 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3522 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3523 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3524 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3525 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3526 VIXL_ASSERT(allow_macro_instructions_); 3527 VIXL_ASSERT(OutsideITBlock()); 3528 MacroEmissionCheckScope guard(this); 3529 ITScope it_scope(this, &cond, guard); 3530 smlabb(cond, rd, rn, rm, ra); 3531 } 3532 void Smlabb(Register rd, Register rn, Register rm, Register ra) { 3533 Smlabb(al, rd, rn, rm, ra); 3534 } 3535 3536 void Smlabt( 3537 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3538 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3539 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3540 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3541 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3542 VIXL_ASSERT(allow_macro_instructions_); 3543 VIXL_ASSERT(OutsideITBlock()); 3544 MacroEmissionCheckScope guard(this); 3545 ITScope it_scope(this, &cond, guard); 3546 smlabt(cond, rd, rn, rm, ra); 3547 } 3548 void Smlabt(Register rd, Register rn, Register rm, Register ra) { 3549 Smlabt(al, rd, rn, rm, ra); 3550 } 3551 3552 void Smlad( 3553 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3554 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3555 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3556 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3557 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3558 VIXL_ASSERT(allow_macro_instructions_); 3559 VIXL_ASSERT(OutsideITBlock()); 3560 MacroEmissionCheckScope guard(this); 3561 ITScope it_scope(this, &cond, guard); 3562 smlad(cond, rd, rn, rm, ra); 3563 } 3564 void Smlad(Register rd, Register rn, Register rm, Register ra) { 3565 Smlad(al, rd, rn, rm, ra); 3566 } 3567 3568 void Smladx( 3569 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3570 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3571 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3572 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3573 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3574 VIXL_ASSERT(allow_macro_instructions_); 3575 VIXL_ASSERT(OutsideITBlock()); 3576 MacroEmissionCheckScope guard(this); 3577 ITScope it_scope(this, &cond, guard); 3578 smladx(cond, rd, rn, rm, ra); 3579 } 3580 void Smladx(Register rd, Register rn, Register rm, Register ra) { 3581 Smladx(al, rd, rn, rm, ra); 3582 } 3583 3584 void Smlal( 3585 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3586 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3587 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3588 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3589 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3590 VIXL_ASSERT(allow_macro_instructions_); 3591 VIXL_ASSERT(OutsideITBlock()); 3592 MacroEmissionCheckScope guard(this); 3593 ITScope it_scope(this, &cond, guard); 3594 smlal(cond, rdlo, rdhi, rn, rm); 3595 } 3596 void Smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3597 Smlal(al, rdlo, rdhi, rn, rm); 3598 } 3599 3600 void Smlalbb( 3601 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3602 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3603 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3604 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3605 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3606 VIXL_ASSERT(allow_macro_instructions_); 3607 VIXL_ASSERT(OutsideITBlock()); 3608 MacroEmissionCheckScope guard(this); 3609 ITScope it_scope(this, &cond, guard); 3610 smlalbb(cond, rdlo, rdhi, rn, rm); 3611 } 3612 void Smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3613 Smlalbb(al, rdlo, rdhi, rn, rm); 3614 } 3615 3616 void Smlalbt( 3617 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3618 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3619 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3620 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3621 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3622 VIXL_ASSERT(allow_macro_instructions_); 3623 VIXL_ASSERT(OutsideITBlock()); 3624 MacroEmissionCheckScope guard(this); 3625 ITScope it_scope(this, &cond, guard); 3626 smlalbt(cond, rdlo, rdhi, rn, rm); 3627 } 3628 void Smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3629 Smlalbt(al, rdlo, rdhi, rn, rm); 3630 } 3631 3632 void Smlald( 3633 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3634 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3635 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3638 VIXL_ASSERT(allow_macro_instructions_); 3639 VIXL_ASSERT(OutsideITBlock()); 3640 MacroEmissionCheckScope guard(this); 3641 ITScope it_scope(this, &cond, guard); 3642 smlald(cond, rdlo, rdhi, rn, rm); 3643 } 3644 void Smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3645 Smlald(al, rdlo, rdhi, rn, rm); 3646 } 3647 3648 void Smlaldx( 3649 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3650 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3651 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3652 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3653 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3654 VIXL_ASSERT(allow_macro_instructions_); 3655 VIXL_ASSERT(OutsideITBlock()); 3656 MacroEmissionCheckScope guard(this); 3657 ITScope it_scope(this, &cond, guard); 3658 smlaldx(cond, rdlo, rdhi, rn, rm); 3659 } 3660 void Smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3661 Smlaldx(al, rdlo, rdhi, rn, rm); 3662 } 3663 3664 void Smlals( 3665 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3666 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3667 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3668 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3669 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3670 VIXL_ASSERT(allow_macro_instructions_); 3671 VIXL_ASSERT(OutsideITBlock()); 3672 MacroEmissionCheckScope guard(this); 3673 ITScope it_scope(this, &cond, guard); 3674 smlals(cond, rdlo, rdhi, rn, rm); 3675 } 3676 void Smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3677 Smlals(al, rdlo, rdhi, rn, rm); 3678 } 3679 3680 void Smlaltb( 3681 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3682 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3683 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3684 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3685 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3686 VIXL_ASSERT(allow_macro_instructions_); 3687 VIXL_ASSERT(OutsideITBlock()); 3688 MacroEmissionCheckScope guard(this); 3689 ITScope it_scope(this, &cond, guard); 3690 smlaltb(cond, rdlo, rdhi, rn, rm); 3691 } 3692 void Smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3693 Smlaltb(al, rdlo, rdhi, rn, rm); 3694 } 3695 3696 void Smlaltt( 3697 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3699 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3700 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3701 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3702 VIXL_ASSERT(allow_macro_instructions_); 3703 VIXL_ASSERT(OutsideITBlock()); 3704 MacroEmissionCheckScope guard(this); 3705 ITScope it_scope(this, &cond, guard); 3706 smlaltt(cond, rdlo, rdhi, rn, rm); 3707 } 3708 void Smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3709 Smlaltt(al, rdlo, rdhi, rn, rm); 3710 } 3711 3712 void Smlatb( 3713 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3714 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3715 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3716 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3717 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3718 VIXL_ASSERT(allow_macro_instructions_); 3719 VIXL_ASSERT(OutsideITBlock()); 3720 MacroEmissionCheckScope guard(this); 3721 ITScope it_scope(this, &cond, guard); 3722 smlatb(cond, rd, rn, rm, ra); 3723 } 3724 void Smlatb(Register rd, Register rn, Register rm, Register ra) { 3725 Smlatb(al, rd, rn, rm, ra); 3726 } 3727 3728 void Smlatt( 3729 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3730 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3731 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3732 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3733 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3734 VIXL_ASSERT(allow_macro_instructions_); 3735 VIXL_ASSERT(OutsideITBlock()); 3736 MacroEmissionCheckScope guard(this); 3737 ITScope it_scope(this, &cond, guard); 3738 smlatt(cond, rd, rn, rm, ra); 3739 } 3740 void Smlatt(Register rd, Register rn, Register rm, Register ra) { 3741 Smlatt(al, rd, rn, rm, ra); 3742 } 3743 3744 void Smlawb( 3745 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3746 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3747 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3748 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3749 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3750 VIXL_ASSERT(allow_macro_instructions_); 3751 VIXL_ASSERT(OutsideITBlock()); 3752 MacroEmissionCheckScope guard(this); 3753 ITScope it_scope(this, &cond, guard); 3754 smlawb(cond, rd, rn, rm, ra); 3755 } 3756 void Smlawb(Register rd, Register rn, Register rm, Register ra) { 3757 Smlawb(al, rd, rn, rm, ra); 3758 } 3759 3760 void Smlawt( 3761 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3762 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3763 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3764 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3765 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3766 VIXL_ASSERT(allow_macro_instructions_); 3767 VIXL_ASSERT(OutsideITBlock()); 3768 MacroEmissionCheckScope guard(this); 3769 ITScope it_scope(this, &cond, guard); 3770 smlawt(cond, rd, rn, rm, ra); 3771 } 3772 void Smlawt(Register rd, Register rn, Register rm, Register ra) { 3773 Smlawt(al, rd, rn, rm, ra); 3774 } 3775 3776 void Smlsd( 3777 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3779 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3780 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3781 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3782 VIXL_ASSERT(allow_macro_instructions_); 3783 VIXL_ASSERT(OutsideITBlock()); 3784 MacroEmissionCheckScope guard(this); 3785 ITScope it_scope(this, &cond, guard); 3786 smlsd(cond, rd, rn, rm, ra); 3787 } 3788 void Smlsd(Register rd, Register rn, Register rm, Register ra) { 3789 Smlsd(al, rd, rn, rm, ra); 3790 } 3791 3792 void Smlsdx( 3793 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3794 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3795 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3796 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3797 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3798 VIXL_ASSERT(allow_macro_instructions_); 3799 VIXL_ASSERT(OutsideITBlock()); 3800 MacroEmissionCheckScope guard(this); 3801 ITScope it_scope(this, &cond, guard); 3802 smlsdx(cond, rd, rn, rm, ra); 3803 } 3804 void Smlsdx(Register rd, Register rn, Register rm, Register ra) { 3805 Smlsdx(al, rd, rn, rm, ra); 3806 } 3807 3808 void Smlsld( 3809 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3810 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3811 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3812 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3814 VIXL_ASSERT(allow_macro_instructions_); 3815 VIXL_ASSERT(OutsideITBlock()); 3816 MacroEmissionCheckScope guard(this); 3817 ITScope it_scope(this, &cond, guard); 3818 smlsld(cond, rdlo, rdhi, rn, rm); 3819 } 3820 void Smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3821 Smlsld(al, rdlo, rdhi, rn, rm); 3822 } 3823 3824 void Smlsldx( 3825 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3826 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3827 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3828 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3829 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3830 VIXL_ASSERT(allow_macro_instructions_); 3831 VIXL_ASSERT(OutsideITBlock()); 3832 MacroEmissionCheckScope guard(this); 3833 ITScope it_scope(this, &cond, guard); 3834 smlsldx(cond, rdlo, rdhi, rn, rm); 3835 } 3836 void Smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3837 Smlsldx(al, rdlo, rdhi, rn, rm); 3838 } 3839 3840 void Smmla( 3841 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3842 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3843 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3844 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3845 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3846 VIXL_ASSERT(allow_macro_instructions_); 3847 VIXL_ASSERT(OutsideITBlock()); 3848 MacroEmissionCheckScope guard(this); 3849 ITScope it_scope(this, &cond, guard); 3850 smmla(cond, rd, rn, rm, ra); 3851 } 3852 void Smmla(Register rd, Register rn, Register rm, Register ra) { 3853 Smmla(al, rd, rn, rm, ra); 3854 } 3855 3856 void Smmlar( 3857 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3858 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3859 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3860 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3861 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3862 VIXL_ASSERT(allow_macro_instructions_); 3863 VIXL_ASSERT(OutsideITBlock()); 3864 MacroEmissionCheckScope guard(this); 3865 ITScope it_scope(this, &cond, guard); 3866 smmlar(cond, rd, rn, rm, ra); 3867 } 3868 void Smmlar(Register rd, Register rn, Register rm, Register ra) { 3869 Smmlar(al, rd, rn, rm, ra); 3870 } 3871 3872 void Smmls( 3873 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3874 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3875 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3876 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3877 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3878 VIXL_ASSERT(allow_macro_instructions_); 3879 VIXL_ASSERT(OutsideITBlock()); 3880 MacroEmissionCheckScope guard(this); 3881 ITScope it_scope(this, &cond, guard); 3882 smmls(cond, rd, rn, rm, ra); 3883 } 3884 void Smmls(Register rd, Register rn, Register rm, Register ra) { 3885 Smmls(al, rd, rn, rm, ra); 3886 } 3887 3888 void Smmlsr( 3889 Condition cond, Register rd, Register rn, Register rm, Register ra) { 3890 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3891 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3892 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3893 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 3894 VIXL_ASSERT(allow_macro_instructions_); 3895 VIXL_ASSERT(OutsideITBlock()); 3896 MacroEmissionCheckScope guard(this); 3897 ITScope it_scope(this, &cond, guard); 3898 smmlsr(cond, rd, rn, rm, ra); 3899 } 3900 void Smmlsr(Register rd, Register rn, Register rm, Register ra) { 3901 Smmlsr(al, rd, rn, rm, ra); 3902 } 3903 3904 void Smmul(Condition cond, Register rd, Register rn, Register rm) { 3905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3906 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3907 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3908 VIXL_ASSERT(allow_macro_instructions_); 3909 VIXL_ASSERT(OutsideITBlock()); 3910 MacroEmissionCheckScope guard(this); 3911 ITScope it_scope(this, &cond, guard); 3912 smmul(cond, rd, rn, rm); 3913 } 3914 void Smmul(Register rd, Register rn, Register rm) { Smmul(al, rd, rn, rm); } 3915 3916 void Smmulr(Condition cond, Register rd, Register rn, Register rm) { 3917 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3919 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3920 VIXL_ASSERT(allow_macro_instructions_); 3921 VIXL_ASSERT(OutsideITBlock()); 3922 MacroEmissionCheckScope guard(this); 3923 ITScope it_scope(this, &cond, guard); 3924 smmulr(cond, rd, rn, rm); 3925 } 3926 void Smmulr(Register rd, Register rn, Register rm) { Smmulr(al, rd, rn, rm); } 3927 3928 void Smuad(Condition cond, Register rd, Register rn, Register rm) { 3929 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3930 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3932 VIXL_ASSERT(allow_macro_instructions_); 3933 VIXL_ASSERT(OutsideITBlock()); 3934 MacroEmissionCheckScope guard(this); 3935 ITScope it_scope(this, &cond, guard); 3936 smuad(cond, rd, rn, rm); 3937 } 3938 void Smuad(Register rd, Register rn, Register rm) { Smuad(al, rd, rn, rm); } 3939 3940 void Smuadx(Condition cond, Register rd, Register rn, Register rm) { 3941 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3942 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3943 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3944 VIXL_ASSERT(allow_macro_instructions_); 3945 VIXL_ASSERT(OutsideITBlock()); 3946 MacroEmissionCheckScope guard(this); 3947 ITScope it_scope(this, &cond, guard); 3948 smuadx(cond, rd, rn, rm); 3949 } 3950 void Smuadx(Register rd, Register rn, Register rm) { Smuadx(al, rd, rn, rm); } 3951 3952 void Smulbb(Condition cond, Register rd, Register rn, Register rm) { 3953 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3954 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3955 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3956 VIXL_ASSERT(allow_macro_instructions_); 3957 VIXL_ASSERT(OutsideITBlock()); 3958 MacroEmissionCheckScope guard(this); 3959 ITScope it_scope(this, &cond, guard); 3960 smulbb(cond, rd, rn, rm); 3961 } 3962 void Smulbb(Register rd, Register rn, Register rm) { Smulbb(al, rd, rn, rm); } 3963 3964 void Smulbt(Condition cond, Register rd, Register rn, Register rm) { 3965 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 3966 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3967 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3968 VIXL_ASSERT(allow_macro_instructions_); 3969 VIXL_ASSERT(OutsideITBlock()); 3970 MacroEmissionCheckScope guard(this); 3971 ITScope it_scope(this, &cond, guard); 3972 smulbt(cond, rd, rn, rm); 3973 } 3974 void Smulbt(Register rd, Register rn, Register rm) { Smulbt(al, rd, rn, rm); } 3975 3976 void Smull( 3977 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 3978 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 3979 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 3980 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 3981 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 3982 VIXL_ASSERT(allow_macro_instructions_); 3983 VIXL_ASSERT(OutsideITBlock()); 3984 MacroEmissionCheckScope guard(this); 3985 ITScope it_scope(this, &cond, guard); 3986 smull(cond, rdlo, rdhi, rn, rm); 3987 } 3988 void Smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3989 Smull(al, rdlo, rdhi, rn, rm); 3990 } 3991 void Smull(FlagsUpdate flags, 3992 Condition cond, 3993 Register rdlo, 3994 Register rdhi, 3995 Register rn, 3996 Register rm) { 3997 switch (flags) { 3998 case LeaveFlags: 3999 Smull(cond, rdlo, rdhi, rn, rm); 4000 break; 4001 case SetFlags: 4002 Smulls(cond, rdlo, rdhi, rn, rm); 4003 break; 4004 case DontCare: 4005 Smull(cond, rdlo, rdhi, rn, rm); 4006 break; 4007 } 4008 } 4009 void Smull(FlagsUpdate flags, 4010 Register rdlo, 4011 Register rdhi, 4012 Register rn, 4013 Register rm) { 4014 Smull(flags, al, rdlo, rdhi, rn, rm); 4015 } 4016 4017 void Smulls( 4018 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4019 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4020 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4021 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4022 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4023 VIXL_ASSERT(allow_macro_instructions_); 4024 VIXL_ASSERT(OutsideITBlock()); 4025 MacroEmissionCheckScope guard(this); 4026 ITScope it_scope(this, &cond, guard); 4027 smulls(cond, rdlo, rdhi, rn, rm); 4028 } 4029 void Smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 4030 Smulls(al, rdlo, rdhi, rn, rm); 4031 } 4032 4033 void Smultb(Condition cond, Register rd, Register rn, Register rm) { 4034 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4035 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4036 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4037 VIXL_ASSERT(allow_macro_instructions_); 4038 VIXL_ASSERT(OutsideITBlock()); 4039 MacroEmissionCheckScope guard(this); 4040 ITScope it_scope(this, &cond, guard); 4041 smultb(cond, rd, rn, rm); 4042 } 4043 void Smultb(Register rd, Register rn, Register rm) { Smultb(al, rd, rn, rm); } 4044 4045 void Smultt(Condition cond, Register rd, Register rn, Register rm) { 4046 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4047 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4048 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4049 VIXL_ASSERT(allow_macro_instructions_); 4050 VIXL_ASSERT(OutsideITBlock()); 4051 MacroEmissionCheckScope guard(this); 4052 ITScope it_scope(this, &cond, guard); 4053 smultt(cond, rd, rn, rm); 4054 } 4055 void Smultt(Register rd, Register rn, Register rm) { Smultt(al, rd, rn, rm); } 4056 4057 void Smulwb(Condition cond, Register rd, Register rn, Register rm) { 4058 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4059 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4060 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4061 VIXL_ASSERT(allow_macro_instructions_); 4062 VIXL_ASSERT(OutsideITBlock()); 4063 MacroEmissionCheckScope guard(this); 4064 ITScope it_scope(this, &cond, guard); 4065 smulwb(cond, rd, rn, rm); 4066 } 4067 void Smulwb(Register rd, Register rn, Register rm) { Smulwb(al, rd, rn, rm); } 4068 4069 void Smulwt(Condition cond, Register rd, Register rn, Register rm) { 4070 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4071 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4072 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4073 VIXL_ASSERT(allow_macro_instructions_); 4074 VIXL_ASSERT(OutsideITBlock()); 4075 MacroEmissionCheckScope guard(this); 4076 ITScope it_scope(this, &cond, guard); 4077 smulwt(cond, rd, rn, rm); 4078 } 4079 void Smulwt(Register rd, Register rn, Register rm) { Smulwt(al, rd, rn, rm); } 4080 4081 void Smusd(Condition cond, Register rd, Register rn, Register rm) { 4082 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4083 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4084 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4085 VIXL_ASSERT(allow_macro_instructions_); 4086 VIXL_ASSERT(OutsideITBlock()); 4087 MacroEmissionCheckScope guard(this); 4088 ITScope it_scope(this, &cond, guard); 4089 smusd(cond, rd, rn, rm); 4090 } 4091 void Smusd(Register rd, Register rn, Register rm) { Smusd(al, rd, rn, rm); } 4092 4093 void Smusdx(Condition cond, Register rd, Register rn, Register rm) { 4094 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4095 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4097 VIXL_ASSERT(allow_macro_instructions_); 4098 VIXL_ASSERT(OutsideITBlock()); 4099 MacroEmissionCheckScope guard(this); 4100 ITScope it_scope(this, &cond, guard); 4101 smusdx(cond, rd, rn, rm); 4102 } 4103 void Smusdx(Register rd, Register rn, Register rm) { Smusdx(al, rd, rn, rm); } 4104 4105 void Ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 4106 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4107 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4108 VIXL_ASSERT(allow_macro_instructions_); 4109 VIXL_ASSERT(OutsideITBlock()); 4110 MacroEmissionCheckScope guard(this); 4111 ITScope it_scope(this, &cond, guard); 4112 ssat(cond, rd, imm, operand); 4113 } 4114 void Ssat(Register rd, uint32_t imm, const Operand& operand) { 4115 Ssat(al, rd, imm, operand); 4116 } 4117 4118 void Ssat16(Condition cond, Register rd, uint32_t imm, Register rn) { 4119 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4120 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4121 VIXL_ASSERT(allow_macro_instructions_); 4122 VIXL_ASSERT(OutsideITBlock()); 4123 MacroEmissionCheckScope guard(this); 4124 ITScope it_scope(this, &cond, guard); 4125 ssat16(cond, rd, imm, rn); 4126 } 4127 void Ssat16(Register rd, uint32_t imm, Register rn) { 4128 Ssat16(al, rd, imm, rn); 4129 } 4130 4131 void Ssax(Condition cond, Register rd, Register rn, Register rm) { 4132 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4133 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4134 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4135 VIXL_ASSERT(allow_macro_instructions_); 4136 VIXL_ASSERT(OutsideITBlock()); 4137 MacroEmissionCheckScope guard(this); 4138 ITScope it_scope(this, &cond, guard); 4139 ssax(cond, rd, rn, rm); 4140 } 4141 void Ssax(Register rd, Register rn, Register rm) { Ssax(al, rd, rn, rm); } 4142 4143 void Ssub16(Condition cond, Register rd, Register rn, Register rm) { 4144 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4145 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4146 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4147 VIXL_ASSERT(allow_macro_instructions_); 4148 VIXL_ASSERT(OutsideITBlock()); 4149 MacroEmissionCheckScope guard(this); 4150 ITScope it_scope(this, &cond, guard); 4151 ssub16(cond, rd, rn, rm); 4152 } 4153 void Ssub16(Register rd, Register rn, Register rm) { Ssub16(al, rd, rn, rm); } 4154 4155 void Ssub8(Condition cond, Register rd, Register rn, Register rm) { 4156 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4157 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4159 VIXL_ASSERT(allow_macro_instructions_); 4160 VIXL_ASSERT(OutsideITBlock()); 4161 MacroEmissionCheckScope guard(this); 4162 ITScope it_scope(this, &cond, guard); 4163 ssub8(cond, rd, rn, rm); 4164 } 4165 void Ssub8(Register rd, Register rn, Register rm) { Ssub8(al, rd, rn, rm); } 4166 4167 void Stl(Condition cond, Register rt, const MemOperand& operand) { 4168 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4169 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4170 VIXL_ASSERT(allow_macro_instructions_); 4171 VIXL_ASSERT(OutsideITBlock()); 4172 MacroEmissionCheckScope guard(this); 4173 ITScope it_scope(this, &cond, guard); 4174 stl(cond, rt, operand); 4175 } 4176 void Stl(Register rt, const MemOperand& operand) { Stl(al, rt, operand); } 4177 4178 void Stlb(Condition cond, Register rt, const MemOperand& operand) { 4179 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4180 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4181 VIXL_ASSERT(allow_macro_instructions_); 4182 VIXL_ASSERT(OutsideITBlock()); 4183 MacroEmissionCheckScope guard(this); 4184 ITScope it_scope(this, &cond, guard); 4185 stlb(cond, rt, operand); 4186 } 4187 void Stlb(Register rt, const MemOperand& operand) { Stlb(al, rt, operand); } 4188 4189 void Stlex(Condition cond, 4190 Register rd, 4191 Register rt, 4192 const MemOperand& operand) { 4193 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4194 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4195 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4196 VIXL_ASSERT(allow_macro_instructions_); 4197 VIXL_ASSERT(OutsideITBlock()); 4198 MacroEmissionCheckScope guard(this); 4199 ITScope it_scope(this, &cond, guard); 4200 stlex(cond, rd, rt, operand); 4201 } 4202 void Stlex(Register rd, Register rt, const MemOperand& operand) { 4203 Stlex(al, rd, rt, operand); 4204 } 4205 4206 void Stlexb(Condition cond, 4207 Register rd, 4208 Register rt, 4209 const MemOperand& operand) { 4210 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4211 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4212 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4213 VIXL_ASSERT(allow_macro_instructions_); 4214 VIXL_ASSERT(OutsideITBlock()); 4215 MacroEmissionCheckScope guard(this); 4216 ITScope it_scope(this, &cond, guard); 4217 stlexb(cond, rd, rt, operand); 4218 } 4219 void Stlexb(Register rd, Register rt, const MemOperand& operand) { 4220 Stlexb(al, rd, rt, operand); 4221 } 4222 4223 void Stlexd(Condition cond, 4224 Register rd, 4225 Register rt, 4226 Register rt2, 4227 const MemOperand& operand) { 4228 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4229 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4230 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4231 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4232 VIXL_ASSERT(allow_macro_instructions_); 4233 VIXL_ASSERT(OutsideITBlock()); 4234 MacroEmissionCheckScope guard(this); 4235 ITScope it_scope(this, &cond, guard); 4236 stlexd(cond, rd, rt, rt2, operand); 4237 } 4238 void Stlexd(Register rd, 4239 Register rt, 4240 Register rt2, 4241 const MemOperand& operand) { 4242 Stlexd(al, rd, rt, rt2, operand); 4243 } 4244 4245 void Stlexh(Condition cond, 4246 Register rd, 4247 Register rt, 4248 const MemOperand& operand) { 4249 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4250 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4251 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4252 VIXL_ASSERT(allow_macro_instructions_); 4253 VIXL_ASSERT(OutsideITBlock()); 4254 MacroEmissionCheckScope guard(this); 4255 ITScope it_scope(this, &cond, guard); 4256 stlexh(cond, rd, rt, operand); 4257 } 4258 void Stlexh(Register rd, Register rt, const MemOperand& operand) { 4259 Stlexh(al, rd, rt, operand); 4260 } 4261 4262 void Stlh(Condition cond, Register rt, const MemOperand& operand) { 4263 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4264 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4265 VIXL_ASSERT(allow_macro_instructions_); 4266 VIXL_ASSERT(OutsideITBlock()); 4267 MacroEmissionCheckScope guard(this); 4268 ITScope it_scope(this, &cond, guard); 4269 stlh(cond, rt, operand); 4270 } 4271 void Stlh(Register rt, const MemOperand& operand) { Stlh(al, rt, operand); } 4272 4273 void Stm(Condition cond, 4274 Register rn, 4275 WriteBack write_back, 4276 RegisterList registers) { 4277 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4278 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4279 VIXL_ASSERT(allow_macro_instructions_); 4280 VIXL_ASSERT(OutsideITBlock()); 4281 MacroEmissionCheckScope guard(this); 4282 ITScope it_scope(this, &cond, guard); 4283 stm(cond, rn, write_back, registers); 4284 } 4285 void Stm(Register rn, WriteBack write_back, RegisterList registers) { 4286 Stm(al, rn, write_back, registers); 4287 } 4288 4289 void Stmda(Condition cond, 4290 Register rn, 4291 WriteBack write_back, 4292 RegisterList registers) { 4293 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4294 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4295 VIXL_ASSERT(allow_macro_instructions_); 4296 VIXL_ASSERT(OutsideITBlock()); 4297 MacroEmissionCheckScope guard(this); 4298 ITScope it_scope(this, &cond, guard); 4299 stmda(cond, rn, write_back, registers); 4300 } 4301 void Stmda(Register rn, WriteBack write_back, RegisterList registers) { 4302 Stmda(al, rn, write_back, registers); 4303 } 4304 4305 void Stmdb(Condition cond, 4306 Register rn, 4307 WriteBack write_back, 4308 RegisterList registers) { 4309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4310 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4311 VIXL_ASSERT(allow_macro_instructions_); 4312 VIXL_ASSERT(OutsideITBlock()); 4313 MacroEmissionCheckScope guard(this); 4314 ITScope it_scope(this, &cond, guard); 4315 stmdb(cond, rn, write_back, registers); 4316 } 4317 void Stmdb(Register rn, WriteBack write_back, RegisterList registers) { 4318 Stmdb(al, rn, write_back, registers); 4319 } 4320 4321 void Stmea(Condition cond, 4322 Register rn, 4323 WriteBack write_back, 4324 RegisterList registers) { 4325 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4326 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4327 VIXL_ASSERT(allow_macro_instructions_); 4328 VIXL_ASSERT(OutsideITBlock()); 4329 MacroEmissionCheckScope guard(this); 4330 ITScope it_scope(this, &cond, guard); 4331 stmea(cond, rn, write_back, registers); 4332 } 4333 void Stmea(Register rn, WriteBack write_back, RegisterList registers) { 4334 Stmea(al, rn, write_back, registers); 4335 } 4336 4337 void Stmed(Condition cond, 4338 Register rn, 4339 WriteBack write_back, 4340 RegisterList registers) { 4341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4342 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4343 VIXL_ASSERT(allow_macro_instructions_); 4344 VIXL_ASSERT(OutsideITBlock()); 4345 MacroEmissionCheckScope guard(this); 4346 ITScope it_scope(this, &cond, guard); 4347 stmed(cond, rn, write_back, registers); 4348 } 4349 void Stmed(Register rn, WriteBack write_back, RegisterList registers) { 4350 Stmed(al, rn, write_back, registers); 4351 } 4352 4353 void Stmfa(Condition cond, 4354 Register rn, 4355 WriteBack write_back, 4356 RegisterList registers) { 4357 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4358 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4359 VIXL_ASSERT(allow_macro_instructions_); 4360 VIXL_ASSERT(OutsideITBlock()); 4361 MacroEmissionCheckScope guard(this); 4362 ITScope it_scope(this, &cond, guard); 4363 stmfa(cond, rn, write_back, registers); 4364 } 4365 void Stmfa(Register rn, WriteBack write_back, RegisterList registers) { 4366 Stmfa(al, rn, write_back, registers); 4367 } 4368 4369 void Stmfd(Condition cond, 4370 Register rn, 4371 WriteBack write_back, 4372 RegisterList registers) { 4373 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4374 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4375 VIXL_ASSERT(allow_macro_instructions_); 4376 VIXL_ASSERT(OutsideITBlock()); 4377 MacroEmissionCheckScope guard(this); 4378 ITScope it_scope(this, &cond, guard); 4379 stmfd(cond, rn, write_back, registers); 4380 } 4381 void Stmfd(Register rn, WriteBack write_back, RegisterList registers) { 4382 Stmfd(al, rn, write_back, registers); 4383 } 4384 4385 void Stmib(Condition cond, 4386 Register rn, 4387 WriteBack write_back, 4388 RegisterList registers) { 4389 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4390 VIXL_ASSERT(!AliasesAvailableScratchRegister(registers)); 4391 VIXL_ASSERT(allow_macro_instructions_); 4392 VIXL_ASSERT(OutsideITBlock()); 4393 MacroEmissionCheckScope guard(this); 4394 ITScope it_scope(this, &cond, guard); 4395 stmib(cond, rn, write_back, registers); 4396 } 4397 void Stmib(Register rn, WriteBack write_back, RegisterList registers) { 4398 Stmib(al, rn, write_back, registers); 4399 } 4400 4401 void Str(Condition cond, Register rt, const MemOperand& operand) { 4402 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4403 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4404 VIXL_ASSERT(allow_macro_instructions_); 4405 VIXL_ASSERT(OutsideITBlock()); 4406 MacroEmissionCheckScope guard(this); 4407 bool can_use_it = 4408 // STR{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4409 (operand.IsImmediate() && rt.IsLow() && 4410 operand.GetBaseRegister().IsLow() && 4411 operand.IsOffsetImmediateWithinRange(0, 124, 4) && 4412 (operand.GetAddrMode() == Offset)) || 4413 // STR{<c>}{<q>} <Rt>, [SP{, #{+}<imm>}] ; T2 4414 (operand.IsImmediate() && rt.IsLow() && 4415 operand.GetBaseRegister().IsSP() && 4416 operand.IsOffsetImmediateWithinRange(0, 1020, 4) && 4417 (operand.GetAddrMode() == Offset)) || 4418 // STR{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4419 (operand.IsPlainRegister() && rt.IsLow() && 4420 operand.GetBaseRegister().IsLow() && 4421 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4422 (operand.GetAddrMode() == Offset)); 4423 ITScope it_scope(this, &cond, guard, can_use_it); 4424 str(cond, rt, operand); 4425 } 4426 void Str(Register rt, const MemOperand& operand) { Str(al, rt, operand); } 4427 4428 void Strb(Condition cond, Register rt, const MemOperand& operand) { 4429 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4430 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4431 VIXL_ASSERT(allow_macro_instructions_); 4432 VIXL_ASSERT(OutsideITBlock()); 4433 MacroEmissionCheckScope guard(this); 4434 bool can_use_it = 4435 // STRB{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4436 (operand.IsImmediate() && rt.IsLow() && 4437 operand.GetBaseRegister().IsLow() && 4438 operand.IsOffsetImmediateWithinRange(0, 31) && 4439 (operand.GetAddrMode() == Offset)) || 4440 // STRB{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4441 (operand.IsPlainRegister() && rt.IsLow() && 4442 operand.GetBaseRegister().IsLow() && 4443 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4444 (operand.GetAddrMode() == Offset)); 4445 ITScope it_scope(this, &cond, guard, can_use_it); 4446 strb(cond, rt, operand); 4447 } 4448 void Strb(Register rt, const MemOperand& operand) { Strb(al, rt, operand); } 4449 4450 void Strd(Condition cond, 4451 Register rt, 4452 Register rt2, 4453 const MemOperand& operand) { 4454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4455 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4456 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4457 VIXL_ASSERT(allow_macro_instructions_); 4458 VIXL_ASSERT(OutsideITBlock()); 4459 MacroEmissionCheckScope guard(this); 4460 ITScope it_scope(this, &cond, guard); 4461 strd(cond, rt, rt2, operand); 4462 } 4463 void Strd(Register rt, Register rt2, const MemOperand& operand) { 4464 Strd(al, rt, rt2, operand); 4465 } 4466 4467 void Strex(Condition cond, 4468 Register rd, 4469 Register rt, 4470 const MemOperand& operand) { 4471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4473 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4474 VIXL_ASSERT(allow_macro_instructions_); 4475 VIXL_ASSERT(OutsideITBlock()); 4476 MacroEmissionCheckScope guard(this); 4477 ITScope it_scope(this, &cond, guard); 4478 strex(cond, rd, rt, operand); 4479 } 4480 void Strex(Register rd, Register rt, const MemOperand& operand) { 4481 Strex(al, rd, rt, operand); 4482 } 4483 4484 void Strexb(Condition cond, 4485 Register rd, 4486 Register rt, 4487 const MemOperand& operand) { 4488 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4489 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4490 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4491 VIXL_ASSERT(allow_macro_instructions_); 4492 VIXL_ASSERT(OutsideITBlock()); 4493 MacroEmissionCheckScope guard(this); 4494 ITScope it_scope(this, &cond, guard); 4495 strexb(cond, rd, rt, operand); 4496 } 4497 void Strexb(Register rd, Register rt, const MemOperand& operand) { 4498 Strexb(al, rd, rt, operand); 4499 } 4500 4501 void Strexd(Condition cond, 4502 Register rd, 4503 Register rt, 4504 Register rt2, 4505 const MemOperand& operand) { 4506 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4507 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4508 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 4509 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4510 VIXL_ASSERT(allow_macro_instructions_); 4511 VIXL_ASSERT(OutsideITBlock()); 4512 MacroEmissionCheckScope guard(this); 4513 ITScope it_scope(this, &cond, guard); 4514 strexd(cond, rd, rt, rt2, operand); 4515 } 4516 void Strexd(Register rd, 4517 Register rt, 4518 Register rt2, 4519 const MemOperand& operand) { 4520 Strexd(al, rd, rt, rt2, operand); 4521 } 4522 4523 void Strexh(Condition cond, 4524 Register rd, 4525 Register rt, 4526 const MemOperand& operand) { 4527 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4528 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4529 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4530 VIXL_ASSERT(allow_macro_instructions_); 4531 VIXL_ASSERT(OutsideITBlock()); 4532 MacroEmissionCheckScope guard(this); 4533 ITScope it_scope(this, &cond, guard); 4534 strexh(cond, rd, rt, operand); 4535 } 4536 void Strexh(Register rd, Register rt, const MemOperand& operand) { 4537 Strexh(al, rd, rt, operand); 4538 } 4539 4540 void Strh(Condition cond, Register rt, const MemOperand& operand) { 4541 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 4542 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4543 VIXL_ASSERT(allow_macro_instructions_); 4544 VIXL_ASSERT(OutsideITBlock()); 4545 MacroEmissionCheckScope guard(this); 4546 bool can_use_it = 4547 // STRH{<c>}{<q>} <Rt>, [<Rn> {, #{+}<imm>}] ; T1 4548 (operand.IsImmediate() && rt.IsLow() && 4549 operand.GetBaseRegister().IsLow() && 4550 operand.IsOffsetImmediateWithinRange(0, 62, 2) && 4551 (operand.GetAddrMode() == Offset)) || 4552 // STRH{<c>}{<q>} <Rt>, [<Rn>, {+}<Rm>] ; T1 4553 (operand.IsPlainRegister() && rt.IsLow() && 4554 operand.GetBaseRegister().IsLow() && 4555 operand.GetOffsetRegister().IsLow() && operand.GetSign().IsPlus() && 4556 (operand.GetAddrMode() == Offset)); 4557 ITScope it_scope(this, &cond, guard, can_use_it); 4558 strh(cond, rt, operand); 4559 } 4560 void Strh(Register rt, const MemOperand& operand) { Strh(al, rt, operand); } 4561 4562 void Sub(Condition cond, Register rd, Register rn, const Operand& operand) { 4563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4564 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4565 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4566 VIXL_ASSERT(allow_macro_instructions_); 4567 VIXL_ASSERT(OutsideITBlock()); 4568 MacroEmissionCheckScope guard(this); 4569 if (cond.Is(al) && rd.Is(rn) && operand.IsImmediate()) { 4570 uint32_t immediate = operand.GetImmediate(); 4571 if (immediate == 0) { 4572 return; 4573 } 4574 } 4575 bool can_use_it = 4576 // SUB<c>{<q>} <Rd>, <Rn>, #<imm3> ; T1 4577 (operand.IsImmediate() && (operand.GetImmediate() <= 7) && rn.IsLow() && 4578 rd.IsLow()) || 4579 // SUB<c>{<q>} {<Rdn>,} <Rdn>, #<imm8> ; T2 4580 (operand.IsImmediate() && (operand.GetImmediate() <= 255) && 4581 rd.IsLow() && rn.Is(rd)) || 4582 // SUB<c>{<q>} <Rd>, <Rn>, <Rm> 4583 (operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 4584 operand.GetBaseRegister().IsLow()); 4585 ITScope it_scope(this, &cond, guard, can_use_it); 4586 sub(cond, rd, rn, operand); 4587 } 4588 void Sub(Register rd, Register rn, const Operand& operand) { 4589 Sub(al, rd, rn, operand); 4590 } 4591 void Sub(FlagsUpdate flags, 4592 Condition cond, 4593 Register rd, 4594 Register rn, 4595 const Operand& operand) { 4596 switch (flags) { 4597 case LeaveFlags: 4598 Sub(cond, rd, rn, operand); 4599 break; 4600 case SetFlags: 4601 Subs(cond, rd, rn, operand); 4602 break; 4603 case DontCare: 4604 bool setflags_is_smaller = 4605 IsUsingT32() && cond.Is(al) && 4606 ((operand.IsPlainRegister() && rd.IsLow() && rn.IsLow() && 4607 operand.GetBaseRegister().IsLow()) || 4608 (operand.IsImmediate() && 4609 ((rd.IsLow() && rn.IsLow() && (operand.GetImmediate() < 8)) || 4610 (rd.IsLow() && rn.Is(rd) && (operand.GetImmediate() < 256))))); 4611 if (setflags_is_smaller) { 4612 Subs(cond, rd, rn, operand); 4613 } else { 4614 bool changed_op_is_smaller = 4615 operand.IsImmediate() && (operand.GetSignedImmediate() < 0) && 4616 ((rd.IsLow() && rn.IsLow() && 4617 (operand.GetSignedImmediate() >= -7)) || 4618 (rd.IsLow() && rn.Is(rd) && 4619 (operand.GetSignedImmediate() >= -255))); 4620 if (changed_op_is_smaller) { 4621 Adds(cond, rd, rn, -operand.GetSignedImmediate()); 4622 } else { 4623 Sub(cond, rd, rn, operand); 4624 } 4625 } 4626 break; 4627 } 4628 } 4629 void Sub(FlagsUpdate flags, 4630 Register rd, 4631 Register rn, 4632 const Operand& operand) { 4633 Sub(flags, al, rd, rn, operand); 4634 } 4635 4636 void Subs(Condition cond, Register rd, Register rn, const Operand& operand) { 4637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4638 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4639 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4640 VIXL_ASSERT(allow_macro_instructions_); 4641 VIXL_ASSERT(OutsideITBlock()); 4642 MacroEmissionCheckScope guard(this); 4643 ITScope it_scope(this, &cond, guard); 4644 subs(cond, rd, rn, operand); 4645 } 4646 void Subs(Register rd, Register rn, const Operand& operand) { 4647 Subs(al, rd, rn, operand); 4648 } 4649 4650 void Svc(Condition cond, uint32_t imm) { 4651 VIXL_ASSERT(allow_macro_instructions_); 4652 VIXL_ASSERT(OutsideITBlock()); 4653 MacroEmissionCheckScope guard(this); 4654 ITScope it_scope(this, &cond, guard); 4655 svc(cond, imm); 4656 } 4657 void Svc(uint32_t imm) { Svc(al, imm); } 4658 4659 void Sxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 4660 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4662 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4663 VIXL_ASSERT(allow_macro_instructions_); 4664 VIXL_ASSERT(OutsideITBlock()); 4665 MacroEmissionCheckScope guard(this); 4666 ITScope it_scope(this, &cond, guard); 4667 sxtab(cond, rd, rn, operand); 4668 } 4669 void Sxtab(Register rd, Register rn, const Operand& operand) { 4670 Sxtab(al, rd, rn, operand); 4671 } 4672 4673 void Sxtab16(Condition cond, 4674 Register rd, 4675 Register rn, 4676 const Operand& operand) { 4677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4678 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4679 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4680 VIXL_ASSERT(allow_macro_instructions_); 4681 VIXL_ASSERT(OutsideITBlock()); 4682 MacroEmissionCheckScope guard(this); 4683 ITScope it_scope(this, &cond, guard); 4684 sxtab16(cond, rd, rn, operand); 4685 } 4686 void Sxtab16(Register rd, Register rn, const Operand& operand) { 4687 Sxtab16(al, rd, rn, operand); 4688 } 4689 4690 void Sxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 4691 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4693 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4694 VIXL_ASSERT(allow_macro_instructions_); 4695 VIXL_ASSERT(OutsideITBlock()); 4696 MacroEmissionCheckScope guard(this); 4697 ITScope it_scope(this, &cond, guard); 4698 sxtah(cond, rd, rn, operand); 4699 } 4700 void Sxtah(Register rd, Register rn, const Operand& operand) { 4701 Sxtah(al, rd, rn, operand); 4702 } 4703 4704 void Sxtb(Condition cond, Register rd, const Operand& operand) { 4705 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4706 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4707 VIXL_ASSERT(allow_macro_instructions_); 4708 VIXL_ASSERT(OutsideITBlock()); 4709 MacroEmissionCheckScope guard(this); 4710 ITScope it_scope(this, &cond, guard); 4711 sxtb(cond, rd, operand); 4712 } 4713 void Sxtb(Register rd, const Operand& operand) { Sxtb(al, rd, operand); } 4714 4715 void Sxtb16(Condition cond, Register rd, const Operand& operand) { 4716 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4717 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4718 VIXL_ASSERT(allow_macro_instructions_); 4719 VIXL_ASSERT(OutsideITBlock()); 4720 MacroEmissionCheckScope guard(this); 4721 ITScope it_scope(this, &cond, guard); 4722 sxtb16(cond, rd, operand); 4723 } 4724 void Sxtb16(Register rd, const Operand& operand) { Sxtb16(al, rd, operand); } 4725 4726 void Sxth(Condition cond, Register rd, const Operand& operand) { 4727 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4728 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4729 VIXL_ASSERT(allow_macro_instructions_); 4730 VIXL_ASSERT(OutsideITBlock()); 4731 MacroEmissionCheckScope guard(this); 4732 ITScope it_scope(this, &cond, guard); 4733 sxth(cond, rd, operand); 4734 } 4735 void Sxth(Register rd, const Operand& operand) { Sxth(al, rd, operand); } 4736 4737 void Teq(Condition cond, Register rn, const Operand& operand) { 4738 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4739 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4740 VIXL_ASSERT(allow_macro_instructions_); 4741 VIXL_ASSERT(OutsideITBlock()); 4742 MacroEmissionCheckScope guard(this); 4743 ITScope it_scope(this, &cond, guard); 4744 teq(cond, rn, operand); 4745 } 4746 void Teq(Register rn, const Operand& operand) { Teq(al, rn, operand); } 4747 4748 void Tst(Condition cond, Register rn, const Operand& operand) { 4749 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4750 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 4751 VIXL_ASSERT(allow_macro_instructions_); 4752 VIXL_ASSERT(OutsideITBlock()); 4753 MacroEmissionCheckScope guard(this); 4754 bool can_use_it = 4755 // TST{<c>}{<q>} <Rn>, <Rm> ; T1 4756 operand.IsPlainRegister() && rn.IsLow() && 4757 operand.GetBaseRegister().IsLow(); 4758 ITScope it_scope(this, &cond, guard, can_use_it); 4759 tst(cond, rn, operand); 4760 } 4761 void Tst(Register rn, const Operand& operand) { Tst(al, rn, operand); } 4762 4763 void Uadd16(Condition cond, Register rd, Register rn, Register rm) { 4764 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4765 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4766 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4767 VIXL_ASSERT(allow_macro_instructions_); 4768 VIXL_ASSERT(OutsideITBlock()); 4769 MacroEmissionCheckScope guard(this); 4770 ITScope it_scope(this, &cond, guard); 4771 uadd16(cond, rd, rn, rm); 4772 } 4773 void Uadd16(Register rd, Register rn, Register rm) { Uadd16(al, rd, rn, rm); } 4774 4775 void Uadd8(Condition cond, Register rd, Register rn, Register rm) { 4776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4779 VIXL_ASSERT(allow_macro_instructions_); 4780 VIXL_ASSERT(OutsideITBlock()); 4781 MacroEmissionCheckScope guard(this); 4782 ITScope it_scope(this, &cond, guard); 4783 uadd8(cond, rd, rn, rm); 4784 } 4785 void Uadd8(Register rd, Register rn, Register rm) { Uadd8(al, rd, rn, rm); } 4786 4787 void Uasx(Condition cond, Register rd, Register rn, Register rm) { 4788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4790 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4791 VIXL_ASSERT(allow_macro_instructions_); 4792 VIXL_ASSERT(OutsideITBlock()); 4793 MacroEmissionCheckScope guard(this); 4794 ITScope it_scope(this, &cond, guard); 4795 uasx(cond, rd, rn, rm); 4796 } 4797 void Uasx(Register rd, Register rn, Register rm) { Uasx(al, rd, rn, rm); } 4798 4799 void Ubfx( 4800 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width) { 4801 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4802 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4803 VIXL_ASSERT(allow_macro_instructions_); 4804 VIXL_ASSERT(OutsideITBlock()); 4805 MacroEmissionCheckScope guard(this); 4806 ITScope it_scope(this, &cond, guard); 4807 ubfx(cond, rd, rn, lsb, width); 4808 } 4809 void Ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width) { 4810 Ubfx(al, rd, rn, lsb, width); 4811 } 4812 4813 void Udf(Condition cond, uint32_t imm) { 4814 VIXL_ASSERT(allow_macro_instructions_); 4815 VIXL_ASSERT(OutsideITBlock()); 4816 MacroEmissionCheckScope guard(this); 4817 ITScope it_scope(this, &cond, guard); 4818 udf(cond, imm); 4819 } 4820 void Udf(uint32_t imm) { Udf(al, imm); } 4821 4822 void Udiv(Condition cond, Register rd, Register rn, Register rm) { 4823 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4824 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4825 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4826 VIXL_ASSERT(allow_macro_instructions_); 4827 VIXL_ASSERT(OutsideITBlock()); 4828 MacroEmissionCheckScope guard(this); 4829 ITScope it_scope(this, &cond, guard); 4830 udiv(cond, rd, rn, rm); 4831 } 4832 void Udiv(Register rd, Register rn, Register rm) { Udiv(al, rd, rn, rm); } 4833 4834 void Uhadd16(Condition cond, Register rd, Register rn, Register rm) { 4835 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4837 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4838 VIXL_ASSERT(allow_macro_instructions_); 4839 VIXL_ASSERT(OutsideITBlock()); 4840 MacroEmissionCheckScope guard(this); 4841 ITScope it_scope(this, &cond, guard); 4842 uhadd16(cond, rd, rn, rm); 4843 } 4844 void Uhadd16(Register rd, Register rn, Register rm) { 4845 Uhadd16(al, rd, rn, rm); 4846 } 4847 4848 void Uhadd8(Condition cond, Register rd, Register rn, Register rm) { 4849 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4850 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4851 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4852 VIXL_ASSERT(allow_macro_instructions_); 4853 VIXL_ASSERT(OutsideITBlock()); 4854 MacroEmissionCheckScope guard(this); 4855 ITScope it_scope(this, &cond, guard); 4856 uhadd8(cond, rd, rn, rm); 4857 } 4858 void Uhadd8(Register rd, Register rn, Register rm) { Uhadd8(al, rd, rn, rm); } 4859 4860 void Uhasx(Condition cond, Register rd, Register rn, Register rm) { 4861 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4862 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4863 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4864 VIXL_ASSERT(allow_macro_instructions_); 4865 VIXL_ASSERT(OutsideITBlock()); 4866 MacroEmissionCheckScope guard(this); 4867 ITScope it_scope(this, &cond, guard); 4868 uhasx(cond, rd, rn, rm); 4869 } 4870 void Uhasx(Register rd, Register rn, Register rm) { Uhasx(al, rd, rn, rm); } 4871 4872 void Uhsax(Condition cond, Register rd, Register rn, Register rm) { 4873 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4874 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4875 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4876 VIXL_ASSERT(allow_macro_instructions_); 4877 VIXL_ASSERT(OutsideITBlock()); 4878 MacroEmissionCheckScope guard(this); 4879 ITScope it_scope(this, &cond, guard); 4880 uhsax(cond, rd, rn, rm); 4881 } 4882 void Uhsax(Register rd, Register rn, Register rm) { Uhsax(al, rd, rn, rm); } 4883 4884 void Uhsub16(Condition cond, Register rd, Register rn, Register rm) { 4885 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4886 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4887 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4888 VIXL_ASSERT(allow_macro_instructions_); 4889 VIXL_ASSERT(OutsideITBlock()); 4890 MacroEmissionCheckScope guard(this); 4891 ITScope it_scope(this, &cond, guard); 4892 uhsub16(cond, rd, rn, rm); 4893 } 4894 void Uhsub16(Register rd, Register rn, Register rm) { 4895 Uhsub16(al, rd, rn, rm); 4896 } 4897 4898 void Uhsub8(Condition cond, Register rd, Register rn, Register rm) { 4899 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 4900 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4901 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4902 VIXL_ASSERT(allow_macro_instructions_); 4903 VIXL_ASSERT(OutsideITBlock()); 4904 MacroEmissionCheckScope guard(this); 4905 ITScope it_scope(this, &cond, guard); 4906 uhsub8(cond, rd, rn, rm); 4907 } 4908 void Uhsub8(Register rd, Register rn, Register rm) { Uhsub8(al, rd, rn, rm); } 4909 4910 void Umaal( 4911 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4912 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4913 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4914 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4915 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4916 VIXL_ASSERT(allow_macro_instructions_); 4917 VIXL_ASSERT(OutsideITBlock()); 4918 MacroEmissionCheckScope guard(this); 4919 ITScope it_scope(this, &cond, guard); 4920 umaal(cond, rdlo, rdhi, rn, rm); 4921 } 4922 void Umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 4923 Umaal(al, rdlo, rdhi, rn, rm); 4924 } 4925 4926 void Umlal( 4927 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4928 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4929 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4930 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4932 VIXL_ASSERT(allow_macro_instructions_); 4933 VIXL_ASSERT(OutsideITBlock()); 4934 MacroEmissionCheckScope guard(this); 4935 ITScope it_scope(this, &cond, guard); 4936 umlal(cond, rdlo, rdhi, rn, rm); 4937 } 4938 void Umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 4939 Umlal(al, rdlo, rdhi, rn, rm); 4940 } 4941 void Umlal(FlagsUpdate flags, 4942 Condition cond, 4943 Register rdlo, 4944 Register rdhi, 4945 Register rn, 4946 Register rm) { 4947 switch (flags) { 4948 case LeaveFlags: 4949 Umlal(cond, rdlo, rdhi, rn, rm); 4950 break; 4951 case SetFlags: 4952 Umlals(cond, rdlo, rdhi, rn, rm); 4953 break; 4954 case DontCare: 4955 Umlal(cond, rdlo, rdhi, rn, rm); 4956 break; 4957 } 4958 } 4959 void Umlal(FlagsUpdate flags, 4960 Register rdlo, 4961 Register rdhi, 4962 Register rn, 4963 Register rm) { 4964 Umlal(flags, al, rdlo, rdhi, rn, rm); 4965 } 4966 4967 void Umlals( 4968 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4969 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4971 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4972 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4973 VIXL_ASSERT(allow_macro_instructions_); 4974 VIXL_ASSERT(OutsideITBlock()); 4975 MacroEmissionCheckScope guard(this); 4976 ITScope it_scope(this, &cond, guard); 4977 umlals(cond, rdlo, rdhi, rn, rm); 4978 } 4979 void Umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 4980 Umlals(al, rdlo, rdhi, rn, rm); 4981 } 4982 4983 void Umull( 4984 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 4985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 4986 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 4987 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 4988 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 4989 VIXL_ASSERT(allow_macro_instructions_); 4990 VIXL_ASSERT(OutsideITBlock()); 4991 MacroEmissionCheckScope guard(this); 4992 ITScope it_scope(this, &cond, guard); 4993 umull(cond, rdlo, rdhi, rn, rm); 4994 } 4995 void Umull(Register rdlo, Register rdhi, Register rn, Register rm) { 4996 Umull(al, rdlo, rdhi, rn, rm); 4997 } 4998 void Umull(FlagsUpdate flags, 4999 Condition cond, 5000 Register rdlo, 5001 Register rdhi, 5002 Register rn, 5003 Register rm) { 5004 switch (flags) { 5005 case LeaveFlags: 5006 Umull(cond, rdlo, rdhi, rn, rm); 5007 break; 5008 case SetFlags: 5009 Umulls(cond, rdlo, rdhi, rn, rm); 5010 break; 5011 case DontCare: 5012 Umull(cond, rdlo, rdhi, rn, rm); 5013 break; 5014 } 5015 } 5016 void Umull(FlagsUpdate flags, 5017 Register rdlo, 5018 Register rdhi, 5019 Register rn, 5020 Register rm) { 5021 Umull(flags, al, rdlo, rdhi, rn, rm); 5022 } 5023 5024 void Umulls( 5025 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm) { 5026 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdlo)); 5027 VIXL_ASSERT(!AliasesAvailableScratchRegister(rdhi)); 5028 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5029 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5030 VIXL_ASSERT(allow_macro_instructions_); 5031 VIXL_ASSERT(OutsideITBlock()); 5032 MacroEmissionCheckScope guard(this); 5033 ITScope it_scope(this, &cond, guard); 5034 umulls(cond, rdlo, rdhi, rn, rm); 5035 } 5036 void Umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 5037 Umulls(al, rdlo, rdhi, rn, rm); 5038 } 5039 5040 void Uqadd16(Condition cond, Register rd, Register rn, Register rm) { 5041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5042 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5043 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5044 VIXL_ASSERT(allow_macro_instructions_); 5045 VIXL_ASSERT(OutsideITBlock()); 5046 MacroEmissionCheckScope guard(this); 5047 ITScope it_scope(this, &cond, guard); 5048 uqadd16(cond, rd, rn, rm); 5049 } 5050 void Uqadd16(Register rd, Register rn, Register rm) { 5051 Uqadd16(al, rd, rn, rm); 5052 } 5053 5054 void Uqadd8(Condition cond, Register rd, Register rn, Register rm) { 5055 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5056 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5057 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5058 VIXL_ASSERT(allow_macro_instructions_); 5059 VIXL_ASSERT(OutsideITBlock()); 5060 MacroEmissionCheckScope guard(this); 5061 ITScope it_scope(this, &cond, guard); 5062 uqadd8(cond, rd, rn, rm); 5063 } 5064 void Uqadd8(Register rd, Register rn, Register rm) { Uqadd8(al, rd, rn, rm); } 5065 5066 void Uqasx(Condition cond, Register rd, Register rn, Register rm) { 5067 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5068 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5069 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5070 VIXL_ASSERT(allow_macro_instructions_); 5071 VIXL_ASSERT(OutsideITBlock()); 5072 MacroEmissionCheckScope guard(this); 5073 ITScope it_scope(this, &cond, guard); 5074 uqasx(cond, rd, rn, rm); 5075 } 5076 void Uqasx(Register rd, Register rn, Register rm) { Uqasx(al, rd, rn, rm); } 5077 5078 void Uqsax(Condition cond, Register rd, Register rn, Register rm) { 5079 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5080 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5081 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5082 VIXL_ASSERT(allow_macro_instructions_); 5083 VIXL_ASSERT(OutsideITBlock()); 5084 MacroEmissionCheckScope guard(this); 5085 ITScope it_scope(this, &cond, guard); 5086 uqsax(cond, rd, rn, rm); 5087 } 5088 void Uqsax(Register rd, Register rn, Register rm) { Uqsax(al, rd, rn, rm); } 5089 5090 void Uqsub16(Condition cond, Register rd, Register rn, Register rm) { 5091 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5092 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5093 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5094 VIXL_ASSERT(allow_macro_instructions_); 5095 VIXL_ASSERT(OutsideITBlock()); 5096 MacroEmissionCheckScope guard(this); 5097 ITScope it_scope(this, &cond, guard); 5098 uqsub16(cond, rd, rn, rm); 5099 } 5100 void Uqsub16(Register rd, Register rn, Register rm) { 5101 Uqsub16(al, rd, rn, rm); 5102 } 5103 5104 void Uqsub8(Condition cond, Register rd, Register rn, Register rm) { 5105 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5106 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5107 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5108 VIXL_ASSERT(allow_macro_instructions_); 5109 VIXL_ASSERT(OutsideITBlock()); 5110 MacroEmissionCheckScope guard(this); 5111 ITScope it_scope(this, &cond, guard); 5112 uqsub8(cond, rd, rn, rm); 5113 } 5114 void Uqsub8(Register rd, Register rn, Register rm) { Uqsub8(al, rd, rn, rm); } 5115 5116 void Usad8(Condition cond, Register rd, Register rn, Register rm) { 5117 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5118 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5119 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5120 VIXL_ASSERT(allow_macro_instructions_); 5121 VIXL_ASSERT(OutsideITBlock()); 5122 MacroEmissionCheckScope guard(this); 5123 ITScope it_scope(this, &cond, guard); 5124 usad8(cond, rd, rn, rm); 5125 } 5126 void Usad8(Register rd, Register rn, Register rm) { Usad8(al, rd, rn, rm); } 5127 5128 void Usada8( 5129 Condition cond, Register rd, Register rn, Register rm, Register ra) { 5130 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5131 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5132 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5133 VIXL_ASSERT(!AliasesAvailableScratchRegister(ra)); 5134 VIXL_ASSERT(allow_macro_instructions_); 5135 VIXL_ASSERT(OutsideITBlock()); 5136 MacroEmissionCheckScope guard(this); 5137 ITScope it_scope(this, &cond, guard); 5138 usada8(cond, rd, rn, rm, ra); 5139 } 5140 void Usada8(Register rd, Register rn, Register rm, Register ra) { 5141 Usada8(al, rd, rn, rm, ra); 5142 } 5143 5144 void Usat(Condition cond, Register rd, uint32_t imm, const Operand& operand) { 5145 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5146 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5147 VIXL_ASSERT(allow_macro_instructions_); 5148 VIXL_ASSERT(OutsideITBlock()); 5149 MacroEmissionCheckScope guard(this); 5150 ITScope it_scope(this, &cond, guard); 5151 usat(cond, rd, imm, operand); 5152 } 5153 void Usat(Register rd, uint32_t imm, const Operand& operand) { 5154 Usat(al, rd, imm, operand); 5155 } 5156 5157 void Usat16(Condition cond, Register rd, uint32_t imm, Register rn) { 5158 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5159 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5160 VIXL_ASSERT(allow_macro_instructions_); 5161 VIXL_ASSERT(OutsideITBlock()); 5162 MacroEmissionCheckScope guard(this); 5163 ITScope it_scope(this, &cond, guard); 5164 usat16(cond, rd, imm, rn); 5165 } 5166 void Usat16(Register rd, uint32_t imm, Register rn) { 5167 Usat16(al, rd, imm, rn); 5168 } 5169 5170 void Usax(Condition cond, Register rd, Register rn, Register rm) { 5171 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5172 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5173 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5174 VIXL_ASSERT(allow_macro_instructions_); 5175 VIXL_ASSERT(OutsideITBlock()); 5176 MacroEmissionCheckScope guard(this); 5177 ITScope it_scope(this, &cond, guard); 5178 usax(cond, rd, rn, rm); 5179 } 5180 void Usax(Register rd, Register rn, Register rm) { Usax(al, rd, rn, rm); } 5181 5182 void Usub16(Condition cond, Register rd, Register rn, Register rm) { 5183 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5184 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5185 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5186 VIXL_ASSERT(allow_macro_instructions_); 5187 VIXL_ASSERT(OutsideITBlock()); 5188 MacroEmissionCheckScope guard(this); 5189 ITScope it_scope(this, &cond, guard); 5190 usub16(cond, rd, rn, rm); 5191 } 5192 void Usub16(Register rd, Register rn, Register rm) { Usub16(al, rd, rn, rm); } 5193 5194 void Usub8(Condition cond, Register rd, Register rn, Register rm) { 5195 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5196 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5197 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5198 VIXL_ASSERT(allow_macro_instructions_); 5199 VIXL_ASSERT(OutsideITBlock()); 5200 MacroEmissionCheckScope guard(this); 5201 ITScope it_scope(this, &cond, guard); 5202 usub8(cond, rd, rn, rm); 5203 } 5204 void Usub8(Register rd, Register rn, Register rm) { Usub8(al, rd, rn, rm); } 5205 5206 void Uxtab(Condition cond, Register rd, Register rn, const Operand& operand) { 5207 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5208 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5209 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5210 VIXL_ASSERT(allow_macro_instructions_); 5211 VIXL_ASSERT(OutsideITBlock()); 5212 MacroEmissionCheckScope guard(this); 5213 ITScope it_scope(this, &cond, guard); 5214 uxtab(cond, rd, rn, operand); 5215 } 5216 void Uxtab(Register rd, Register rn, const Operand& operand) { 5217 Uxtab(al, rd, rn, operand); 5218 } 5219 5220 void Uxtab16(Condition cond, 5221 Register rd, 5222 Register rn, 5223 const Operand& operand) { 5224 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5225 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5226 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5227 VIXL_ASSERT(allow_macro_instructions_); 5228 VIXL_ASSERT(OutsideITBlock()); 5229 MacroEmissionCheckScope guard(this); 5230 ITScope it_scope(this, &cond, guard); 5231 uxtab16(cond, rd, rn, operand); 5232 } 5233 void Uxtab16(Register rd, Register rn, const Operand& operand) { 5234 Uxtab16(al, rd, rn, operand); 5235 } 5236 5237 void Uxtah(Condition cond, Register rd, Register rn, const Operand& operand) { 5238 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5239 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5240 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5241 VIXL_ASSERT(allow_macro_instructions_); 5242 VIXL_ASSERT(OutsideITBlock()); 5243 MacroEmissionCheckScope guard(this); 5244 ITScope it_scope(this, &cond, guard); 5245 uxtah(cond, rd, rn, operand); 5246 } 5247 void Uxtah(Register rd, Register rn, const Operand& operand) { 5248 Uxtah(al, rd, rn, operand); 5249 } 5250 5251 void Uxtb(Condition cond, Register rd, const Operand& operand) { 5252 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5253 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5254 VIXL_ASSERT(allow_macro_instructions_); 5255 VIXL_ASSERT(OutsideITBlock()); 5256 MacroEmissionCheckScope guard(this); 5257 ITScope it_scope(this, &cond, guard); 5258 uxtb(cond, rd, operand); 5259 } 5260 void Uxtb(Register rd, const Operand& operand) { Uxtb(al, rd, operand); } 5261 5262 void Uxtb16(Condition cond, Register rd, const Operand& operand) { 5263 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5264 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5265 VIXL_ASSERT(allow_macro_instructions_); 5266 VIXL_ASSERT(OutsideITBlock()); 5267 MacroEmissionCheckScope guard(this); 5268 ITScope it_scope(this, &cond, guard); 5269 uxtb16(cond, rd, operand); 5270 } 5271 void Uxtb16(Register rd, const Operand& operand) { Uxtb16(al, rd, operand); } 5272 5273 void Uxth(Condition cond, Register rd, const Operand& operand) { 5274 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5275 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5276 VIXL_ASSERT(allow_macro_instructions_); 5277 VIXL_ASSERT(OutsideITBlock()); 5278 MacroEmissionCheckScope guard(this); 5279 ITScope it_scope(this, &cond, guard); 5280 uxth(cond, rd, operand); 5281 } 5282 void Uxth(Register rd, const Operand& operand) { Uxth(al, rd, operand); } 5283 5284 void Vaba( 5285 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5286 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5287 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5288 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5289 VIXL_ASSERT(allow_macro_instructions_); 5290 VIXL_ASSERT(OutsideITBlock()); 5291 MacroEmissionCheckScope guard(this); 5292 ITScope it_scope(this, &cond, guard); 5293 vaba(cond, dt, rd, rn, rm); 5294 } 5295 void Vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5296 Vaba(al, dt, rd, rn, rm); 5297 } 5298 5299 void Vaba( 5300 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5302 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5303 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5304 VIXL_ASSERT(allow_macro_instructions_); 5305 VIXL_ASSERT(OutsideITBlock()); 5306 MacroEmissionCheckScope guard(this); 5307 ITScope it_scope(this, &cond, guard); 5308 vaba(cond, dt, rd, rn, rm); 5309 } 5310 void Vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5311 Vaba(al, dt, rd, rn, rm); 5312 } 5313 5314 void Vabal( 5315 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5316 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5317 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5318 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5319 VIXL_ASSERT(allow_macro_instructions_); 5320 VIXL_ASSERT(OutsideITBlock()); 5321 MacroEmissionCheckScope guard(this); 5322 ITScope it_scope(this, &cond, guard); 5323 vabal(cond, dt, rd, rn, rm); 5324 } 5325 void Vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5326 Vabal(al, dt, rd, rn, rm); 5327 } 5328 5329 void Vabd( 5330 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5331 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5332 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5333 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5334 VIXL_ASSERT(allow_macro_instructions_); 5335 VIXL_ASSERT(OutsideITBlock()); 5336 MacroEmissionCheckScope guard(this); 5337 ITScope it_scope(this, &cond, guard); 5338 vabd(cond, dt, rd, rn, rm); 5339 } 5340 void Vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5341 Vabd(al, dt, rd, rn, rm); 5342 } 5343 5344 void Vabd( 5345 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5346 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5347 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5348 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5349 VIXL_ASSERT(allow_macro_instructions_); 5350 VIXL_ASSERT(OutsideITBlock()); 5351 MacroEmissionCheckScope guard(this); 5352 ITScope it_scope(this, &cond, guard); 5353 vabd(cond, dt, rd, rn, rm); 5354 } 5355 void Vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5356 Vabd(al, dt, rd, rn, rm); 5357 } 5358 5359 void Vabdl( 5360 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5361 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5363 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5364 VIXL_ASSERT(allow_macro_instructions_); 5365 VIXL_ASSERT(OutsideITBlock()); 5366 MacroEmissionCheckScope guard(this); 5367 ITScope it_scope(this, &cond, guard); 5368 vabdl(cond, dt, rd, rn, rm); 5369 } 5370 void Vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5371 Vabdl(al, dt, rd, rn, rm); 5372 } 5373 5374 void Vabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 5375 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5376 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5377 VIXL_ASSERT(allow_macro_instructions_); 5378 VIXL_ASSERT(OutsideITBlock()); 5379 MacroEmissionCheckScope guard(this); 5380 ITScope it_scope(this, &cond, guard); 5381 vabs(cond, dt, rd, rm); 5382 } 5383 void Vabs(DataType dt, DRegister rd, DRegister rm) { Vabs(al, dt, rd, rm); } 5384 5385 void Vabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 5386 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5387 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5388 VIXL_ASSERT(allow_macro_instructions_); 5389 VIXL_ASSERT(OutsideITBlock()); 5390 MacroEmissionCheckScope guard(this); 5391 ITScope it_scope(this, &cond, guard); 5392 vabs(cond, dt, rd, rm); 5393 } 5394 void Vabs(DataType dt, QRegister rd, QRegister rm) { Vabs(al, dt, rd, rm); } 5395 5396 void Vabs(Condition cond, DataType dt, SRegister rd, SRegister rm) { 5397 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5398 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5399 VIXL_ASSERT(allow_macro_instructions_); 5400 VIXL_ASSERT(OutsideITBlock()); 5401 MacroEmissionCheckScope guard(this); 5402 ITScope it_scope(this, &cond, guard); 5403 vabs(cond, dt, rd, rm); 5404 } 5405 void Vabs(DataType dt, SRegister rd, SRegister rm) { Vabs(al, dt, rd, rm); } 5406 5407 void Vacge( 5408 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5409 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5410 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5411 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5412 VIXL_ASSERT(allow_macro_instructions_); 5413 VIXL_ASSERT(OutsideITBlock()); 5414 MacroEmissionCheckScope guard(this); 5415 ITScope it_scope(this, &cond, guard); 5416 vacge(cond, dt, rd, rn, rm); 5417 } 5418 void Vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5419 Vacge(al, dt, rd, rn, rm); 5420 } 5421 5422 void Vacge( 5423 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5424 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5425 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5426 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5427 VIXL_ASSERT(allow_macro_instructions_); 5428 VIXL_ASSERT(OutsideITBlock()); 5429 MacroEmissionCheckScope guard(this); 5430 ITScope it_scope(this, &cond, guard); 5431 vacge(cond, dt, rd, rn, rm); 5432 } 5433 void Vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5434 Vacge(al, dt, rd, rn, rm); 5435 } 5436 5437 void Vacgt( 5438 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5439 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5440 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5441 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5442 VIXL_ASSERT(allow_macro_instructions_); 5443 VIXL_ASSERT(OutsideITBlock()); 5444 MacroEmissionCheckScope guard(this); 5445 ITScope it_scope(this, &cond, guard); 5446 vacgt(cond, dt, rd, rn, rm); 5447 } 5448 void Vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5449 Vacgt(al, dt, rd, rn, rm); 5450 } 5451 5452 void Vacgt( 5453 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5455 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5456 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5457 VIXL_ASSERT(allow_macro_instructions_); 5458 VIXL_ASSERT(OutsideITBlock()); 5459 MacroEmissionCheckScope guard(this); 5460 ITScope it_scope(this, &cond, guard); 5461 vacgt(cond, dt, rd, rn, rm); 5462 } 5463 void Vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5464 Vacgt(al, dt, rd, rn, rm); 5465 } 5466 5467 void Vacle( 5468 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5470 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5472 VIXL_ASSERT(allow_macro_instructions_); 5473 VIXL_ASSERT(OutsideITBlock()); 5474 MacroEmissionCheckScope guard(this); 5475 ITScope it_scope(this, &cond, guard); 5476 vacle(cond, dt, rd, rn, rm); 5477 } 5478 void Vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5479 Vacle(al, dt, rd, rn, rm); 5480 } 5481 5482 void Vacle( 5483 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5484 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5487 VIXL_ASSERT(allow_macro_instructions_); 5488 VIXL_ASSERT(OutsideITBlock()); 5489 MacroEmissionCheckScope guard(this); 5490 ITScope it_scope(this, &cond, guard); 5491 vacle(cond, dt, rd, rn, rm); 5492 } 5493 void Vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5494 Vacle(al, dt, rd, rn, rm); 5495 } 5496 5497 void Vaclt( 5498 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5499 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5500 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5501 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5502 VIXL_ASSERT(allow_macro_instructions_); 5503 VIXL_ASSERT(OutsideITBlock()); 5504 MacroEmissionCheckScope guard(this); 5505 ITScope it_scope(this, &cond, guard); 5506 vaclt(cond, dt, rd, rn, rm); 5507 } 5508 void Vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5509 Vaclt(al, dt, rd, rn, rm); 5510 } 5511 5512 void Vaclt( 5513 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5514 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5515 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5516 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5517 VIXL_ASSERT(allow_macro_instructions_); 5518 VIXL_ASSERT(OutsideITBlock()); 5519 MacroEmissionCheckScope guard(this); 5520 ITScope it_scope(this, &cond, guard); 5521 vaclt(cond, dt, rd, rn, rm); 5522 } 5523 void Vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5524 Vaclt(al, dt, rd, rn, rm); 5525 } 5526 5527 void Vadd( 5528 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5529 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5530 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5531 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5532 VIXL_ASSERT(allow_macro_instructions_); 5533 VIXL_ASSERT(OutsideITBlock()); 5534 MacroEmissionCheckScope guard(this); 5535 ITScope it_scope(this, &cond, guard); 5536 vadd(cond, dt, rd, rn, rm); 5537 } 5538 void Vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5539 Vadd(al, dt, rd, rn, rm); 5540 } 5541 5542 void Vadd( 5543 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5544 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5546 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5547 VIXL_ASSERT(allow_macro_instructions_); 5548 VIXL_ASSERT(OutsideITBlock()); 5549 MacroEmissionCheckScope guard(this); 5550 ITScope it_scope(this, &cond, guard); 5551 vadd(cond, dt, rd, rn, rm); 5552 } 5553 void Vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5554 Vadd(al, dt, rd, rn, rm); 5555 } 5556 5557 void Vadd( 5558 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5559 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5560 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5561 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5562 VIXL_ASSERT(allow_macro_instructions_); 5563 VIXL_ASSERT(OutsideITBlock()); 5564 MacroEmissionCheckScope guard(this); 5565 ITScope it_scope(this, &cond, guard); 5566 vadd(cond, dt, rd, rn, rm); 5567 } 5568 void Vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5569 Vadd(al, dt, rd, rn, rm); 5570 } 5571 5572 void Vaddhn( 5573 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5574 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5575 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5576 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5577 VIXL_ASSERT(allow_macro_instructions_); 5578 VIXL_ASSERT(OutsideITBlock()); 5579 MacroEmissionCheckScope guard(this); 5580 ITScope it_scope(this, &cond, guard); 5581 vaddhn(cond, dt, rd, rn, rm); 5582 } 5583 void Vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5584 Vaddhn(al, dt, rd, rn, rm); 5585 } 5586 5587 void Vaddl( 5588 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5589 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5590 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5591 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5592 VIXL_ASSERT(allow_macro_instructions_); 5593 VIXL_ASSERT(OutsideITBlock()); 5594 MacroEmissionCheckScope guard(this); 5595 ITScope it_scope(this, &cond, guard); 5596 vaddl(cond, dt, rd, rn, rm); 5597 } 5598 void Vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5599 Vaddl(al, dt, rd, rn, rm); 5600 } 5601 5602 void Vaddw( 5603 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5604 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5605 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5606 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5607 VIXL_ASSERT(allow_macro_instructions_); 5608 VIXL_ASSERT(OutsideITBlock()); 5609 MacroEmissionCheckScope guard(this); 5610 ITScope it_scope(this, &cond, guard); 5611 vaddw(cond, dt, rd, rn, rm); 5612 } 5613 void Vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 5614 Vaddw(al, dt, rd, rn, rm); 5615 } 5616 5617 void Vand(Condition cond, 5618 DataType dt, 5619 DRegister rd, 5620 DRegister rn, 5621 const DOperand& operand) { 5622 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5623 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5624 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5625 VIXL_ASSERT(allow_macro_instructions_); 5626 VIXL_ASSERT(OutsideITBlock()); 5627 MacroEmissionCheckScope guard(this); 5628 ITScope it_scope(this, &cond, guard); 5629 vand(cond, dt, rd, rn, operand); 5630 } 5631 void Vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5632 Vand(al, dt, rd, rn, operand); 5633 } 5634 5635 void Vand(Condition cond, 5636 DataType dt, 5637 QRegister rd, 5638 QRegister rn, 5639 const QOperand& operand) { 5640 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5641 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5642 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5643 VIXL_ASSERT(allow_macro_instructions_); 5644 VIXL_ASSERT(OutsideITBlock()); 5645 MacroEmissionCheckScope guard(this); 5646 ITScope it_scope(this, &cond, guard); 5647 vand(cond, dt, rd, rn, operand); 5648 } 5649 void Vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5650 Vand(al, dt, rd, rn, operand); 5651 } 5652 5653 void Vbic(Condition cond, 5654 DataType dt, 5655 DRegister rd, 5656 DRegister rn, 5657 const DOperand& operand) { 5658 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5659 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5660 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5661 VIXL_ASSERT(allow_macro_instructions_); 5662 VIXL_ASSERT(OutsideITBlock()); 5663 MacroEmissionCheckScope guard(this); 5664 ITScope it_scope(this, &cond, guard); 5665 vbic(cond, dt, rd, rn, operand); 5666 } 5667 void Vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5668 Vbic(al, dt, rd, rn, operand); 5669 } 5670 5671 void Vbic(Condition cond, 5672 DataType dt, 5673 QRegister rd, 5674 QRegister rn, 5675 const QOperand& operand) { 5676 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5678 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5679 VIXL_ASSERT(allow_macro_instructions_); 5680 VIXL_ASSERT(OutsideITBlock()); 5681 MacroEmissionCheckScope guard(this); 5682 ITScope it_scope(this, &cond, guard); 5683 vbic(cond, dt, rd, rn, operand); 5684 } 5685 void Vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5686 Vbic(al, dt, rd, rn, operand); 5687 } 5688 5689 void Vbif( 5690 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5691 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5692 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5693 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5694 VIXL_ASSERT(allow_macro_instructions_); 5695 VIXL_ASSERT(OutsideITBlock()); 5696 MacroEmissionCheckScope guard(this); 5697 ITScope it_scope(this, &cond, guard); 5698 vbif(cond, dt, rd, rn, rm); 5699 } 5700 void Vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5701 Vbif(al, dt, rd, rn, rm); 5702 } 5703 void Vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5704 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 5705 } 5706 void Vbif(DRegister rd, DRegister rn, DRegister rm) { 5707 Vbif(al, kDataTypeValueNone, rd, rn, rm); 5708 } 5709 5710 void Vbif( 5711 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5712 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5713 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5714 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5715 VIXL_ASSERT(allow_macro_instructions_); 5716 VIXL_ASSERT(OutsideITBlock()); 5717 MacroEmissionCheckScope guard(this); 5718 ITScope it_scope(this, &cond, guard); 5719 vbif(cond, dt, rd, rn, rm); 5720 } 5721 void Vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5722 Vbif(al, dt, rd, rn, rm); 5723 } 5724 void Vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5725 Vbif(cond, kDataTypeValueNone, rd, rn, rm); 5726 } 5727 void Vbif(QRegister rd, QRegister rn, QRegister rm) { 5728 Vbif(al, kDataTypeValueNone, rd, rn, rm); 5729 } 5730 5731 void Vbit( 5732 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5733 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5734 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5735 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5736 VIXL_ASSERT(allow_macro_instructions_); 5737 VIXL_ASSERT(OutsideITBlock()); 5738 MacroEmissionCheckScope guard(this); 5739 ITScope it_scope(this, &cond, guard); 5740 vbit(cond, dt, rd, rn, rm); 5741 } 5742 void Vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5743 Vbit(al, dt, rd, rn, rm); 5744 } 5745 void Vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5746 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 5747 } 5748 void Vbit(DRegister rd, DRegister rn, DRegister rm) { 5749 Vbit(al, kDataTypeValueNone, rd, rn, rm); 5750 } 5751 5752 void Vbit( 5753 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5754 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5755 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5756 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5757 VIXL_ASSERT(allow_macro_instructions_); 5758 VIXL_ASSERT(OutsideITBlock()); 5759 MacroEmissionCheckScope guard(this); 5760 ITScope it_scope(this, &cond, guard); 5761 vbit(cond, dt, rd, rn, rm); 5762 } 5763 void Vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5764 Vbit(al, dt, rd, rn, rm); 5765 } 5766 void Vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5767 Vbit(cond, kDataTypeValueNone, rd, rn, rm); 5768 } 5769 void Vbit(QRegister rd, QRegister rn, QRegister rm) { 5770 Vbit(al, kDataTypeValueNone, rd, rn, rm); 5771 } 5772 5773 void Vbsl( 5774 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5775 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5778 VIXL_ASSERT(allow_macro_instructions_); 5779 VIXL_ASSERT(OutsideITBlock()); 5780 MacroEmissionCheckScope guard(this); 5781 ITScope it_scope(this, &cond, guard); 5782 vbsl(cond, dt, rd, rn, rm); 5783 } 5784 void Vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5785 Vbsl(al, dt, rd, rn, rm); 5786 } 5787 void Vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 5788 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 5789 } 5790 void Vbsl(DRegister rd, DRegister rn, DRegister rm) { 5791 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 5792 } 5793 5794 void Vbsl( 5795 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5796 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5797 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5798 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5799 VIXL_ASSERT(allow_macro_instructions_); 5800 VIXL_ASSERT(OutsideITBlock()); 5801 MacroEmissionCheckScope guard(this); 5802 ITScope it_scope(this, &cond, guard); 5803 vbsl(cond, dt, rd, rn, rm); 5804 } 5805 void Vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5806 Vbsl(al, dt, rd, rn, rm); 5807 } 5808 void Vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 5809 Vbsl(cond, kDataTypeValueNone, rd, rn, rm); 5810 } 5811 void Vbsl(QRegister rd, QRegister rn, QRegister rm) { 5812 Vbsl(al, kDataTypeValueNone, rd, rn, rm); 5813 } 5814 5815 void Vceq(Condition cond, 5816 DataType dt, 5817 DRegister rd, 5818 DRegister rm, 5819 const DOperand& operand) { 5820 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5821 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5822 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5823 VIXL_ASSERT(allow_macro_instructions_); 5824 VIXL_ASSERT(OutsideITBlock()); 5825 MacroEmissionCheckScope guard(this); 5826 ITScope it_scope(this, &cond, guard); 5827 vceq(cond, dt, rd, rm, operand); 5828 } 5829 void Vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5830 Vceq(al, dt, rd, rm, operand); 5831 } 5832 5833 void Vceq(Condition cond, 5834 DataType dt, 5835 QRegister rd, 5836 QRegister rm, 5837 const QOperand& operand) { 5838 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5839 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5840 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5841 VIXL_ASSERT(allow_macro_instructions_); 5842 VIXL_ASSERT(OutsideITBlock()); 5843 MacroEmissionCheckScope guard(this); 5844 ITScope it_scope(this, &cond, guard); 5845 vceq(cond, dt, rd, rm, operand); 5846 } 5847 void Vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5848 Vceq(al, dt, rd, rm, operand); 5849 } 5850 5851 void Vceq( 5852 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5853 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5854 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5856 VIXL_ASSERT(allow_macro_instructions_); 5857 VIXL_ASSERT(OutsideITBlock()); 5858 MacroEmissionCheckScope guard(this); 5859 ITScope it_scope(this, &cond, guard); 5860 vceq(cond, dt, rd, rn, rm); 5861 } 5862 void Vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5863 Vceq(al, dt, rd, rn, rm); 5864 } 5865 5866 void Vceq( 5867 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5868 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5869 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5870 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5871 VIXL_ASSERT(allow_macro_instructions_); 5872 VIXL_ASSERT(OutsideITBlock()); 5873 MacroEmissionCheckScope guard(this); 5874 ITScope it_scope(this, &cond, guard); 5875 vceq(cond, dt, rd, rn, rm); 5876 } 5877 void Vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5878 Vceq(al, dt, rd, rn, rm); 5879 } 5880 5881 void Vcge(Condition cond, 5882 DataType dt, 5883 DRegister rd, 5884 DRegister rm, 5885 const DOperand& operand) { 5886 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5887 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5888 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5889 VIXL_ASSERT(allow_macro_instructions_); 5890 VIXL_ASSERT(OutsideITBlock()); 5891 MacroEmissionCheckScope guard(this); 5892 ITScope it_scope(this, &cond, guard); 5893 vcge(cond, dt, rd, rm, operand); 5894 } 5895 void Vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5896 Vcge(al, dt, rd, rm, operand); 5897 } 5898 5899 void Vcge(Condition cond, 5900 DataType dt, 5901 QRegister rd, 5902 QRegister rm, 5903 const QOperand& operand) { 5904 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5905 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5906 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5907 VIXL_ASSERT(allow_macro_instructions_); 5908 VIXL_ASSERT(OutsideITBlock()); 5909 MacroEmissionCheckScope guard(this); 5910 ITScope it_scope(this, &cond, guard); 5911 vcge(cond, dt, rd, rm, operand); 5912 } 5913 void Vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5914 Vcge(al, dt, rd, rm, operand); 5915 } 5916 5917 void Vcge( 5918 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5919 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5920 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5921 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5922 VIXL_ASSERT(allow_macro_instructions_); 5923 VIXL_ASSERT(OutsideITBlock()); 5924 MacroEmissionCheckScope guard(this); 5925 ITScope it_scope(this, &cond, guard); 5926 vcge(cond, dt, rd, rn, rm); 5927 } 5928 void Vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5929 Vcge(al, dt, rd, rn, rm); 5930 } 5931 5932 void Vcge( 5933 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5934 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5935 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5936 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5937 VIXL_ASSERT(allow_macro_instructions_); 5938 VIXL_ASSERT(OutsideITBlock()); 5939 MacroEmissionCheckScope guard(this); 5940 ITScope it_scope(this, &cond, guard); 5941 vcge(cond, dt, rd, rn, rm); 5942 } 5943 void Vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5944 Vcge(al, dt, rd, rn, rm); 5945 } 5946 5947 void Vcgt(Condition cond, 5948 DataType dt, 5949 DRegister rd, 5950 DRegister rm, 5951 const DOperand& operand) { 5952 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5953 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5954 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5955 VIXL_ASSERT(allow_macro_instructions_); 5956 VIXL_ASSERT(OutsideITBlock()); 5957 MacroEmissionCheckScope guard(this); 5958 ITScope it_scope(this, &cond, guard); 5959 vcgt(cond, dt, rd, rm, operand); 5960 } 5961 void Vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5962 Vcgt(al, dt, rd, rm, operand); 5963 } 5964 5965 void Vcgt(Condition cond, 5966 DataType dt, 5967 QRegister rd, 5968 QRegister rm, 5969 const QOperand& operand) { 5970 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5971 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5972 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 5973 VIXL_ASSERT(allow_macro_instructions_); 5974 VIXL_ASSERT(OutsideITBlock()); 5975 MacroEmissionCheckScope guard(this); 5976 ITScope it_scope(this, &cond, guard); 5977 vcgt(cond, dt, rd, rm, operand); 5978 } 5979 void Vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5980 Vcgt(al, dt, rd, rm, operand); 5981 } 5982 5983 void Vcgt( 5984 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 5986 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 5987 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 5988 VIXL_ASSERT(allow_macro_instructions_); 5989 VIXL_ASSERT(OutsideITBlock()); 5990 MacroEmissionCheckScope guard(this); 5991 ITScope it_scope(this, &cond, guard); 5992 vcgt(cond, dt, rd, rn, rm); 5993 } 5994 void Vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5995 Vcgt(al, dt, rd, rn, rm); 5996 } 5997 5998 void Vcgt( 5999 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6000 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6001 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6002 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6003 VIXL_ASSERT(allow_macro_instructions_); 6004 VIXL_ASSERT(OutsideITBlock()); 6005 MacroEmissionCheckScope guard(this); 6006 ITScope it_scope(this, &cond, guard); 6007 vcgt(cond, dt, rd, rn, rm); 6008 } 6009 void Vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6010 Vcgt(al, dt, rd, rn, rm); 6011 } 6012 6013 void Vcle(Condition cond, 6014 DataType dt, 6015 DRegister rd, 6016 DRegister rm, 6017 const DOperand& operand) { 6018 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6019 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6020 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6021 VIXL_ASSERT(allow_macro_instructions_); 6022 VIXL_ASSERT(OutsideITBlock()); 6023 MacroEmissionCheckScope guard(this); 6024 ITScope it_scope(this, &cond, guard); 6025 vcle(cond, dt, rd, rm, operand); 6026 } 6027 void Vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 6028 Vcle(al, dt, rd, rm, operand); 6029 } 6030 6031 void Vcle(Condition cond, 6032 DataType dt, 6033 QRegister rd, 6034 QRegister rm, 6035 const QOperand& operand) { 6036 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6037 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6038 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6039 VIXL_ASSERT(allow_macro_instructions_); 6040 VIXL_ASSERT(OutsideITBlock()); 6041 MacroEmissionCheckScope guard(this); 6042 ITScope it_scope(this, &cond, guard); 6043 vcle(cond, dt, rd, rm, operand); 6044 } 6045 void Vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 6046 Vcle(al, dt, rd, rm, operand); 6047 } 6048 6049 void Vcle( 6050 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6051 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6053 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6054 VIXL_ASSERT(allow_macro_instructions_); 6055 VIXL_ASSERT(OutsideITBlock()); 6056 MacroEmissionCheckScope guard(this); 6057 ITScope it_scope(this, &cond, guard); 6058 vcle(cond, dt, rd, rn, rm); 6059 } 6060 void Vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6061 Vcle(al, dt, rd, rn, rm); 6062 } 6063 6064 void Vcle( 6065 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6066 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6067 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6068 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6069 VIXL_ASSERT(allow_macro_instructions_); 6070 VIXL_ASSERT(OutsideITBlock()); 6071 MacroEmissionCheckScope guard(this); 6072 ITScope it_scope(this, &cond, guard); 6073 vcle(cond, dt, rd, rn, rm); 6074 } 6075 void Vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6076 Vcle(al, dt, rd, rn, rm); 6077 } 6078 6079 void Vcls(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6080 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6081 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6082 VIXL_ASSERT(allow_macro_instructions_); 6083 VIXL_ASSERT(OutsideITBlock()); 6084 MacroEmissionCheckScope guard(this); 6085 ITScope it_scope(this, &cond, guard); 6086 vcls(cond, dt, rd, rm); 6087 } 6088 void Vcls(DataType dt, DRegister rd, DRegister rm) { Vcls(al, dt, rd, rm); } 6089 6090 void Vcls(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6091 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6092 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6093 VIXL_ASSERT(allow_macro_instructions_); 6094 VIXL_ASSERT(OutsideITBlock()); 6095 MacroEmissionCheckScope guard(this); 6096 ITScope it_scope(this, &cond, guard); 6097 vcls(cond, dt, rd, rm); 6098 } 6099 void Vcls(DataType dt, QRegister rd, QRegister rm) { Vcls(al, dt, rd, rm); } 6100 6101 void Vclt(Condition cond, 6102 DataType dt, 6103 DRegister rd, 6104 DRegister rm, 6105 const DOperand& operand) { 6106 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6107 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6108 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6109 VIXL_ASSERT(allow_macro_instructions_); 6110 VIXL_ASSERT(OutsideITBlock()); 6111 MacroEmissionCheckScope guard(this); 6112 ITScope it_scope(this, &cond, guard); 6113 vclt(cond, dt, rd, rm, operand); 6114 } 6115 void Vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 6116 Vclt(al, dt, rd, rm, operand); 6117 } 6118 6119 void Vclt(Condition cond, 6120 DataType dt, 6121 QRegister rd, 6122 QRegister rm, 6123 const QOperand& operand) { 6124 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6125 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6126 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6127 VIXL_ASSERT(allow_macro_instructions_); 6128 VIXL_ASSERT(OutsideITBlock()); 6129 MacroEmissionCheckScope guard(this); 6130 ITScope it_scope(this, &cond, guard); 6131 vclt(cond, dt, rd, rm, operand); 6132 } 6133 void Vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 6134 Vclt(al, dt, rd, rm, operand); 6135 } 6136 6137 void Vclt( 6138 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6139 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6140 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6141 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6142 VIXL_ASSERT(allow_macro_instructions_); 6143 VIXL_ASSERT(OutsideITBlock()); 6144 MacroEmissionCheckScope guard(this); 6145 ITScope it_scope(this, &cond, guard); 6146 vclt(cond, dt, rd, rn, rm); 6147 } 6148 void Vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6149 Vclt(al, dt, rd, rn, rm); 6150 } 6151 6152 void Vclt( 6153 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6154 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6155 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6156 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6157 VIXL_ASSERT(allow_macro_instructions_); 6158 VIXL_ASSERT(OutsideITBlock()); 6159 MacroEmissionCheckScope guard(this); 6160 ITScope it_scope(this, &cond, guard); 6161 vclt(cond, dt, rd, rn, rm); 6162 } 6163 void Vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6164 Vclt(al, dt, rd, rn, rm); 6165 } 6166 6167 void Vclz(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6168 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6169 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6170 VIXL_ASSERT(allow_macro_instructions_); 6171 VIXL_ASSERT(OutsideITBlock()); 6172 MacroEmissionCheckScope guard(this); 6173 ITScope it_scope(this, &cond, guard); 6174 vclz(cond, dt, rd, rm); 6175 } 6176 void Vclz(DataType dt, DRegister rd, DRegister rm) { Vclz(al, dt, rd, rm); } 6177 6178 void Vclz(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6179 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6180 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6181 VIXL_ASSERT(allow_macro_instructions_); 6182 VIXL_ASSERT(OutsideITBlock()); 6183 MacroEmissionCheckScope guard(this); 6184 ITScope it_scope(this, &cond, guard); 6185 vclz(cond, dt, rd, rm); 6186 } 6187 void Vclz(DataType dt, QRegister rd, QRegister rm) { Vclz(al, dt, rd, rm); } 6188 6189 void Vcmp(Condition cond, 6190 DataType dt, 6191 SRegister rd, 6192 const SOperand& operand) { 6193 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6194 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6195 VIXL_ASSERT(allow_macro_instructions_); 6196 VIXL_ASSERT(OutsideITBlock()); 6197 MacroEmissionCheckScope guard(this); 6198 ITScope it_scope(this, &cond, guard); 6199 vcmp(cond, dt, rd, operand); 6200 } 6201 void Vcmp(DataType dt, SRegister rd, const SOperand& operand) { 6202 Vcmp(al, dt, rd, operand); 6203 } 6204 6205 void Vcmp(Condition cond, 6206 DataType dt, 6207 DRegister rd, 6208 const DOperand& operand) { 6209 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6210 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6211 VIXL_ASSERT(allow_macro_instructions_); 6212 VIXL_ASSERT(OutsideITBlock()); 6213 MacroEmissionCheckScope guard(this); 6214 ITScope it_scope(this, &cond, guard); 6215 vcmp(cond, dt, rd, operand); 6216 } 6217 void Vcmp(DataType dt, DRegister rd, const DOperand& operand) { 6218 Vcmp(al, dt, rd, operand); 6219 } 6220 6221 void Vcmpe(Condition cond, 6222 DataType dt, 6223 SRegister rd, 6224 const SOperand& operand) { 6225 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6226 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6227 VIXL_ASSERT(allow_macro_instructions_); 6228 VIXL_ASSERT(OutsideITBlock()); 6229 MacroEmissionCheckScope guard(this); 6230 ITScope it_scope(this, &cond, guard); 6231 vcmpe(cond, dt, rd, operand); 6232 } 6233 void Vcmpe(DataType dt, SRegister rd, const SOperand& operand) { 6234 Vcmpe(al, dt, rd, operand); 6235 } 6236 6237 void Vcmpe(Condition cond, 6238 DataType dt, 6239 DRegister rd, 6240 const DOperand& operand) { 6241 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6242 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6243 VIXL_ASSERT(allow_macro_instructions_); 6244 VIXL_ASSERT(OutsideITBlock()); 6245 MacroEmissionCheckScope guard(this); 6246 ITScope it_scope(this, &cond, guard); 6247 vcmpe(cond, dt, rd, operand); 6248 } 6249 void Vcmpe(DataType dt, DRegister rd, const DOperand& operand) { 6250 Vcmpe(al, dt, rd, operand); 6251 } 6252 6253 void Vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 6254 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6255 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6256 VIXL_ASSERT(allow_macro_instructions_); 6257 VIXL_ASSERT(OutsideITBlock()); 6258 MacroEmissionCheckScope guard(this); 6259 ITScope it_scope(this, &cond, guard); 6260 vcnt(cond, dt, rd, rm); 6261 } 6262 void Vcnt(DataType dt, DRegister rd, DRegister rm) { Vcnt(al, dt, rd, rm); } 6263 6264 void Vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm) { 6265 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6266 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6267 VIXL_ASSERT(allow_macro_instructions_); 6268 VIXL_ASSERT(OutsideITBlock()); 6269 MacroEmissionCheckScope guard(this); 6270 ITScope it_scope(this, &cond, guard); 6271 vcnt(cond, dt, rd, rm); 6272 } 6273 void Vcnt(DataType dt, QRegister rd, QRegister rm) { Vcnt(al, dt, rd, rm); } 6274 6275 void Vcvt( 6276 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6277 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6278 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6279 VIXL_ASSERT(allow_macro_instructions_); 6280 VIXL_ASSERT(OutsideITBlock()); 6281 MacroEmissionCheckScope guard(this); 6282 ITScope it_scope(this, &cond, guard); 6283 vcvt(cond, dt1, dt2, rd, rm); 6284 } 6285 void Vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6286 Vcvt(al, dt1, dt2, rd, rm); 6287 } 6288 6289 void Vcvt( 6290 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6291 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6292 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6293 VIXL_ASSERT(allow_macro_instructions_); 6294 VIXL_ASSERT(OutsideITBlock()); 6295 MacroEmissionCheckScope guard(this); 6296 ITScope it_scope(this, &cond, guard); 6297 vcvt(cond, dt1, dt2, rd, rm); 6298 } 6299 void Vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6300 Vcvt(al, dt1, dt2, rd, rm); 6301 } 6302 6303 void Vcvt(Condition cond, 6304 DataType dt1, 6305 DataType dt2, 6306 DRegister rd, 6307 DRegister rm, 6308 int32_t fbits) { 6309 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6310 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6311 VIXL_ASSERT(allow_macro_instructions_); 6312 VIXL_ASSERT(OutsideITBlock()); 6313 MacroEmissionCheckScope guard(this); 6314 ITScope it_scope(this, &cond, guard); 6315 vcvt(cond, dt1, dt2, rd, rm, fbits); 6316 } 6317 void Vcvt( 6318 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 6319 Vcvt(al, dt1, dt2, rd, rm, fbits); 6320 } 6321 6322 void Vcvt(Condition cond, 6323 DataType dt1, 6324 DataType dt2, 6325 QRegister rd, 6326 QRegister rm, 6327 int32_t fbits) { 6328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6330 VIXL_ASSERT(allow_macro_instructions_); 6331 VIXL_ASSERT(OutsideITBlock()); 6332 MacroEmissionCheckScope guard(this); 6333 ITScope it_scope(this, &cond, guard); 6334 vcvt(cond, dt1, dt2, rd, rm, fbits); 6335 } 6336 void Vcvt( 6337 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 6338 Vcvt(al, dt1, dt2, rd, rm, fbits); 6339 } 6340 6341 void Vcvt(Condition cond, 6342 DataType dt1, 6343 DataType dt2, 6344 SRegister rd, 6345 SRegister rm, 6346 int32_t fbits) { 6347 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6348 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6349 VIXL_ASSERT(allow_macro_instructions_); 6350 VIXL_ASSERT(OutsideITBlock()); 6351 MacroEmissionCheckScope guard(this); 6352 ITScope it_scope(this, &cond, guard); 6353 vcvt(cond, dt1, dt2, rd, rm, fbits); 6354 } 6355 void Vcvt( 6356 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 6357 Vcvt(al, dt1, dt2, rd, rm, fbits); 6358 } 6359 6360 void Vcvt( 6361 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6362 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6363 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6364 VIXL_ASSERT(allow_macro_instructions_); 6365 VIXL_ASSERT(OutsideITBlock()); 6366 MacroEmissionCheckScope guard(this); 6367 ITScope it_scope(this, &cond, guard); 6368 vcvt(cond, dt1, dt2, rd, rm); 6369 } 6370 void Vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6371 Vcvt(al, dt1, dt2, rd, rm); 6372 } 6373 6374 void Vcvt( 6375 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6376 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6377 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6378 VIXL_ASSERT(allow_macro_instructions_); 6379 VIXL_ASSERT(OutsideITBlock()); 6380 MacroEmissionCheckScope guard(this); 6381 ITScope it_scope(this, &cond, guard); 6382 vcvt(cond, dt1, dt2, rd, rm); 6383 } 6384 void Vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6385 Vcvt(al, dt1, dt2, rd, rm); 6386 } 6387 6388 void Vcvt( 6389 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 6390 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6391 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6392 VIXL_ASSERT(allow_macro_instructions_); 6393 VIXL_ASSERT(OutsideITBlock()); 6394 MacroEmissionCheckScope guard(this); 6395 ITScope it_scope(this, &cond, guard); 6396 vcvt(cond, dt1, dt2, rd, rm); 6397 } 6398 void Vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 6399 Vcvt(al, dt1, dt2, rd, rm); 6400 } 6401 6402 void Vcvt( 6403 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 6404 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6405 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6406 VIXL_ASSERT(allow_macro_instructions_); 6407 VIXL_ASSERT(OutsideITBlock()); 6408 MacroEmissionCheckScope guard(this); 6409 ITScope it_scope(this, &cond, guard); 6410 vcvt(cond, dt1, dt2, rd, rm); 6411 } 6412 void Vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 6413 Vcvt(al, dt1, dt2, rd, rm); 6414 } 6415 6416 void Vcvt( 6417 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6419 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6420 VIXL_ASSERT(allow_macro_instructions_); 6421 VIXL_ASSERT(OutsideITBlock()); 6422 MacroEmissionCheckScope guard(this); 6423 ITScope it_scope(this, &cond, guard); 6424 vcvt(cond, dt1, dt2, rd, rm); 6425 } 6426 void Vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6427 Vcvt(al, dt1, dt2, rd, rm); 6428 } 6429 6430 void Vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6431 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6432 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6433 VIXL_ASSERT(allow_macro_instructions_); 6434 VIXL_ASSERT(OutsideITBlock()); 6435 MacroEmissionCheckScope guard(this); 6436 vcvta(dt1, dt2, rd, rm); 6437 } 6438 6439 void Vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6440 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6441 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6442 VIXL_ASSERT(allow_macro_instructions_); 6443 VIXL_ASSERT(OutsideITBlock()); 6444 MacroEmissionCheckScope guard(this); 6445 vcvta(dt1, dt2, rd, rm); 6446 } 6447 6448 void Vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6449 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6450 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6451 VIXL_ASSERT(allow_macro_instructions_); 6452 VIXL_ASSERT(OutsideITBlock()); 6453 MacroEmissionCheckScope guard(this); 6454 vcvta(dt1, dt2, rd, rm); 6455 } 6456 6457 void Vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6458 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6459 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6460 VIXL_ASSERT(allow_macro_instructions_); 6461 VIXL_ASSERT(OutsideITBlock()); 6462 MacroEmissionCheckScope guard(this); 6463 vcvta(dt1, dt2, rd, rm); 6464 } 6465 6466 void Vcvtb( 6467 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6468 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6469 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6470 VIXL_ASSERT(allow_macro_instructions_); 6471 VIXL_ASSERT(OutsideITBlock()); 6472 MacroEmissionCheckScope guard(this); 6473 ITScope it_scope(this, &cond, guard); 6474 vcvtb(cond, dt1, dt2, rd, rm); 6475 } 6476 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6477 Vcvtb(al, dt1, dt2, rd, rm); 6478 } 6479 6480 void Vcvtb( 6481 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6482 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6483 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6484 VIXL_ASSERT(allow_macro_instructions_); 6485 VIXL_ASSERT(OutsideITBlock()); 6486 MacroEmissionCheckScope guard(this); 6487 ITScope it_scope(this, &cond, guard); 6488 vcvtb(cond, dt1, dt2, rd, rm); 6489 } 6490 void Vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6491 Vcvtb(al, dt1, dt2, rd, rm); 6492 } 6493 6494 void Vcvtb( 6495 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6496 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6497 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6498 VIXL_ASSERT(allow_macro_instructions_); 6499 VIXL_ASSERT(OutsideITBlock()); 6500 MacroEmissionCheckScope guard(this); 6501 ITScope it_scope(this, &cond, guard); 6502 vcvtb(cond, dt1, dt2, rd, rm); 6503 } 6504 void Vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6505 Vcvtb(al, dt1, dt2, rd, rm); 6506 } 6507 6508 void Vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6509 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6510 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6511 VIXL_ASSERT(allow_macro_instructions_); 6512 VIXL_ASSERT(OutsideITBlock()); 6513 MacroEmissionCheckScope guard(this); 6514 vcvtm(dt1, dt2, rd, rm); 6515 } 6516 6517 void Vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6518 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6519 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6520 VIXL_ASSERT(allow_macro_instructions_); 6521 VIXL_ASSERT(OutsideITBlock()); 6522 MacroEmissionCheckScope guard(this); 6523 vcvtm(dt1, dt2, rd, rm); 6524 } 6525 6526 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6527 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6528 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6529 VIXL_ASSERT(allow_macro_instructions_); 6530 VIXL_ASSERT(OutsideITBlock()); 6531 MacroEmissionCheckScope guard(this); 6532 vcvtm(dt1, dt2, rd, rm); 6533 } 6534 6535 void Vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6536 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6537 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6538 VIXL_ASSERT(allow_macro_instructions_); 6539 VIXL_ASSERT(OutsideITBlock()); 6540 MacroEmissionCheckScope guard(this); 6541 vcvtm(dt1, dt2, rd, rm); 6542 } 6543 6544 void Vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6546 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6547 VIXL_ASSERT(allow_macro_instructions_); 6548 VIXL_ASSERT(OutsideITBlock()); 6549 MacroEmissionCheckScope guard(this); 6550 vcvtn(dt1, dt2, rd, rm); 6551 } 6552 6553 void Vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6554 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6555 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6556 VIXL_ASSERT(allow_macro_instructions_); 6557 VIXL_ASSERT(OutsideITBlock()); 6558 MacroEmissionCheckScope guard(this); 6559 vcvtn(dt1, dt2, rd, rm); 6560 } 6561 6562 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6564 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6565 VIXL_ASSERT(allow_macro_instructions_); 6566 VIXL_ASSERT(OutsideITBlock()); 6567 MacroEmissionCheckScope guard(this); 6568 vcvtn(dt1, dt2, rd, rm); 6569 } 6570 6571 void Vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6572 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6573 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6574 VIXL_ASSERT(allow_macro_instructions_); 6575 VIXL_ASSERT(OutsideITBlock()); 6576 MacroEmissionCheckScope guard(this); 6577 vcvtn(dt1, dt2, rd, rm); 6578 } 6579 6580 void Vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 6581 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6582 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6583 VIXL_ASSERT(allow_macro_instructions_); 6584 VIXL_ASSERT(OutsideITBlock()); 6585 MacroEmissionCheckScope guard(this); 6586 vcvtp(dt1, dt2, rd, rm); 6587 } 6588 6589 void Vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 6590 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6591 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6592 VIXL_ASSERT(allow_macro_instructions_); 6593 VIXL_ASSERT(OutsideITBlock()); 6594 MacroEmissionCheckScope guard(this); 6595 vcvtp(dt1, dt2, rd, rm); 6596 } 6597 6598 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6599 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6600 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6601 VIXL_ASSERT(allow_macro_instructions_); 6602 VIXL_ASSERT(OutsideITBlock()); 6603 MacroEmissionCheckScope guard(this); 6604 vcvtp(dt1, dt2, rd, rm); 6605 } 6606 6607 void Vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6608 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6609 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6610 VIXL_ASSERT(allow_macro_instructions_); 6611 VIXL_ASSERT(OutsideITBlock()); 6612 MacroEmissionCheckScope guard(this); 6613 vcvtp(dt1, dt2, rd, rm); 6614 } 6615 6616 void Vcvtr( 6617 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6618 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6619 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6620 VIXL_ASSERT(allow_macro_instructions_); 6621 VIXL_ASSERT(OutsideITBlock()); 6622 MacroEmissionCheckScope guard(this); 6623 ITScope it_scope(this, &cond, guard); 6624 vcvtr(cond, dt1, dt2, rd, rm); 6625 } 6626 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6627 Vcvtr(al, dt1, dt2, rd, rm); 6628 } 6629 6630 void Vcvtr( 6631 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6632 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6633 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6634 VIXL_ASSERT(allow_macro_instructions_); 6635 VIXL_ASSERT(OutsideITBlock()); 6636 MacroEmissionCheckScope guard(this); 6637 ITScope it_scope(this, &cond, guard); 6638 vcvtr(cond, dt1, dt2, rd, rm); 6639 } 6640 void Vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6641 Vcvtr(al, dt1, dt2, rd, rm); 6642 } 6643 6644 void Vcvtt( 6645 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6646 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6647 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6648 VIXL_ASSERT(allow_macro_instructions_); 6649 VIXL_ASSERT(OutsideITBlock()); 6650 MacroEmissionCheckScope guard(this); 6651 ITScope it_scope(this, &cond, guard); 6652 vcvtt(cond, dt1, dt2, rd, rm); 6653 } 6654 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 6655 Vcvtt(al, dt1, dt2, rd, rm); 6656 } 6657 6658 void Vcvtt( 6659 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6660 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6662 VIXL_ASSERT(allow_macro_instructions_); 6663 VIXL_ASSERT(OutsideITBlock()); 6664 MacroEmissionCheckScope guard(this); 6665 ITScope it_scope(this, &cond, guard); 6666 vcvtt(cond, dt1, dt2, rd, rm); 6667 } 6668 void Vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 6669 Vcvtt(al, dt1, dt2, rd, rm); 6670 } 6671 6672 void Vcvtt( 6673 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6674 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6675 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6676 VIXL_ASSERT(allow_macro_instructions_); 6677 VIXL_ASSERT(OutsideITBlock()); 6678 MacroEmissionCheckScope guard(this); 6679 ITScope it_scope(this, &cond, guard); 6680 vcvtt(cond, dt1, dt2, rd, rm); 6681 } 6682 void Vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 6683 Vcvtt(al, dt1, dt2, rd, rm); 6684 } 6685 6686 void Vdiv( 6687 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6688 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6689 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6690 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6691 VIXL_ASSERT(allow_macro_instructions_); 6692 VIXL_ASSERT(OutsideITBlock()); 6693 MacroEmissionCheckScope guard(this); 6694 ITScope it_scope(this, &cond, guard); 6695 vdiv(cond, dt, rd, rn, rm); 6696 } 6697 void Vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6698 Vdiv(al, dt, rd, rn, rm); 6699 } 6700 6701 void Vdiv( 6702 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6703 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6704 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6705 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6706 VIXL_ASSERT(allow_macro_instructions_); 6707 VIXL_ASSERT(OutsideITBlock()); 6708 MacroEmissionCheckScope guard(this); 6709 ITScope it_scope(this, &cond, guard); 6710 vdiv(cond, dt, rd, rn, rm); 6711 } 6712 void Vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6713 Vdiv(al, dt, rd, rn, rm); 6714 } 6715 6716 void Vdup(Condition cond, DataType dt, QRegister rd, Register rt) { 6717 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6718 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 6719 VIXL_ASSERT(allow_macro_instructions_); 6720 VIXL_ASSERT(OutsideITBlock()); 6721 MacroEmissionCheckScope guard(this); 6722 ITScope it_scope(this, &cond, guard); 6723 vdup(cond, dt, rd, rt); 6724 } 6725 void Vdup(DataType dt, QRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 6726 6727 void Vdup(Condition cond, DataType dt, DRegister rd, Register rt) { 6728 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6729 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 6730 VIXL_ASSERT(allow_macro_instructions_); 6731 VIXL_ASSERT(OutsideITBlock()); 6732 MacroEmissionCheckScope guard(this); 6733 ITScope it_scope(this, &cond, guard); 6734 vdup(cond, dt, rd, rt); 6735 } 6736 void Vdup(DataType dt, DRegister rd, Register rt) { Vdup(al, dt, rd, rt); } 6737 6738 void Vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm) { 6739 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6740 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6741 VIXL_ASSERT(allow_macro_instructions_); 6742 VIXL_ASSERT(OutsideITBlock()); 6743 MacroEmissionCheckScope guard(this); 6744 ITScope it_scope(this, &cond, guard); 6745 vdup(cond, dt, rd, rm); 6746 } 6747 void Vdup(DataType dt, DRegister rd, DRegisterLane rm) { 6748 Vdup(al, dt, rd, rm); 6749 } 6750 6751 void Vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm) { 6752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6753 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6754 VIXL_ASSERT(allow_macro_instructions_); 6755 VIXL_ASSERT(OutsideITBlock()); 6756 MacroEmissionCheckScope guard(this); 6757 ITScope it_scope(this, &cond, guard); 6758 vdup(cond, dt, rd, rm); 6759 } 6760 void Vdup(DataType dt, QRegister rd, DRegisterLane rm) { 6761 Vdup(al, dt, rd, rm); 6762 } 6763 6764 void Veor( 6765 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6766 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6767 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6768 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6769 VIXL_ASSERT(allow_macro_instructions_); 6770 VIXL_ASSERT(OutsideITBlock()); 6771 MacroEmissionCheckScope guard(this); 6772 ITScope it_scope(this, &cond, guard); 6773 veor(cond, dt, rd, rn, rm); 6774 } 6775 void Veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6776 Veor(al, dt, rd, rn, rm); 6777 } 6778 void Veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 6779 Veor(cond, kDataTypeValueNone, rd, rn, rm); 6780 } 6781 void Veor(DRegister rd, DRegister rn, DRegister rm) { 6782 Veor(al, kDataTypeValueNone, rd, rn, rm); 6783 } 6784 6785 void Veor( 6786 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6787 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6790 VIXL_ASSERT(allow_macro_instructions_); 6791 VIXL_ASSERT(OutsideITBlock()); 6792 MacroEmissionCheckScope guard(this); 6793 ITScope it_scope(this, &cond, guard); 6794 veor(cond, dt, rd, rn, rm); 6795 } 6796 void Veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6797 Veor(al, dt, rd, rn, rm); 6798 } 6799 void Veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 6800 Veor(cond, kDataTypeValueNone, rd, rn, rm); 6801 } 6802 void Veor(QRegister rd, QRegister rn, QRegister rm) { 6803 Veor(al, kDataTypeValueNone, rd, rn, rm); 6804 } 6805 6806 void Vext(Condition cond, 6807 DataType dt, 6808 DRegister rd, 6809 DRegister rn, 6810 DRegister rm, 6811 const DOperand& operand) { 6812 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6813 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6814 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6815 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6816 VIXL_ASSERT(allow_macro_instructions_); 6817 VIXL_ASSERT(OutsideITBlock()); 6818 MacroEmissionCheckScope guard(this); 6819 ITScope it_scope(this, &cond, guard); 6820 vext(cond, dt, rd, rn, rm, operand); 6821 } 6822 void Vext(DataType dt, 6823 DRegister rd, 6824 DRegister rn, 6825 DRegister rm, 6826 const DOperand& operand) { 6827 Vext(al, dt, rd, rn, rm, operand); 6828 } 6829 6830 void Vext(Condition cond, 6831 DataType dt, 6832 QRegister rd, 6833 QRegister rn, 6834 QRegister rm, 6835 const QOperand& operand) { 6836 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6837 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6838 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6839 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 6840 VIXL_ASSERT(allow_macro_instructions_); 6841 VIXL_ASSERT(OutsideITBlock()); 6842 MacroEmissionCheckScope guard(this); 6843 ITScope it_scope(this, &cond, guard); 6844 vext(cond, dt, rd, rn, rm, operand); 6845 } 6846 void Vext(DataType dt, 6847 QRegister rd, 6848 QRegister rn, 6849 QRegister rm, 6850 const QOperand& operand) { 6851 Vext(al, dt, rd, rn, rm, operand); 6852 } 6853 6854 void Vfma( 6855 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6856 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6857 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6858 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6859 VIXL_ASSERT(allow_macro_instructions_); 6860 VIXL_ASSERT(OutsideITBlock()); 6861 MacroEmissionCheckScope guard(this); 6862 ITScope it_scope(this, &cond, guard); 6863 vfma(cond, dt, rd, rn, rm); 6864 } 6865 void Vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6866 Vfma(al, dt, rd, rn, rm); 6867 } 6868 6869 void Vfma( 6870 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6871 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6872 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6873 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6874 VIXL_ASSERT(allow_macro_instructions_); 6875 VIXL_ASSERT(OutsideITBlock()); 6876 MacroEmissionCheckScope guard(this); 6877 ITScope it_scope(this, &cond, guard); 6878 vfma(cond, dt, rd, rn, rm); 6879 } 6880 void Vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6881 Vfma(al, dt, rd, rn, rm); 6882 } 6883 6884 void Vfma( 6885 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6886 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6887 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6888 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6889 VIXL_ASSERT(allow_macro_instructions_); 6890 VIXL_ASSERT(OutsideITBlock()); 6891 MacroEmissionCheckScope guard(this); 6892 ITScope it_scope(this, &cond, guard); 6893 vfma(cond, dt, rd, rn, rm); 6894 } 6895 void Vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6896 Vfma(al, dt, rd, rn, rm); 6897 } 6898 6899 void Vfms( 6900 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6901 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6903 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6904 VIXL_ASSERT(allow_macro_instructions_); 6905 VIXL_ASSERT(OutsideITBlock()); 6906 MacroEmissionCheckScope guard(this); 6907 ITScope it_scope(this, &cond, guard); 6908 vfms(cond, dt, rd, rn, rm); 6909 } 6910 void Vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6911 Vfms(al, dt, rd, rn, rm); 6912 } 6913 6914 void Vfms( 6915 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6916 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6917 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6918 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6919 VIXL_ASSERT(allow_macro_instructions_); 6920 VIXL_ASSERT(OutsideITBlock()); 6921 MacroEmissionCheckScope guard(this); 6922 ITScope it_scope(this, &cond, guard); 6923 vfms(cond, dt, rd, rn, rm); 6924 } 6925 void Vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6926 Vfms(al, dt, rd, rn, rm); 6927 } 6928 6929 void Vfms( 6930 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6931 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6932 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6933 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6934 VIXL_ASSERT(allow_macro_instructions_); 6935 VIXL_ASSERT(OutsideITBlock()); 6936 MacroEmissionCheckScope guard(this); 6937 ITScope it_scope(this, &cond, guard); 6938 vfms(cond, dt, rd, rn, rm); 6939 } 6940 void Vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6941 Vfms(al, dt, rd, rn, rm); 6942 } 6943 6944 void Vfnma( 6945 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6946 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6947 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6948 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6949 VIXL_ASSERT(allow_macro_instructions_); 6950 VIXL_ASSERT(OutsideITBlock()); 6951 MacroEmissionCheckScope guard(this); 6952 ITScope it_scope(this, &cond, guard); 6953 vfnma(cond, dt, rd, rn, rm); 6954 } 6955 void Vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6956 Vfnma(al, dt, rd, rn, rm); 6957 } 6958 6959 void Vfnma( 6960 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6961 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6962 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6963 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6964 VIXL_ASSERT(allow_macro_instructions_); 6965 VIXL_ASSERT(OutsideITBlock()); 6966 MacroEmissionCheckScope guard(this); 6967 ITScope it_scope(this, &cond, guard); 6968 vfnma(cond, dt, rd, rn, rm); 6969 } 6970 void Vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6971 Vfnma(al, dt, rd, rn, rm); 6972 } 6973 6974 void Vfnms( 6975 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6976 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6977 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6978 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6979 VIXL_ASSERT(allow_macro_instructions_); 6980 VIXL_ASSERT(OutsideITBlock()); 6981 MacroEmissionCheckScope guard(this); 6982 ITScope it_scope(this, &cond, guard); 6983 vfnms(cond, dt, rd, rn, rm); 6984 } 6985 void Vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6986 Vfnms(al, dt, rd, rn, rm); 6987 } 6988 6989 void Vfnms( 6990 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 6992 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 6993 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 6994 VIXL_ASSERT(allow_macro_instructions_); 6995 VIXL_ASSERT(OutsideITBlock()); 6996 MacroEmissionCheckScope guard(this); 6997 ITScope it_scope(this, &cond, guard); 6998 vfnms(cond, dt, rd, rn, rm); 6999 } 7000 void Vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7001 Vfnms(al, dt, rd, rn, rm); 7002 } 7003 7004 void Vhadd( 7005 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7006 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7007 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7008 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7009 VIXL_ASSERT(allow_macro_instructions_); 7010 VIXL_ASSERT(OutsideITBlock()); 7011 MacroEmissionCheckScope guard(this); 7012 ITScope it_scope(this, &cond, guard); 7013 vhadd(cond, dt, rd, rn, rm); 7014 } 7015 void Vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7016 Vhadd(al, dt, rd, rn, rm); 7017 } 7018 7019 void Vhadd( 7020 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7021 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7022 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7023 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7024 VIXL_ASSERT(allow_macro_instructions_); 7025 VIXL_ASSERT(OutsideITBlock()); 7026 MacroEmissionCheckScope guard(this); 7027 ITScope it_scope(this, &cond, guard); 7028 vhadd(cond, dt, rd, rn, rm); 7029 } 7030 void Vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7031 Vhadd(al, dt, rd, rn, rm); 7032 } 7033 7034 void Vhsub( 7035 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7036 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7037 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7038 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7039 VIXL_ASSERT(allow_macro_instructions_); 7040 VIXL_ASSERT(OutsideITBlock()); 7041 MacroEmissionCheckScope guard(this); 7042 ITScope it_scope(this, &cond, guard); 7043 vhsub(cond, dt, rd, rn, rm); 7044 } 7045 void Vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7046 Vhsub(al, dt, rd, rn, rm); 7047 } 7048 7049 void Vhsub( 7050 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7051 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7052 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7053 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7054 VIXL_ASSERT(allow_macro_instructions_); 7055 VIXL_ASSERT(OutsideITBlock()); 7056 MacroEmissionCheckScope guard(this); 7057 ITScope it_scope(this, &cond, guard); 7058 vhsub(cond, dt, rd, rn, rm); 7059 } 7060 void Vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7061 Vhsub(al, dt, rd, rn, rm); 7062 } 7063 7064 void Vld1(Condition cond, 7065 DataType dt, 7066 const NeonRegisterList& nreglist, 7067 const AlignedMemOperand& operand) { 7068 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7069 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7070 VIXL_ASSERT(allow_macro_instructions_); 7071 VIXL_ASSERT(OutsideITBlock()); 7072 MacroEmissionCheckScope guard(this); 7073 ITScope it_scope(this, &cond, guard); 7074 vld1(cond, dt, nreglist, operand); 7075 } 7076 void Vld1(DataType dt, 7077 const NeonRegisterList& nreglist, 7078 const AlignedMemOperand& operand) { 7079 Vld1(al, dt, nreglist, operand); 7080 } 7081 7082 void Vld2(Condition cond, 7083 DataType dt, 7084 const NeonRegisterList& nreglist, 7085 const AlignedMemOperand& operand) { 7086 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7087 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7088 VIXL_ASSERT(allow_macro_instructions_); 7089 VIXL_ASSERT(OutsideITBlock()); 7090 MacroEmissionCheckScope guard(this); 7091 ITScope it_scope(this, &cond, guard); 7092 vld2(cond, dt, nreglist, operand); 7093 } 7094 void Vld2(DataType dt, 7095 const NeonRegisterList& nreglist, 7096 const AlignedMemOperand& operand) { 7097 Vld2(al, dt, nreglist, operand); 7098 } 7099 7100 void Vld3(Condition cond, 7101 DataType dt, 7102 const NeonRegisterList& nreglist, 7103 const AlignedMemOperand& operand) { 7104 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7105 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7106 VIXL_ASSERT(allow_macro_instructions_); 7107 VIXL_ASSERT(OutsideITBlock()); 7108 MacroEmissionCheckScope guard(this); 7109 ITScope it_scope(this, &cond, guard); 7110 vld3(cond, dt, nreglist, operand); 7111 } 7112 void Vld3(DataType dt, 7113 const NeonRegisterList& nreglist, 7114 const AlignedMemOperand& operand) { 7115 Vld3(al, dt, nreglist, operand); 7116 } 7117 7118 void Vld3(Condition cond, 7119 DataType dt, 7120 const NeonRegisterList& nreglist, 7121 const MemOperand& operand) { 7122 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7123 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7124 VIXL_ASSERT(allow_macro_instructions_); 7125 VIXL_ASSERT(OutsideITBlock()); 7126 MacroEmissionCheckScope guard(this); 7127 ITScope it_scope(this, &cond, guard); 7128 vld3(cond, dt, nreglist, operand); 7129 } 7130 void Vld3(DataType dt, 7131 const NeonRegisterList& nreglist, 7132 const MemOperand& operand) { 7133 Vld3(al, dt, nreglist, operand); 7134 } 7135 7136 void Vld4(Condition cond, 7137 DataType dt, 7138 const NeonRegisterList& nreglist, 7139 const AlignedMemOperand& operand) { 7140 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 7141 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7142 VIXL_ASSERT(allow_macro_instructions_); 7143 VIXL_ASSERT(OutsideITBlock()); 7144 MacroEmissionCheckScope guard(this); 7145 ITScope it_scope(this, &cond, guard); 7146 vld4(cond, dt, nreglist, operand); 7147 } 7148 void Vld4(DataType dt, 7149 const NeonRegisterList& nreglist, 7150 const AlignedMemOperand& operand) { 7151 Vld4(al, dt, nreglist, operand); 7152 } 7153 7154 void Vldm(Condition cond, 7155 DataType dt, 7156 Register rn, 7157 WriteBack write_back, 7158 DRegisterList dreglist) { 7159 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7160 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7161 VIXL_ASSERT(allow_macro_instructions_); 7162 VIXL_ASSERT(OutsideITBlock()); 7163 MacroEmissionCheckScope guard(this); 7164 ITScope it_scope(this, &cond, guard); 7165 vldm(cond, dt, rn, write_back, dreglist); 7166 } 7167 void Vldm(DataType dt, 7168 Register rn, 7169 WriteBack write_back, 7170 DRegisterList dreglist) { 7171 Vldm(al, dt, rn, write_back, dreglist); 7172 } 7173 void Vldm(Condition cond, 7174 Register rn, 7175 WriteBack write_back, 7176 DRegisterList dreglist) { 7177 Vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 7178 } 7179 void Vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 7180 Vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 7181 } 7182 7183 void Vldm(Condition cond, 7184 DataType dt, 7185 Register rn, 7186 WriteBack write_back, 7187 SRegisterList sreglist) { 7188 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7189 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7190 VIXL_ASSERT(allow_macro_instructions_); 7191 VIXL_ASSERT(OutsideITBlock()); 7192 MacroEmissionCheckScope guard(this); 7193 ITScope it_scope(this, &cond, guard); 7194 vldm(cond, dt, rn, write_back, sreglist); 7195 } 7196 void Vldm(DataType dt, 7197 Register rn, 7198 WriteBack write_back, 7199 SRegisterList sreglist) { 7200 Vldm(al, dt, rn, write_back, sreglist); 7201 } 7202 void Vldm(Condition cond, 7203 Register rn, 7204 WriteBack write_back, 7205 SRegisterList sreglist) { 7206 Vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 7207 } 7208 void Vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 7209 Vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 7210 } 7211 7212 void Vldmdb(Condition cond, 7213 DataType dt, 7214 Register rn, 7215 WriteBack write_back, 7216 DRegisterList dreglist) { 7217 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7218 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7219 VIXL_ASSERT(allow_macro_instructions_); 7220 VIXL_ASSERT(OutsideITBlock()); 7221 MacroEmissionCheckScope guard(this); 7222 ITScope it_scope(this, &cond, guard); 7223 vldmdb(cond, dt, rn, write_back, dreglist); 7224 } 7225 void Vldmdb(DataType dt, 7226 Register rn, 7227 WriteBack write_back, 7228 DRegisterList dreglist) { 7229 Vldmdb(al, dt, rn, write_back, dreglist); 7230 } 7231 void Vldmdb(Condition cond, 7232 Register rn, 7233 WriteBack write_back, 7234 DRegisterList dreglist) { 7235 Vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 7236 } 7237 void Vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 7238 Vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 7239 } 7240 7241 void Vldmdb(Condition cond, 7242 DataType dt, 7243 Register rn, 7244 WriteBack write_back, 7245 SRegisterList sreglist) { 7246 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7247 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7248 VIXL_ASSERT(allow_macro_instructions_); 7249 VIXL_ASSERT(OutsideITBlock()); 7250 MacroEmissionCheckScope guard(this); 7251 ITScope it_scope(this, &cond, guard); 7252 vldmdb(cond, dt, rn, write_back, sreglist); 7253 } 7254 void Vldmdb(DataType dt, 7255 Register rn, 7256 WriteBack write_back, 7257 SRegisterList sreglist) { 7258 Vldmdb(al, dt, rn, write_back, sreglist); 7259 } 7260 void Vldmdb(Condition cond, 7261 Register rn, 7262 WriteBack write_back, 7263 SRegisterList sreglist) { 7264 Vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 7265 } 7266 void Vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 7267 Vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 7268 } 7269 7270 void Vldmia(Condition cond, 7271 DataType dt, 7272 Register rn, 7273 WriteBack write_back, 7274 DRegisterList dreglist) { 7275 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7276 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 7277 VIXL_ASSERT(allow_macro_instructions_); 7278 VIXL_ASSERT(OutsideITBlock()); 7279 MacroEmissionCheckScope guard(this); 7280 ITScope it_scope(this, &cond, guard); 7281 vldmia(cond, dt, rn, write_back, dreglist); 7282 } 7283 void Vldmia(DataType dt, 7284 Register rn, 7285 WriteBack write_back, 7286 DRegisterList dreglist) { 7287 Vldmia(al, dt, rn, write_back, dreglist); 7288 } 7289 void Vldmia(Condition cond, 7290 Register rn, 7291 WriteBack write_back, 7292 DRegisterList dreglist) { 7293 Vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 7294 } 7295 void Vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 7296 Vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 7297 } 7298 7299 void Vldmia(Condition cond, 7300 DataType dt, 7301 Register rn, 7302 WriteBack write_back, 7303 SRegisterList sreglist) { 7304 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7305 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 7306 VIXL_ASSERT(allow_macro_instructions_); 7307 VIXL_ASSERT(OutsideITBlock()); 7308 MacroEmissionCheckScope guard(this); 7309 ITScope it_scope(this, &cond, guard); 7310 vldmia(cond, dt, rn, write_back, sreglist); 7311 } 7312 void Vldmia(DataType dt, 7313 Register rn, 7314 WriteBack write_back, 7315 SRegisterList sreglist) { 7316 Vldmia(al, dt, rn, write_back, sreglist); 7317 } 7318 void Vldmia(Condition cond, 7319 Register rn, 7320 WriteBack write_back, 7321 SRegisterList sreglist) { 7322 Vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 7323 } 7324 void Vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 7325 Vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 7326 } 7327 7328 7329 void Vldr(Condition cond, 7330 DataType dt, 7331 DRegister rd, 7332 const MemOperand& operand) { 7333 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7334 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7335 VIXL_ASSERT(allow_macro_instructions_); 7336 VIXL_ASSERT(OutsideITBlock()); 7337 MacroEmissionCheckScope guard(this); 7338 ITScope it_scope(this, &cond, guard); 7339 vldr(cond, dt, rd, operand); 7340 } 7341 void Vldr(DataType dt, DRegister rd, const MemOperand& operand) { 7342 Vldr(al, dt, rd, operand); 7343 } 7344 void Vldr(Condition cond, DRegister rd, const MemOperand& operand) { 7345 Vldr(cond, Untyped64, rd, operand); 7346 } 7347 void Vldr(DRegister rd, const MemOperand& operand) { 7348 Vldr(al, Untyped64, rd, operand); 7349 } 7350 7351 7352 void Vldr(Condition cond, 7353 DataType dt, 7354 SRegister rd, 7355 const MemOperand& operand) { 7356 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7357 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7358 VIXL_ASSERT(allow_macro_instructions_); 7359 VIXL_ASSERT(OutsideITBlock()); 7360 MacroEmissionCheckScope guard(this); 7361 ITScope it_scope(this, &cond, guard); 7362 vldr(cond, dt, rd, operand); 7363 } 7364 void Vldr(DataType dt, SRegister rd, const MemOperand& operand) { 7365 Vldr(al, dt, rd, operand); 7366 } 7367 void Vldr(Condition cond, SRegister rd, const MemOperand& operand) { 7368 Vldr(cond, Untyped32, rd, operand); 7369 } 7370 void Vldr(SRegister rd, const MemOperand& operand) { 7371 Vldr(al, Untyped32, rd, operand); 7372 } 7373 7374 void Vmax( 7375 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7376 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7377 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7378 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7379 VIXL_ASSERT(allow_macro_instructions_); 7380 VIXL_ASSERT(OutsideITBlock()); 7381 MacroEmissionCheckScope guard(this); 7382 ITScope it_scope(this, &cond, guard); 7383 vmax(cond, dt, rd, rn, rm); 7384 } 7385 void Vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7386 Vmax(al, dt, rd, rn, rm); 7387 } 7388 7389 void Vmax( 7390 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7391 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7392 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7393 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7394 VIXL_ASSERT(allow_macro_instructions_); 7395 VIXL_ASSERT(OutsideITBlock()); 7396 MacroEmissionCheckScope guard(this); 7397 ITScope it_scope(this, &cond, guard); 7398 vmax(cond, dt, rd, rn, rm); 7399 } 7400 void Vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7401 Vmax(al, dt, rd, rn, rm); 7402 } 7403 7404 void Vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7405 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7406 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7407 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7408 VIXL_ASSERT(allow_macro_instructions_); 7409 VIXL_ASSERT(OutsideITBlock()); 7410 MacroEmissionCheckScope guard(this); 7411 vmaxnm(dt, rd, rn, rm); 7412 } 7413 7414 void Vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7415 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7416 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7417 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7418 VIXL_ASSERT(allow_macro_instructions_); 7419 VIXL_ASSERT(OutsideITBlock()); 7420 MacroEmissionCheckScope guard(this); 7421 vmaxnm(dt, rd, rn, rm); 7422 } 7423 7424 void Vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7425 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7426 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7427 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7428 VIXL_ASSERT(allow_macro_instructions_); 7429 VIXL_ASSERT(OutsideITBlock()); 7430 MacroEmissionCheckScope guard(this); 7431 vmaxnm(dt, rd, rn, rm); 7432 } 7433 7434 void Vmin( 7435 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7436 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7437 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7438 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7439 VIXL_ASSERT(allow_macro_instructions_); 7440 VIXL_ASSERT(OutsideITBlock()); 7441 MacroEmissionCheckScope guard(this); 7442 ITScope it_scope(this, &cond, guard); 7443 vmin(cond, dt, rd, rn, rm); 7444 } 7445 void Vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7446 Vmin(al, dt, rd, rn, rm); 7447 } 7448 7449 void Vmin( 7450 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7451 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7452 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7453 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7454 VIXL_ASSERT(allow_macro_instructions_); 7455 VIXL_ASSERT(OutsideITBlock()); 7456 MacroEmissionCheckScope guard(this); 7457 ITScope it_scope(this, &cond, guard); 7458 vmin(cond, dt, rd, rn, rm); 7459 } 7460 void Vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7461 Vmin(al, dt, rd, rn, rm); 7462 } 7463 7464 void Vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7465 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7466 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7467 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7468 VIXL_ASSERT(allow_macro_instructions_); 7469 VIXL_ASSERT(OutsideITBlock()); 7470 MacroEmissionCheckScope guard(this); 7471 vminnm(dt, rd, rn, rm); 7472 } 7473 7474 void Vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7475 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7476 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7477 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7478 VIXL_ASSERT(allow_macro_instructions_); 7479 VIXL_ASSERT(OutsideITBlock()); 7480 MacroEmissionCheckScope guard(this); 7481 vminnm(dt, rd, rn, rm); 7482 } 7483 7484 void Vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7485 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7486 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7487 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7488 VIXL_ASSERT(allow_macro_instructions_); 7489 VIXL_ASSERT(OutsideITBlock()); 7490 MacroEmissionCheckScope guard(this); 7491 vminnm(dt, rd, rn, rm); 7492 } 7493 7494 void Vmla(Condition cond, 7495 DataType dt, 7496 DRegister rd, 7497 DRegister rn, 7498 DRegisterLane rm) { 7499 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7500 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7501 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7502 VIXL_ASSERT(allow_macro_instructions_); 7503 VIXL_ASSERT(OutsideITBlock()); 7504 MacroEmissionCheckScope guard(this); 7505 ITScope it_scope(this, &cond, guard); 7506 vmla(cond, dt, rd, rn, rm); 7507 } 7508 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7509 Vmla(al, dt, rd, rn, rm); 7510 } 7511 7512 void Vmla(Condition cond, 7513 DataType dt, 7514 QRegister rd, 7515 QRegister rn, 7516 DRegisterLane rm) { 7517 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7518 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7519 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7520 VIXL_ASSERT(allow_macro_instructions_); 7521 VIXL_ASSERT(OutsideITBlock()); 7522 MacroEmissionCheckScope guard(this); 7523 ITScope it_scope(this, &cond, guard); 7524 vmla(cond, dt, rd, rn, rm); 7525 } 7526 void Vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7527 Vmla(al, dt, rd, rn, rm); 7528 } 7529 7530 void Vmla( 7531 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7532 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7533 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7534 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7535 VIXL_ASSERT(allow_macro_instructions_); 7536 VIXL_ASSERT(OutsideITBlock()); 7537 MacroEmissionCheckScope guard(this); 7538 ITScope it_scope(this, &cond, guard); 7539 vmla(cond, dt, rd, rn, rm); 7540 } 7541 void Vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7542 Vmla(al, dt, rd, rn, rm); 7543 } 7544 7545 void Vmla( 7546 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7547 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7548 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7549 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7550 VIXL_ASSERT(allow_macro_instructions_); 7551 VIXL_ASSERT(OutsideITBlock()); 7552 MacroEmissionCheckScope guard(this); 7553 ITScope it_scope(this, &cond, guard); 7554 vmla(cond, dt, rd, rn, rm); 7555 } 7556 void Vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7557 Vmla(al, dt, rd, rn, rm); 7558 } 7559 7560 void Vmla( 7561 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7562 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7564 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7565 VIXL_ASSERT(allow_macro_instructions_); 7566 VIXL_ASSERT(OutsideITBlock()); 7567 MacroEmissionCheckScope guard(this); 7568 ITScope it_scope(this, &cond, guard); 7569 vmla(cond, dt, rd, rn, rm); 7570 } 7571 void Vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7572 Vmla(al, dt, rd, rn, rm); 7573 } 7574 7575 void Vmlal(Condition cond, 7576 DataType dt, 7577 QRegister rd, 7578 DRegister rn, 7579 DRegisterLane rm) { 7580 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7581 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7582 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7583 VIXL_ASSERT(allow_macro_instructions_); 7584 VIXL_ASSERT(OutsideITBlock()); 7585 MacroEmissionCheckScope guard(this); 7586 ITScope it_scope(this, &cond, guard); 7587 vmlal(cond, dt, rd, rn, rm); 7588 } 7589 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 7590 Vmlal(al, dt, rd, rn, rm); 7591 } 7592 7593 void Vmlal( 7594 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7595 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7596 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7597 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7598 VIXL_ASSERT(allow_macro_instructions_); 7599 VIXL_ASSERT(OutsideITBlock()); 7600 MacroEmissionCheckScope guard(this); 7601 ITScope it_scope(this, &cond, guard); 7602 vmlal(cond, dt, rd, rn, rm); 7603 } 7604 void Vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7605 Vmlal(al, dt, rd, rn, rm); 7606 } 7607 7608 void Vmls(Condition cond, 7609 DataType dt, 7610 DRegister rd, 7611 DRegister rn, 7612 DRegisterLane rm) { 7613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7614 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7615 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7616 VIXL_ASSERT(allow_macro_instructions_); 7617 VIXL_ASSERT(OutsideITBlock()); 7618 MacroEmissionCheckScope guard(this); 7619 ITScope it_scope(this, &cond, guard); 7620 vmls(cond, dt, rd, rn, rm); 7621 } 7622 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 7623 Vmls(al, dt, rd, rn, rm); 7624 } 7625 7626 void Vmls(Condition cond, 7627 DataType dt, 7628 QRegister rd, 7629 QRegister rn, 7630 DRegisterLane rm) { 7631 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7632 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7633 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7634 VIXL_ASSERT(allow_macro_instructions_); 7635 VIXL_ASSERT(OutsideITBlock()); 7636 MacroEmissionCheckScope guard(this); 7637 ITScope it_scope(this, &cond, guard); 7638 vmls(cond, dt, rd, rn, rm); 7639 } 7640 void Vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 7641 Vmls(al, dt, rd, rn, rm); 7642 } 7643 7644 void Vmls( 7645 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7646 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7647 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7648 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7649 VIXL_ASSERT(allow_macro_instructions_); 7650 VIXL_ASSERT(OutsideITBlock()); 7651 MacroEmissionCheckScope guard(this); 7652 ITScope it_scope(this, &cond, guard); 7653 vmls(cond, dt, rd, rn, rm); 7654 } 7655 void Vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7656 Vmls(al, dt, rd, rn, rm); 7657 } 7658 7659 void Vmls( 7660 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7661 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7662 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7664 VIXL_ASSERT(allow_macro_instructions_); 7665 VIXL_ASSERT(OutsideITBlock()); 7666 MacroEmissionCheckScope guard(this); 7667 ITScope it_scope(this, &cond, guard); 7668 vmls(cond, dt, rd, rn, rm); 7669 } 7670 void Vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7671 Vmls(al, dt, rd, rn, rm); 7672 } 7673 7674 void Vmls( 7675 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7676 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7678 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7679 VIXL_ASSERT(allow_macro_instructions_); 7680 VIXL_ASSERT(OutsideITBlock()); 7681 MacroEmissionCheckScope guard(this); 7682 ITScope it_scope(this, &cond, guard); 7683 vmls(cond, dt, rd, rn, rm); 7684 } 7685 void Vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 7686 Vmls(al, dt, rd, rn, rm); 7687 } 7688 7689 void Vmlsl(Condition cond, 7690 DataType dt, 7691 QRegister rd, 7692 DRegister rn, 7693 DRegisterLane rm) { 7694 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7695 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7696 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7697 VIXL_ASSERT(allow_macro_instructions_); 7698 VIXL_ASSERT(OutsideITBlock()); 7699 MacroEmissionCheckScope guard(this); 7700 ITScope it_scope(this, &cond, guard); 7701 vmlsl(cond, dt, rd, rn, rm); 7702 } 7703 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 7704 Vmlsl(al, dt, rd, rn, rm); 7705 } 7706 7707 void Vmlsl( 7708 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7709 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7710 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7711 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7712 VIXL_ASSERT(allow_macro_instructions_); 7713 VIXL_ASSERT(OutsideITBlock()); 7714 MacroEmissionCheckScope guard(this); 7715 ITScope it_scope(this, &cond, guard); 7716 vmlsl(cond, dt, rd, rn, rm); 7717 } 7718 void Vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 7719 Vmlsl(al, dt, rd, rn, rm); 7720 } 7721 7722 void Vmov(Condition cond, Register rt, SRegister rn) { 7723 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7724 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7725 VIXL_ASSERT(allow_macro_instructions_); 7726 VIXL_ASSERT(OutsideITBlock()); 7727 MacroEmissionCheckScope guard(this); 7728 ITScope it_scope(this, &cond, guard); 7729 vmov(cond, rt, rn); 7730 } 7731 void Vmov(Register rt, SRegister rn) { Vmov(al, rt, rn); } 7732 7733 void Vmov(Condition cond, SRegister rn, Register rt) { 7734 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7735 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7736 VIXL_ASSERT(allow_macro_instructions_); 7737 VIXL_ASSERT(OutsideITBlock()); 7738 MacroEmissionCheckScope guard(this); 7739 ITScope it_scope(this, &cond, guard); 7740 vmov(cond, rn, rt); 7741 } 7742 void Vmov(SRegister rn, Register rt) { Vmov(al, rn, rt); } 7743 7744 void Vmov(Condition cond, Register rt, Register rt2, DRegister rm) { 7745 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7746 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7747 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7748 VIXL_ASSERT(allow_macro_instructions_); 7749 VIXL_ASSERT(OutsideITBlock()); 7750 MacroEmissionCheckScope guard(this); 7751 ITScope it_scope(this, &cond, guard); 7752 vmov(cond, rt, rt2, rm); 7753 } 7754 void Vmov(Register rt, Register rt2, DRegister rm) { Vmov(al, rt, rt2, rm); } 7755 7756 void Vmov(Condition cond, DRegister rm, Register rt, Register rt2) { 7757 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7758 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7759 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7760 VIXL_ASSERT(allow_macro_instructions_); 7761 VIXL_ASSERT(OutsideITBlock()); 7762 MacroEmissionCheckScope guard(this); 7763 ITScope it_scope(this, &cond, guard); 7764 vmov(cond, rm, rt, rt2); 7765 } 7766 void Vmov(DRegister rm, Register rt, Register rt2) { Vmov(al, rm, rt, rt2); } 7767 7768 void Vmov( 7769 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1) { 7770 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7771 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7772 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7773 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm1)); 7774 VIXL_ASSERT(allow_macro_instructions_); 7775 VIXL_ASSERT(OutsideITBlock()); 7776 MacroEmissionCheckScope guard(this); 7777 ITScope it_scope(this, &cond, guard); 7778 vmov(cond, rt, rt2, rm, rm1); 7779 } 7780 void Vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 7781 Vmov(al, rt, rt2, rm, rm1); 7782 } 7783 7784 void Vmov( 7785 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2) { 7786 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7787 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm1)); 7788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7789 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt2)); 7790 VIXL_ASSERT(allow_macro_instructions_); 7791 VIXL_ASSERT(OutsideITBlock()); 7792 MacroEmissionCheckScope guard(this); 7793 ITScope it_scope(this, &cond, guard); 7794 vmov(cond, rm, rm1, rt, rt2); 7795 } 7796 void Vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 7797 Vmov(al, rm, rm1, rt, rt2); 7798 } 7799 7800 void Vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt) { 7801 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7802 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7803 VIXL_ASSERT(allow_macro_instructions_); 7804 VIXL_ASSERT(OutsideITBlock()); 7805 MacroEmissionCheckScope guard(this); 7806 ITScope it_scope(this, &cond, guard); 7807 vmov(cond, dt, rd, rt); 7808 } 7809 void Vmov(DataType dt, DRegisterLane rd, Register rt) { 7810 Vmov(al, dt, rd, rt); 7811 } 7812 void Vmov(Condition cond, DRegisterLane rd, Register rt) { 7813 Vmov(cond, kDataTypeValueNone, rd, rt); 7814 } 7815 void Vmov(DRegisterLane rd, Register rt) { 7816 Vmov(al, kDataTypeValueNone, rd, rt); 7817 } 7818 7819 void Vmov(Condition cond, 7820 DataType dt, 7821 DRegister rd, 7822 const DOperand& operand) { 7823 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7824 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7825 VIXL_ASSERT(allow_macro_instructions_); 7826 VIXL_ASSERT(OutsideITBlock()); 7827 MacroEmissionCheckScope guard(this); 7828 ITScope it_scope(this, &cond, guard); 7829 vmov(cond, dt, rd, operand); 7830 } 7831 void Vmov(DataType dt, DRegister rd, const DOperand& operand) { 7832 Vmov(al, dt, rd, operand); 7833 } 7834 7835 void Vmov(Condition cond, 7836 DataType dt, 7837 QRegister rd, 7838 const QOperand& operand) { 7839 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7840 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7841 VIXL_ASSERT(allow_macro_instructions_); 7842 VIXL_ASSERT(OutsideITBlock()); 7843 MacroEmissionCheckScope guard(this); 7844 ITScope it_scope(this, &cond, guard); 7845 vmov(cond, dt, rd, operand); 7846 } 7847 void Vmov(DataType dt, QRegister rd, const QOperand& operand) { 7848 Vmov(al, dt, rd, operand); 7849 } 7850 7851 void Vmov(Condition cond, 7852 DataType dt, 7853 SRegister rd, 7854 const SOperand& operand) { 7855 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7856 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 7857 VIXL_ASSERT(allow_macro_instructions_); 7858 VIXL_ASSERT(OutsideITBlock()); 7859 MacroEmissionCheckScope guard(this); 7860 ITScope it_scope(this, &cond, guard); 7861 vmov(cond, dt, rd, operand); 7862 } 7863 void Vmov(DataType dt, SRegister rd, const SOperand& operand) { 7864 Vmov(al, dt, rd, operand); 7865 } 7866 7867 void Vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn) { 7868 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7869 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7870 VIXL_ASSERT(allow_macro_instructions_); 7871 VIXL_ASSERT(OutsideITBlock()); 7872 MacroEmissionCheckScope guard(this); 7873 ITScope it_scope(this, &cond, guard); 7874 vmov(cond, dt, rt, rn); 7875 } 7876 void Vmov(DataType dt, Register rt, DRegisterLane rn) { 7877 Vmov(al, dt, rt, rn); 7878 } 7879 void Vmov(Condition cond, Register rt, DRegisterLane rn) { 7880 Vmov(cond, kDataTypeValueNone, rt, rn); 7881 } 7882 void Vmov(Register rt, DRegisterLane rn) { 7883 Vmov(al, kDataTypeValueNone, rt, rn); 7884 } 7885 7886 void Vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm) { 7887 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7888 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7889 VIXL_ASSERT(allow_macro_instructions_); 7890 VIXL_ASSERT(OutsideITBlock()); 7891 MacroEmissionCheckScope guard(this); 7892 ITScope it_scope(this, &cond, guard); 7893 vmovl(cond, dt, rd, rm); 7894 } 7895 void Vmovl(DataType dt, QRegister rd, DRegister rm) { Vmovl(al, dt, rd, rm); } 7896 7897 void Vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 7898 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7899 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7900 VIXL_ASSERT(allow_macro_instructions_); 7901 VIXL_ASSERT(OutsideITBlock()); 7902 MacroEmissionCheckScope guard(this); 7903 ITScope it_scope(this, &cond, guard); 7904 vmovn(cond, dt, rd, rm); 7905 } 7906 void Vmovn(DataType dt, DRegister rd, QRegister rm) { Vmovn(al, dt, rd, rm); } 7907 7908 void Vmrs(Condition cond, 7909 RegisterOrAPSR_nzcv rt, 7910 SpecialFPRegister spec_reg) { 7911 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7912 VIXL_ASSERT(allow_macro_instructions_); 7913 VIXL_ASSERT(OutsideITBlock()); 7914 MacroEmissionCheckScope guard(this); 7915 ITScope it_scope(this, &cond, guard); 7916 vmrs(cond, rt, spec_reg); 7917 } 7918 void Vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 7919 Vmrs(al, rt, spec_reg); 7920 } 7921 7922 void Vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt) { 7923 VIXL_ASSERT(!AliasesAvailableScratchRegister(rt)); 7924 VIXL_ASSERT(allow_macro_instructions_); 7925 VIXL_ASSERT(OutsideITBlock()); 7926 MacroEmissionCheckScope guard(this); 7927 ITScope it_scope(this, &cond, guard); 7928 vmsr(cond, spec_reg, rt); 7929 } 7930 void Vmsr(SpecialFPRegister spec_reg, Register rt) { Vmsr(al, spec_reg, rt); } 7931 7932 void Vmul(Condition cond, 7933 DataType dt, 7934 DRegister rd, 7935 DRegister rn, 7936 DRegister dm, 7937 unsigned index) { 7938 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7939 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7940 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 7941 VIXL_ASSERT(allow_macro_instructions_); 7942 VIXL_ASSERT(OutsideITBlock()); 7943 MacroEmissionCheckScope guard(this); 7944 ITScope it_scope(this, &cond, guard); 7945 vmul(cond, dt, rd, rn, dm, index); 7946 } 7947 void Vmul( 7948 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 7949 Vmul(al, dt, rd, rn, dm, index); 7950 } 7951 7952 void Vmul(Condition cond, 7953 DataType dt, 7954 QRegister rd, 7955 QRegister rn, 7956 DRegister dm, 7957 unsigned index) { 7958 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7959 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7960 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 7961 VIXL_ASSERT(allow_macro_instructions_); 7962 VIXL_ASSERT(OutsideITBlock()); 7963 MacroEmissionCheckScope guard(this); 7964 ITScope it_scope(this, &cond, guard); 7965 vmul(cond, dt, rd, rn, dm, index); 7966 } 7967 void Vmul( 7968 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 7969 Vmul(al, dt, rd, rn, dm, index); 7970 } 7971 7972 void Vmul( 7973 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7974 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7975 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7976 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7977 VIXL_ASSERT(allow_macro_instructions_); 7978 VIXL_ASSERT(OutsideITBlock()); 7979 MacroEmissionCheckScope guard(this); 7980 ITScope it_scope(this, &cond, guard); 7981 vmul(cond, dt, rd, rn, rm); 7982 } 7983 void Vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 7984 Vmul(al, dt, rd, rn, rm); 7985 } 7986 7987 void Vmul( 7988 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7989 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 7990 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 7991 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 7992 VIXL_ASSERT(allow_macro_instructions_); 7993 VIXL_ASSERT(OutsideITBlock()); 7994 MacroEmissionCheckScope guard(this); 7995 ITScope it_scope(this, &cond, guard); 7996 vmul(cond, dt, rd, rn, rm); 7997 } 7998 void Vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 7999 Vmul(al, dt, rd, rn, rm); 8000 } 8001 8002 void Vmul( 8003 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8004 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8005 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8006 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8007 VIXL_ASSERT(allow_macro_instructions_); 8008 VIXL_ASSERT(OutsideITBlock()); 8009 MacroEmissionCheckScope guard(this); 8010 ITScope it_scope(this, &cond, guard); 8011 vmul(cond, dt, rd, rn, rm); 8012 } 8013 void Vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8014 Vmul(al, dt, rd, rn, rm); 8015 } 8016 8017 void Vmull(Condition cond, 8018 DataType dt, 8019 QRegister rd, 8020 DRegister rn, 8021 DRegister dm, 8022 unsigned index) { 8023 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8024 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8025 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 8026 VIXL_ASSERT(allow_macro_instructions_); 8027 VIXL_ASSERT(OutsideITBlock()); 8028 MacroEmissionCheckScope guard(this); 8029 ITScope it_scope(this, &cond, guard); 8030 vmull(cond, dt, rd, rn, dm, index); 8031 } 8032 void Vmull( 8033 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 8034 Vmull(al, dt, rd, rn, dm, index); 8035 } 8036 8037 void Vmull( 8038 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8039 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8042 VIXL_ASSERT(allow_macro_instructions_); 8043 VIXL_ASSERT(OutsideITBlock()); 8044 MacroEmissionCheckScope guard(this); 8045 ITScope it_scope(this, &cond, guard); 8046 vmull(cond, dt, rd, rn, rm); 8047 } 8048 void Vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8049 Vmull(al, dt, rd, rn, rm); 8050 } 8051 8052 void Vmvn(Condition cond, 8053 DataType dt, 8054 DRegister rd, 8055 const DOperand& operand) { 8056 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8057 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8058 VIXL_ASSERT(allow_macro_instructions_); 8059 VIXL_ASSERT(OutsideITBlock()); 8060 MacroEmissionCheckScope guard(this); 8061 ITScope it_scope(this, &cond, guard); 8062 vmvn(cond, dt, rd, operand); 8063 } 8064 void Vmvn(DataType dt, DRegister rd, const DOperand& operand) { 8065 Vmvn(al, dt, rd, operand); 8066 } 8067 8068 void Vmvn(Condition cond, 8069 DataType dt, 8070 QRegister rd, 8071 const QOperand& operand) { 8072 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8073 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8074 VIXL_ASSERT(allow_macro_instructions_); 8075 VIXL_ASSERT(OutsideITBlock()); 8076 MacroEmissionCheckScope guard(this); 8077 ITScope it_scope(this, &cond, guard); 8078 vmvn(cond, dt, rd, operand); 8079 } 8080 void Vmvn(DataType dt, QRegister rd, const QOperand& operand) { 8081 Vmvn(al, dt, rd, operand); 8082 } 8083 8084 void Vneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8085 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8086 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8087 VIXL_ASSERT(allow_macro_instructions_); 8088 VIXL_ASSERT(OutsideITBlock()); 8089 MacroEmissionCheckScope guard(this); 8090 ITScope it_scope(this, &cond, guard); 8091 vneg(cond, dt, rd, rm); 8092 } 8093 void Vneg(DataType dt, DRegister rd, DRegister rm) { Vneg(al, dt, rd, rm); } 8094 8095 void Vneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8097 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8098 VIXL_ASSERT(allow_macro_instructions_); 8099 VIXL_ASSERT(OutsideITBlock()); 8100 MacroEmissionCheckScope guard(this); 8101 ITScope it_scope(this, &cond, guard); 8102 vneg(cond, dt, rd, rm); 8103 } 8104 void Vneg(DataType dt, QRegister rd, QRegister rm) { Vneg(al, dt, rd, rm); } 8105 8106 void Vneg(Condition cond, DataType dt, SRegister rd, SRegister rm) { 8107 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8108 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8109 VIXL_ASSERT(allow_macro_instructions_); 8110 VIXL_ASSERT(OutsideITBlock()); 8111 MacroEmissionCheckScope guard(this); 8112 ITScope it_scope(this, &cond, guard); 8113 vneg(cond, dt, rd, rm); 8114 } 8115 void Vneg(DataType dt, SRegister rd, SRegister rm) { Vneg(al, dt, rd, rm); } 8116 8117 void Vnmla( 8118 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8119 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8120 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8121 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8122 VIXL_ASSERT(allow_macro_instructions_); 8123 VIXL_ASSERT(OutsideITBlock()); 8124 MacroEmissionCheckScope guard(this); 8125 ITScope it_scope(this, &cond, guard); 8126 vnmla(cond, dt, rd, rn, rm); 8127 } 8128 void Vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8129 Vnmla(al, dt, rd, rn, rm); 8130 } 8131 8132 void Vnmla( 8133 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8134 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8136 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8137 VIXL_ASSERT(allow_macro_instructions_); 8138 VIXL_ASSERT(OutsideITBlock()); 8139 MacroEmissionCheckScope guard(this); 8140 ITScope it_scope(this, &cond, guard); 8141 vnmla(cond, dt, rd, rn, rm); 8142 } 8143 void Vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8144 Vnmla(al, dt, rd, rn, rm); 8145 } 8146 8147 void Vnmls( 8148 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8149 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8150 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8151 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8152 VIXL_ASSERT(allow_macro_instructions_); 8153 VIXL_ASSERT(OutsideITBlock()); 8154 MacroEmissionCheckScope guard(this); 8155 ITScope it_scope(this, &cond, guard); 8156 vnmls(cond, dt, rd, rn, rm); 8157 } 8158 void Vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8159 Vnmls(al, dt, rd, rn, rm); 8160 } 8161 8162 void Vnmls( 8163 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8164 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8165 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8166 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8167 VIXL_ASSERT(allow_macro_instructions_); 8168 VIXL_ASSERT(OutsideITBlock()); 8169 MacroEmissionCheckScope guard(this); 8170 ITScope it_scope(this, &cond, guard); 8171 vnmls(cond, dt, rd, rn, rm); 8172 } 8173 void Vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8174 Vnmls(al, dt, rd, rn, rm); 8175 } 8176 8177 void Vnmul( 8178 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8179 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8180 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8181 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8182 VIXL_ASSERT(allow_macro_instructions_); 8183 VIXL_ASSERT(OutsideITBlock()); 8184 MacroEmissionCheckScope guard(this); 8185 ITScope it_scope(this, &cond, guard); 8186 vnmul(cond, dt, rd, rn, rm); 8187 } 8188 void Vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 8189 Vnmul(al, dt, rd, rn, rm); 8190 } 8191 8192 void Vnmul( 8193 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8194 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8195 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8196 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8197 VIXL_ASSERT(allow_macro_instructions_); 8198 VIXL_ASSERT(OutsideITBlock()); 8199 MacroEmissionCheckScope guard(this); 8200 ITScope it_scope(this, &cond, guard); 8201 vnmul(cond, dt, rd, rn, rm); 8202 } 8203 void Vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8204 Vnmul(al, dt, rd, rn, rm); 8205 } 8206 8207 void Vorn(Condition cond, 8208 DataType dt, 8209 DRegister rd, 8210 DRegister rn, 8211 const DOperand& operand) { 8212 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8213 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8214 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8215 VIXL_ASSERT(allow_macro_instructions_); 8216 VIXL_ASSERT(OutsideITBlock()); 8217 MacroEmissionCheckScope guard(this); 8218 ITScope it_scope(this, &cond, guard); 8219 vorn(cond, dt, rd, rn, operand); 8220 } 8221 void Vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 8222 Vorn(al, dt, rd, rn, operand); 8223 } 8224 8225 void Vorn(Condition cond, 8226 DataType dt, 8227 QRegister rd, 8228 QRegister rn, 8229 const QOperand& operand) { 8230 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8231 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8232 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8233 VIXL_ASSERT(allow_macro_instructions_); 8234 VIXL_ASSERT(OutsideITBlock()); 8235 MacroEmissionCheckScope guard(this); 8236 ITScope it_scope(this, &cond, guard); 8237 vorn(cond, dt, rd, rn, operand); 8238 } 8239 void Vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 8240 Vorn(al, dt, rd, rn, operand); 8241 } 8242 8243 void Vorr(Condition cond, 8244 DataType dt, 8245 DRegister rd, 8246 DRegister rn, 8247 const DOperand& operand) { 8248 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8249 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8250 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8251 VIXL_ASSERT(allow_macro_instructions_); 8252 VIXL_ASSERT(OutsideITBlock()); 8253 MacroEmissionCheckScope guard(this); 8254 ITScope it_scope(this, &cond, guard); 8255 vorr(cond, dt, rd, rn, operand); 8256 } 8257 void Vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 8258 Vorr(al, dt, rd, rn, operand); 8259 } 8260 void Vorr(Condition cond, 8261 DRegister rd, 8262 DRegister rn, 8263 const DOperand& operand) { 8264 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 8265 } 8266 void Vorr(DRegister rd, DRegister rn, const DOperand& operand) { 8267 Vorr(al, kDataTypeValueNone, rd, rn, operand); 8268 } 8269 8270 void Vorr(Condition cond, 8271 DataType dt, 8272 QRegister rd, 8273 QRegister rn, 8274 const QOperand& operand) { 8275 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8276 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8277 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8278 VIXL_ASSERT(allow_macro_instructions_); 8279 VIXL_ASSERT(OutsideITBlock()); 8280 MacroEmissionCheckScope guard(this); 8281 ITScope it_scope(this, &cond, guard); 8282 vorr(cond, dt, rd, rn, operand); 8283 } 8284 void Vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 8285 Vorr(al, dt, rd, rn, operand); 8286 } 8287 void Vorr(Condition cond, 8288 QRegister rd, 8289 QRegister rn, 8290 const QOperand& operand) { 8291 Vorr(cond, kDataTypeValueNone, rd, rn, operand); 8292 } 8293 void Vorr(QRegister rd, QRegister rn, const QOperand& operand) { 8294 Vorr(al, kDataTypeValueNone, rd, rn, operand); 8295 } 8296 8297 void Vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8298 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8299 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8300 VIXL_ASSERT(allow_macro_instructions_); 8301 VIXL_ASSERT(OutsideITBlock()); 8302 MacroEmissionCheckScope guard(this); 8303 ITScope it_scope(this, &cond, guard); 8304 vpadal(cond, dt, rd, rm); 8305 } 8306 void Vpadal(DataType dt, DRegister rd, DRegister rm) { 8307 Vpadal(al, dt, rd, rm); 8308 } 8309 8310 void Vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8311 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8312 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8313 VIXL_ASSERT(allow_macro_instructions_); 8314 VIXL_ASSERT(OutsideITBlock()); 8315 MacroEmissionCheckScope guard(this); 8316 ITScope it_scope(this, &cond, guard); 8317 vpadal(cond, dt, rd, rm); 8318 } 8319 void Vpadal(DataType dt, QRegister rd, QRegister rm) { 8320 Vpadal(al, dt, rd, rm); 8321 } 8322 8323 void Vpadd( 8324 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8325 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8326 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8327 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8328 VIXL_ASSERT(allow_macro_instructions_); 8329 VIXL_ASSERT(OutsideITBlock()); 8330 MacroEmissionCheckScope guard(this); 8331 ITScope it_scope(this, &cond, guard); 8332 vpadd(cond, dt, rd, rn, rm); 8333 } 8334 void Vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8335 Vpadd(al, dt, rd, rn, rm); 8336 } 8337 8338 void Vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8339 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8340 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8341 VIXL_ASSERT(allow_macro_instructions_); 8342 VIXL_ASSERT(OutsideITBlock()); 8343 MacroEmissionCheckScope guard(this); 8344 ITScope it_scope(this, &cond, guard); 8345 vpaddl(cond, dt, rd, rm); 8346 } 8347 void Vpaddl(DataType dt, DRegister rd, DRegister rm) { 8348 Vpaddl(al, dt, rd, rm); 8349 } 8350 8351 void Vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8352 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8353 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8354 VIXL_ASSERT(allow_macro_instructions_); 8355 VIXL_ASSERT(OutsideITBlock()); 8356 MacroEmissionCheckScope guard(this); 8357 ITScope it_scope(this, &cond, guard); 8358 vpaddl(cond, dt, rd, rm); 8359 } 8360 void Vpaddl(DataType dt, QRegister rd, QRegister rm) { 8361 Vpaddl(al, dt, rd, rm); 8362 } 8363 8364 void Vpmax( 8365 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8366 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8367 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8368 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8369 VIXL_ASSERT(allow_macro_instructions_); 8370 VIXL_ASSERT(OutsideITBlock()); 8371 MacroEmissionCheckScope guard(this); 8372 ITScope it_scope(this, &cond, guard); 8373 vpmax(cond, dt, rd, rn, rm); 8374 } 8375 void Vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8376 Vpmax(al, dt, rd, rn, rm); 8377 } 8378 8379 void Vpmin( 8380 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8381 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8382 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8383 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8384 VIXL_ASSERT(allow_macro_instructions_); 8385 VIXL_ASSERT(OutsideITBlock()); 8386 MacroEmissionCheckScope guard(this); 8387 ITScope it_scope(this, &cond, guard); 8388 vpmin(cond, dt, rd, rn, rm); 8389 } 8390 void Vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8391 Vpmin(al, dt, rd, rn, rm); 8392 } 8393 8394 void Vpop(Condition cond, DataType dt, DRegisterList dreglist) { 8395 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 8396 VIXL_ASSERT(allow_macro_instructions_); 8397 VIXL_ASSERT(OutsideITBlock()); 8398 MacroEmissionCheckScope guard(this); 8399 ITScope it_scope(this, &cond, guard); 8400 vpop(cond, dt, dreglist); 8401 } 8402 void Vpop(DataType dt, DRegisterList dreglist) { Vpop(al, dt, dreglist); } 8403 void Vpop(Condition cond, DRegisterList dreglist) { 8404 Vpop(cond, kDataTypeValueNone, dreglist); 8405 } 8406 void Vpop(DRegisterList dreglist) { Vpop(al, kDataTypeValueNone, dreglist); } 8407 8408 void Vpop(Condition cond, DataType dt, SRegisterList sreglist) { 8409 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 8410 VIXL_ASSERT(allow_macro_instructions_); 8411 VIXL_ASSERT(OutsideITBlock()); 8412 MacroEmissionCheckScope guard(this); 8413 ITScope it_scope(this, &cond, guard); 8414 vpop(cond, dt, sreglist); 8415 } 8416 void Vpop(DataType dt, SRegisterList sreglist) { Vpop(al, dt, sreglist); } 8417 void Vpop(Condition cond, SRegisterList sreglist) { 8418 Vpop(cond, kDataTypeValueNone, sreglist); 8419 } 8420 void Vpop(SRegisterList sreglist) { Vpop(al, kDataTypeValueNone, sreglist); } 8421 8422 void Vpush(Condition cond, DataType dt, DRegisterList dreglist) { 8423 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 8424 VIXL_ASSERT(allow_macro_instructions_); 8425 VIXL_ASSERT(OutsideITBlock()); 8426 MacroEmissionCheckScope guard(this); 8427 ITScope it_scope(this, &cond, guard); 8428 vpush(cond, dt, dreglist); 8429 } 8430 void Vpush(DataType dt, DRegisterList dreglist) { Vpush(al, dt, dreglist); } 8431 void Vpush(Condition cond, DRegisterList dreglist) { 8432 Vpush(cond, kDataTypeValueNone, dreglist); 8433 } 8434 void Vpush(DRegisterList dreglist) { 8435 Vpush(al, kDataTypeValueNone, dreglist); 8436 } 8437 8438 void Vpush(Condition cond, DataType dt, SRegisterList sreglist) { 8439 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 8440 VIXL_ASSERT(allow_macro_instructions_); 8441 VIXL_ASSERT(OutsideITBlock()); 8442 MacroEmissionCheckScope guard(this); 8443 ITScope it_scope(this, &cond, guard); 8444 vpush(cond, dt, sreglist); 8445 } 8446 void Vpush(DataType dt, SRegisterList sreglist) { Vpush(al, dt, sreglist); } 8447 void Vpush(Condition cond, SRegisterList sreglist) { 8448 Vpush(cond, kDataTypeValueNone, sreglist); 8449 } 8450 void Vpush(SRegisterList sreglist) { 8451 Vpush(al, kDataTypeValueNone, sreglist); 8452 } 8453 8454 void Vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8455 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8456 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8457 VIXL_ASSERT(allow_macro_instructions_); 8458 VIXL_ASSERT(OutsideITBlock()); 8459 MacroEmissionCheckScope guard(this); 8460 ITScope it_scope(this, &cond, guard); 8461 vqabs(cond, dt, rd, rm); 8462 } 8463 void Vqabs(DataType dt, DRegister rd, DRegister rm) { Vqabs(al, dt, rd, rm); } 8464 8465 void Vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8466 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8467 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8468 VIXL_ASSERT(allow_macro_instructions_); 8469 VIXL_ASSERT(OutsideITBlock()); 8470 MacroEmissionCheckScope guard(this); 8471 ITScope it_scope(this, &cond, guard); 8472 vqabs(cond, dt, rd, rm); 8473 } 8474 void Vqabs(DataType dt, QRegister rd, QRegister rm) { Vqabs(al, dt, rd, rm); } 8475 8476 void Vqadd( 8477 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8478 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8479 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8480 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8481 VIXL_ASSERT(allow_macro_instructions_); 8482 VIXL_ASSERT(OutsideITBlock()); 8483 MacroEmissionCheckScope guard(this); 8484 ITScope it_scope(this, &cond, guard); 8485 vqadd(cond, dt, rd, rn, rm); 8486 } 8487 void Vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8488 Vqadd(al, dt, rd, rn, rm); 8489 } 8490 8491 void Vqadd( 8492 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8493 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8494 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8495 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8496 VIXL_ASSERT(allow_macro_instructions_); 8497 VIXL_ASSERT(OutsideITBlock()); 8498 MacroEmissionCheckScope guard(this); 8499 ITScope it_scope(this, &cond, guard); 8500 vqadd(cond, dt, rd, rn, rm); 8501 } 8502 void Vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8503 Vqadd(al, dt, rd, rn, rm); 8504 } 8505 8506 void Vqdmlal( 8507 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8508 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8509 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8510 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8511 VIXL_ASSERT(allow_macro_instructions_); 8512 VIXL_ASSERT(OutsideITBlock()); 8513 MacroEmissionCheckScope guard(this); 8514 ITScope it_scope(this, &cond, guard); 8515 vqdmlal(cond, dt, rd, rn, rm); 8516 } 8517 void Vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8518 Vqdmlal(al, dt, rd, rn, rm); 8519 } 8520 8521 void Vqdmlal(Condition cond, 8522 DataType dt, 8523 QRegister rd, 8524 DRegister rn, 8525 DRegister dm, 8526 unsigned index) { 8527 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8528 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8529 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 8530 VIXL_ASSERT(allow_macro_instructions_); 8531 VIXL_ASSERT(OutsideITBlock()); 8532 MacroEmissionCheckScope guard(this); 8533 ITScope it_scope(this, &cond, guard); 8534 vqdmlal(cond, dt, rd, rn, dm, index); 8535 } 8536 void Vqdmlal( 8537 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 8538 Vqdmlal(al, dt, rd, rn, dm, index); 8539 } 8540 8541 void Vqdmlsl( 8542 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8543 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8544 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8545 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8546 VIXL_ASSERT(allow_macro_instructions_); 8547 VIXL_ASSERT(OutsideITBlock()); 8548 MacroEmissionCheckScope guard(this); 8549 ITScope it_scope(this, &cond, guard); 8550 vqdmlsl(cond, dt, rd, rn, rm); 8551 } 8552 void Vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8553 Vqdmlsl(al, dt, rd, rn, rm); 8554 } 8555 8556 void Vqdmlsl(Condition cond, 8557 DataType dt, 8558 QRegister rd, 8559 DRegister rn, 8560 DRegister dm, 8561 unsigned index) { 8562 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8563 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8564 VIXL_ASSERT(!AliasesAvailableScratchRegister(dm)); 8565 VIXL_ASSERT(allow_macro_instructions_); 8566 VIXL_ASSERT(OutsideITBlock()); 8567 MacroEmissionCheckScope guard(this); 8568 ITScope it_scope(this, &cond, guard); 8569 vqdmlsl(cond, dt, rd, rn, dm, index); 8570 } 8571 void Vqdmlsl( 8572 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 8573 Vqdmlsl(al, dt, rd, rn, dm, index); 8574 } 8575 8576 void Vqdmulh( 8577 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8578 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8579 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8580 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8581 VIXL_ASSERT(allow_macro_instructions_); 8582 VIXL_ASSERT(OutsideITBlock()); 8583 MacroEmissionCheckScope guard(this); 8584 ITScope it_scope(this, &cond, guard); 8585 vqdmulh(cond, dt, rd, rn, rm); 8586 } 8587 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8588 Vqdmulh(al, dt, rd, rn, rm); 8589 } 8590 8591 void Vqdmulh( 8592 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8593 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8594 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8595 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8596 VIXL_ASSERT(allow_macro_instructions_); 8597 VIXL_ASSERT(OutsideITBlock()); 8598 MacroEmissionCheckScope guard(this); 8599 ITScope it_scope(this, &cond, guard); 8600 vqdmulh(cond, dt, rd, rn, rm); 8601 } 8602 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8603 Vqdmulh(al, dt, rd, rn, rm); 8604 } 8605 8606 void Vqdmulh(Condition cond, 8607 DataType dt, 8608 DRegister rd, 8609 DRegister rn, 8610 DRegisterLane rm) { 8611 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8612 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8613 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8614 VIXL_ASSERT(allow_macro_instructions_); 8615 VIXL_ASSERT(OutsideITBlock()); 8616 MacroEmissionCheckScope guard(this); 8617 ITScope it_scope(this, &cond, guard); 8618 vqdmulh(cond, dt, rd, rn, rm); 8619 } 8620 void Vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 8621 Vqdmulh(al, dt, rd, rn, rm); 8622 } 8623 8624 void Vqdmulh(Condition cond, 8625 DataType dt, 8626 QRegister rd, 8627 QRegister rn, 8628 DRegisterLane rm) { 8629 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8630 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8631 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8632 VIXL_ASSERT(allow_macro_instructions_); 8633 VIXL_ASSERT(OutsideITBlock()); 8634 MacroEmissionCheckScope guard(this); 8635 ITScope it_scope(this, &cond, guard); 8636 vqdmulh(cond, dt, rd, rn, rm); 8637 } 8638 void Vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 8639 Vqdmulh(al, dt, rd, rn, rm); 8640 } 8641 8642 void Vqdmull( 8643 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8644 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8645 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8646 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8647 VIXL_ASSERT(allow_macro_instructions_); 8648 VIXL_ASSERT(OutsideITBlock()); 8649 MacroEmissionCheckScope guard(this); 8650 ITScope it_scope(this, &cond, guard); 8651 vqdmull(cond, dt, rd, rn, rm); 8652 } 8653 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 8654 Vqdmull(al, dt, rd, rn, rm); 8655 } 8656 8657 void Vqdmull(Condition cond, 8658 DataType dt, 8659 QRegister rd, 8660 DRegister rn, 8661 DRegisterLane rm) { 8662 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8663 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8664 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8665 VIXL_ASSERT(allow_macro_instructions_); 8666 VIXL_ASSERT(OutsideITBlock()); 8667 MacroEmissionCheckScope guard(this); 8668 ITScope it_scope(this, &cond, guard); 8669 vqdmull(cond, dt, rd, rn, rm); 8670 } 8671 void Vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 8672 Vqdmull(al, dt, rd, rn, rm); 8673 } 8674 8675 void Vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm) { 8676 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8677 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8678 VIXL_ASSERT(allow_macro_instructions_); 8679 VIXL_ASSERT(OutsideITBlock()); 8680 MacroEmissionCheckScope guard(this); 8681 ITScope it_scope(this, &cond, guard); 8682 vqmovn(cond, dt, rd, rm); 8683 } 8684 void Vqmovn(DataType dt, DRegister rd, QRegister rm) { 8685 Vqmovn(al, dt, rd, rm); 8686 } 8687 8688 void Vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm) { 8689 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8690 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8691 VIXL_ASSERT(allow_macro_instructions_); 8692 VIXL_ASSERT(OutsideITBlock()); 8693 MacroEmissionCheckScope guard(this); 8694 ITScope it_scope(this, &cond, guard); 8695 vqmovun(cond, dt, rd, rm); 8696 } 8697 void Vqmovun(DataType dt, DRegister rd, QRegister rm) { 8698 Vqmovun(al, dt, rd, rm); 8699 } 8700 8701 void Vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm) { 8702 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8703 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8704 VIXL_ASSERT(allow_macro_instructions_); 8705 VIXL_ASSERT(OutsideITBlock()); 8706 MacroEmissionCheckScope guard(this); 8707 ITScope it_scope(this, &cond, guard); 8708 vqneg(cond, dt, rd, rm); 8709 } 8710 void Vqneg(DataType dt, DRegister rd, DRegister rm) { Vqneg(al, dt, rd, rm); } 8711 8712 void Vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm) { 8713 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8714 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8715 VIXL_ASSERT(allow_macro_instructions_); 8716 VIXL_ASSERT(OutsideITBlock()); 8717 MacroEmissionCheckScope guard(this); 8718 ITScope it_scope(this, &cond, guard); 8719 vqneg(cond, dt, rd, rm); 8720 } 8721 void Vqneg(DataType dt, QRegister rd, QRegister rm) { Vqneg(al, dt, rd, rm); } 8722 8723 void Vqrdmulh( 8724 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8725 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8726 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8727 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8728 VIXL_ASSERT(allow_macro_instructions_); 8729 VIXL_ASSERT(OutsideITBlock()); 8730 MacroEmissionCheckScope guard(this); 8731 ITScope it_scope(this, &cond, guard); 8732 vqrdmulh(cond, dt, rd, rn, rm); 8733 } 8734 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8735 Vqrdmulh(al, dt, rd, rn, rm); 8736 } 8737 8738 void Vqrdmulh( 8739 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8740 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8741 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8742 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8743 VIXL_ASSERT(allow_macro_instructions_); 8744 VIXL_ASSERT(OutsideITBlock()); 8745 MacroEmissionCheckScope guard(this); 8746 ITScope it_scope(this, &cond, guard); 8747 vqrdmulh(cond, dt, rd, rn, rm); 8748 } 8749 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8750 Vqrdmulh(al, dt, rd, rn, rm); 8751 } 8752 8753 void Vqrdmulh(Condition cond, 8754 DataType dt, 8755 DRegister rd, 8756 DRegister rn, 8757 DRegisterLane rm) { 8758 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8759 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8760 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8761 VIXL_ASSERT(allow_macro_instructions_); 8762 VIXL_ASSERT(OutsideITBlock()); 8763 MacroEmissionCheckScope guard(this); 8764 ITScope it_scope(this, &cond, guard); 8765 vqrdmulh(cond, dt, rd, rn, rm); 8766 } 8767 void Vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 8768 Vqrdmulh(al, dt, rd, rn, rm); 8769 } 8770 8771 void Vqrdmulh(Condition cond, 8772 DataType dt, 8773 QRegister rd, 8774 QRegister rn, 8775 DRegisterLane rm) { 8776 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8777 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8778 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8779 VIXL_ASSERT(allow_macro_instructions_); 8780 VIXL_ASSERT(OutsideITBlock()); 8781 MacroEmissionCheckScope guard(this); 8782 ITScope it_scope(this, &cond, guard); 8783 vqrdmulh(cond, dt, rd, rn, rm); 8784 } 8785 void Vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 8786 Vqrdmulh(al, dt, rd, rn, rm); 8787 } 8788 8789 void Vqrshl( 8790 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 8791 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8792 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8793 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8794 VIXL_ASSERT(allow_macro_instructions_); 8795 VIXL_ASSERT(OutsideITBlock()); 8796 MacroEmissionCheckScope guard(this); 8797 ITScope it_scope(this, &cond, guard); 8798 vqrshl(cond, dt, rd, rm, rn); 8799 } 8800 void Vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 8801 Vqrshl(al, dt, rd, rm, rn); 8802 } 8803 8804 void Vqrshl( 8805 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 8806 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8807 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8808 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8809 VIXL_ASSERT(allow_macro_instructions_); 8810 VIXL_ASSERT(OutsideITBlock()); 8811 MacroEmissionCheckScope guard(this); 8812 ITScope it_scope(this, &cond, guard); 8813 vqrshl(cond, dt, rd, rm, rn); 8814 } 8815 void Vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 8816 Vqrshl(al, dt, rd, rm, rn); 8817 } 8818 8819 void Vqrshrn(Condition cond, 8820 DataType dt, 8821 DRegister rd, 8822 QRegister rm, 8823 const QOperand& operand) { 8824 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8825 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8826 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8827 VIXL_ASSERT(allow_macro_instructions_); 8828 VIXL_ASSERT(OutsideITBlock()); 8829 MacroEmissionCheckScope guard(this); 8830 ITScope it_scope(this, &cond, guard); 8831 vqrshrn(cond, dt, rd, rm, operand); 8832 } 8833 void Vqrshrn(DataType dt, 8834 DRegister rd, 8835 QRegister rm, 8836 const QOperand& operand) { 8837 Vqrshrn(al, dt, rd, rm, operand); 8838 } 8839 8840 void Vqrshrun(Condition cond, 8841 DataType dt, 8842 DRegister rd, 8843 QRegister rm, 8844 const QOperand& operand) { 8845 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8846 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8847 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8848 VIXL_ASSERT(allow_macro_instructions_); 8849 VIXL_ASSERT(OutsideITBlock()); 8850 MacroEmissionCheckScope guard(this); 8851 ITScope it_scope(this, &cond, guard); 8852 vqrshrun(cond, dt, rd, rm, operand); 8853 } 8854 void Vqrshrun(DataType dt, 8855 DRegister rd, 8856 QRegister rm, 8857 const QOperand& operand) { 8858 Vqrshrun(al, dt, rd, rm, operand); 8859 } 8860 8861 void Vqshl(Condition cond, 8862 DataType dt, 8863 DRegister rd, 8864 DRegister rm, 8865 const DOperand& operand) { 8866 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8867 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8868 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8869 VIXL_ASSERT(allow_macro_instructions_); 8870 VIXL_ASSERT(OutsideITBlock()); 8871 MacroEmissionCheckScope guard(this); 8872 ITScope it_scope(this, &cond, guard); 8873 vqshl(cond, dt, rd, rm, operand); 8874 } 8875 void Vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 8876 Vqshl(al, dt, rd, rm, operand); 8877 } 8878 8879 void Vqshl(Condition cond, 8880 DataType dt, 8881 QRegister rd, 8882 QRegister rm, 8883 const QOperand& operand) { 8884 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8885 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8886 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8887 VIXL_ASSERT(allow_macro_instructions_); 8888 VIXL_ASSERT(OutsideITBlock()); 8889 MacroEmissionCheckScope guard(this); 8890 ITScope it_scope(this, &cond, guard); 8891 vqshl(cond, dt, rd, rm, operand); 8892 } 8893 void Vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 8894 Vqshl(al, dt, rd, rm, operand); 8895 } 8896 8897 void Vqshlu(Condition cond, 8898 DataType dt, 8899 DRegister rd, 8900 DRegister rm, 8901 const DOperand& operand) { 8902 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8903 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8904 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8905 VIXL_ASSERT(allow_macro_instructions_); 8906 VIXL_ASSERT(OutsideITBlock()); 8907 MacroEmissionCheckScope guard(this); 8908 ITScope it_scope(this, &cond, guard); 8909 vqshlu(cond, dt, rd, rm, operand); 8910 } 8911 void Vqshlu(DataType dt, 8912 DRegister rd, 8913 DRegister rm, 8914 const DOperand& operand) { 8915 Vqshlu(al, dt, rd, rm, operand); 8916 } 8917 8918 void Vqshlu(Condition cond, 8919 DataType dt, 8920 QRegister rd, 8921 QRegister rm, 8922 const QOperand& operand) { 8923 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8924 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8925 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8926 VIXL_ASSERT(allow_macro_instructions_); 8927 VIXL_ASSERT(OutsideITBlock()); 8928 MacroEmissionCheckScope guard(this); 8929 ITScope it_scope(this, &cond, guard); 8930 vqshlu(cond, dt, rd, rm, operand); 8931 } 8932 void Vqshlu(DataType dt, 8933 QRegister rd, 8934 QRegister rm, 8935 const QOperand& operand) { 8936 Vqshlu(al, dt, rd, rm, operand); 8937 } 8938 8939 void Vqshrn(Condition cond, 8940 DataType dt, 8941 DRegister rd, 8942 QRegister rm, 8943 const QOperand& operand) { 8944 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8945 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8946 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8947 VIXL_ASSERT(allow_macro_instructions_); 8948 VIXL_ASSERT(OutsideITBlock()); 8949 MacroEmissionCheckScope guard(this); 8950 ITScope it_scope(this, &cond, guard); 8951 vqshrn(cond, dt, rd, rm, operand); 8952 } 8953 void Vqshrn(DataType dt, 8954 DRegister rd, 8955 QRegister rm, 8956 const QOperand& operand) { 8957 Vqshrn(al, dt, rd, rm, operand); 8958 } 8959 8960 void Vqshrun(Condition cond, 8961 DataType dt, 8962 DRegister rd, 8963 QRegister rm, 8964 const QOperand& operand) { 8965 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8966 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8967 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 8968 VIXL_ASSERT(allow_macro_instructions_); 8969 VIXL_ASSERT(OutsideITBlock()); 8970 MacroEmissionCheckScope guard(this); 8971 ITScope it_scope(this, &cond, guard); 8972 vqshrun(cond, dt, rd, rm, operand); 8973 } 8974 void Vqshrun(DataType dt, 8975 DRegister rd, 8976 QRegister rm, 8977 const QOperand& operand) { 8978 Vqshrun(al, dt, rd, rm, operand); 8979 } 8980 8981 void Vqsub( 8982 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8983 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8984 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 8985 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 8986 VIXL_ASSERT(allow_macro_instructions_); 8987 VIXL_ASSERT(OutsideITBlock()); 8988 MacroEmissionCheckScope guard(this); 8989 ITScope it_scope(this, &cond, guard); 8990 vqsub(cond, dt, rd, rn, rm); 8991 } 8992 void Vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 8993 Vqsub(al, dt, rd, rn, rm); 8994 } 8995 8996 void Vqsub( 8997 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 8998 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 8999 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9000 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9001 VIXL_ASSERT(allow_macro_instructions_); 9002 VIXL_ASSERT(OutsideITBlock()); 9003 MacroEmissionCheckScope guard(this); 9004 ITScope it_scope(this, &cond, guard); 9005 vqsub(cond, dt, rd, rn, rm); 9006 } 9007 void Vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9008 Vqsub(al, dt, rd, rn, rm); 9009 } 9010 9011 void Vraddhn( 9012 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9013 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9014 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9015 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9016 VIXL_ASSERT(allow_macro_instructions_); 9017 VIXL_ASSERT(OutsideITBlock()); 9018 MacroEmissionCheckScope guard(this); 9019 ITScope it_scope(this, &cond, guard); 9020 vraddhn(cond, dt, rd, rn, rm); 9021 } 9022 void Vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9023 Vraddhn(al, dt, rd, rn, rm); 9024 } 9025 9026 void Vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9027 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9028 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9029 VIXL_ASSERT(allow_macro_instructions_); 9030 VIXL_ASSERT(OutsideITBlock()); 9031 MacroEmissionCheckScope guard(this); 9032 ITScope it_scope(this, &cond, guard); 9033 vrecpe(cond, dt, rd, rm); 9034 } 9035 void Vrecpe(DataType dt, DRegister rd, DRegister rm) { 9036 Vrecpe(al, dt, rd, rm); 9037 } 9038 9039 void Vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9040 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9041 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9042 VIXL_ASSERT(allow_macro_instructions_); 9043 VIXL_ASSERT(OutsideITBlock()); 9044 MacroEmissionCheckScope guard(this); 9045 ITScope it_scope(this, &cond, guard); 9046 vrecpe(cond, dt, rd, rm); 9047 } 9048 void Vrecpe(DataType dt, QRegister rd, QRegister rm) { 9049 Vrecpe(al, dt, rd, rm); 9050 } 9051 9052 void Vrecps( 9053 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9054 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9055 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9056 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9057 VIXL_ASSERT(allow_macro_instructions_); 9058 VIXL_ASSERT(OutsideITBlock()); 9059 MacroEmissionCheckScope guard(this); 9060 ITScope it_scope(this, &cond, guard); 9061 vrecps(cond, dt, rd, rn, rm); 9062 } 9063 void Vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9064 Vrecps(al, dt, rd, rn, rm); 9065 } 9066 9067 void Vrecps( 9068 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9069 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9070 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9071 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9072 VIXL_ASSERT(allow_macro_instructions_); 9073 VIXL_ASSERT(OutsideITBlock()); 9074 MacroEmissionCheckScope guard(this); 9075 ITScope it_scope(this, &cond, guard); 9076 vrecps(cond, dt, rd, rn, rm); 9077 } 9078 void Vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9079 Vrecps(al, dt, rd, rn, rm); 9080 } 9081 9082 void Vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9083 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9084 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9085 VIXL_ASSERT(allow_macro_instructions_); 9086 VIXL_ASSERT(OutsideITBlock()); 9087 MacroEmissionCheckScope guard(this); 9088 ITScope it_scope(this, &cond, guard); 9089 vrev16(cond, dt, rd, rm); 9090 } 9091 void Vrev16(DataType dt, DRegister rd, DRegister rm) { 9092 Vrev16(al, dt, rd, rm); 9093 } 9094 9095 void Vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9096 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9097 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9098 VIXL_ASSERT(allow_macro_instructions_); 9099 VIXL_ASSERT(OutsideITBlock()); 9100 MacroEmissionCheckScope guard(this); 9101 ITScope it_scope(this, &cond, guard); 9102 vrev16(cond, dt, rd, rm); 9103 } 9104 void Vrev16(DataType dt, QRegister rd, QRegister rm) { 9105 Vrev16(al, dt, rd, rm); 9106 } 9107 9108 void Vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9109 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9110 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9111 VIXL_ASSERT(allow_macro_instructions_); 9112 VIXL_ASSERT(OutsideITBlock()); 9113 MacroEmissionCheckScope guard(this); 9114 ITScope it_scope(this, &cond, guard); 9115 vrev32(cond, dt, rd, rm); 9116 } 9117 void Vrev32(DataType dt, DRegister rd, DRegister rm) { 9118 Vrev32(al, dt, rd, rm); 9119 } 9120 9121 void Vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9122 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9123 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9124 VIXL_ASSERT(allow_macro_instructions_); 9125 VIXL_ASSERT(OutsideITBlock()); 9126 MacroEmissionCheckScope guard(this); 9127 ITScope it_scope(this, &cond, guard); 9128 vrev32(cond, dt, rd, rm); 9129 } 9130 void Vrev32(DataType dt, QRegister rd, QRegister rm) { 9131 Vrev32(al, dt, rd, rm); 9132 } 9133 9134 void Vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9135 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9136 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9137 VIXL_ASSERT(allow_macro_instructions_); 9138 VIXL_ASSERT(OutsideITBlock()); 9139 MacroEmissionCheckScope guard(this); 9140 ITScope it_scope(this, &cond, guard); 9141 vrev64(cond, dt, rd, rm); 9142 } 9143 void Vrev64(DataType dt, DRegister rd, DRegister rm) { 9144 Vrev64(al, dt, rd, rm); 9145 } 9146 9147 void Vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9148 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9149 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9150 VIXL_ASSERT(allow_macro_instructions_); 9151 VIXL_ASSERT(OutsideITBlock()); 9152 MacroEmissionCheckScope guard(this); 9153 ITScope it_scope(this, &cond, guard); 9154 vrev64(cond, dt, rd, rm); 9155 } 9156 void Vrev64(DataType dt, QRegister rd, QRegister rm) { 9157 Vrev64(al, dt, rd, rm); 9158 } 9159 9160 void Vrhadd( 9161 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9162 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9163 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9164 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9165 VIXL_ASSERT(allow_macro_instructions_); 9166 VIXL_ASSERT(OutsideITBlock()); 9167 MacroEmissionCheckScope guard(this); 9168 ITScope it_scope(this, &cond, guard); 9169 vrhadd(cond, dt, rd, rn, rm); 9170 } 9171 void Vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9172 Vrhadd(al, dt, rd, rn, rm); 9173 } 9174 9175 void Vrhadd( 9176 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9177 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9178 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9179 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9180 VIXL_ASSERT(allow_macro_instructions_); 9181 VIXL_ASSERT(OutsideITBlock()); 9182 MacroEmissionCheckScope guard(this); 9183 ITScope it_scope(this, &cond, guard); 9184 vrhadd(cond, dt, rd, rn, rm); 9185 } 9186 void Vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9187 Vrhadd(al, dt, rd, rn, rm); 9188 } 9189 9190 void Vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9191 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9192 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9193 VIXL_ASSERT(allow_macro_instructions_); 9194 VIXL_ASSERT(OutsideITBlock()); 9195 MacroEmissionCheckScope guard(this); 9196 vrinta(dt1, dt2, rd, rm); 9197 } 9198 9199 void Vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9200 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9201 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9202 VIXL_ASSERT(allow_macro_instructions_); 9203 VIXL_ASSERT(OutsideITBlock()); 9204 MacroEmissionCheckScope guard(this); 9205 vrinta(dt1, dt2, rd, rm); 9206 } 9207 9208 void Vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9209 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9210 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9211 VIXL_ASSERT(allow_macro_instructions_); 9212 VIXL_ASSERT(OutsideITBlock()); 9213 MacroEmissionCheckScope guard(this); 9214 vrinta(dt1, dt2, rd, rm); 9215 } 9216 9217 void Vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9218 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9219 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9220 VIXL_ASSERT(allow_macro_instructions_); 9221 VIXL_ASSERT(OutsideITBlock()); 9222 MacroEmissionCheckScope guard(this); 9223 vrintm(dt1, dt2, rd, rm); 9224 } 9225 9226 void Vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9227 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9228 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9229 VIXL_ASSERT(allow_macro_instructions_); 9230 VIXL_ASSERT(OutsideITBlock()); 9231 MacroEmissionCheckScope guard(this); 9232 vrintm(dt1, dt2, rd, rm); 9233 } 9234 9235 void Vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9236 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9238 VIXL_ASSERT(allow_macro_instructions_); 9239 VIXL_ASSERT(OutsideITBlock()); 9240 MacroEmissionCheckScope guard(this); 9241 vrintm(dt1, dt2, rd, rm); 9242 } 9243 9244 void Vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9245 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9246 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9247 VIXL_ASSERT(allow_macro_instructions_); 9248 VIXL_ASSERT(OutsideITBlock()); 9249 MacroEmissionCheckScope guard(this); 9250 vrintn(dt1, dt2, rd, rm); 9251 } 9252 9253 void Vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9254 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9255 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9256 VIXL_ASSERT(allow_macro_instructions_); 9257 VIXL_ASSERT(OutsideITBlock()); 9258 MacroEmissionCheckScope guard(this); 9259 vrintn(dt1, dt2, rd, rm); 9260 } 9261 9262 void Vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9263 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9264 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9265 VIXL_ASSERT(allow_macro_instructions_); 9266 VIXL_ASSERT(OutsideITBlock()); 9267 MacroEmissionCheckScope guard(this); 9268 vrintn(dt1, dt2, rd, rm); 9269 } 9270 9271 void Vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9272 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9273 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9274 VIXL_ASSERT(allow_macro_instructions_); 9275 VIXL_ASSERT(OutsideITBlock()); 9276 MacroEmissionCheckScope guard(this); 9277 vrintp(dt1, dt2, rd, rm); 9278 } 9279 9280 void Vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9281 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9282 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9283 VIXL_ASSERT(allow_macro_instructions_); 9284 VIXL_ASSERT(OutsideITBlock()); 9285 MacroEmissionCheckScope guard(this); 9286 vrintp(dt1, dt2, rd, rm); 9287 } 9288 9289 void Vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9290 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9291 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9292 VIXL_ASSERT(allow_macro_instructions_); 9293 VIXL_ASSERT(OutsideITBlock()); 9294 MacroEmissionCheckScope guard(this); 9295 vrintp(dt1, dt2, rd, rm); 9296 } 9297 9298 void Vrintr( 9299 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9300 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9301 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9302 VIXL_ASSERT(allow_macro_instructions_); 9303 VIXL_ASSERT(OutsideITBlock()); 9304 MacroEmissionCheckScope guard(this); 9305 ITScope it_scope(this, &cond, guard); 9306 vrintr(cond, dt1, dt2, rd, rm); 9307 } 9308 void Vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9309 Vrintr(al, dt1, dt2, rd, rm); 9310 } 9311 9312 void Vrintr( 9313 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9314 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9315 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9316 VIXL_ASSERT(allow_macro_instructions_); 9317 VIXL_ASSERT(OutsideITBlock()); 9318 MacroEmissionCheckScope guard(this); 9319 ITScope it_scope(this, &cond, guard); 9320 vrintr(cond, dt1, dt2, rd, rm); 9321 } 9322 void Vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9323 Vrintr(al, dt1, dt2, rd, rm); 9324 } 9325 9326 void Vrintx( 9327 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9330 VIXL_ASSERT(allow_macro_instructions_); 9331 VIXL_ASSERT(OutsideITBlock()); 9332 MacroEmissionCheckScope guard(this); 9333 ITScope it_scope(this, &cond, guard); 9334 vrintx(cond, dt1, dt2, rd, rm); 9335 } 9336 void Vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9337 Vrintx(al, dt1, dt2, rd, rm); 9338 } 9339 9340 void Vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9341 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9342 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9343 VIXL_ASSERT(allow_macro_instructions_); 9344 VIXL_ASSERT(OutsideITBlock()); 9345 MacroEmissionCheckScope guard(this); 9346 vrintx(dt1, dt2, rd, rm); 9347 } 9348 9349 void Vrintx( 9350 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9351 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9352 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9353 VIXL_ASSERT(allow_macro_instructions_); 9354 VIXL_ASSERT(OutsideITBlock()); 9355 MacroEmissionCheckScope guard(this); 9356 ITScope it_scope(this, &cond, guard); 9357 vrintx(cond, dt1, dt2, rd, rm); 9358 } 9359 void Vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9360 Vrintx(al, dt1, dt2, rd, rm); 9361 } 9362 9363 void Vrintz( 9364 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9365 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9366 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9367 VIXL_ASSERT(allow_macro_instructions_); 9368 VIXL_ASSERT(OutsideITBlock()); 9369 MacroEmissionCheckScope guard(this); 9370 ITScope it_scope(this, &cond, guard); 9371 vrintz(cond, dt1, dt2, rd, rm); 9372 } 9373 void Vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 9374 Vrintz(al, dt1, dt2, rd, rm); 9375 } 9376 9377 void Vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 9378 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9379 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9380 VIXL_ASSERT(allow_macro_instructions_); 9381 VIXL_ASSERT(OutsideITBlock()); 9382 MacroEmissionCheckScope guard(this); 9383 vrintz(dt1, dt2, rd, rm); 9384 } 9385 9386 void Vrintz( 9387 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9388 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9389 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9390 VIXL_ASSERT(allow_macro_instructions_); 9391 VIXL_ASSERT(OutsideITBlock()); 9392 MacroEmissionCheckScope guard(this); 9393 ITScope it_scope(this, &cond, guard); 9394 vrintz(cond, dt1, dt2, rd, rm); 9395 } 9396 void Vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 9397 Vrintz(al, dt1, dt2, rd, rm); 9398 } 9399 9400 void Vrshl( 9401 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn) { 9402 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9403 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9404 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9405 VIXL_ASSERT(allow_macro_instructions_); 9406 VIXL_ASSERT(OutsideITBlock()); 9407 MacroEmissionCheckScope guard(this); 9408 ITScope it_scope(this, &cond, guard); 9409 vrshl(cond, dt, rd, rm, rn); 9410 } 9411 void Vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 9412 Vrshl(al, dt, rd, rm, rn); 9413 } 9414 9415 void Vrshl( 9416 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn) { 9417 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9418 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9419 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9420 VIXL_ASSERT(allow_macro_instructions_); 9421 VIXL_ASSERT(OutsideITBlock()); 9422 MacroEmissionCheckScope guard(this); 9423 ITScope it_scope(this, &cond, guard); 9424 vrshl(cond, dt, rd, rm, rn); 9425 } 9426 void Vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 9427 Vrshl(al, dt, rd, rm, rn); 9428 } 9429 9430 void Vrshr(Condition cond, 9431 DataType dt, 9432 DRegister rd, 9433 DRegister rm, 9434 const DOperand& operand) { 9435 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9436 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9437 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9438 VIXL_ASSERT(allow_macro_instructions_); 9439 VIXL_ASSERT(OutsideITBlock()); 9440 MacroEmissionCheckScope guard(this); 9441 ITScope it_scope(this, &cond, guard); 9442 vrshr(cond, dt, rd, rm, operand); 9443 } 9444 void Vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9445 Vrshr(al, dt, rd, rm, operand); 9446 } 9447 9448 void Vrshr(Condition cond, 9449 DataType dt, 9450 QRegister rd, 9451 QRegister rm, 9452 const QOperand& operand) { 9453 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9454 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9455 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9456 VIXL_ASSERT(allow_macro_instructions_); 9457 VIXL_ASSERT(OutsideITBlock()); 9458 MacroEmissionCheckScope guard(this); 9459 ITScope it_scope(this, &cond, guard); 9460 vrshr(cond, dt, rd, rm, operand); 9461 } 9462 void Vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9463 Vrshr(al, dt, rd, rm, operand); 9464 } 9465 9466 void Vrshrn(Condition cond, 9467 DataType dt, 9468 DRegister rd, 9469 QRegister rm, 9470 const QOperand& operand) { 9471 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9473 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9474 VIXL_ASSERT(allow_macro_instructions_); 9475 VIXL_ASSERT(OutsideITBlock()); 9476 MacroEmissionCheckScope guard(this); 9477 ITScope it_scope(this, &cond, guard); 9478 vrshrn(cond, dt, rd, rm, operand); 9479 } 9480 void Vrshrn(DataType dt, 9481 DRegister rd, 9482 QRegister rm, 9483 const QOperand& operand) { 9484 Vrshrn(al, dt, rd, rm, operand); 9485 } 9486 9487 void Vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9488 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9489 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9490 VIXL_ASSERT(allow_macro_instructions_); 9491 VIXL_ASSERT(OutsideITBlock()); 9492 MacroEmissionCheckScope guard(this); 9493 ITScope it_scope(this, &cond, guard); 9494 vrsqrte(cond, dt, rd, rm); 9495 } 9496 void Vrsqrte(DataType dt, DRegister rd, DRegister rm) { 9497 Vrsqrte(al, dt, rd, rm); 9498 } 9499 9500 void Vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm) { 9501 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9502 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9503 VIXL_ASSERT(allow_macro_instructions_); 9504 VIXL_ASSERT(OutsideITBlock()); 9505 MacroEmissionCheckScope guard(this); 9506 ITScope it_scope(this, &cond, guard); 9507 vrsqrte(cond, dt, rd, rm); 9508 } 9509 void Vrsqrte(DataType dt, QRegister rd, QRegister rm) { 9510 Vrsqrte(al, dt, rd, rm); 9511 } 9512 9513 void Vrsqrts( 9514 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9515 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9516 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9517 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9518 VIXL_ASSERT(allow_macro_instructions_); 9519 VIXL_ASSERT(OutsideITBlock()); 9520 MacroEmissionCheckScope guard(this); 9521 ITScope it_scope(this, &cond, guard); 9522 vrsqrts(cond, dt, rd, rn, rm); 9523 } 9524 void Vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9525 Vrsqrts(al, dt, rd, rn, rm); 9526 } 9527 9528 void Vrsqrts( 9529 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9530 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9531 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9532 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9533 VIXL_ASSERT(allow_macro_instructions_); 9534 VIXL_ASSERT(OutsideITBlock()); 9535 MacroEmissionCheckScope guard(this); 9536 ITScope it_scope(this, &cond, guard); 9537 vrsqrts(cond, dt, rd, rn, rm); 9538 } 9539 void Vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 9540 Vrsqrts(al, dt, rd, rn, rm); 9541 } 9542 9543 void Vrsra(Condition cond, 9544 DataType dt, 9545 DRegister rd, 9546 DRegister rm, 9547 const DOperand& operand) { 9548 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9549 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9550 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9551 VIXL_ASSERT(allow_macro_instructions_); 9552 VIXL_ASSERT(OutsideITBlock()); 9553 MacroEmissionCheckScope guard(this); 9554 ITScope it_scope(this, &cond, guard); 9555 vrsra(cond, dt, rd, rm, operand); 9556 } 9557 void Vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9558 Vrsra(al, dt, rd, rm, operand); 9559 } 9560 9561 void Vrsra(Condition cond, 9562 DataType dt, 9563 QRegister rd, 9564 QRegister rm, 9565 const QOperand& operand) { 9566 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9567 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9568 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9569 VIXL_ASSERT(allow_macro_instructions_); 9570 VIXL_ASSERT(OutsideITBlock()); 9571 MacroEmissionCheckScope guard(this); 9572 ITScope it_scope(this, &cond, guard); 9573 vrsra(cond, dt, rd, rm, operand); 9574 } 9575 void Vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9576 Vrsra(al, dt, rd, rm, operand); 9577 } 9578 9579 void Vrsubhn( 9580 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9581 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9582 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9583 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9584 VIXL_ASSERT(allow_macro_instructions_); 9585 VIXL_ASSERT(OutsideITBlock()); 9586 MacroEmissionCheckScope guard(this); 9587 ITScope it_scope(this, &cond, guard); 9588 vrsubhn(cond, dt, rd, rn, rm); 9589 } 9590 void Vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 9591 Vrsubhn(al, dt, rd, rn, rm); 9592 } 9593 9594 void Vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9595 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9596 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9597 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9598 VIXL_ASSERT(allow_macro_instructions_); 9599 VIXL_ASSERT(OutsideITBlock()); 9600 MacroEmissionCheckScope guard(this); 9601 vseleq(dt, rd, rn, rm); 9602 } 9603 9604 void Vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9605 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9606 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9607 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9608 VIXL_ASSERT(allow_macro_instructions_); 9609 VIXL_ASSERT(OutsideITBlock()); 9610 MacroEmissionCheckScope guard(this); 9611 vseleq(dt, rd, rn, rm); 9612 } 9613 9614 void Vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9615 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9616 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9617 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9618 VIXL_ASSERT(allow_macro_instructions_); 9619 VIXL_ASSERT(OutsideITBlock()); 9620 MacroEmissionCheckScope guard(this); 9621 vselge(dt, rd, rn, rm); 9622 } 9623 9624 void Vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9625 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9626 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9627 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9628 VIXL_ASSERT(allow_macro_instructions_); 9629 VIXL_ASSERT(OutsideITBlock()); 9630 MacroEmissionCheckScope guard(this); 9631 vselge(dt, rd, rn, rm); 9632 } 9633 9634 void Vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9635 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9636 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9637 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9638 VIXL_ASSERT(allow_macro_instructions_); 9639 VIXL_ASSERT(OutsideITBlock()); 9640 MacroEmissionCheckScope guard(this); 9641 vselgt(dt, rd, rn, rm); 9642 } 9643 9644 void Vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9645 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9646 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9647 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9648 VIXL_ASSERT(allow_macro_instructions_); 9649 VIXL_ASSERT(OutsideITBlock()); 9650 MacroEmissionCheckScope guard(this); 9651 vselgt(dt, rd, rn, rm); 9652 } 9653 9654 void Vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 9655 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9656 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9657 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9658 VIXL_ASSERT(allow_macro_instructions_); 9659 VIXL_ASSERT(OutsideITBlock()); 9660 MacroEmissionCheckScope guard(this); 9661 vselvs(dt, rd, rn, rm); 9662 } 9663 9664 void Vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 9665 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9666 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 9667 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9668 VIXL_ASSERT(allow_macro_instructions_); 9669 VIXL_ASSERT(OutsideITBlock()); 9670 MacroEmissionCheckScope guard(this); 9671 vselvs(dt, rd, rn, rm); 9672 } 9673 9674 void Vshl(Condition cond, 9675 DataType dt, 9676 DRegister rd, 9677 DRegister rm, 9678 const DOperand& operand) { 9679 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9680 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9681 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9682 VIXL_ASSERT(allow_macro_instructions_); 9683 VIXL_ASSERT(OutsideITBlock()); 9684 MacroEmissionCheckScope guard(this); 9685 ITScope it_scope(this, &cond, guard); 9686 vshl(cond, dt, rd, rm, operand); 9687 } 9688 void Vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9689 Vshl(al, dt, rd, rm, operand); 9690 } 9691 9692 void Vshl(Condition cond, 9693 DataType dt, 9694 QRegister rd, 9695 QRegister rm, 9696 const QOperand& operand) { 9697 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9698 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9699 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9700 VIXL_ASSERT(allow_macro_instructions_); 9701 VIXL_ASSERT(OutsideITBlock()); 9702 MacroEmissionCheckScope guard(this); 9703 ITScope it_scope(this, &cond, guard); 9704 vshl(cond, dt, rd, rm, operand); 9705 } 9706 void Vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9707 Vshl(al, dt, rd, rm, operand); 9708 } 9709 9710 void Vshll(Condition cond, 9711 DataType dt, 9712 QRegister rd, 9713 DRegister rm, 9714 const DOperand& operand) { 9715 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9716 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9717 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9718 VIXL_ASSERT(allow_macro_instructions_); 9719 VIXL_ASSERT(OutsideITBlock()); 9720 MacroEmissionCheckScope guard(this); 9721 ITScope it_scope(this, &cond, guard); 9722 vshll(cond, dt, rd, rm, operand); 9723 } 9724 void Vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 9725 Vshll(al, dt, rd, rm, operand); 9726 } 9727 9728 void Vshr(Condition cond, 9729 DataType dt, 9730 DRegister rd, 9731 DRegister rm, 9732 const DOperand& operand) { 9733 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9734 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9735 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9736 VIXL_ASSERT(allow_macro_instructions_); 9737 VIXL_ASSERT(OutsideITBlock()); 9738 MacroEmissionCheckScope guard(this); 9739 ITScope it_scope(this, &cond, guard); 9740 vshr(cond, dt, rd, rm, operand); 9741 } 9742 void Vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9743 Vshr(al, dt, rd, rm, operand); 9744 } 9745 9746 void Vshr(Condition cond, 9747 DataType dt, 9748 QRegister rd, 9749 QRegister rm, 9750 const QOperand& operand) { 9751 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9752 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9753 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9754 VIXL_ASSERT(allow_macro_instructions_); 9755 VIXL_ASSERT(OutsideITBlock()); 9756 MacroEmissionCheckScope guard(this); 9757 ITScope it_scope(this, &cond, guard); 9758 vshr(cond, dt, rd, rm, operand); 9759 } 9760 void Vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9761 Vshr(al, dt, rd, rm, operand); 9762 } 9763 9764 void Vshrn(Condition cond, 9765 DataType dt, 9766 DRegister rd, 9767 QRegister rm, 9768 const QOperand& operand) { 9769 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9770 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9771 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9772 VIXL_ASSERT(allow_macro_instructions_); 9773 VIXL_ASSERT(OutsideITBlock()); 9774 MacroEmissionCheckScope guard(this); 9775 ITScope it_scope(this, &cond, guard); 9776 vshrn(cond, dt, rd, rm, operand); 9777 } 9778 void Vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 9779 Vshrn(al, dt, rd, rm, operand); 9780 } 9781 9782 void Vsli(Condition cond, 9783 DataType dt, 9784 DRegister rd, 9785 DRegister rm, 9786 const DOperand& operand) { 9787 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9788 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9789 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9790 VIXL_ASSERT(allow_macro_instructions_); 9791 VIXL_ASSERT(OutsideITBlock()); 9792 MacroEmissionCheckScope guard(this); 9793 ITScope it_scope(this, &cond, guard); 9794 vsli(cond, dt, rd, rm, operand); 9795 } 9796 void Vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9797 Vsli(al, dt, rd, rm, operand); 9798 } 9799 9800 void Vsli(Condition cond, 9801 DataType dt, 9802 QRegister rd, 9803 QRegister rm, 9804 const QOperand& operand) { 9805 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9806 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9807 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9808 VIXL_ASSERT(allow_macro_instructions_); 9809 VIXL_ASSERT(OutsideITBlock()); 9810 MacroEmissionCheckScope guard(this); 9811 ITScope it_scope(this, &cond, guard); 9812 vsli(cond, dt, rd, rm, operand); 9813 } 9814 void Vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9815 Vsli(al, dt, rd, rm, operand); 9816 } 9817 9818 void Vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm) { 9819 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9820 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9821 VIXL_ASSERT(allow_macro_instructions_); 9822 VIXL_ASSERT(OutsideITBlock()); 9823 MacroEmissionCheckScope guard(this); 9824 ITScope it_scope(this, &cond, guard); 9825 vsqrt(cond, dt, rd, rm); 9826 } 9827 void Vsqrt(DataType dt, SRegister rd, SRegister rm) { Vsqrt(al, dt, rd, rm); } 9828 9829 void Vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm) { 9830 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9831 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9832 VIXL_ASSERT(allow_macro_instructions_); 9833 VIXL_ASSERT(OutsideITBlock()); 9834 MacroEmissionCheckScope guard(this); 9835 ITScope it_scope(this, &cond, guard); 9836 vsqrt(cond, dt, rd, rm); 9837 } 9838 void Vsqrt(DataType dt, DRegister rd, DRegister rm) { Vsqrt(al, dt, rd, rm); } 9839 9840 void Vsra(Condition cond, 9841 DataType dt, 9842 DRegister rd, 9843 DRegister rm, 9844 const DOperand& operand) { 9845 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9846 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9847 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9848 VIXL_ASSERT(allow_macro_instructions_); 9849 VIXL_ASSERT(OutsideITBlock()); 9850 MacroEmissionCheckScope guard(this); 9851 ITScope it_scope(this, &cond, guard); 9852 vsra(cond, dt, rd, rm, operand); 9853 } 9854 void Vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9855 Vsra(al, dt, rd, rm, operand); 9856 } 9857 9858 void Vsra(Condition cond, 9859 DataType dt, 9860 QRegister rd, 9861 QRegister rm, 9862 const QOperand& operand) { 9863 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9864 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9865 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9866 VIXL_ASSERT(allow_macro_instructions_); 9867 VIXL_ASSERT(OutsideITBlock()); 9868 MacroEmissionCheckScope guard(this); 9869 ITScope it_scope(this, &cond, guard); 9870 vsra(cond, dt, rd, rm, operand); 9871 } 9872 void Vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9873 Vsra(al, dt, rd, rm, operand); 9874 } 9875 9876 void Vsri(Condition cond, 9877 DataType dt, 9878 DRegister rd, 9879 DRegister rm, 9880 const DOperand& operand) { 9881 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9882 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9883 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9884 VIXL_ASSERT(allow_macro_instructions_); 9885 VIXL_ASSERT(OutsideITBlock()); 9886 MacroEmissionCheckScope guard(this); 9887 ITScope it_scope(this, &cond, guard); 9888 vsri(cond, dt, rd, rm, operand); 9889 } 9890 void Vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 9891 Vsri(al, dt, rd, rm, operand); 9892 } 9893 9894 void Vsri(Condition cond, 9895 DataType dt, 9896 QRegister rd, 9897 QRegister rm, 9898 const QOperand& operand) { 9899 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 9900 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 9901 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9902 VIXL_ASSERT(allow_macro_instructions_); 9903 VIXL_ASSERT(OutsideITBlock()); 9904 MacroEmissionCheckScope guard(this); 9905 ITScope it_scope(this, &cond, guard); 9906 vsri(cond, dt, rd, rm, operand); 9907 } 9908 void Vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 9909 Vsri(al, dt, rd, rm, operand); 9910 } 9911 9912 void Vst1(Condition cond, 9913 DataType dt, 9914 const NeonRegisterList& nreglist, 9915 const AlignedMemOperand& operand) { 9916 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9917 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9918 VIXL_ASSERT(allow_macro_instructions_); 9919 VIXL_ASSERT(OutsideITBlock()); 9920 MacroEmissionCheckScope guard(this); 9921 ITScope it_scope(this, &cond, guard); 9922 vst1(cond, dt, nreglist, operand); 9923 } 9924 void Vst1(DataType dt, 9925 const NeonRegisterList& nreglist, 9926 const AlignedMemOperand& operand) { 9927 Vst1(al, dt, nreglist, operand); 9928 } 9929 9930 void Vst2(Condition cond, 9931 DataType dt, 9932 const NeonRegisterList& nreglist, 9933 const AlignedMemOperand& operand) { 9934 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9935 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9936 VIXL_ASSERT(allow_macro_instructions_); 9937 VIXL_ASSERT(OutsideITBlock()); 9938 MacroEmissionCheckScope guard(this); 9939 ITScope it_scope(this, &cond, guard); 9940 vst2(cond, dt, nreglist, operand); 9941 } 9942 void Vst2(DataType dt, 9943 const NeonRegisterList& nreglist, 9944 const AlignedMemOperand& operand) { 9945 Vst2(al, dt, nreglist, operand); 9946 } 9947 9948 void Vst3(Condition cond, 9949 DataType dt, 9950 const NeonRegisterList& nreglist, 9951 const AlignedMemOperand& operand) { 9952 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9953 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9954 VIXL_ASSERT(allow_macro_instructions_); 9955 VIXL_ASSERT(OutsideITBlock()); 9956 MacroEmissionCheckScope guard(this); 9957 ITScope it_scope(this, &cond, guard); 9958 vst3(cond, dt, nreglist, operand); 9959 } 9960 void Vst3(DataType dt, 9961 const NeonRegisterList& nreglist, 9962 const AlignedMemOperand& operand) { 9963 Vst3(al, dt, nreglist, operand); 9964 } 9965 9966 void Vst3(Condition cond, 9967 DataType dt, 9968 const NeonRegisterList& nreglist, 9969 const MemOperand& operand) { 9970 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9971 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9972 VIXL_ASSERT(allow_macro_instructions_); 9973 VIXL_ASSERT(OutsideITBlock()); 9974 MacroEmissionCheckScope guard(this); 9975 ITScope it_scope(this, &cond, guard); 9976 vst3(cond, dt, nreglist, operand); 9977 } 9978 void Vst3(DataType dt, 9979 const NeonRegisterList& nreglist, 9980 const MemOperand& operand) { 9981 Vst3(al, dt, nreglist, operand); 9982 } 9983 9984 void Vst4(Condition cond, 9985 DataType dt, 9986 const NeonRegisterList& nreglist, 9987 const AlignedMemOperand& operand) { 9988 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 9989 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 9990 VIXL_ASSERT(allow_macro_instructions_); 9991 VIXL_ASSERT(OutsideITBlock()); 9992 MacroEmissionCheckScope guard(this); 9993 ITScope it_scope(this, &cond, guard); 9994 vst4(cond, dt, nreglist, operand); 9995 } 9996 void Vst4(DataType dt, 9997 const NeonRegisterList& nreglist, 9998 const AlignedMemOperand& operand) { 9999 Vst4(al, dt, nreglist, operand); 10000 } 10001 10002 void Vstm(Condition cond, 10003 DataType dt, 10004 Register rn, 10005 WriteBack write_back, 10006 DRegisterList dreglist) { 10007 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10008 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 10009 VIXL_ASSERT(allow_macro_instructions_); 10010 VIXL_ASSERT(OutsideITBlock()); 10011 MacroEmissionCheckScope guard(this); 10012 ITScope it_scope(this, &cond, guard); 10013 vstm(cond, dt, rn, write_back, dreglist); 10014 } 10015 void Vstm(DataType dt, 10016 Register rn, 10017 WriteBack write_back, 10018 DRegisterList dreglist) { 10019 Vstm(al, dt, rn, write_back, dreglist); 10020 } 10021 void Vstm(Condition cond, 10022 Register rn, 10023 WriteBack write_back, 10024 DRegisterList dreglist) { 10025 Vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 10026 } 10027 void Vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 10028 Vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 10029 } 10030 10031 void Vstm(Condition cond, 10032 DataType dt, 10033 Register rn, 10034 WriteBack write_back, 10035 SRegisterList sreglist) { 10036 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10037 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 10038 VIXL_ASSERT(allow_macro_instructions_); 10039 VIXL_ASSERT(OutsideITBlock()); 10040 MacroEmissionCheckScope guard(this); 10041 ITScope it_scope(this, &cond, guard); 10042 vstm(cond, dt, rn, write_back, sreglist); 10043 } 10044 void Vstm(DataType dt, 10045 Register rn, 10046 WriteBack write_back, 10047 SRegisterList sreglist) { 10048 Vstm(al, dt, rn, write_back, sreglist); 10049 } 10050 void Vstm(Condition cond, 10051 Register rn, 10052 WriteBack write_back, 10053 SRegisterList sreglist) { 10054 Vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 10055 } 10056 void Vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 10057 Vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 10058 } 10059 10060 void Vstmdb(Condition cond, 10061 DataType dt, 10062 Register rn, 10063 WriteBack write_back, 10064 DRegisterList dreglist) { 10065 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10066 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 10067 VIXL_ASSERT(allow_macro_instructions_); 10068 VIXL_ASSERT(OutsideITBlock()); 10069 MacroEmissionCheckScope guard(this); 10070 ITScope it_scope(this, &cond, guard); 10071 vstmdb(cond, dt, rn, write_back, dreglist); 10072 } 10073 void Vstmdb(DataType dt, 10074 Register rn, 10075 WriteBack write_back, 10076 DRegisterList dreglist) { 10077 Vstmdb(al, dt, rn, write_back, dreglist); 10078 } 10079 void Vstmdb(Condition cond, 10080 Register rn, 10081 WriteBack write_back, 10082 DRegisterList dreglist) { 10083 Vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 10084 } 10085 void Vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 10086 Vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 10087 } 10088 10089 void Vstmdb(Condition cond, 10090 DataType dt, 10091 Register rn, 10092 WriteBack write_back, 10093 SRegisterList sreglist) { 10094 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10095 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 10096 VIXL_ASSERT(allow_macro_instructions_); 10097 VIXL_ASSERT(OutsideITBlock()); 10098 MacroEmissionCheckScope guard(this); 10099 ITScope it_scope(this, &cond, guard); 10100 vstmdb(cond, dt, rn, write_back, sreglist); 10101 } 10102 void Vstmdb(DataType dt, 10103 Register rn, 10104 WriteBack write_back, 10105 SRegisterList sreglist) { 10106 Vstmdb(al, dt, rn, write_back, sreglist); 10107 } 10108 void Vstmdb(Condition cond, 10109 Register rn, 10110 WriteBack write_back, 10111 SRegisterList sreglist) { 10112 Vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 10113 } 10114 void Vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 10115 Vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 10116 } 10117 10118 void Vstmia(Condition cond, 10119 DataType dt, 10120 Register rn, 10121 WriteBack write_back, 10122 DRegisterList dreglist) { 10123 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10124 VIXL_ASSERT(!AliasesAvailableScratchRegister(dreglist)); 10125 VIXL_ASSERT(allow_macro_instructions_); 10126 VIXL_ASSERT(OutsideITBlock()); 10127 MacroEmissionCheckScope guard(this); 10128 ITScope it_scope(this, &cond, guard); 10129 vstmia(cond, dt, rn, write_back, dreglist); 10130 } 10131 void Vstmia(DataType dt, 10132 Register rn, 10133 WriteBack write_back, 10134 DRegisterList dreglist) { 10135 Vstmia(al, dt, rn, write_back, dreglist); 10136 } 10137 void Vstmia(Condition cond, 10138 Register rn, 10139 WriteBack write_back, 10140 DRegisterList dreglist) { 10141 Vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 10142 } 10143 void Vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 10144 Vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 10145 } 10146 10147 void Vstmia(Condition cond, 10148 DataType dt, 10149 Register rn, 10150 WriteBack write_back, 10151 SRegisterList sreglist) { 10152 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10153 VIXL_ASSERT(!AliasesAvailableScratchRegister(sreglist)); 10154 VIXL_ASSERT(allow_macro_instructions_); 10155 VIXL_ASSERT(OutsideITBlock()); 10156 MacroEmissionCheckScope guard(this); 10157 ITScope it_scope(this, &cond, guard); 10158 vstmia(cond, dt, rn, write_back, sreglist); 10159 } 10160 void Vstmia(DataType dt, 10161 Register rn, 10162 WriteBack write_back, 10163 SRegisterList sreglist) { 10164 Vstmia(al, dt, rn, write_back, sreglist); 10165 } 10166 void Vstmia(Condition cond, 10167 Register rn, 10168 WriteBack write_back, 10169 SRegisterList sreglist) { 10170 Vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 10171 } 10172 void Vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 10173 Vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 10174 } 10175 10176 void Vstr(Condition cond, 10177 DataType dt, 10178 DRegister rd, 10179 const MemOperand& operand) { 10180 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10181 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 10182 VIXL_ASSERT(allow_macro_instructions_); 10183 VIXL_ASSERT(OutsideITBlock()); 10184 MacroEmissionCheckScope guard(this); 10185 ITScope it_scope(this, &cond, guard); 10186 vstr(cond, dt, rd, operand); 10187 } 10188 void Vstr(DataType dt, DRegister rd, const MemOperand& operand) { 10189 Vstr(al, dt, rd, operand); 10190 } 10191 void Vstr(Condition cond, DRegister rd, const MemOperand& operand) { 10192 Vstr(cond, Untyped64, rd, operand); 10193 } 10194 void Vstr(DRegister rd, const MemOperand& operand) { 10195 Vstr(al, Untyped64, rd, operand); 10196 } 10197 10198 void Vstr(Condition cond, 10199 DataType dt, 10200 SRegister rd, 10201 const MemOperand& operand) { 10202 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10203 VIXL_ASSERT(!AliasesAvailableScratchRegister(operand)); 10204 VIXL_ASSERT(allow_macro_instructions_); 10205 VIXL_ASSERT(OutsideITBlock()); 10206 MacroEmissionCheckScope guard(this); 10207 ITScope it_scope(this, &cond, guard); 10208 vstr(cond, dt, rd, operand); 10209 } 10210 void Vstr(DataType dt, SRegister rd, const MemOperand& operand) { 10211 Vstr(al, dt, rd, operand); 10212 } 10213 void Vstr(Condition cond, SRegister rd, const MemOperand& operand) { 10214 Vstr(cond, Untyped32, rd, operand); 10215 } 10216 void Vstr(SRegister rd, const MemOperand& operand) { 10217 Vstr(al, Untyped32, rd, operand); 10218 } 10219 10220 void Vsub( 10221 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10222 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10223 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10224 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10225 VIXL_ASSERT(allow_macro_instructions_); 10226 VIXL_ASSERT(OutsideITBlock()); 10227 MacroEmissionCheckScope guard(this); 10228 ITScope it_scope(this, &cond, guard); 10229 vsub(cond, dt, rd, rn, rm); 10230 } 10231 void Vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10232 Vsub(al, dt, rd, rn, rm); 10233 } 10234 10235 void Vsub( 10236 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10237 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10238 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10239 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10240 VIXL_ASSERT(allow_macro_instructions_); 10241 VIXL_ASSERT(OutsideITBlock()); 10242 MacroEmissionCheckScope guard(this); 10243 ITScope it_scope(this, &cond, guard); 10244 vsub(cond, dt, rd, rn, rm); 10245 } 10246 void Vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10247 Vsub(al, dt, rd, rn, rm); 10248 } 10249 10250 void Vsub( 10251 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm) { 10252 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10253 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10254 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10255 VIXL_ASSERT(allow_macro_instructions_); 10256 VIXL_ASSERT(OutsideITBlock()); 10257 MacroEmissionCheckScope guard(this); 10258 ITScope it_scope(this, &cond, guard); 10259 vsub(cond, dt, rd, rn, rm); 10260 } 10261 void Vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 10262 Vsub(al, dt, rd, rn, rm); 10263 } 10264 10265 void Vsubhn( 10266 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm) { 10267 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10268 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10269 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10270 VIXL_ASSERT(allow_macro_instructions_); 10271 VIXL_ASSERT(OutsideITBlock()); 10272 MacroEmissionCheckScope guard(this); 10273 ITScope it_scope(this, &cond, guard); 10274 vsubhn(cond, dt, rd, rn, rm); 10275 } 10276 void Vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 10277 Vsubhn(al, dt, rd, rn, rm); 10278 } 10279 10280 void Vsubl( 10281 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm) { 10282 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10283 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10284 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10285 VIXL_ASSERT(allow_macro_instructions_); 10286 VIXL_ASSERT(OutsideITBlock()); 10287 MacroEmissionCheckScope guard(this); 10288 ITScope it_scope(this, &cond, guard); 10289 vsubl(cond, dt, rd, rn, rm); 10290 } 10291 void Vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 10292 Vsubl(al, dt, rd, rn, rm); 10293 } 10294 10295 void Vsubw( 10296 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm) { 10297 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10298 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10299 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10300 VIXL_ASSERT(allow_macro_instructions_); 10301 VIXL_ASSERT(OutsideITBlock()); 10302 MacroEmissionCheckScope guard(this); 10303 ITScope it_scope(this, &cond, guard); 10304 vsubw(cond, dt, rd, rn, rm); 10305 } 10306 void Vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 10307 Vsubw(al, dt, rd, rn, rm); 10308 } 10309 10310 void Vswp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10311 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10312 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10313 VIXL_ASSERT(allow_macro_instructions_); 10314 VIXL_ASSERT(OutsideITBlock()); 10315 MacroEmissionCheckScope guard(this); 10316 ITScope it_scope(this, &cond, guard); 10317 vswp(cond, dt, rd, rm); 10318 } 10319 void Vswp(DataType dt, DRegister rd, DRegister rm) { Vswp(al, dt, rd, rm); } 10320 void Vswp(Condition cond, DRegister rd, DRegister rm) { 10321 Vswp(cond, kDataTypeValueNone, rd, rm); 10322 } 10323 void Vswp(DRegister rd, DRegister rm) { 10324 Vswp(al, kDataTypeValueNone, rd, rm); 10325 } 10326 10327 void Vswp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10328 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10329 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10330 VIXL_ASSERT(allow_macro_instructions_); 10331 VIXL_ASSERT(OutsideITBlock()); 10332 MacroEmissionCheckScope guard(this); 10333 ITScope it_scope(this, &cond, guard); 10334 vswp(cond, dt, rd, rm); 10335 } 10336 void Vswp(DataType dt, QRegister rd, QRegister rm) { Vswp(al, dt, rd, rm); } 10337 void Vswp(Condition cond, QRegister rd, QRegister rm) { 10338 Vswp(cond, kDataTypeValueNone, rd, rm); 10339 } 10340 void Vswp(QRegister rd, QRegister rm) { 10341 Vswp(al, kDataTypeValueNone, rd, rm); 10342 } 10343 10344 void Vtbl(Condition cond, 10345 DataType dt, 10346 DRegister rd, 10347 const NeonRegisterList& nreglist, 10348 DRegister rm) { 10349 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10350 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 10351 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10352 VIXL_ASSERT(allow_macro_instructions_); 10353 VIXL_ASSERT(OutsideITBlock()); 10354 MacroEmissionCheckScope guard(this); 10355 ITScope it_scope(this, &cond, guard); 10356 vtbl(cond, dt, rd, nreglist, rm); 10357 } 10358 void Vtbl(DataType dt, 10359 DRegister rd, 10360 const NeonRegisterList& nreglist, 10361 DRegister rm) { 10362 Vtbl(al, dt, rd, nreglist, rm); 10363 } 10364 10365 void Vtbx(Condition cond, 10366 DataType dt, 10367 DRegister rd, 10368 const NeonRegisterList& nreglist, 10369 DRegister rm) { 10370 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10371 VIXL_ASSERT(!AliasesAvailableScratchRegister(nreglist)); 10372 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10373 VIXL_ASSERT(allow_macro_instructions_); 10374 VIXL_ASSERT(OutsideITBlock()); 10375 MacroEmissionCheckScope guard(this); 10376 ITScope it_scope(this, &cond, guard); 10377 vtbx(cond, dt, rd, nreglist, rm); 10378 } 10379 void Vtbx(DataType dt, 10380 DRegister rd, 10381 const NeonRegisterList& nreglist, 10382 DRegister rm) { 10383 Vtbx(al, dt, rd, nreglist, rm); 10384 } 10385 10386 void Vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10387 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10388 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10389 VIXL_ASSERT(allow_macro_instructions_); 10390 VIXL_ASSERT(OutsideITBlock()); 10391 MacroEmissionCheckScope guard(this); 10392 ITScope it_scope(this, &cond, guard); 10393 vtrn(cond, dt, rd, rm); 10394 } 10395 void Vtrn(DataType dt, DRegister rd, DRegister rm) { Vtrn(al, dt, rd, rm); } 10396 10397 void Vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10398 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10399 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10400 VIXL_ASSERT(allow_macro_instructions_); 10401 VIXL_ASSERT(OutsideITBlock()); 10402 MacroEmissionCheckScope guard(this); 10403 ITScope it_scope(this, &cond, guard); 10404 vtrn(cond, dt, rd, rm); 10405 } 10406 void Vtrn(DataType dt, QRegister rd, QRegister rm) { Vtrn(al, dt, rd, rm); } 10407 10408 void Vtst( 10409 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10410 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10411 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10412 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10413 VIXL_ASSERT(allow_macro_instructions_); 10414 VIXL_ASSERT(OutsideITBlock()); 10415 MacroEmissionCheckScope guard(this); 10416 ITScope it_scope(this, &cond, guard); 10417 vtst(cond, dt, rd, rn, rm); 10418 } 10419 void Vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 10420 Vtst(al, dt, rd, rn, rm); 10421 } 10422 10423 void Vtst( 10424 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10425 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10426 VIXL_ASSERT(!AliasesAvailableScratchRegister(rn)); 10427 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10428 VIXL_ASSERT(allow_macro_instructions_); 10429 VIXL_ASSERT(OutsideITBlock()); 10430 MacroEmissionCheckScope guard(this); 10431 ITScope it_scope(this, &cond, guard); 10432 vtst(cond, dt, rd, rn, rm); 10433 } 10434 void Vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 10435 Vtst(al, dt, rd, rn, rm); 10436 } 10437 10438 void Vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10439 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10440 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10441 VIXL_ASSERT(allow_macro_instructions_); 10442 VIXL_ASSERT(OutsideITBlock()); 10443 MacroEmissionCheckScope guard(this); 10444 ITScope it_scope(this, &cond, guard); 10445 vuzp(cond, dt, rd, rm); 10446 } 10447 void Vuzp(DataType dt, DRegister rd, DRegister rm) { Vuzp(al, dt, rd, rm); } 10448 10449 void Vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10450 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10451 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10452 VIXL_ASSERT(allow_macro_instructions_); 10453 VIXL_ASSERT(OutsideITBlock()); 10454 MacroEmissionCheckScope guard(this); 10455 ITScope it_scope(this, &cond, guard); 10456 vuzp(cond, dt, rd, rm); 10457 } 10458 void Vuzp(DataType dt, QRegister rd, QRegister rm) { Vuzp(al, dt, rd, rm); } 10459 10460 void Vzip(Condition cond, DataType dt, DRegister rd, DRegister rm) { 10461 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10462 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10463 VIXL_ASSERT(allow_macro_instructions_); 10464 VIXL_ASSERT(OutsideITBlock()); 10465 MacroEmissionCheckScope guard(this); 10466 ITScope it_scope(this, &cond, guard); 10467 vzip(cond, dt, rd, rm); 10468 } 10469 void Vzip(DataType dt, DRegister rd, DRegister rm) { Vzip(al, dt, rd, rm); } 10470 10471 void Vzip(Condition cond, DataType dt, QRegister rd, QRegister rm) { 10472 VIXL_ASSERT(!AliasesAvailableScratchRegister(rd)); 10473 VIXL_ASSERT(!AliasesAvailableScratchRegister(rm)); 10474 VIXL_ASSERT(allow_macro_instructions_); 10475 VIXL_ASSERT(OutsideITBlock()); 10476 MacroEmissionCheckScope guard(this); 10477 ITScope it_scope(this, &cond, guard); 10478 vzip(cond, dt, rd, rm); 10479 } 10480 void Vzip(DataType dt, QRegister rd, QRegister rm) { Vzip(al, dt, rd, rm); } 10481 10482 void Yield(Condition cond) { 10483 VIXL_ASSERT(allow_macro_instructions_); 10484 VIXL_ASSERT(OutsideITBlock()); 10485 MacroEmissionCheckScope guard(this); 10486 ITScope it_scope(this, &cond, guard); 10487 yield(cond); 10488 } 10489 void Yield() { Yield(al); } 10490 void Vabs(Condition cond, VRegister rd, VRegister rm) { 10491 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10492 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10493 if (rd.IsS()) { 10494 Vabs(cond, F32, rd.S(), rm.S()); 10495 } else { 10496 Vabs(cond, F64, rd.D(), rm.D()); 10497 } 10498 } 10499 void Vabs(VRegister rd, VRegister rm) { Vabs(al, rd, rm); } 10500 void Vadd(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10501 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10502 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10503 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10504 if (rd.IsS()) { 10505 Vadd(cond, F32, rd.S(), rn.S(), rm.S()); 10506 } else { 10507 Vadd(cond, F64, rd.D(), rn.D(), rm.D()); 10508 } 10509 } 10510 void Vadd(VRegister rd, VRegister rn, VRegister rm) { Vadd(al, rd, rn, rm); } 10511 void Vcmp(Condition cond, VRegister rd, VRegister rm) { 10512 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10513 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10514 if (rd.IsS()) { 10515 Vcmp(cond, F32, rd.S(), rm.S()); 10516 } else { 10517 Vcmp(cond, F64, rd.D(), rm.D()); 10518 } 10519 } 10520 void Vcmp(VRegister rd, VRegister rm) { Vcmp(al, rd, rm); } 10521 void Vcmpe(Condition cond, VRegister rd, VRegister rm) { 10522 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10523 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10524 if (rd.IsS()) { 10525 Vcmpe(cond, F32, rd.S(), rm.S()); 10526 } else { 10527 Vcmpe(cond, F64, rd.D(), rm.D()); 10528 } 10529 } 10530 void Vcmpe(VRegister rd, VRegister rm) { Vcmpe(al, rd, rm); } 10531 void Vdiv(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10532 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10533 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10534 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10535 if (rd.IsS()) { 10536 Vdiv(cond, F32, rd.S(), rn.S(), rm.S()); 10537 } else { 10538 Vdiv(cond, F64, rd.D(), rn.D(), rm.D()); 10539 } 10540 } 10541 void Vdiv(VRegister rd, VRegister rn, VRegister rm) { Vdiv(al, rd, rn, rm); } 10542 void Vfma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10543 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10544 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10545 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10546 if (rd.IsS()) { 10547 Vfma(cond, F32, rd.S(), rn.S(), rm.S()); 10548 } else { 10549 Vfma(cond, F64, rd.D(), rn.D(), rm.D()); 10550 } 10551 } 10552 void Vfma(VRegister rd, VRegister rn, VRegister rm) { Vfma(al, rd, rn, rm); } 10553 void Vfms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10554 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10555 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10556 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10557 if (rd.IsS()) { 10558 Vfms(cond, F32, rd.S(), rn.S(), rm.S()); 10559 } else { 10560 Vfms(cond, F64, rd.D(), rn.D(), rm.D()); 10561 } 10562 } 10563 void Vfms(VRegister rd, VRegister rn, VRegister rm) { Vfms(al, rd, rn, rm); } 10564 void Vfnma(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10565 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10566 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10567 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10568 if (rd.IsS()) { 10569 Vfnma(cond, F32, rd.S(), rn.S(), rm.S()); 10570 } else { 10571 Vfnma(cond, F64, rd.D(), rn.D(), rm.D()); 10572 } 10573 } 10574 void Vfnma(VRegister rd, VRegister rn, VRegister rm) { 10575 Vfnma(al, rd, rn, rm); 10576 } 10577 void Vfnms(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10578 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10579 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10580 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10581 if (rd.IsS()) { 10582 Vfnms(cond, F32, rd.S(), rn.S(), rm.S()); 10583 } else { 10584 Vfnms(cond, F64, rd.D(), rn.D(), rm.D()); 10585 } 10586 } 10587 void Vfnms(VRegister rd, VRegister rn, VRegister rm) { 10588 Vfnms(al, rd, rn, rm); 10589 } 10590 void Vmaxnm(VRegister rd, VRegister rn, VRegister rm) { 10591 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10592 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10593 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10594 if (rd.IsS()) { 10595 Vmaxnm(F32, rd.S(), rn.S(), rm.S()); 10596 } else { 10597 Vmaxnm(F64, rd.D(), rn.D(), rm.D()); 10598 } 10599 } 10600 void Vminnm(VRegister rd, VRegister rn, VRegister rm) { 10601 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10602 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10603 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10604 if (rd.IsS()) { 10605 Vminnm(F32, rd.S(), rn.S(), rm.S()); 10606 } else { 10607 Vminnm(F64, rd.D(), rn.D(), rm.D()); 10608 } 10609 } 10610 void Vmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10611 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10612 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10613 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10614 if (rd.IsS()) { 10615 Vmla(cond, F32, rd.S(), rn.S(), rm.S()); 10616 } else { 10617 Vmla(cond, F64, rd.D(), rn.D(), rm.D()); 10618 } 10619 } 10620 void Vmla(VRegister rd, VRegister rn, VRegister rm) { Vmla(al, rd, rn, rm); } 10621 void Vmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10622 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10623 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10624 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10625 if (rd.IsS()) { 10626 Vmls(cond, F32, rd.S(), rn.S(), rm.S()); 10627 } else { 10628 Vmls(cond, F64, rd.D(), rn.D(), rm.D()); 10629 } 10630 } 10631 void Vmls(VRegister rd, VRegister rn, VRegister rm) { Vmls(al, rd, rn, rm); } 10632 void Vmov(Condition cond, VRegister rd, VRegister rm) { 10633 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10634 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10635 if (rd.IsS()) { 10636 Vmov(cond, F32, rd.S(), rm.S()); 10637 } else { 10638 Vmov(cond, F64, rd.D(), rm.D()); 10639 } 10640 } 10641 void Vmov(VRegister rd, VRegister rm) { Vmov(al, rd, rm); } 10642 void Vmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10643 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10644 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10645 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10646 if (rd.IsS()) { 10647 Vmul(cond, F32, rd.S(), rn.S(), rm.S()); 10648 } else { 10649 Vmul(cond, F64, rd.D(), rn.D(), rm.D()); 10650 } 10651 } 10652 void Vmul(VRegister rd, VRegister rn, VRegister rm) { Vmul(al, rd, rn, rm); } 10653 void Vneg(Condition cond, VRegister rd, VRegister rm) { 10654 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10655 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10656 if (rd.IsS()) { 10657 Vneg(cond, F32, rd.S(), rm.S()); 10658 } else { 10659 Vneg(cond, F64, rd.D(), rm.D()); 10660 } 10661 } 10662 void Vneg(VRegister rd, VRegister rm) { Vneg(al, rd, rm); } 10663 void Vnmla(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10664 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10665 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10666 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10667 if (rd.IsS()) { 10668 Vnmla(cond, F32, rd.S(), rn.S(), rm.S()); 10669 } else { 10670 Vnmla(cond, F64, rd.D(), rn.D(), rm.D()); 10671 } 10672 } 10673 void Vnmla(VRegister rd, VRegister rn, VRegister rm) { 10674 Vnmla(al, rd, rn, rm); 10675 } 10676 void Vnmls(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10677 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10678 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10679 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10680 if (rd.IsS()) { 10681 Vnmls(cond, F32, rd.S(), rn.S(), rm.S()); 10682 } else { 10683 Vnmls(cond, F64, rd.D(), rn.D(), rm.D()); 10684 } 10685 } 10686 void Vnmls(VRegister rd, VRegister rn, VRegister rm) { 10687 Vnmls(al, rd, rn, rm); 10688 } 10689 void Vnmul(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10690 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10691 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10692 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10693 if (rd.IsS()) { 10694 Vnmul(cond, F32, rd.S(), rn.S(), rm.S()); 10695 } else { 10696 Vnmul(cond, F64, rd.D(), rn.D(), rm.D()); 10697 } 10698 } 10699 void Vnmul(VRegister rd, VRegister rn, VRegister rm) { 10700 Vnmul(al, rd, rn, rm); 10701 } 10702 void Vseleq(VRegister rd, VRegister rn, VRegister rm) { 10703 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10704 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10705 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10706 if (rd.IsS()) { 10707 Vseleq(F32, rd.S(), rn.S(), rm.S()); 10708 } else { 10709 Vseleq(F64, rd.D(), rn.D(), rm.D()); 10710 } 10711 } 10712 void Vselge(VRegister rd, VRegister rn, VRegister rm) { 10713 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10714 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10715 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10716 if (rd.IsS()) { 10717 Vselge(F32, rd.S(), rn.S(), rm.S()); 10718 } else { 10719 Vselge(F64, rd.D(), rn.D(), rm.D()); 10720 } 10721 } 10722 void Vselgt(VRegister rd, VRegister rn, VRegister rm) { 10723 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10724 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10725 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10726 if (rd.IsS()) { 10727 Vselgt(F32, rd.S(), rn.S(), rm.S()); 10728 } else { 10729 Vselgt(F64, rd.D(), rn.D(), rm.D()); 10730 } 10731 } 10732 void Vselvs(VRegister rd, VRegister rn, VRegister rm) { 10733 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10734 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10735 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10736 if (rd.IsS()) { 10737 Vselvs(F32, rd.S(), rn.S(), rm.S()); 10738 } else { 10739 Vselvs(F64, rd.D(), rn.D(), rm.D()); 10740 } 10741 } 10742 void Vsqrt(Condition cond, VRegister rd, VRegister rm) { 10743 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10744 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10745 if (rd.IsS()) { 10746 Vsqrt(cond, F32, rd.S(), rm.S()); 10747 } else { 10748 Vsqrt(cond, F64, rd.D(), rm.D()); 10749 } 10750 } 10751 void Vsqrt(VRegister rd, VRegister rm) { Vsqrt(al, rd, rm); } 10752 void Vsub(Condition cond, VRegister rd, VRegister rn, VRegister rm) { 10753 VIXL_ASSERT(rd.IsS() || rd.IsD()); 10754 VIXL_ASSERT(rd.GetType() == rn.GetType()); 10755 VIXL_ASSERT(rd.GetType() == rm.GetType()); 10756 if (rd.IsS()) { 10757 Vsub(cond, F32, rd.S(), rn.S(), rm.S()); 10758 } else { 10759 Vsub(cond, F64, rd.D(), rn.D(), rm.D()); 10760 } 10761 } 10762 void Vsub(VRegister rd, VRegister rn, VRegister rm) { Vsub(al, rd, rn, rm); } 10763 // End of generated code. 10764 10765 virtual bool AllowUnpredictable() VIXL_OVERRIDE { 10766 VIXL_ABORT_WITH_MSG("Unpredictable instruction.\n"); 10767 return false; 10768 } 10769 virtual bool AllowStronglyDiscouraged() VIXL_OVERRIDE { 10770 VIXL_ABORT_WITH_MSG( 10771 "ARM strongly recommends to not use this instruction.\n"); 10772 return false; 10773 } 10774 10775 private: 10776 bool NeedBranch(Condition* cond) { return !cond->Is(al) && IsUsingT32(); } 10777 static const int kBranchSize = kMaxInstructionSizeInBytes; 10778 10779 RegisterList available_; 10780 VRegisterList available_vfp_; 10781 UseScratchRegisterScope* current_scratch_scope_; 10782 MacroAssemblerContext context_; 10783 PoolManager<int32_t> pool_manager_; 10784 bool generate_simulator_code_; 10785 bool allow_macro_instructions_; 10786 Label* pool_end_; 10787 10788 friend class TestMacroAssembler; 10789 }; 10790 10791 // This scope utility allows scratch registers to be managed safely. The 10792 // MacroAssembler's GetScratchRegisterList() is used as a pool of scratch 10793 // registers. These registers can be allocated on demand, and will be returned 10794 // at the end of the scope. 10795 // 10796 // When the scope ends, the MacroAssembler's lists will be restored to their 10797 // original state, even if the lists were modified by some other means. 10798 // 10799 // Scopes must nest perfectly. That is, they must be destructed in reverse 10800 // construction order. Otherwise, it is not clear how to handle cases where one 10801 // scope acquires a register that was included in a now-closing scope. With 10802 // perfect nesting, this cannot occur. 10803 class UseScratchRegisterScope { 10804 public: 10805 // This constructor implicitly calls the `Open` function to initialise the 10806 // scope, so it is ready to use immediately after it has been constructed. 10807 explicit UseScratchRegisterScope(MacroAssembler* masm) 10808 : masm_(NULL), parent_(NULL), old_available_(0), old_available_vfp_(0) { 10809 Open(masm); 10810 } 10811 // This constructor allows deferred and optional initialisation of the scope. 10812 // The user is required to explicitly call the `Open` function before using 10813 // the scope. 10814 UseScratchRegisterScope() 10815 : masm_(NULL), parent_(NULL), old_available_(0), old_available_vfp_(0) {} 10816 10817 // This function performs the actual initialisation work. 10818 void Open(MacroAssembler* masm); 10819 10820 // The destructor always implicitly calls the `Close` function. 10821 ~UseScratchRegisterScope() { Close(); } 10822 10823 // This function performs the cleaning-up work. It must succeed even if the 10824 // scope has not been opened. It is safe to call multiple times. 10825 void Close(); 10826 10827 bool IsAvailable(const Register& reg) const; 10828 bool IsAvailable(const VRegister& reg) const; 10829 10830 // Take a register from the temp list. It will be returned automatically when 10831 // the scope ends. 10832 Register Acquire(); 10833 VRegister AcquireV(unsigned size_in_bits); 10834 QRegister AcquireQ(); 10835 DRegister AcquireD(); 10836 SRegister AcquireS(); 10837 10838 // Explicitly release an acquired (or excluded) register, putting it back in 10839 // the temp list. 10840 void Release(const Register& reg); 10841 void Release(const VRegister& reg); 10842 10843 // Make the specified registers available as scratch registers for the 10844 // duration of this scope. 10845 void Include(const RegisterList& list); 10846 void Include(const Register& reg1, 10847 const Register& reg2 = NoReg, 10848 const Register& reg3 = NoReg, 10849 const Register& reg4 = NoReg) { 10850 Include(RegisterList(reg1, reg2, reg3, reg4)); 10851 } 10852 void Include(const VRegisterList& list); 10853 void Include(const VRegister& reg1, 10854 const VRegister& reg2 = NoVReg, 10855 const VRegister& reg3 = NoVReg, 10856 const VRegister& reg4 = NoVReg) { 10857 Include(VRegisterList(reg1, reg2, reg3, reg4)); 10858 } 10859 10860 // Make sure that the specified registers are not available in this scope. 10861 // This can be used to prevent helper functions from using sensitive 10862 // registers, for example. 10863 void Exclude(const RegisterList& list); 10864 void Exclude(const Register& reg1, 10865 const Register& reg2 = NoReg, 10866 const Register& reg3 = NoReg, 10867 const Register& reg4 = NoReg) { 10868 Exclude(RegisterList(reg1, reg2, reg3, reg4)); 10869 } 10870 void Exclude(const VRegisterList& list); 10871 void Exclude(const VRegister& reg1, 10872 const VRegister& reg2 = NoVReg, 10873 const VRegister& reg3 = NoVReg, 10874 const VRegister& reg4 = NoVReg) { 10875 Exclude(VRegisterList(reg1, reg2, reg3, reg4)); 10876 } 10877 10878 // A convenience helper to exclude any registers used by the operand. 10879 void Exclude(const Operand& operand); 10880 10881 // Prevent any scratch registers from being used in this scope. 10882 void ExcludeAll(); 10883 10884 private: 10885 // The MacroAssembler maintains a list of available scratch registers, and 10886 // also keeps track of the most recently-opened scope so that on destruction 10887 // we can check that scopes do not outlive their parents. 10888 MacroAssembler* masm_; 10889 UseScratchRegisterScope* parent_; 10890 10891 // The state of the available lists at the start of this scope. 10892 uint32_t old_available_; // kRRegister 10893 uint64_t old_available_vfp_; // kVRegister 10894 10895 VIXL_DEBUG_NO_RETURN UseScratchRegisterScope(const UseScratchRegisterScope&) { 10896 VIXL_UNREACHABLE(); 10897 } 10898 VIXL_DEBUG_NO_RETURN void operator=(const UseScratchRegisterScope&) { 10899 VIXL_UNREACHABLE(); 10900 } 10901 }; 10902 10903 10904 } // namespace aarch32 10905 } // namespace vixl 10906 10907 #endif // VIXL_AARCH32_MACRO_ASSEMBLER_AARCH32_H_ 10908
