1 // Copyright 2017, VIXL authors 2 // All rights reserved. 3 // 4 // Redistribution and use in source and binary forms, with or without 5 // modification, are permitted provided that the following conditions are met: 6 // 7 // * Redistributions of source code must retain the above copyright notice, 8 // this list of conditions and the following disclaimer. 9 // * Redistributions in binary form must reproduce the above copyright notice, 10 // this list of conditions and the following disclaimer in the documentation 11 // and/or other materials provided with the distribution. 12 // * Neither the name of ARM Limited nor the names of its contributors may be 13 // used to endorse or promote products derived from this software without 14 // specific prior written permission. 15 // 16 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND 17 // ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 // WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 // DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE 20 // FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 // DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 // SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 23 // CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 24 // OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 27 #ifndef VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 28 #define VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 29 30 #include "assembler-base-vixl.h" 31 32 #include "aarch32/instructions-aarch32.h" 33 #include "aarch32/location-aarch32.h" 34 35 namespace vixl { 36 namespace aarch32 { 37 38 class Assembler : public internal::AssemblerBase { 39 InstructionSet isa_; 40 Condition first_condition_; 41 uint16_t it_mask_; 42 bool has_32_dregs_; 43 bool allow_unpredictable_; 44 bool allow_strongly_discouraged_; 45 46 protected: 47 void EmitT32_16(uint16_t instr); 48 void EmitT32_32(uint32_t instr); 49 void EmitA32(uint32_t instr); 50 // Check that the condition of the current instruction is consistent with the 51 // IT state. 52 void CheckIT(Condition condition) { 53 #ifdef VIXL_DEBUG 54 PerformCheckIT(condition); 55 #else 56 USE(condition); 57 #endif 58 } 59 #ifdef VIXL_DEBUG 60 void PerformCheckIT(Condition condition); 61 #endif 62 void AdvanceIT() { 63 first_condition_ = 64 Condition((first_condition_.GetCondition() & 0xe) | (it_mask_ >> 3)); 65 it_mask_ = (it_mask_ << 1) & 0xf; 66 } 67 // Virtual, in order to be overridden by the MacroAssembler, which needs to 68 // notify the pool manager. 69 virtual void BindHelper(Label* label); 70 71 uint32_t Link(uint32_t instr, 72 Location* location, 73 const Location::EmitOperator& op, 74 const ReferenceInfo* info); 75 76 public: 77 class AllowUnpredictableScope { 78 Assembler* assembler_; 79 bool old_; 80 81 public: 82 explicit AllowUnpredictableScope(Assembler* assembler) 83 : assembler_(assembler), old_(assembler->allow_unpredictable_) { 84 assembler_->allow_unpredictable_ = true; 85 } 86 ~AllowUnpredictableScope() { assembler_->allow_unpredictable_ = old_; } 87 }; 88 class AllowStronglyDiscouragedScope { 89 Assembler* assembler_; 90 bool old_; 91 92 public: 93 explicit AllowStronglyDiscouragedScope(Assembler* assembler) 94 : assembler_(assembler), old_(assembler->allow_strongly_discouraged_) { 95 assembler_->allow_strongly_discouraged_ = true; 96 } 97 ~AllowStronglyDiscouragedScope() { 98 assembler_->allow_strongly_discouraged_ = old_; 99 } 100 }; 101 102 explicit Assembler(InstructionSet isa = kDefaultISA) 103 : isa_(isa), 104 first_condition_(al), 105 it_mask_(0), 106 has_32_dregs_(true), 107 allow_unpredictable_(false), 108 allow_strongly_discouraged_(false) { 109 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 110 // Avoid compiler warning. 111 USE(isa_); 112 VIXL_ASSERT(isa == A32); 113 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 114 USE(isa_); 115 VIXL_ASSERT(isa == T32); 116 #endif 117 } 118 explicit Assembler(size_t capacity, InstructionSet isa = kDefaultISA) 119 : AssemblerBase(capacity), 120 isa_(isa), 121 first_condition_(al), 122 it_mask_(0), 123 has_32_dregs_(true), 124 allow_unpredictable_(false), 125 allow_strongly_discouraged_(false) { 126 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 127 VIXL_ASSERT(isa == A32); 128 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 129 VIXL_ASSERT(isa == T32); 130 #endif 131 } 132 Assembler(byte* buffer, size_t capacity, InstructionSet isa = kDefaultISA) 133 : AssemblerBase(buffer, capacity), 134 isa_(isa), 135 first_condition_(al), 136 it_mask_(0), 137 has_32_dregs_(true), 138 allow_unpredictable_(false), 139 allow_strongly_discouraged_(false) { 140 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 141 VIXL_ASSERT(isa == A32); 142 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 143 VIXL_ASSERT(isa == T32); 144 #endif 145 } 146 virtual ~Assembler() {} 147 148 void UseInstructionSet(InstructionSet isa) { 149 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 150 USE(isa); 151 VIXL_ASSERT(isa == A32); 152 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 153 USE(isa); 154 VIXL_ASSERT(isa == T32); 155 #else 156 VIXL_ASSERT((isa_ == isa) || (GetCursorOffset() == 0)); 157 isa_ = isa; 158 #endif 159 } 160 161 #if defined(VIXL_INCLUDE_TARGET_A32_ONLY) 162 InstructionSet GetInstructionSetInUse() const { return A32; } 163 #elif defined(VIXL_INCLUDE_TARGET_T32_ONLY) 164 InstructionSet GetInstructionSetInUse() const { return T32; } 165 #else 166 InstructionSet GetInstructionSetInUse() const { return isa_; } 167 #endif 168 169 void UseT32() { UseInstructionSet(T32); } 170 void UseA32() { UseInstructionSet(A32); } 171 bool IsUsingT32() const { return GetInstructionSetInUse() == T32; } 172 bool IsUsingA32() const { return GetInstructionSetInUse() == A32; } 173 174 void SetIT(Condition first_condition, uint16_t it_mask) { 175 VIXL_ASSERT(it_mask_ == 0); 176 first_condition_ = first_condition; 177 it_mask_ = it_mask; 178 } 179 bool InITBlock() { return it_mask_ != 0; } 180 bool OutsideITBlock() { return it_mask_ == 0; } 181 bool OutsideITBlockOrLast() { return (it_mask_ == 0) || (it_mask_ == 0x8); } 182 bool OutsideITBlockAndAlOrLast(Condition cond) { 183 return ((it_mask_ == 0) && cond.Is(al)) || (it_mask_ == 0x8); 184 } 185 void CheckNotIT() { VIXL_ASSERT(it_mask_ == 0); } 186 bool Has32DRegs() const { return has_32_dregs_; } 187 void SetHas32DRegs(bool has_32_dregs) { has_32_dregs_ = has_32_dregs; } 188 189 int32_t GetCursorOffset() const { 190 ptrdiff_t offset = buffer_.GetCursorOffset(); 191 VIXL_ASSERT(IsInt32(offset)); 192 return static_cast<int32_t>(offset); 193 } 194 195 uint32_t GetArchitectureStatePCOffset() const { return IsUsingT32() ? 4 : 8; } 196 197 // Bind a raw Location that will never be tracked by the pool manager. 198 void bind(Location* location) { 199 VIXL_ASSERT(AllowAssembler()); 200 VIXL_ASSERT(!location->IsBound()); 201 location->SetLocation(this, GetCursorOffset()); 202 location->MarkBound(); 203 } 204 205 // Bind a Label, which may be tracked by the pool manager in the presence of a 206 // MacroAssembler. 207 void bind(Label* label) { 208 VIXL_ASSERT(AllowAssembler()); 209 BindHelper(label); 210 } 211 212 void place(RawLiteral* literal) { 213 VIXL_ASSERT(AllowAssembler()); 214 VIXL_ASSERT(literal->IsManuallyPlaced()); 215 literal->SetLocation(this, GetCursorOffset()); 216 literal->MarkBound(); 217 GetBuffer()->EnsureSpaceFor(literal->GetSize()); 218 GetBuffer()->EmitData(literal->GetDataAddress(), literal->GetSize()); 219 } 220 221 size_t GetSizeOfCodeGeneratedSince(Label* label) const { 222 VIXL_ASSERT(label->IsBound()); 223 return buffer_.GetOffsetFrom(label->GetLocation()); 224 } 225 226 // Helpers for it instruction. 227 void it(Condition cond) { it(cond, 0x8); } 228 void itt(Condition cond) { it(cond, 0x4); } 229 void ite(Condition cond) { it(cond, 0xc); } 230 void ittt(Condition cond) { it(cond, 0x2); } 231 void itet(Condition cond) { it(cond, 0xa); } 232 void itte(Condition cond) { it(cond, 0x6); } 233 void itee(Condition cond) { it(cond, 0xe); } 234 void itttt(Condition cond) { it(cond, 0x1); } 235 void itett(Condition cond) { it(cond, 0x9); } 236 void ittet(Condition cond) { it(cond, 0x5); } 237 void iteet(Condition cond) { it(cond, 0xd); } 238 void ittte(Condition cond) { it(cond, 0x3); } 239 void itete(Condition cond) { it(cond, 0xb); } 240 void ittee(Condition cond) { it(cond, 0x7); } 241 void iteee(Condition cond) { it(cond, 0xf); } 242 243 // Start of generated code. 244 typedef void (Assembler::*InstructionCondSizeRROp)(Condition cond, 245 EncodingSize size, 246 Register rd, 247 Register rn, 248 const Operand& operand); 249 typedef void (Assembler::*InstructionCondROp)(Condition cond, 250 Register rd, 251 const Operand& operand); 252 typedef void (Assembler::*InstructionROp)(Register rd, 253 const Operand& operand); 254 typedef void (Assembler::*InstructionCondRROp)(Condition cond, 255 Register rd, 256 Register rn, 257 const Operand& operand); 258 typedef void (Assembler::*InstructionCondSizeRL)(Condition cond, 259 EncodingSize size, 260 Register rd, 261 Location* location); 262 typedef void (Assembler::*InstructionCondSizeL)(Condition cond, 263 EncodingSize size, 264 Location* location); 265 typedef void (Assembler::*InstructionCondRII)(Condition cond, 266 Register rd, 267 uint32_t lsb, 268 uint32_t width); 269 typedef void (Assembler::*InstructionCondRRII)( 270 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 271 typedef void (Assembler::*InstructionCondI)(Condition cond, uint32_t imm); 272 typedef void (Assembler::*InstructionCondL)(Condition cond, 273 Location* location); 274 typedef void (Assembler::*InstructionCondR)(Condition cond, Register rm); 275 typedef void (Assembler::*InstructionRL)(Register rn, Location* location); 276 typedef void (Assembler::*InstructionCond)(Condition cond); 277 typedef void (Assembler::*InstructionCondRR)(Condition cond, 278 Register rd, 279 Register rm); 280 typedef void (Assembler::*InstructionCondSizeROp)(Condition cond, 281 EncodingSize size, 282 Register rn, 283 const Operand& operand); 284 typedef void (Assembler::*InstructionCondRRR)(Condition cond, 285 Register rd, 286 Register rn, 287 Register rm); 288 typedef void (Assembler::*InstructionCondBa)(Condition cond, 289 MemoryBarrier option); 290 typedef void (Assembler::*InstructionCondRwbDrl)(Condition cond, 291 Register rn, 292 WriteBack write_back, 293 DRegisterList dreglist); 294 typedef void (Assembler::*InstructionCondRMop)(Condition cond, 295 Register rt, 296 const MemOperand& operand); 297 typedef void (Assembler::*InstructionCondRRMop)(Condition cond, 298 Register rt, 299 Register rt2, 300 const MemOperand& operand); 301 typedef void (Assembler::*InstructionCondSizeRwbRl)(Condition cond, 302 EncodingSize size, 303 Register rn, 304 WriteBack write_back, 305 RegisterList registers); 306 typedef void (Assembler::*InstructionCondRwbRl)(Condition cond, 307 Register rn, 308 WriteBack write_back, 309 RegisterList registers); 310 typedef void (Assembler::*InstructionCondSizeRMop)(Condition cond, 311 EncodingSize size, 312 Register rt, 313 const MemOperand& operand); 314 typedef void (Assembler::*InstructionCondRL)(Condition cond, 315 Register rt, 316 Location* location); 317 typedef void (Assembler::*InstructionCondRRL)(Condition cond, 318 Register rt, 319 Register rt2, 320 Location* location); 321 typedef void (Assembler::*InstructionCondRRRR)( 322 Condition cond, Register rd, Register rn, Register rm, Register ra); 323 typedef void (Assembler::*InstructionCondRSr)(Condition cond, 324 Register rd, 325 SpecialRegister spec_reg); 326 typedef void (Assembler::*InstructionCondMsrOp)( 327 Condition cond, MaskedSpecialRegister spec_reg, const Operand& operand); 328 typedef void (Assembler::*InstructionCondSizeRRR)( 329 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 330 typedef void (Assembler::*InstructionCondSize)(Condition cond, 331 EncodingSize size); 332 typedef void (Assembler::*InstructionCondMop)(Condition cond, 333 const MemOperand& operand); 334 typedef void (Assembler::*InstructionCondSizeRl)(Condition cond, 335 EncodingSize size, 336 RegisterList registers); 337 typedef void (Assembler::*InstructionCondSizeOrl)(Condition cond, 338 EncodingSize size, 339 Register rt); 340 typedef void (Assembler::*InstructionCondSizeRR)(Condition cond, 341 EncodingSize size, 342 Register rd, 343 Register rm); 344 typedef void (Assembler::*InstructionDtQQQ)(DataType dt, 345 QRegister rd, 346 QRegister rn, 347 QRegister rm); 348 typedef void (Assembler::*InstructionCondRIOp)(Condition cond, 349 Register rd, 350 uint32_t imm, 351 const Operand& operand); 352 typedef void (Assembler::*InstructionCondRIR)(Condition cond, 353 Register rd, 354 uint32_t imm, 355 Register rn); 356 typedef void (Assembler::*InstructionCondRRRMop)(Condition cond, 357 Register rd, 358 Register rt, 359 Register rt2, 360 const MemOperand& operand); 361 typedef void (Assembler::*InstructionCondSizeI)(Condition cond, 362 EncodingSize size, 363 uint32_t imm); 364 typedef void (Assembler::*InstructionCondDtDDD)( 365 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 366 typedef void (Assembler::*InstructionCondDtQQQ)( 367 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 368 typedef void (Assembler::*InstructionCondDtQDD)( 369 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 370 typedef void (Assembler::*InstructionCondDtDD)(Condition cond, 371 DataType dt, 372 DRegister rd, 373 DRegister rm); 374 typedef void (Assembler::*InstructionCondDtQQ)(Condition cond, 375 DataType dt, 376 QRegister rd, 377 QRegister rm); 378 typedef void (Assembler::*InstructionCondDtSS)(Condition cond, 379 DataType dt, 380 SRegister rd, 381 SRegister rm); 382 typedef void (Assembler::*InstructionCondDtSSS)( 383 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 384 typedef void (Assembler::*InstructionCondDtDQQ)( 385 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 386 typedef void (Assembler::*InstructionCondDtQQD)( 387 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 388 typedef void (Assembler::*InstructionCondDtDDDop)(Condition cond, 389 DataType dt, 390 DRegister rd, 391 DRegister rn, 392 const DOperand& operand); 393 typedef void (Assembler::*InstructionCondDtQQQop)(Condition cond, 394 DataType dt, 395 QRegister rd, 396 QRegister rn, 397 const QOperand& operand); 398 typedef void (Assembler::*InstructionCondDtSSop)(Condition cond, 399 DataType dt, 400 SRegister rd, 401 const SOperand& operand); 402 typedef void (Assembler::*InstructionCondDtDDop)(Condition cond, 403 DataType dt, 404 DRegister rd, 405 const DOperand& operand); 406 typedef void (Assembler::*InstructionCondDtDtDS)( 407 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 408 typedef void (Assembler::*InstructionCondDtDtSD)( 409 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 410 typedef void (Assembler::*InstructionCondDtDtDDSi)(Condition cond, 411 DataType dt1, 412 DataType dt2, 413 DRegister rd, 414 DRegister rm, 415 int32_t fbits); 416 typedef void (Assembler::*InstructionCondDtDtQQSi)(Condition cond, 417 DataType dt1, 418 DataType dt2, 419 QRegister rd, 420 QRegister rm, 421 int32_t fbits); 422 typedef void (Assembler::*InstructionCondDtDtSSSi)(Condition cond, 423 DataType dt1, 424 DataType dt2, 425 SRegister rd, 426 SRegister rm, 427 int32_t fbits); 428 typedef void (Assembler::*InstructionCondDtDtDD)( 429 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 430 typedef void (Assembler::*InstructionCondDtDtQQ)( 431 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 432 typedef void (Assembler::*InstructionCondDtDtDQ)( 433 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 434 typedef void (Assembler::*InstructionCondDtDtQD)( 435 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 436 typedef void (Assembler::*InstructionCondDtDtSS)( 437 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 438 typedef void (Assembler::*InstructionDtDtDD)(DataType dt1, 439 DataType dt2, 440 DRegister rd, 441 DRegister rm); 442 typedef void (Assembler::*InstructionDtDtQQ)(DataType dt1, 443 DataType dt2, 444 QRegister rd, 445 QRegister rm); 446 typedef void (Assembler::*InstructionDtDtSS)(DataType dt1, 447 DataType dt2, 448 SRegister rd, 449 SRegister rm); 450 typedef void (Assembler::*InstructionDtDtSD)(DataType dt1, 451 DataType dt2, 452 SRegister rd, 453 DRegister rm); 454 typedef void (Assembler::*InstructionCondDtQR)(Condition cond, 455 DataType dt, 456 QRegister rd, 457 Register rt); 458 typedef void (Assembler::*InstructionCondDtDR)(Condition cond, 459 DataType dt, 460 DRegister rd, 461 Register rt); 462 typedef void (Assembler::*InstructionCondDtDDx)(Condition cond, 463 DataType dt, 464 DRegister rd, 465 DRegisterLane rm); 466 typedef void (Assembler::*InstructionCondDtQDx)(Condition cond, 467 DataType dt, 468 QRegister rd, 469 DRegisterLane rm); 470 typedef void (Assembler::*InstructionCondDtDDDDop)(Condition cond, 471 DataType dt, 472 DRegister rd, 473 DRegister rn, 474 DRegister rm, 475 const DOperand& operand); 476 typedef void (Assembler::*InstructionCondDtQQQQop)(Condition cond, 477 DataType dt, 478 QRegister rd, 479 QRegister rn, 480 QRegister rm, 481 const QOperand& operand); 482 typedef void (Assembler::*InstructionCondDtNrlAmop)( 483 Condition cond, 484 DataType dt, 485 const NeonRegisterList& nreglist, 486 const AlignedMemOperand& operand); 487 typedef void (Assembler::*InstructionCondDtNrlMop)( 488 Condition cond, 489 DataType dt, 490 const NeonRegisterList& nreglist, 491 const MemOperand& operand); 492 typedef void (Assembler::*InstructionCondDtRwbDrl)(Condition cond, 493 DataType dt, 494 Register rn, 495 WriteBack write_back, 496 DRegisterList dreglist); 497 typedef void (Assembler::*InstructionCondDtRwbSrl)(Condition cond, 498 DataType dt, 499 Register rn, 500 WriteBack write_back, 501 SRegisterList sreglist); 502 typedef void (Assembler::*InstructionCondDtDL)(Condition cond, 503 DataType dt, 504 DRegister rd, 505 Location* location); 506 typedef void (Assembler::*InstructionCondDtDMop)(Condition cond, 507 DataType dt, 508 DRegister rd, 509 const MemOperand& operand); 510 typedef void (Assembler::*InstructionCondDtSL)(Condition cond, 511 DataType dt, 512 SRegister rd, 513 Location* location); 514 typedef void (Assembler::*InstructionCondDtSMop)(Condition cond, 515 DataType dt, 516 SRegister rd, 517 const MemOperand& operand); 518 typedef void (Assembler::*InstructionDtDDD)(DataType dt, 519 DRegister rd, 520 DRegister rn, 521 DRegister rm); 522 typedef void (Assembler::*InstructionDtSSS)(DataType dt, 523 SRegister rd, 524 SRegister rn, 525 SRegister rm); 526 typedef void (Assembler::*InstructionCondDtDDDx)(Condition cond, 527 DataType dt, 528 DRegister rd, 529 DRegister rn, 530 DRegisterLane rm); 531 typedef void (Assembler::*InstructionCondDtQQDx)(Condition cond, 532 DataType dt, 533 QRegister rd, 534 QRegister rn, 535 DRegisterLane rm); 536 typedef void (Assembler::*InstructionCondDtQDDx)(Condition cond, 537 DataType dt, 538 QRegister rd, 539 DRegister rn, 540 DRegisterLane rm); 541 typedef void (Assembler::*InstructionCondRS)(Condition cond, 542 Register rt, 543 SRegister rn); 544 typedef void (Assembler::*InstructionCondSR)(Condition cond, 545 SRegister rn, 546 Register rt); 547 typedef void (Assembler::*InstructionCondRRD)(Condition cond, 548 Register rt, 549 Register rt2, 550 DRegister rm); 551 typedef void (Assembler::*InstructionCondDRR)(Condition cond, 552 DRegister rm, 553 Register rt, 554 Register rt2); 555 typedef void (Assembler::*InstructionCondRRSS)( 556 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 557 typedef void (Assembler::*InstructionCondSSRR)( 558 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 559 typedef void (Assembler::*InstructionCondDtDxR)(Condition cond, 560 DataType dt, 561 DRegisterLane rd, 562 Register rt); 563 typedef void (Assembler::*InstructionCondDtQQop)(Condition cond, 564 DataType dt, 565 QRegister rd, 566 const QOperand& operand); 567 typedef void (Assembler::*InstructionCondDtRDx)(Condition cond, 568 DataType dt, 569 Register rt, 570 DRegisterLane rn); 571 typedef void (Assembler::*InstructionCondDtQD)(Condition cond, 572 DataType dt, 573 QRegister rd, 574 DRegister rm); 575 typedef void (Assembler::*InstructionCondDtDQ)(Condition cond, 576 DataType dt, 577 DRegister rd, 578 QRegister rm); 579 typedef void (Assembler::*InstructionCondRoaSfp)(Condition cond, 580 RegisterOrAPSR_nzcv rt, 581 SpecialFPRegister spec_reg); 582 typedef void (Assembler::*InstructionCondSfpR)(Condition cond, 583 SpecialFPRegister spec_reg, 584 Register rt); 585 typedef void (Assembler::*InstructionCondDtDDIr)(Condition cond, 586 DataType dt, 587 DRegister rd, 588 DRegister rn, 589 DRegister dm, 590 unsigned index); 591 typedef void (Assembler::*InstructionCondDtQQIr)(Condition cond, 592 DataType dt, 593 QRegister rd, 594 QRegister rn, 595 DRegister dm, 596 unsigned index); 597 typedef void (Assembler::*InstructionCondDtQDIr)(Condition cond, 598 DataType dt, 599 QRegister rd, 600 DRegister rn, 601 DRegister dm, 602 unsigned index); 603 typedef void (Assembler::*InstructionCondDtDrl)(Condition cond, 604 DataType dt, 605 DRegisterList dreglist); 606 typedef void (Assembler::*InstructionCondDtSrl)(Condition cond, 607 DataType dt, 608 SRegisterList sreglist); 609 typedef void (Assembler::*InstructionCondDtDQQop)(Condition cond, 610 DataType dt, 611 DRegister rd, 612 QRegister rm, 613 const QOperand& operand); 614 typedef void (Assembler::*InstructionCondDtQDDop)(Condition cond, 615 DataType dt, 616 QRegister rd, 617 DRegister rm, 618 const DOperand& operand); 619 typedef void (Assembler::*InstructionCondDtDNrlD)( 620 Condition cond, 621 DataType dt, 622 DRegister rd, 623 const NeonRegisterList& nreglist, 624 DRegister rm); 625 virtual void Delegate(InstructionType type, 626 InstructionCondSizeRROp /*instruction*/, 627 Condition /*cond*/, 628 EncodingSize /*size*/, 629 Register /*rd*/, 630 Register /*rn*/, 631 const Operand& /*operand*/) { 632 USE(type); 633 VIXL_ASSERT((type == kAdc) || (type == kAdcs) || (type == kAdd) || 634 (type == kAdds) || (type == kAnd) || (type == kAnds) || 635 (type == kAsr) || (type == kAsrs) || (type == kBic) || 636 (type == kBics) || (type == kEor) || (type == kEors) || 637 (type == kLsl) || (type == kLsls) || (type == kLsr) || 638 (type == kLsrs) || (type == kOrr) || (type == kOrrs) || 639 (type == kRor) || (type == kRors) || (type == kRsb) || 640 (type == kRsbs) || (type == kSbc) || (type == kSbcs) || 641 (type == kSub) || (type == kSubs)); 642 UnimplementedDelegate(type); 643 } 644 virtual void Delegate(InstructionType type, 645 InstructionCondROp /*instruction*/, 646 Condition /*cond*/, 647 Register /*rd*/, 648 const Operand& /*operand*/) { 649 USE(type); 650 VIXL_ASSERT((type == kAdd) || (type == kMovt) || (type == kMovw) || 651 (type == kSub) || (type == kSxtb16) || (type == kTeq) || 652 (type == kUxtb16)); 653 UnimplementedDelegate(type); 654 } 655 virtual void Delegate(InstructionType type, 656 InstructionROp /*instruction*/, 657 Register /*rd*/, 658 const Operand& /*operand*/) { 659 USE(type); 660 VIXL_ASSERT((type == kAdds) || (type == kSubs)); 661 UnimplementedDelegate(type); 662 } 663 virtual void Delegate(InstructionType type, 664 InstructionCondRROp /*instruction*/, 665 Condition /*cond*/, 666 Register /*rd*/, 667 Register /*rn*/, 668 const Operand& /*operand*/) { 669 USE(type); 670 VIXL_ASSERT((type == kAddw) || (type == kOrn) || (type == kOrns) || 671 (type == kPkhbt) || (type == kPkhtb) || (type == kRsc) || 672 (type == kRscs) || (type == kSubw) || (type == kSxtab) || 673 (type == kSxtab16) || (type == kSxtah) || (type == kUxtab) || 674 (type == kUxtab16) || (type == kUxtah)); 675 UnimplementedDelegate(type); 676 } 677 virtual void Delegate(InstructionType type, 678 InstructionCondSizeRL /*instruction*/, 679 Condition /*cond*/, 680 EncodingSize /*size*/, 681 Register /*rd*/, 682 Location* /*location*/) { 683 USE(type); 684 VIXL_ASSERT((type == kAdr) || (type == kLdr)); 685 UnimplementedDelegate(type); 686 } 687 virtual void Delegate(InstructionType type, 688 InstructionCondSizeL /*instruction*/, 689 Condition /*cond*/, 690 EncodingSize /*size*/, 691 Location* /*location*/) { 692 USE(type); 693 VIXL_ASSERT((type == kB)); 694 UnimplementedDelegate(type); 695 } 696 virtual void Delegate(InstructionType type, 697 InstructionCondRII /*instruction*/, 698 Condition /*cond*/, 699 Register /*rd*/, 700 uint32_t /*lsb*/, 701 uint32_t /*width*/) { 702 USE(type); 703 VIXL_ASSERT((type == kBfc)); 704 UnimplementedDelegate(type); 705 } 706 virtual void Delegate(InstructionType type, 707 InstructionCondRRII /*instruction*/, 708 Condition /*cond*/, 709 Register /*rd*/, 710 Register /*rn*/, 711 uint32_t /*lsb*/, 712 uint32_t /*width*/) { 713 USE(type); 714 VIXL_ASSERT((type == kBfi) || (type == kSbfx) || (type == kUbfx)); 715 UnimplementedDelegate(type); 716 } 717 virtual void Delegate(InstructionType type, 718 InstructionCondI /*instruction*/, 719 Condition /*cond*/, 720 uint32_t /*imm*/) { 721 USE(type); 722 VIXL_ASSERT((type == kBkpt) || (type == kHlt) || (type == kHvc) || 723 (type == kSvc)); 724 UnimplementedDelegate(type); 725 } 726 virtual void Delegate(InstructionType type, 727 InstructionCondL /*instruction*/, 728 Condition /*cond*/, 729 Location* /*location*/) { 730 USE(type); 731 VIXL_ASSERT((type == kBl) || (type == kBlx) || (type == kPld) || 732 (type == kPli)); 733 UnimplementedDelegate(type); 734 } 735 virtual void Delegate(InstructionType type, 736 InstructionCondR /*instruction*/, 737 Condition /*cond*/, 738 Register /*rm*/) { 739 USE(type); 740 VIXL_ASSERT((type == kBlx) || (type == kBx) || (type == kBxj)); 741 UnimplementedDelegate(type); 742 } 743 virtual void Delegate(InstructionType type, 744 InstructionRL /*instruction*/, 745 Register /*rn*/, 746 Location* /*location*/) { 747 USE(type); 748 VIXL_ASSERT((type == kCbnz) || (type == kCbz)); 749 UnimplementedDelegate(type); 750 } 751 virtual void Delegate(InstructionType type, 752 InstructionCond /*instruction*/, 753 Condition /*cond*/) { 754 USE(type); 755 VIXL_ASSERT((type == kClrex)); 756 UnimplementedDelegate(type); 757 } 758 virtual void Delegate(InstructionType type, 759 InstructionCondRR /*instruction*/, 760 Condition /*cond*/, 761 Register /*rd*/, 762 Register /*rm*/) { 763 USE(type); 764 VIXL_ASSERT((type == kClz) || (type == kRbit) || (type == kRrx) || 765 (type == kRrxs)); 766 UnimplementedDelegate(type); 767 } 768 virtual void Delegate(InstructionType type, 769 InstructionCondSizeROp /*instruction*/, 770 Condition /*cond*/, 771 EncodingSize /*size*/, 772 Register /*rn*/, 773 const Operand& /*operand*/) { 774 USE(type); 775 VIXL_ASSERT((type == kCmn) || (type == kCmp) || (type == kMov) || 776 (type == kMovs) || (type == kMvn) || (type == kMvns) || 777 (type == kSxtb) || (type == kSxth) || (type == kTst) || 778 (type == kUxtb) || (type == kUxth)); 779 UnimplementedDelegate(type); 780 } 781 virtual void Delegate(InstructionType type, 782 InstructionCondRRR /*instruction*/, 783 Condition /*cond*/, 784 Register /*rd*/, 785 Register /*rn*/, 786 Register /*rm*/) { 787 USE(type); 788 VIXL_ASSERT((type == kCrc32b) || (type == kCrc32cb) || (type == kCrc32ch) || 789 (type == kCrc32cw) || (type == kCrc32h) || (type == kCrc32w) || 790 (type == kMuls) || (type == kQadd) || (type == kQadd16) || 791 (type == kQadd8) || (type == kQasx) || (type == kQdadd) || 792 (type == kQdsub) || (type == kQsax) || (type == kQsub) || 793 (type == kQsub16) || (type == kQsub8) || (type == kSadd16) || 794 (type == kSadd8) || (type == kSasx) || (type == kSdiv) || 795 (type == kSel) || (type == kShadd16) || (type == kShadd8) || 796 (type == kShasx) || (type == kShsax) || (type == kShsub16) || 797 (type == kShsub8) || (type == kSmmul) || (type == kSmmulr) || 798 (type == kSmuad) || (type == kSmuadx) || (type == kSmulbb) || 799 (type == kSmulbt) || (type == kSmultb) || (type == kSmultt) || 800 (type == kSmulwb) || (type == kSmulwt) || (type == kSmusd) || 801 (type == kSmusdx) || (type == kSsax) || (type == kSsub16) || 802 (type == kSsub8) || (type == kUadd16) || (type == kUadd8) || 803 (type == kUasx) || (type == kUdiv) || (type == kUhadd16) || 804 (type == kUhadd8) || (type == kUhasx) || (type == kUhsax) || 805 (type == kUhsub16) || (type == kUhsub8) || (type == kUqadd16) || 806 (type == kUqadd8) || (type == kUqasx) || (type == kUqsax) || 807 (type == kUqsub16) || (type == kUqsub8) || (type == kUsad8) || 808 (type == kUsax) || (type == kUsub16) || (type == kUsub8)); 809 UnimplementedDelegate(type); 810 } 811 virtual void Delegate(InstructionType type, 812 InstructionCondBa /*instruction*/, 813 Condition /*cond*/, 814 MemoryBarrier /*option*/) { 815 USE(type); 816 VIXL_ASSERT((type == kDmb) || (type == kDsb) || (type == kIsb)); 817 UnimplementedDelegate(type); 818 } 819 virtual void Delegate(InstructionType type, 820 InstructionCondRwbDrl /*instruction*/, 821 Condition /*cond*/, 822 Register /*rn*/, 823 WriteBack /*write_back*/, 824 DRegisterList /*dreglist*/) { 825 USE(type); 826 VIXL_ASSERT((type == kFldmdbx) || (type == kFldmiax) || 827 (type == kFstmdbx) || (type == kFstmiax)); 828 UnimplementedDelegate(type); 829 } 830 virtual void DelegateIt(Condition /*cond*/, uint16_t /*mask*/) { 831 UnimplementedDelegate(kIt); 832 } 833 virtual void Delegate(InstructionType type, 834 InstructionCondRMop /*instruction*/, 835 Condition /*cond*/, 836 Register /*rt*/, 837 const MemOperand& /*operand*/) { 838 USE(type); 839 VIXL_ASSERT((type == kLda) || (type == kLdab) || (type == kLdaex) || 840 (type == kLdaexb) || (type == kLdaexh) || (type == kLdah) || 841 (type == kLdrex) || (type == kLdrexb) || (type == kLdrexh) || 842 (type == kStl) || (type == kStlb) || (type == kStlh)); 843 UnimplementedDelegate(type); 844 } 845 virtual void Delegate(InstructionType type, 846 InstructionCondRRMop /*instruction*/, 847 Condition /*cond*/, 848 Register /*rt*/, 849 Register /*rt2*/, 850 const MemOperand& /*operand*/) { 851 USE(type); 852 VIXL_ASSERT((type == kLdaexd) || (type == kLdrd) || (type == kLdrexd) || 853 (type == kStlex) || (type == kStlexb) || (type == kStlexh) || 854 (type == kStrd) || (type == kStrex) || (type == kStrexb) || 855 (type == kStrexh)); 856 UnimplementedDelegate(type); 857 } 858 virtual void Delegate(InstructionType type, 859 InstructionCondSizeRwbRl /*instruction*/, 860 Condition /*cond*/, 861 EncodingSize /*size*/, 862 Register /*rn*/, 863 WriteBack /*write_back*/, 864 RegisterList /*registers*/) { 865 USE(type); 866 VIXL_ASSERT((type == kLdm) || (type == kLdmfd) || (type == kStm) || 867 (type == kStmdb) || (type == kStmea)); 868 UnimplementedDelegate(type); 869 } 870 virtual void Delegate(InstructionType type, 871 InstructionCondRwbRl /*instruction*/, 872 Condition /*cond*/, 873 Register /*rn*/, 874 WriteBack /*write_back*/, 875 RegisterList /*registers*/) { 876 USE(type); 877 VIXL_ASSERT((type == kLdmda) || (type == kLdmdb) || (type == kLdmea) || 878 (type == kLdmed) || (type == kLdmfa) || (type == kLdmib) || 879 (type == kStmda) || (type == kStmed) || (type == kStmfa) || 880 (type == kStmfd) || (type == kStmib)); 881 UnimplementedDelegate(type); 882 } 883 virtual void Delegate(InstructionType type, 884 InstructionCondSizeRMop /*instruction*/, 885 Condition /*cond*/, 886 EncodingSize /*size*/, 887 Register /*rt*/, 888 const MemOperand& /*operand*/) { 889 USE(type); 890 VIXL_ASSERT((type == kLdr) || (type == kLdrb) || (type == kLdrh) || 891 (type == kLdrsb) || (type == kLdrsh) || (type == kStr) || 892 (type == kStrb) || (type == kStrh)); 893 UnimplementedDelegate(type); 894 } 895 virtual void Delegate(InstructionType type, 896 InstructionCondRL /*instruction*/, 897 Condition /*cond*/, 898 Register /*rt*/, 899 Location* /*location*/) { 900 USE(type); 901 VIXL_ASSERT((type == kLdrb) || (type == kLdrh) || (type == kLdrsb) || 902 (type == kLdrsh)); 903 UnimplementedDelegate(type); 904 } 905 virtual void Delegate(InstructionType type, 906 InstructionCondRRL /*instruction*/, 907 Condition /*cond*/, 908 Register /*rt*/, 909 Register /*rt2*/, 910 Location* /*location*/) { 911 USE(type); 912 VIXL_ASSERT((type == kLdrd)); 913 UnimplementedDelegate(type); 914 } 915 virtual void Delegate(InstructionType type, 916 InstructionCondRRRR /*instruction*/, 917 Condition /*cond*/, 918 Register /*rd*/, 919 Register /*rn*/, 920 Register /*rm*/, 921 Register /*ra*/) { 922 USE(type); 923 VIXL_ASSERT((type == kMla) || (type == kMlas) || (type == kMls) || 924 (type == kSmlabb) || (type == kSmlabt) || (type == kSmlad) || 925 (type == kSmladx) || (type == kSmlal) || (type == kSmlalbb) || 926 (type == kSmlalbt) || (type == kSmlald) || (type == kSmlaldx) || 927 (type == kSmlals) || (type == kSmlaltb) || (type == kSmlaltt) || 928 (type == kSmlatb) || (type == kSmlatt) || (type == kSmlawb) || 929 (type == kSmlawt) || (type == kSmlsd) || (type == kSmlsdx) || 930 (type == kSmlsld) || (type == kSmlsldx) || (type == kSmmla) || 931 (type == kSmmlar) || (type == kSmmls) || (type == kSmmlsr) || 932 (type == kSmull) || (type == kSmulls) || (type == kUmaal) || 933 (type == kUmlal) || (type == kUmlals) || (type == kUmull) || 934 (type == kUmulls) || (type == kUsada8)); 935 UnimplementedDelegate(type); 936 } 937 virtual void Delegate(InstructionType type, 938 InstructionCondRSr /*instruction*/, 939 Condition /*cond*/, 940 Register /*rd*/, 941 SpecialRegister /*spec_reg*/) { 942 USE(type); 943 VIXL_ASSERT((type == kMrs)); 944 UnimplementedDelegate(type); 945 } 946 virtual void Delegate(InstructionType type, 947 InstructionCondMsrOp /*instruction*/, 948 Condition /*cond*/, 949 MaskedSpecialRegister /*spec_reg*/, 950 const Operand& /*operand*/) { 951 USE(type); 952 VIXL_ASSERT((type == kMsr)); 953 UnimplementedDelegate(type); 954 } 955 virtual void Delegate(InstructionType type, 956 InstructionCondSizeRRR /*instruction*/, 957 Condition /*cond*/, 958 EncodingSize /*size*/, 959 Register /*rd*/, 960 Register /*rn*/, 961 Register /*rm*/) { 962 USE(type); 963 VIXL_ASSERT((type == kMul)); 964 UnimplementedDelegate(type); 965 } 966 virtual void Delegate(InstructionType type, 967 InstructionCondSize /*instruction*/, 968 Condition /*cond*/, 969 EncodingSize /*size*/) { 970 USE(type); 971 VIXL_ASSERT((type == kNop) || (type == kYield)); 972 UnimplementedDelegate(type); 973 } 974 virtual void Delegate(InstructionType type, 975 InstructionCondMop /*instruction*/, 976 Condition /*cond*/, 977 const MemOperand& /*operand*/) { 978 USE(type); 979 VIXL_ASSERT((type == kPld) || (type == kPldw) || (type == kPli)); 980 UnimplementedDelegate(type); 981 } 982 virtual void Delegate(InstructionType type, 983 InstructionCondSizeRl /*instruction*/, 984 Condition /*cond*/, 985 EncodingSize /*size*/, 986 RegisterList /*registers*/) { 987 USE(type); 988 VIXL_ASSERT((type == kPop) || (type == kPush)); 989 UnimplementedDelegate(type); 990 } 991 virtual void Delegate(InstructionType type, 992 InstructionCondSizeOrl /*instruction*/, 993 Condition /*cond*/, 994 EncodingSize /*size*/, 995 Register /*rt*/) { 996 USE(type); 997 VIXL_ASSERT((type == kPop) || (type == kPush)); 998 UnimplementedDelegate(type); 999 } 1000 virtual void Delegate(InstructionType type, 1001 InstructionCondSizeRR /*instruction*/, 1002 Condition /*cond*/, 1003 EncodingSize /*size*/, 1004 Register /*rd*/, 1005 Register /*rm*/) { 1006 USE(type); 1007 VIXL_ASSERT((type == kRev) || (type == kRev16) || (type == kRevsh)); 1008 UnimplementedDelegate(type); 1009 } 1010 virtual void Delegate(InstructionType type, 1011 InstructionDtQQQ /*instruction*/, 1012 DataType /*dt*/, 1013 QRegister /*rd*/, 1014 QRegister /*rn*/, 1015 QRegister /*rm*/) { 1016 USE(type); 1017 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm)); 1018 UnimplementedDelegate(type); 1019 } 1020 virtual void Delegate(InstructionType type, 1021 InstructionCondRIOp /*instruction*/, 1022 Condition /*cond*/, 1023 Register /*rd*/, 1024 uint32_t /*imm*/, 1025 const Operand& /*operand*/) { 1026 USE(type); 1027 VIXL_ASSERT((type == kSsat) || (type == kUsat)); 1028 UnimplementedDelegate(type); 1029 } 1030 virtual void Delegate(InstructionType type, 1031 InstructionCondRIR /*instruction*/, 1032 Condition /*cond*/, 1033 Register /*rd*/, 1034 uint32_t /*imm*/, 1035 Register /*rn*/) { 1036 USE(type); 1037 VIXL_ASSERT((type == kSsat16) || (type == kUsat16)); 1038 UnimplementedDelegate(type); 1039 } 1040 virtual void Delegate(InstructionType type, 1041 InstructionCondRRRMop /*instruction*/, 1042 Condition /*cond*/, 1043 Register /*rd*/, 1044 Register /*rt*/, 1045 Register /*rt2*/, 1046 const MemOperand& /*operand*/) { 1047 USE(type); 1048 VIXL_ASSERT((type == kStlexd) || (type == kStrexd)); 1049 UnimplementedDelegate(type); 1050 } 1051 virtual void Delegate(InstructionType type, 1052 InstructionCondSizeI /*instruction*/, 1053 Condition /*cond*/, 1054 EncodingSize /*size*/, 1055 uint32_t /*imm*/) { 1056 USE(type); 1057 VIXL_ASSERT((type == kUdf)); 1058 UnimplementedDelegate(type); 1059 } 1060 virtual void Delegate(InstructionType type, 1061 InstructionCondDtDDD /*instruction*/, 1062 Condition /*cond*/, 1063 DataType /*dt*/, 1064 DRegister /*rd*/, 1065 DRegister /*rn*/, 1066 DRegister /*rm*/) { 1067 USE(type); 1068 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1069 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1070 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1071 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1072 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1073 (type == kVdiv) || (type == kVeor) || (type == kVfma) || 1074 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1075 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1076 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1077 (type == kVmul) || (type == kVnmla) || (type == kVnmls) || 1078 (type == kVnmul) || (type == kVpadd) || (type == kVpmax) || 1079 (type == kVpmin) || (type == kVqadd) || (type == kVqdmulh) || 1080 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1081 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1082 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1083 UnimplementedDelegate(type); 1084 } 1085 virtual void Delegate(InstructionType type, 1086 InstructionCondDtQQQ /*instruction*/, 1087 Condition /*cond*/, 1088 DataType /*dt*/, 1089 QRegister /*rd*/, 1090 QRegister /*rn*/, 1091 QRegister /*rm*/) { 1092 USE(type); 1093 VIXL_ASSERT((type == kVaba) || (type == kVabd) || (type == kVacge) || 1094 (type == kVacgt) || (type == kVacle) || (type == kVaclt) || 1095 (type == kVadd) || (type == kVbif) || (type == kVbit) || 1096 (type == kVbsl) || (type == kVceq) || (type == kVcge) || 1097 (type == kVcgt) || (type == kVcle) || (type == kVclt) || 1098 (type == kVeor) || (type == kVfma) || (type == kVfms) || 1099 (type == kVhadd) || (type == kVhsub) || (type == kVmax) || 1100 (type == kVmin) || (type == kVmla) || (type == kVmls) || 1101 (type == kVmul) || (type == kVqadd) || (type == kVqdmulh) || 1102 (type == kVqrdmulh) || (type == kVqrshl) || (type == kVqsub) || 1103 (type == kVrecps) || (type == kVrhadd) || (type == kVrshl) || 1104 (type == kVrsqrts) || (type == kVsub) || (type == kVtst)); 1105 UnimplementedDelegate(type); 1106 } 1107 virtual void Delegate(InstructionType type, 1108 InstructionCondDtQDD /*instruction*/, 1109 Condition /*cond*/, 1110 DataType /*dt*/, 1111 QRegister /*rd*/, 1112 DRegister /*rn*/, 1113 DRegister /*rm*/) { 1114 USE(type); 1115 VIXL_ASSERT((type == kVabal) || (type == kVabdl) || (type == kVaddl) || 1116 (type == kVmlal) || (type == kVmlsl) || (type == kVmull) || 1117 (type == kVqdmlal) || (type == kVqdmlsl) || 1118 (type == kVqdmull) || (type == kVsubl)); 1119 UnimplementedDelegate(type); 1120 } 1121 virtual void Delegate(InstructionType type, 1122 InstructionCondDtDD /*instruction*/, 1123 Condition /*cond*/, 1124 DataType /*dt*/, 1125 DRegister /*rd*/, 1126 DRegister /*rm*/) { 1127 USE(type); 1128 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1129 (type == kVcnt) || (type == kVneg) || (type == kVpadal) || 1130 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) || 1131 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) || 1132 (type == kVrev64) || (type == kVrsqrte) || (type == kVsqrt) || 1133 (type == kVswp) || (type == kVtrn) || (type == kVuzp) || 1134 (type == kVzip)); 1135 UnimplementedDelegate(type); 1136 } 1137 virtual void Delegate(InstructionType type, 1138 InstructionCondDtQQ /*instruction*/, 1139 Condition /*cond*/, 1140 DataType /*dt*/, 1141 QRegister /*rd*/, 1142 QRegister /*rm*/) { 1143 USE(type); 1144 VIXL_ASSERT((type == kVabs) || (type == kVcls) || (type == kVclz) || 1145 (type == kVcnt) || (type == kVneg) || (type == kVpadal) || 1146 (type == kVpaddl) || (type == kVqabs) || (type == kVqneg) || 1147 (type == kVrecpe) || (type == kVrev16) || (type == kVrev32) || 1148 (type == kVrev64) || (type == kVrsqrte) || (type == kVswp) || 1149 (type == kVtrn) || (type == kVuzp) || (type == kVzip)); 1150 UnimplementedDelegate(type); 1151 } 1152 virtual void Delegate(InstructionType type, 1153 InstructionCondDtSS /*instruction*/, 1154 Condition /*cond*/, 1155 DataType /*dt*/, 1156 SRegister /*rd*/, 1157 SRegister /*rm*/) { 1158 USE(type); 1159 VIXL_ASSERT((type == kVabs) || (type == kVneg) || (type == kVsqrt)); 1160 UnimplementedDelegate(type); 1161 } 1162 virtual void Delegate(InstructionType type, 1163 InstructionCondDtSSS /*instruction*/, 1164 Condition /*cond*/, 1165 DataType /*dt*/, 1166 SRegister /*rd*/, 1167 SRegister /*rn*/, 1168 SRegister /*rm*/) { 1169 USE(type); 1170 VIXL_ASSERT((type == kVadd) || (type == kVdiv) || (type == kVfma) || 1171 (type == kVfms) || (type == kVfnma) || (type == kVfnms) || 1172 (type == kVmla) || (type == kVmls) || (type == kVmul) || 1173 (type == kVnmla) || (type == kVnmls) || (type == kVnmul) || 1174 (type == kVsub)); 1175 UnimplementedDelegate(type); 1176 } 1177 virtual void Delegate(InstructionType type, 1178 InstructionCondDtDQQ /*instruction*/, 1179 Condition /*cond*/, 1180 DataType /*dt*/, 1181 DRegister /*rd*/, 1182 QRegister /*rn*/, 1183 QRegister /*rm*/) { 1184 USE(type); 1185 VIXL_ASSERT((type == kVaddhn) || (type == kVraddhn) || (type == kVrsubhn) || 1186 (type == kVsubhn)); 1187 UnimplementedDelegate(type); 1188 } 1189 virtual void Delegate(InstructionType type, 1190 InstructionCondDtQQD /*instruction*/, 1191 Condition /*cond*/, 1192 DataType /*dt*/, 1193 QRegister /*rd*/, 1194 QRegister /*rn*/, 1195 DRegister /*rm*/) { 1196 USE(type); 1197 VIXL_ASSERT((type == kVaddw) || (type == kVsubw)); 1198 UnimplementedDelegate(type); 1199 } 1200 virtual void Delegate(InstructionType type, 1201 InstructionCondDtDDDop /*instruction*/, 1202 Condition /*cond*/, 1203 DataType /*dt*/, 1204 DRegister /*rd*/, 1205 DRegister /*rn*/, 1206 const DOperand& /*operand*/) { 1207 USE(type); 1208 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1209 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1210 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1211 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1212 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1213 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1214 UnimplementedDelegate(type); 1215 } 1216 virtual void Delegate(InstructionType type, 1217 InstructionCondDtQQQop /*instruction*/, 1218 Condition /*cond*/, 1219 DataType /*dt*/, 1220 QRegister /*rd*/, 1221 QRegister /*rn*/, 1222 const QOperand& /*operand*/) { 1223 USE(type); 1224 VIXL_ASSERT((type == kVand) || (type == kVbic) || (type == kVceq) || 1225 (type == kVcge) || (type == kVcgt) || (type == kVcle) || 1226 (type == kVclt) || (type == kVorn) || (type == kVorr) || 1227 (type == kVqshl) || (type == kVqshlu) || (type == kVrshr) || 1228 (type == kVrsra) || (type == kVshl) || (type == kVshr) || 1229 (type == kVsli) || (type == kVsra) || (type == kVsri)); 1230 UnimplementedDelegate(type); 1231 } 1232 virtual void Delegate(InstructionType type, 1233 InstructionCondDtSSop /*instruction*/, 1234 Condition /*cond*/, 1235 DataType /*dt*/, 1236 SRegister /*rd*/, 1237 const SOperand& /*operand*/) { 1238 USE(type); 1239 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov)); 1240 UnimplementedDelegate(type); 1241 } 1242 virtual void Delegate(InstructionType type, 1243 InstructionCondDtDDop /*instruction*/, 1244 Condition /*cond*/, 1245 DataType /*dt*/, 1246 DRegister /*rd*/, 1247 const DOperand& /*operand*/) { 1248 USE(type); 1249 VIXL_ASSERT((type == kVcmp) || (type == kVcmpe) || (type == kVmov) || 1250 (type == kVmvn)); 1251 UnimplementedDelegate(type); 1252 } 1253 virtual void Delegate(InstructionType type, 1254 InstructionCondDtDtDS /*instruction*/, 1255 Condition /*cond*/, 1256 DataType /*dt1*/, 1257 DataType /*dt2*/, 1258 DRegister /*rd*/, 1259 SRegister /*rm*/) { 1260 USE(type); 1261 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtt)); 1262 UnimplementedDelegate(type); 1263 } 1264 virtual void Delegate(InstructionType type, 1265 InstructionCondDtDtSD /*instruction*/, 1266 Condition /*cond*/, 1267 DataType /*dt1*/, 1268 DataType /*dt2*/, 1269 SRegister /*rd*/, 1270 DRegister /*rm*/) { 1271 USE(type); 1272 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1273 (type == kVcvtt)); 1274 UnimplementedDelegate(type); 1275 } 1276 virtual void Delegate(InstructionType type, 1277 InstructionCondDtDtDDSi /*instruction*/, 1278 Condition /*cond*/, 1279 DataType /*dt1*/, 1280 DataType /*dt2*/, 1281 DRegister /*rd*/, 1282 DRegister /*rm*/, 1283 int32_t /*fbits*/) { 1284 USE(type); 1285 VIXL_ASSERT((type == kVcvt)); 1286 UnimplementedDelegate(type); 1287 } 1288 virtual void Delegate(InstructionType type, 1289 InstructionCondDtDtQQSi /*instruction*/, 1290 Condition /*cond*/, 1291 DataType /*dt1*/, 1292 DataType /*dt2*/, 1293 QRegister /*rd*/, 1294 QRegister /*rm*/, 1295 int32_t /*fbits*/) { 1296 USE(type); 1297 VIXL_ASSERT((type == kVcvt)); 1298 UnimplementedDelegate(type); 1299 } 1300 virtual void Delegate(InstructionType type, 1301 InstructionCondDtDtSSSi /*instruction*/, 1302 Condition /*cond*/, 1303 DataType /*dt1*/, 1304 DataType /*dt2*/, 1305 SRegister /*rd*/, 1306 SRegister /*rm*/, 1307 int32_t /*fbits*/) { 1308 USE(type); 1309 VIXL_ASSERT((type == kVcvt)); 1310 UnimplementedDelegate(type); 1311 } 1312 virtual void Delegate(InstructionType type, 1313 InstructionCondDtDtDD /*instruction*/, 1314 Condition /*cond*/, 1315 DataType /*dt1*/, 1316 DataType /*dt2*/, 1317 DRegister /*rd*/, 1318 DRegister /*rm*/) { 1319 USE(type); 1320 VIXL_ASSERT((type == kVcvt) || (type == kVrintr) || (type == kVrintx) || 1321 (type == kVrintz)); 1322 UnimplementedDelegate(type); 1323 } 1324 virtual void Delegate(InstructionType type, 1325 InstructionCondDtDtQQ /*instruction*/, 1326 Condition /*cond*/, 1327 DataType /*dt1*/, 1328 DataType /*dt2*/, 1329 QRegister /*rd*/, 1330 QRegister /*rm*/) { 1331 USE(type); 1332 VIXL_ASSERT((type == kVcvt)); 1333 UnimplementedDelegate(type); 1334 } 1335 virtual void Delegate(InstructionType type, 1336 InstructionCondDtDtDQ /*instruction*/, 1337 Condition /*cond*/, 1338 DataType /*dt1*/, 1339 DataType /*dt2*/, 1340 DRegister /*rd*/, 1341 QRegister /*rm*/) { 1342 USE(type); 1343 VIXL_ASSERT((type == kVcvt)); 1344 UnimplementedDelegate(type); 1345 } 1346 virtual void Delegate(InstructionType type, 1347 InstructionCondDtDtQD /*instruction*/, 1348 Condition /*cond*/, 1349 DataType /*dt1*/, 1350 DataType /*dt2*/, 1351 QRegister /*rd*/, 1352 DRegister /*rm*/) { 1353 USE(type); 1354 VIXL_ASSERT((type == kVcvt)); 1355 UnimplementedDelegate(type); 1356 } 1357 virtual void Delegate(InstructionType type, 1358 InstructionCondDtDtSS /*instruction*/, 1359 Condition /*cond*/, 1360 DataType /*dt1*/, 1361 DataType /*dt2*/, 1362 SRegister /*rd*/, 1363 SRegister /*rm*/) { 1364 USE(type); 1365 VIXL_ASSERT((type == kVcvt) || (type == kVcvtb) || (type == kVcvtr) || 1366 (type == kVcvtt) || (type == kVrintr) || (type == kVrintx) || 1367 (type == kVrintz)); 1368 UnimplementedDelegate(type); 1369 } 1370 virtual void Delegate(InstructionType type, 1371 InstructionDtDtDD /*instruction*/, 1372 DataType /*dt1*/, 1373 DataType /*dt2*/, 1374 DRegister /*rd*/, 1375 DRegister /*rm*/) { 1376 USE(type); 1377 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1378 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1379 (type == kVrintn) || (type == kVrintp)); 1380 UnimplementedDelegate(type); 1381 } 1382 virtual void Delegate(InstructionType type, 1383 InstructionDtDtQQ /*instruction*/, 1384 DataType /*dt1*/, 1385 DataType /*dt2*/, 1386 QRegister /*rd*/, 1387 QRegister /*rm*/) { 1388 USE(type); 1389 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1390 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1391 (type == kVrintn) || (type == kVrintp) || (type == kVrintx) || 1392 (type == kVrintz)); 1393 UnimplementedDelegate(type); 1394 } 1395 virtual void Delegate(InstructionType type, 1396 InstructionDtDtSS /*instruction*/, 1397 DataType /*dt1*/, 1398 DataType /*dt2*/, 1399 SRegister /*rd*/, 1400 SRegister /*rm*/) { 1401 USE(type); 1402 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1403 (type == kVcvtp) || (type == kVrinta) || (type == kVrintm) || 1404 (type == kVrintn) || (type == kVrintp)); 1405 UnimplementedDelegate(type); 1406 } 1407 virtual void Delegate(InstructionType type, 1408 InstructionDtDtSD /*instruction*/, 1409 DataType /*dt1*/, 1410 DataType /*dt2*/, 1411 SRegister /*rd*/, 1412 DRegister /*rm*/) { 1413 USE(type); 1414 VIXL_ASSERT((type == kVcvta) || (type == kVcvtm) || (type == kVcvtn) || 1415 (type == kVcvtp)); 1416 UnimplementedDelegate(type); 1417 } 1418 virtual void Delegate(InstructionType type, 1419 InstructionCondDtQR /*instruction*/, 1420 Condition /*cond*/, 1421 DataType /*dt*/, 1422 QRegister /*rd*/, 1423 Register /*rt*/) { 1424 USE(type); 1425 VIXL_ASSERT((type == kVdup)); 1426 UnimplementedDelegate(type); 1427 } 1428 virtual void Delegate(InstructionType type, 1429 InstructionCondDtDR /*instruction*/, 1430 Condition /*cond*/, 1431 DataType /*dt*/, 1432 DRegister /*rd*/, 1433 Register /*rt*/) { 1434 USE(type); 1435 VIXL_ASSERT((type == kVdup)); 1436 UnimplementedDelegate(type); 1437 } 1438 virtual void Delegate(InstructionType type, 1439 InstructionCondDtDDx /*instruction*/, 1440 Condition /*cond*/, 1441 DataType /*dt*/, 1442 DRegister /*rd*/, 1443 DRegisterLane /*rm*/) { 1444 USE(type); 1445 VIXL_ASSERT((type == kVdup)); 1446 UnimplementedDelegate(type); 1447 } 1448 virtual void Delegate(InstructionType type, 1449 InstructionCondDtQDx /*instruction*/, 1450 Condition /*cond*/, 1451 DataType /*dt*/, 1452 QRegister /*rd*/, 1453 DRegisterLane /*rm*/) { 1454 USE(type); 1455 VIXL_ASSERT((type == kVdup)); 1456 UnimplementedDelegate(type); 1457 } 1458 virtual void Delegate(InstructionType type, 1459 InstructionCondDtDDDDop /*instruction*/, 1460 Condition /*cond*/, 1461 DataType /*dt*/, 1462 DRegister /*rd*/, 1463 DRegister /*rn*/, 1464 DRegister /*rm*/, 1465 const DOperand& /*operand*/) { 1466 USE(type); 1467 VIXL_ASSERT((type == kVext)); 1468 UnimplementedDelegate(type); 1469 } 1470 virtual void Delegate(InstructionType type, 1471 InstructionCondDtQQQQop /*instruction*/, 1472 Condition /*cond*/, 1473 DataType /*dt*/, 1474 QRegister /*rd*/, 1475 QRegister /*rn*/, 1476 QRegister /*rm*/, 1477 const QOperand& /*operand*/) { 1478 USE(type); 1479 VIXL_ASSERT((type == kVext)); 1480 UnimplementedDelegate(type); 1481 } 1482 virtual void Delegate(InstructionType type, 1483 InstructionCondDtNrlAmop /*instruction*/, 1484 Condition /*cond*/, 1485 DataType /*dt*/, 1486 const NeonRegisterList& /*nreglist*/, 1487 const AlignedMemOperand& /*operand*/) { 1488 USE(type); 1489 VIXL_ASSERT((type == kVld1) || (type == kVld2) || (type == kVld3) || 1490 (type == kVld4) || (type == kVst1) || (type == kVst2) || 1491 (type == kVst3) || (type == kVst4)); 1492 UnimplementedDelegate(type); 1493 } 1494 virtual void Delegate(InstructionType type, 1495 InstructionCondDtNrlMop /*instruction*/, 1496 Condition /*cond*/, 1497 DataType /*dt*/, 1498 const NeonRegisterList& /*nreglist*/, 1499 const MemOperand& /*operand*/) { 1500 USE(type); 1501 VIXL_ASSERT((type == kVld3) || (type == kVst3)); 1502 UnimplementedDelegate(type); 1503 } 1504 virtual void Delegate(InstructionType type, 1505 InstructionCondDtRwbDrl /*instruction*/, 1506 Condition /*cond*/, 1507 DataType /*dt*/, 1508 Register /*rn*/, 1509 WriteBack /*write_back*/, 1510 DRegisterList /*dreglist*/) { 1511 USE(type); 1512 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1513 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1514 UnimplementedDelegate(type); 1515 } 1516 virtual void Delegate(InstructionType type, 1517 InstructionCondDtRwbSrl /*instruction*/, 1518 Condition /*cond*/, 1519 DataType /*dt*/, 1520 Register /*rn*/, 1521 WriteBack /*write_back*/, 1522 SRegisterList /*sreglist*/) { 1523 USE(type); 1524 VIXL_ASSERT((type == kVldm) || (type == kVldmdb) || (type == kVldmia) || 1525 (type == kVstm) || (type == kVstmdb) || (type == kVstmia)); 1526 UnimplementedDelegate(type); 1527 } 1528 virtual void Delegate(InstructionType type, 1529 InstructionCondDtDL /*instruction*/, 1530 Condition /*cond*/, 1531 DataType /*dt*/, 1532 DRegister /*rd*/, 1533 Location* /*location*/) { 1534 USE(type); 1535 VIXL_ASSERT((type == kVldr)); 1536 UnimplementedDelegate(type); 1537 } 1538 virtual void Delegate(InstructionType type, 1539 InstructionCondDtDMop /*instruction*/, 1540 Condition /*cond*/, 1541 DataType /*dt*/, 1542 DRegister /*rd*/, 1543 const MemOperand& /*operand*/) { 1544 USE(type); 1545 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1546 UnimplementedDelegate(type); 1547 } 1548 virtual void Delegate(InstructionType type, 1549 InstructionCondDtSL /*instruction*/, 1550 Condition /*cond*/, 1551 DataType /*dt*/, 1552 SRegister /*rd*/, 1553 Location* /*location*/) { 1554 USE(type); 1555 VIXL_ASSERT((type == kVldr)); 1556 UnimplementedDelegate(type); 1557 } 1558 virtual void Delegate(InstructionType type, 1559 InstructionCondDtSMop /*instruction*/, 1560 Condition /*cond*/, 1561 DataType /*dt*/, 1562 SRegister /*rd*/, 1563 const MemOperand& /*operand*/) { 1564 USE(type); 1565 VIXL_ASSERT((type == kVldr) || (type == kVstr)); 1566 UnimplementedDelegate(type); 1567 } 1568 virtual void Delegate(InstructionType type, 1569 InstructionDtDDD /*instruction*/, 1570 DataType /*dt*/, 1571 DRegister /*rd*/, 1572 DRegister /*rn*/, 1573 DRegister /*rm*/) { 1574 USE(type); 1575 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1576 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1577 UnimplementedDelegate(type); 1578 } 1579 virtual void Delegate(InstructionType type, 1580 InstructionDtSSS /*instruction*/, 1581 DataType /*dt*/, 1582 SRegister /*rd*/, 1583 SRegister /*rn*/, 1584 SRegister /*rm*/) { 1585 USE(type); 1586 VIXL_ASSERT((type == kVmaxnm) || (type == kVminnm) || (type == kVseleq) || 1587 (type == kVselge) || (type == kVselgt) || (type == kVselvs)); 1588 UnimplementedDelegate(type); 1589 } 1590 virtual void Delegate(InstructionType type, 1591 InstructionCondDtDDDx /*instruction*/, 1592 Condition /*cond*/, 1593 DataType /*dt*/, 1594 DRegister /*rd*/, 1595 DRegister /*rn*/, 1596 DRegisterLane /*rm*/) { 1597 USE(type); 1598 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1599 (type == kVqrdmulh)); 1600 UnimplementedDelegate(type); 1601 } 1602 virtual void Delegate(InstructionType type, 1603 InstructionCondDtQQDx /*instruction*/, 1604 Condition /*cond*/, 1605 DataType /*dt*/, 1606 QRegister /*rd*/, 1607 QRegister /*rn*/, 1608 DRegisterLane /*rm*/) { 1609 USE(type); 1610 VIXL_ASSERT((type == kVmla) || (type == kVmls) || (type == kVqdmulh) || 1611 (type == kVqrdmulh)); 1612 UnimplementedDelegate(type); 1613 } 1614 virtual void Delegate(InstructionType type, 1615 InstructionCondDtQDDx /*instruction*/, 1616 Condition /*cond*/, 1617 DataType /*dt*/, 1618 QRegister /*rd*/, 1619 DRegister /*rn*/, 1620 DRegisterLane /*rm*/) { 1621 USE(type); 1622 VIXL_ASSERT((type == kVmlal) || (type == kVmlsl) || (type == kVqdmull)); 1623 UnimplementedDelegate(type); 1624 } 1625 virtual void Delegate(InstructionType type, 1626 InstructionCondRS /*instruction*/, 1627 Condition /*cond*/, 1628 Register /*rt*/, 1629 SRegister /*rn*/) { 1630 USE(type); 1631 VIXL_ASSERT((type == kVmov)); 1632 UnimplementedDelegate(type); 1633 } 1634 virtual void Delegate(InstructionType type, 1635 InstructionCondSR /*instruction*/, 1636 Condition /*cond*/, 1637 SRegister /*rn*/, 1638 Register /*rt*/) { 1639 USE(type); 1640 VIXL_ASSERT((type == kVmov)); 1641 UnimplementedDelegate(type); 1642 } 1643 virtual void Delegate(InstructionType type, 1644 InstructionCondRRD /*instruction*/, 1645 Condition /*cond*/, 1646 Register /*rt*/, 1647 Register /*rt2*/, 1648 DRegister /*rm*/) { 1649 USE(type); 1650 VIXL_ASSERT((type == kVmov)); 1651 UnimplementedDelegate(type); 1652 } 1653 virtual void Delegate(InstructionType type, 1654 InstructionCondDRR /*instruction*/, 1655 Condition /*cond*/, 1656 DRegister /*rm*/, 1657 Register /*rt*/, 1658 Register /*rt2*/) { 1659 USE(type); 1660 VIXL_ASSERT((type == kVmov)); 1661 UnimplementedDelegate(type); 1662 } 1663 virtual void Delegate(InstructionType type, 1664 InstructionCondRRSS /*instruction*/, 1665 Condition /*cond*/, 1666 Register /*rt*/, 1667 Register /*rt2*/, 1668 SRegister /*rm*/, 1669 SRegister /*rm1*/) { 1670 USE(type); 1671 VIXL_ASSERT((type == kVmov)); 1672 UnimplementedDelegate(type); 1673 } 1674 virtual void Delegate(InstructionType type, 1675 InstructionCondSSRR /*instruction*/, 1676 Condition /*cond*/, 1677 SRegister /*rm*/, 1678 SRegister /*rm1*/, 1679 Register /*rt*/, 1680 Register /*rt2*/) { 1681 USE(type); 1682 VIXL_ASSERT((type == kVmov)); 1683 UnimplementedDelegate(type); 1684 } 1685 virtual void Delegate(InstructionType type, 1686 InstructionCondDtDxR /*instruction*/, 1687 Condition /*cond*/, 1688 DataType /*dt*/, 1689 DRegisterLane /*rd*/, 1690 Register /*rt*/) { 1691 USE(type); 1692 VIXL_ASSERT((type == kVmov)); 1693 UnimplementedDelegate(type); 1694 } 1695 virtual void Delegate(InstructionType type, 1696 InstructionCondDtQQop /*instruction*/, 1697 Condition /*cond*/, 1698 DataType /*dt*/, 1699 QRegister /*rd*/, 1700 const QOperand& /*operand*/) { 1701 USE(type); 1702 VIXL_ASSERT((type == kVmov) || (type == kVmvn)); 1703 UnimplementedDelegate(type); 1704 } 1705 virtual void Delegate(InstructionType type, 1706 InstructionCondDtRDx /*instruction*/, 1707 Condition /*cond*/, 1708 DataType /*dt*/, 1709 Register /*rt*/, 1710 DRegisterLane /*rn*/) { 1711 USE(type); 1712 VIXL_ASSERT((type == kVmov)); 1713 UnimplementedDelegate(type); 1714 } 1715 virtual void Delegate(InstructionType type, 1716 InstructionCondDtQD /*instruction*/, 1717 Condition /*cond*/, 1718 DataType /*dt*/, 1719 QRegister /*rd*/, 1720 DRegister /*rm*/) { 1721 USE(type); 1722 VIXL_ASSERT((type == kVmovl)); 1723 UnimplementedDelegate(type); 1724 } 1725 virtual void Delegate(InstructionType type, 1726 InstructionCondDtDQ /*instruction*/, 1727 Condition /*cond*/, 1728 DataType /*dt*/, 1729 DRegister /*rd*/, 1730 QRegister /*rm*/) { 1731 USE(type); 1732 VIXL_ASSERT((type == kVmovn) || (type == kVqmovn) || (type == kVqmovun)); 1733 UnimplementedDelegate(type); 1734 } 1735 virtual void Delegate(InstructionType type, 1736 InstructionCondRoaSfp /*instruction*/, 1737 Condition /*cond*/, 1738 RegisterOrAPSR_nzcv /*rt*/, 1739 SpecialFPRegister /*spec_reg*/) { 1740 USE(type); 1741 VIXL_ASSERT((type == kVmrs)); 1742 UnimplementedDelegate(type); 1743 } 1744 virtual void Delegate(InstructionType type, 1745 InstructionCondSfpR /*instruction*/, 1746 Condition /*cond*/, 1747 SpecialFPRegister /*spec_reg*/, 1748 Register /*rt*/) { 1749 USE(type); 1750 VIXL_ASSERT((type == kVmsr)); 1751 UnimplementedDelegate(type); 1752 } 1753 virtual void Delegate(InstructionType type, 1754 InstructionCondDtDDIr /*instruction*/, 1755 Condition /*cond*/, 1756 DataType /*dt*/, 1757 DRegister /*rd*/, 1758 DRegister /*rn*/, 1759 DRegister /*dm*/, 1760 unsigned /*index*/) { 1761 USE(type); 1762 VIXL_ASSERT((type == kVmul)); 1763 UnimplementedDelegate(type); 1764 } 1765 virtual void Delegate(InstructionType type, 1766 InstructionCondDtQQIr /*instruction*/, 1767 Condition /*cond*/, 1768 DataType /*dt*/, 1769 QRegister /*rd*/, 1770 QRegister /*rn*/, 1771 DRegister /*dm*/, 1772 unsigned /*index*/) { 1773 USE(type); 1774 VIXL_ASSERT((type == kVmul)); 1775 UnimplementedDelegate(type); 1776 } 1777 virtual void Delegate(InstructionType type, 1778 InstructionCondDtQDIr /*instruction*/, 1779 Condition /*cond*/, 1780 DataType /*dt*/, 1781 QRegister /*rd*/, 1782 DRegister /*rn*/, 1783 DRegister /*dm*/, 1784 unsigned /*index*/) { 1785 USE(type); 1786 VIXL_ASSERT((type == kVmull) || (type == kVqdmlal) || (type == kVqdmlsl)); 1787 UnimplementedDelegate(type); 1788 } 1789 virtual void Delegate(InstructionType type, 1790 InstructionCondDtDrl /*instruction*/, 1791 Condition /*cond*/, 1792 DataType /*dt*/, 1793 DRegisterList /*dreglist*/) { 1794 USE(type); 1795 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1796 UnimplementedDelegate(type); 1797 } 1798 virtual void Delegate(InstructionType type, 1799 InstructionCondDtSrl /*instruction*/, 1800 Condition /*cond*/, 1801 DataType /*dt*/, 1802 SRegisterList /*sreglist*/) { 1803 USE(type); 1804 VIXL_ASSERT((type == kVpop) || (type == kVpush)); 1805 UnimplementedDelegate(type); 1806 } 1807 virtual void Delegate(InstructionType type, 1808 InstructionCondDtDQQop /*instruction*/, 1809 Condition /*cond*/, 1810 DataType /*dt*/, 1811 DRegister /*rd*/, 1812 QRegister /*rm*/, 1813 const QOperand& /*operand*/) { 1814 USE(type); 1815 VIXL_ASSERT((type == kVqrshrn) || (type == kVqrshrun) || 1816 (type == kVqshrn) || (type == kVqshrun) || (type == kVrshrn) || 1817 (type == kVshrn)); 1818 UnimplementedDelegate(type); 1819 } 1820 virtual void Delegate(InstructionType type, 1821 InstructionCondDtQDDop /*instruction*/, 1822 Condition /*cond*/, 1823 DataType /*dt*/, 1824 QRegister /*rd*/, 1825 DRegister /*rm*/, 1826 const DOperand& /*operand*/) { 1827 USE(type); 1828 VIXL_ASSERT((type == kVshll)); 1829 UnimplementedDelegate(type); 1830 } 1831 virtual void Delegate(InstructionType type, 1832 InstructionCondDtDNrlD /*instruction*/, 1833 Condition /*cond*/, 1834 DataType /*dt*/, 1835 DRegister /*rd*/, 1836 const NeonRegisterList& /*nreglist*/, 1837 DRegister /*rm*/) { 1838 USE(type); 1839 VIXL_ASSERT((type == kVtbl) || (type == kVtbx)); 1840 UnimplementedDelegate(type); 1841 } 1842 1843 void adc(Condition cond, 1844 EncodingSize size, 1845 Register rd, 1846 Register rn, 1847 const Operand& operand); 1848 void adc(Register rd, Register rn, const Operand& operand) { 1849 adc(al, Best, rd, rn, operand); 1850 } 1851 void adc(Condition cond, Register rd, Register rn, const Operand& operand) { 1852 adc(cond, Best, rd, rn, operand); 1853 } 1854 void adc(EncodingSize size, 1855 Register rd, 1856 Register rn, 1857 const Operand& operand) { 1858 adc(al, size, rd, rn, operand); 1859 } 1860 1861 void adcs(Condition cond, 1862 EncodingSize size, 1863 Register rd, 1864 Register rn, 1865 const Operand& operand); 1866 void adcs(Register rd, Register rn, const Operand& operand) { 1867 adcs(al, Best, rd, rn, operand); 1868 } 1869 void adcs(Condition cond, Register rd, Register rn, const Operand& operand) { 1870 adcs(cond, Best, rd, rn, operand); 1871 } 1872 void adcs(EncodingSize size, 1873 Register rd, 1874 Register rn, 1875 const Operand& operand) { 1876 adcs(al, size, rd, rn, operand); 1877 } 1878 1879 void add(Condition cond, 1880 EncodingSize size, 1881 Register rd, 1882 Register rn, 1883 const Operand& operand); 1884 void add(Register rd, Register rn, const Operand& operand) { 1885 add(al, Best, rd, rn, operand); 1886 } 1887 void add(Condition cond, Register rd, Register rn, const Operand& operand) { 1888 add(cond, Best, rd, rn, operand); 1889 } 1890 void add(EncodingSize size, 1891 Register rd, 1892 Register rn, 1893 const Operand& operand) { 1894 add(al, size, rd, rn, operand); 1895 } 1896 1897 void add(Condition cond, Register rd, const Operand& operand); 1898 void add(Register rd, const Operand& operand) { add(al, rd, operand); } 1899 1900 void adds(Condition cond, 1901 EncodingSize size, 1902 Register rd, 1903 Register rn, 1904 const Operand& operand); 1905 void adds(Register rd, Register rn, const Operand& operand) { 1906 adds(al, Best, rd, rn, operand); 1907 } 1908 void adds(Condition cond, Register rd, Register rn, const Operand& operand) { 1909 adds(cond, Best, rd, rn, operand); 1910 } 1911 void adds(EncodingSize size, 1912 Register rd, 1913 Register rn, 1914 const Operand& operand) { 1915 adds(al, size, rd, rn, operand); 1916 } 1917 1918 void adds(Register rd, const Operand& operand); 1919 1920 void addw(Condition cond, Register rd, Register rn, const Operand& operand); 1921 void addw(Register rd, Register rn, const Operand& operand) { 1922 addw(al, rd, rn, operand); 1923 } 1924 1925 void adr(Condition cond, EncodingSize size, Register rd, Location* location); 1926 bool adr_info(Condition cond, 1927 EncodingSize size, 1928 Register rd, 1929 Location* location, 1930 const struct ReferenceInfo** info); 1931 void adr(Register rd, Location* location) { adr(al, Best, rd, location); } 1932 void adr(Condition cond, Register rd, Location* location) { 1933 adr(cond, Best, rd, location); 1934 } 1935 void adr(EncodingSize size, Register rd, Location* location) { 1936 adr(al, size, rd, location); 1937 } 1938 1939 void and_(Condition cond, 1940 EncodingSize size, 1941 Register rd, 1942 Register rn, 1943 const Operand& operand); 1944 void and_(Register rd, Register rn, const Operand& operand) { 1945 and_(al, Best, rd, rn, operand); 1946 } 1947 void and_(Condition cond, Register rd, Register rn, const Operand& operand) { 1948 and_(cond, Best, rd, rn, operand); 1949 } 1950 void and_(EncodingSize size, 1951 Register rd, 1952 Register rn, 1953 const Operand& operand) { 1954 and_(al, size, rd, rn, operand); 1955 } 1956 1957 void ands(Condition cond, 1958 EncodingSize size, 1959 Register rd, 1960 Register rn, 1961 const Operand& operand); 1962 void ands(Register rd, Register rn, const Operand& operand) { 1963 ands(al, Best, rd, rn, operand); 1964 } 1965 void ands(Condition cond, Register rd, Register rn, const Operand& operand) { 1966 ands(cond, Best, rd, rn, operand); 1967 } 1968 void ands(EncodingSize size, 1969 Register rd, 1970 Register rn, 1971 const Operand& operand) { 1972 ands(al, size, rd, rn, operand); 1973 } 1974 1975 void asr(Condition cond, 1976 EncodingSize size, 1977 Register rd, 1978 Register rm, 1979 const Operand& operand); 1980 void asr(Register rd, Register rm, const Operand& operand) { 1981 asr(al, Best, rd, rm, operand); 1982 } 1983 void asr(Condition cond, Register rd, Register rm, const Operand& operand) { 1984 asr(cond, Best, rd, rm, operand); 1985 } 1986 void asr(EncodingSize size, 1987 Register rd, 1988 Register rm, 1989 const Operand& operand) { 1990 asr(al, size, rd, rm, operand); 1991 } 1992 1993 void asrs(Condition cond, 1994 EncodingSize size, 1995 Register rd, 1996 Register rm, 1997 const Operand& operand); 1998 void asrs(Register rd, Register rm, const Operand& operand) { 1999 asrs(al, Best, rd, rm, operand); 2000 } 2001 void asrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2002 asrs(cond, Best, rd, rm, operand); 2003 } 2004 void asrs(EncodingSize size, 2005 Register rd, 2006 Register rm, 2007 const Operand& operand) { 2008 asrs(al, size, rd, rm, operand); 2009 } 2010 2011 void b(Condition cond, EncodingSize size, Location* location); 2012 bool b_info(Condition cond, 2013 EncodingSize size, 2014 Location* location, 2015 const struct ReferenceInfo** info); 2016 void b(Location* location) { b(al, Best, location); } 2017 void b(Condition cond, Location* location) { b(cond, Best, location); } 2018 void b(EncodingSize size, Location* location) { b(al, size, location); } 2019 2020 void bfc(Condition cond, Register rd, uint32_t lsb, uint32_t width); 2021 void bfc(Register rd, uint32_t lsb, uint32_t width) { 2022 bfc(al, rd, lsb, width); 2023 } 2024 2025 void bfi( 2026 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 2027 void bfi(Register rd, Register rn, uint32_t lsb, uint32_t width) { 2028 bfi(al, rd, rn, lsb, width); 2029 } 2030 2031 void bic(Condition cond, 2032 EncodingSize size, 2033 Register rd, 2034 Register rn, 2035 const Operand& operand); 2036 void bic(Register rd, Register rn, const Operand& operand) { 2037 bic(al, Best, rd, rn, operand); 2038 } 2039 void bic(Condition cond, Register rd, Register rn, const Operand& operand) { 2040 bic(cond, Best, rd, rn, operand); 2041 } 2042 void bic(EncodingSize size, 2043 Register rd, 2044 Register rn, 2045 const Operand& operand) { 2046 bic(al, size, rd, rn, operand); 2047 } 2048 2049 void bics(Condition cond, 2050 EncodingSize size, 2051 Register rd, 2052 Register rn, 2053 const Operand& operand); 2054 void bics(Register rd, Register rn, const Operand& operand) { 2055 bics(al, Best, rd, rn, operand); 2056 } 2057 void bics(Condition cond, Register rd, Register rn, const Operand& operand) { 2058 bics(cond, Best, rd, rn, operand); 2059 } 2060 void bics(EncodingSize size, 2061 Register rd, 2062 Register rn, 2063 const Operand& operand) { 2064 bics(al, size, rd, rn, operand); 2065 } 2066 2067 void bkpt(Condition cond, uint32_t imm); 2068 void bkpt(uint32_t imm) { bkpt(al, imm); } 2069 2070 void bl(Condition cond, Location* location); 2071 bool bl_info(Condition cond, 2072 Location* location, 2073 const struct ReferenceInfo** info); 2074 void bl(Location* location) { bl(al, location); } 2075 2076 void blx(Condition cond, Location* location); 2077 bool blx_info(Condition cond, 2078 Location* location, 2079 const struct ReferenceInfo** info); 2080 void blx(Location* location) { blx(al, location); } 2081 2082 void blx(Condition cond, Register rm); 2083 void blx(Register rm) { blx(al, rm); } 2084 2085 void bx(Condition cond, Register rm); 2086 void bx(Register rm) { bx(al, rm); } 2087 2088 void bxj(Condition cond, Register rm); 2089 void bxj(Register rm) { bxj(al, rm); } 2090 2091 void cbnz(Register rn, Location* location); 2092 bool cbnz_info(Register rn, 2093 Location* location, 2094 const struct ReferenceInfo** info); 2095 2096 void cbz(Register rn, Location* location); 2097 bool cbz_info(Register rn, 2098 Location* location, 2099 const struct ReferenceInfo** info); 2100 2101 void clrex(Condition cond); 2102 void clrex() { clrex(al); } 2103 2104 void clz(Condition cond, Register rd, Register rm); 2105 void clz(Register rd, Register rm) { clz(al, rd, rm); } 2106 2107 void cmn(Condition cond, 2108 EncodingSize size, 2109 Register rn, 2110 const Operand& operand); 2111 void cmn(Register rn, const Operand& operand) { cmn(al, Best, rn, operand); } 2112 void cmn(Condition cond, Register rn, const Operand& operand) { 2113 cmn(cond, Best, rn, operand); 2114 } 2115 void cmn(EncodingSize size, Register rn, const Operand& operand) { 2116 cmn(al, size, rn, operand); 2117 } 2118 2119 void cmp(Condition cond, 2120 EncodingSize size, 2121 Register rn, 2122 const Operand& operand); 2123 void cmp(Register rn, const Operand& operand) { cmp(al, Best, rn, operand); } 2124 void cmp(Condition cond, Register rn, const Operand& operand) { 2125 cmp(cond, Best, rn, operand); 2126 } 2127 void cmp(EncodingSize size, Register rn, const Operand& operand) { 2128 cmp(al, size, rn, operand); 2129 } 2130 2131 void crc32b(Condition cond, Register rd, Register rn, Register rm); 2132 void crc32b(Register rd, Register rn, Register rm) { crc32b(al, rd, rn, rm); } 2133 2134 void crc32cb(Condition cond, Register rd, Register rn, Register rm); 2135 void crc32cb(Register rd, Register rn, Register rm) { 2136 crc32cb(al, rd, rn, rm); 2137 } 2138 2139 void crc32ch(Condition cond, Register rd, Register rn, Register rm); 2140 void crc32ch(Register rd, Register rn, Register rm) { 2141 crc32ch(al, rd, rn, rm); 2142 } 2143 2144 void crc32cw(Condition cond, Register rd, Register rn, Register rm); 2145 void crc32cw(Register rd, Register rn, Register rm) { 2146 crc32cw(al, rd, rn, rm); 2147 } 2148 2149 void crc32h(Condition cond, Register rd, Register rn, Register rm); 2150 void crc32h(Register rd, Register rn, Register rm) { crc32h(al, rd, rn, rm); } 2151 2152 void crc32w(Condition cond, Register rd, Register rn, Register rm); 2153 void crc32w(Register rd, Register rn, Register rm) { crc32w(al, rd, rn, rm); } 2154 2155 void dmb(Condition cond, MemoryBarrier option); 2156 void dmb(MemoryBarrier option) { dmb(al, option); } 2157 2158 void dsb(Condition cond, MemoryBarrier option); 2159 void dsb(MemoryBarrier option) { dsb(al, option); } 2160 2161 void eor(Condition cond, 2162 EncodingSize size, 2163 Register rd, 2164 Register rn, 2165 const Operand& operand); 2166 void eor(Register rd, Register rn, const Operand& operand) { 2167 eor(al, Best, rd, rn, operand); 2168 } 2169 void eor(Condition cond, Register rd, Register rn, const Operand& operand) { 2170 eor(cond, Best, rd, rn, operand); 2171 } 2172 void eor(EncodingSize size, 2173 Register rd, 2174 Register rn, 2175 const Operand& operand) { 2176 eor(al, size, rd, rn, operand); 2177 } 2178 2179 void eors(Condition cond, 2180 EncodingSize size, 2181 Register rd, 2182 Register rn, 2183 const Operand& operand); 2184 void eors(Register rd, Register rn, const Operand& operand) { 2185 eors(al, Best, rd, rn, operand); 2186 } 2187 void eors(Condition cond, Register rd, Register rn, const Operand& operand) { 2188 eors(cond, Best, rd, rn, operand); 2189 } 2190 void eors(EncodingSize size, 2191 Register rd, 2192 Register rn, 2193 const Operand& operand) { 2194 eors(al, size, rd, rn, operand); 2195 } 2196 2197 void fldmdbx(Condition cond, 2198 Register rn, 2199 WriteBack write_back, 2200 DRegisterList dreglist); 2201 void fldmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2202 fldmdbx(al, rn, write_back, dreglist); 2203 } 2204 2205 void fldmiax(Condition cond, 2206 Register rn, 2207 WriteBack write_back, 2208 DRegisterList dreglist); 2209 void fldmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2210 fldmiax(al, rn, write_back, dreglist); 2211 } 2212 2213 void fstmdbx(Condition cond, 2214 Register rn, 2215 WriteBack write_back, 2216 DRegisterList dreglist); 2217 void fstmdbx(Register rn, WriteBack write_back, DRegisterList dreglist) { 2218 fstmdbx(al, rn, write_back, dreglist); 2219 } 2220 2221 void fstmiax(Condition cond, 2222 Register rn, 2223 WriteBack write_back, 2224 DRegisterList dreglist); 2225 void fstmiax(Register rn, WriteBack write_back, DRegisterList dreglist) { 2226 fstmiax(al, rn, write_back, dreglist); 2227 } 2228 2229 void hlt(Condition cond, uint32_t imm); 2230 void hlt(uint32_t imm) { hlt(al, imm); } 2231 2232 void hvc(Condition cond, uint32_t imm); 2233 void hvc(uint32_t imm) { hvc(al, imm); } 2234 2235 void isb(Condition cond, MemoryBarrier option); 2236 void isb(MemoryBarrier option) { isb(al, option); } 2237 2238 void it(Condition cond, uint16_t mask); 2239 2240 void lda(Condition cond, Register rt, const MemOperand& operand); 2241 void lda(Register rt, const MemOperand& operand) { lda(al, rt, operand); } 2242 2243 void ldab(Condition cond, Register rt, const MemOperand& operand); 2244 void ldab(Register rt, const MemOperand& operand) { ldab(al, rt, operand); } 2245 2246 void ldaex(Condition cond, Register rt, const MemOperand& operand); 2247 void ldaex(Register rt, const MemOperand& operand) { ldaex(al, rt, operand); } 2248 2249 void ldaexb(Condition cond, Register rt, const MemOperand& operand); 2250 void ldaexb(Register rt, const MemOperand& operand) { 2251 ldaexb(al, rt, operand); 2252 } 2253 2254 void ldaexd(Condition cond, 2255 Register rt, 2256 Register rt2, 2257 const MemOperand& operand); 2258 void ldaexd(Register rt, Register rt2, const MemOperand& operand) { 2259 ldaexd(al, rt, rt2, operand); 2260 } 2261 2262 void ldaexh(Condition cond, Register rt, const MemOperand& operand); 2263 void ldaexh(Register rt, const MemOperand& operand) { 2264 ldaexh(al, rt, operand); 2265 } 2266 2267 void ldah(Condition cond, Register rt, const MemOperand& operand); 2268 void ldah(Register rt, const MemOperand& operand) { ldah(al, rt, operand); } 2269 2270 void ldm(Condition cond, 2271 EncodingSize size, 2272 Register rn, 2273 WriteBack write_back, 2274 RegisterList registers); 2275 void ldm(Register rn, WriteBack write_back, RegisterList registers) { 2276 ldm(al, Best, rn, write_back, registers); 2277 } 2278 void ldm(Condition cond, 2279 Register rn, 2280 WriteBack write_back, 2281 RegisterList registers) { 2282 ldm(cond, Best, rn, write_back, registers); 2283 } 2284 void ldm(EncodingSize size, 2285 Register rn, 2286 WriteBack write_back, 2287 RegisterList registers) { 2288 ldm(al, size, rn, write_back, registers); 2289 } 2290 2291 void ldmda(Condition cond, 2292 Register rn, 2293 WriteBack write_back, 2294 RegisterList registers); 2295 void ldmda(Register rn, WriteBack write_back, RegisterList registers) { 2296 ldmda(al, rn, write_back, registers); 2297 } 2298 2299 void ldmdb(Condition cond, 2300 Register rn, 2301 WriteBack write_back, 2302 RegisterList registers); 2303 void ldmdb(Register rn, WriteBack write_back, RegisterList registers) { 2304 ldmdb(al, rn, write_back, registers); 2305 } 2306 2307 void ldmea(Condition cond, 2308 Register rn, 2309 WriteBack write_back, 2310 RegisterList registers); 2311 void ldmea(Register rn, WriteBack write_back, RegisterList registers) { 2312 ldmea(al, rn, write_back, registers); 2313 } 2314 2315 void ldmed(Condition cond, 2316 Register rn, 2317 WriteBack write_back, 2318 RegisterList registers); 2319 void ldmed(Register rn, WriteBack write_back, RegisterList registers) { 2320 ldmed(al, rn, write_back, registers); 2321 } 2322 2323 void ldmfa(Condition cond, 2324 Register rn, 2325 WriteBack write_back, 2326 RegisterList registers); 2327 void ldmfa(Register rn, WriteBack write_back, RegisterList registers) { 2328 ldmfa(al, rn, write_back, registers); 2329 } 2330 2331 void ldmfd(Condition cond, 2332 EncodingSize size, 2333 Register rn, 2334 WriteBack write_back, 2335 RegisterList registers); 2336 void ldmfd(Register rn, WriteBack write_back, RegisterList registers) { 2337 ldmfd(al, Best, rn, write_back, registers); 2338 } 2339 void ldmfd(Condition cond, 2340 Register rn, 2341 WriteBack write_back, 2342 RegisterList registers) { 2343 ldmfd(cond, Best, rn, write_back, registers); 2344 } 2345 void ldmfd(EncodingSize size, 2346 Register rn, 2347 WriteBack write_back, 2348 RegisterList registers) { 2349 ldmfd(al, size, rn, write_back, registers); 2350 } 2351 2352 void ldmib(Condition cond, 2353 Register rn, 2354 WriteBack write_back, 2355 RegisterList registers); 2356 void ldmib(Register rn, WriteBack write_back, RegisterList registers) { 2357 ldmib(al, rn, write_back, registers); 2358 } 2359 2360 void ldr(Condition cond, 2361 EncodingSize size, 2362 Register rt, 2363 const MemOperand& operand); 2364 void ldr(Register rt, const MemOperand& operand) { 2365 ldr(al, Best, rt, operand); 2366 } 2367 void ldr(Condition cond, Register rt, const MemOperand& operand) { 2368 ldr(cond, Best, rt, operand); 2369 } 2370 void ldr(EncodingSize size, Register rt, const MemOperand& operand) { 2371 ldr(al, size, rt, operand); 2372 } 2373 2374 void ldr(Condition cond, EncodingSize size, Register rt, Location* location); 2375 bool ldr_info(Condition cond, 2376 EncodingSize size, 2377 Register rt, 2378 Location* location, 2379 const struct ReferenceInfo** info); 2380 void ldr(Register rt, Location* location) { ldr(al, Best, rt, location); } 2381 void ldr(Condition cond, Register rt, Location* location) { 2382 ldr(cond, Best, rt, location); 2383 } 2384 void ldr(EncodingSize size, Register rt, Location* location) { 2385 ldr(al, size, rt, location); 2386 } 2387 2388 void ldrb(Condition cond, 2389 EncodingSize size, 2390 Register rt, 2391 const MemOperand& operand); 2392 void ldrb(Register rt, const MemOperand& operand) { 2393 ldrb(al, Best, rt, operand); 2394 } 2395 void ldrb(Condition cond, Register rt, const MemOperand& operand) { 2396 ldrb(cond, Best, rt, operand); 2397 } 2398 void ldrb(EncodingSize size, Register rt, const MemOperand& operand) { 2399 ldrb(al, size, rt, operand); 2400 } 2401 2402 void ldrb(Condition cond, Register rt, Location* location); 2403 bool ldrb_info(Condition cond, 2404 Register rt, 2405 Location* location, 2406 const struct ReferenceInfo** info); 2407 void ldrb(Register rt, Location* location) { ldrb(al, rt, location); } 2408 2409 void ldrd(Condition cond, 2410 Register rt, 2411 Register rt2, 2412 const MemOperand& operand); 2413 void ldrd(Register rt, Register rt2, const MemOperand& operand) { 2414 ldrd(al, rt, rt2, operand); 2415 } 2416 2417 void ldrd(Condition cond, Register rt, Register rt2, Location* location); 2418 bool ldrd_info(Condition cond, 2419 Register rt, 2420 Register rt2, 2421 Location* location, 2422 const struct ReferenceInfo** info); 2423 void ldrd(Register rt, Register rt2, Location* location) { 2424 ldrd(al, rt, rt2, location); 2425 } 2426 2427 void ldrex(Condition cond, Register rt, const MemOperand& operand); 2428 void ldrex(Register rt, const MemOperand& operand) { ldrex(al, rt, operand); } 2429 2430 void ldrexb(Condition cond, Register rt, const MemOperand& operand); 2431 void ldrexb(Register rt, const MemOperand& operand) { 2432 ldrexb(al, rt, operand); 2433 } 2434 2435 void ldrexd(Condition cond, 2436 Register rt, 2437 Register rt2, 2438 const MemOperand& operand); 2439 void ldrexd(Register rt, Register rt2, const MemOperand& operand) { 2440 ldrexd(al, rt, rt2, operand); 2441 } 2442 2443 void ldrexh(Condition cond, Register rt, const MemOperand& operand); 2444 void ldrexh(Register rt, const MemOperand& operand) { 2445 ldrexh(al, rt, operand); 2446 } 2447 2448 void ldrh(Condition cond, 2449 EncodingSize size, 2450 Register rt, 2451 const MemOperand& operand); 2452 void ldrh(Register rt, const MemOperand& operand) { 2453 ldrh(al, Best, rt, operand); 2454 } 2455 void ldrh(Condition cond, Register rt, const MemOperand& operand) { 2456 ldrh(cond, Best, rt, operand); 2457 } 2458 void ldrh(EncodingSize size, Register rt, const MemOperand& operand) { 2459 ldrh(al, size, rt, operand); 2460 } 2461 2462 void ldrh(Condition cond, Register rt, Location* location); 2463 bool ldrh_info(Condition cond, 2464 Register rt, 2465 Location* location, 2466 const struct ReferenceInfo** info); 2467 void ldrh(Register rt, Location* location) { ldrh(al, rt, location); } 2468 2469 void ldrsb(Condition cond, 2470 EncodingSize size, 2471 Register rt, 2472 const MemOperand& operand); 2473 void ldrsb(Register rt, const MemOperand& operand) { 2474 ldrsb(al, Best, rt, operand); 2475 } 2476 void ldrsb(Condition cond, Register rt, const MemOperand& operand) { 2477 ldrsb(cond, Best, rt, operand); 2478 } 2479 void ldrsb(EncodingSize size, Register rt, const MemOperand& operand) { 2480 ldrsb(al, size, rt, operand); 2481 } 2482 2483 void ldrsb(Condition cond, Register rt, Location* location); 2484 bool ldrsb_info(Condition cond, 2485 Register rt, 2486 Location* location, 2487 const struct ReferenceInfo** info); 2488 void ldrsb(Register rt, Location* location) { ldrsb(al, rt, location); } 2489 2490 void ldrsh(Condition cond, 2491 EncodingSize size, 2492 Register rt, 2493 const MemOperand& operand); 2494 void ldrsh(Register rt, const MemOperand& operand) { 2495 ldrsh(al, Best, rt, operand); 2496 } 2497 void ldrsh(Condition cond, Register rt, const MemOperand& operand) { 2498 ldrsh(cond, Best, rt, operand); 2499 } 2500 void ldrsh(EncodingSize size, Register rt, const MemOperand& operand) { 2501 ldrsh(al, size, rt, operand); 2502 } 2503 2504 void ldrsh(Condition cond, Register rt, Location* location); 2505 bool ldrsh_info(Condition cond, 2506 Register rt, 2507 Location* location, 2508 const struct ReferenceInfo** info); 2509 void ldrsh(Register rt, Location* location) { ldrsh(al, rt, location); } 2510 2511 void lsl(Condition cond, 2512 EncodingSize size, 2513 Register rd, 2514 Register rm, 2515 const Operand& operand); 2516 void lsl(Register rd, Register rm, const Operand& operand) { 2517 lsl(al, Best, rd, rm, operand); 2518 } 2519 void lsl(Condition cond, Register rd, Register rm, const Operand& operand) { 2520 lsl(cond, Best, rd, rm, operand); 2521 } 2522 void lsl(EncodingSize size, 2523 Register rd, 2524 Register rm, 2525 const Operand& operand) { 2526 lsl(al, size, rd, rm, operand); 2527 } 2528 2529 void lsls(Condition cond, 2530 EncodingSize size, 2531 Register rd, 2532 Register rm, 2533 const Operand& operand); 2534 void lsls(Register rd, Register rm, const Operand& operand) { 2535 lsls(al, Best, rd, rm, operand); 2536 } 2537 void lsls(Condition cond, Register rd, Register rm, const Operand& operand) { 2538 lsls(cond, Best, rd, rm, operand); 2539 } 2540 void lsls(EncodingSize size, 2541 Register rd, 2542 Register rm, 2543 const Operand& operand) { 2544 lsls(al, size, rd, rm, operand); 2545 } 2546 2547 void lsr(Condition cond, 2548 EncodingSize size, 2549 Register rd, 2550 Register rm, 2551 const Operand& operand); 2552 void lsr(Register rd, Register rm, const Operand& operand) { 2553 lsr(al, Best, rd, rm, operand); 2554 } 2555 void lsr(Condition cond, Register rd, Register rm, const Operand& operand) { 2556 lsr(cond, Best, rd, rm, operand); 2557 } 2558 void lsr(EncodingSize size, 2559 Register rd, 2560 Register rm, 2561 const Operand& operand) { 2562 lsr(al, size, rd, rm, operand); 2563 } 2564 2565 void lsrs(Condition cond, 2566 EncodingSize size, 2567 Register rd, 2568 Register rm, 2569 const Operand& operand); 2570 void lsrs(Register rd, Register rm, const Operand& operand) { 2571 lsrs(al, Best, rd, rm, operand); 2572 } 2573 void lsrs(Condition cond, Register rd, Register rm, const Operand& operand) { 2574 lsrs(cond, Best, rd, rm, operand); 2575 } 2576 void lsrs(EncodingSize size, 2577 Register rd, 2578 Register rm, 2579 const Operand& operand) { 2580 lsrs(al, size, rd, rm, operand); 2581 } 2582 2583 void mla(Condition cond, Register rd, Register rn, Register rm, Register ra); 2584 void mla(Register rd, Register rn, Register rm, Register ra) { 2585 mla(al, rd, rn, rm, ra); 2586 } 2587 2588 void mlas(Condition cond, Register rd, Register rn, Register rm, Register ra); 2589 void mlas(Register rd, Register rn, Register rm, Register ra) { 2590 mlas(al, rd, rn, rm, ra); 2591 } 2592 2593 void mls(Condition cond, Register rd, Register rn, Register rm, Register ra); 2594 void mls(Register rd, Register rn, Register rm, Register ra) { 2595 mls(al, rd, rn, rm, ra); 2596 } 2597 2598 void mov(Condition cond, 2599 EncodingSize size, 2600 Register rd, 2601 const Operand& operand); 2602 void mov(Register rd, const Operand& operand) { mov(al, Best, rd, operand); } 2603 void mov(Condition cond, Register rd, const Operand& operand) { 2604 mov(cond, Best, rd, operand); 2605 } 2606 void mov(EncodingSize size, Register rd, const Operand& operand) { 2607 mov(al, size, rd, operand); 2608 } 2609 2610 void movs(Condition cond, 2611 EncodingSize size, 2612 Register rd, 2613 const Operand& operand); 2614 void movs(Register rd, const Operand& operand) { 2615 movs(al, Best, rd, operand); 2616 } 2617 void movs(Condition cond, Register rd, const Operand& operand) { 2618 movs(cond, Best, rd, operand); 2619 } 2620 void movs(EncodingSize size, Register rd, const Operand& operand) { 2621 movs(al, size, rd, operand); 2622 } 2623 2624 void movt(Condition cond, Register rd, const Operand& operand); 2625 void movt(Register rd, const Operand& operand) { movt(al, rd, operand); } 2626 2627 void movw(Condition cond, Register rd, const Operand& operand); 2628 void movw(Register rd, const Operand& operand) { movw(al, rd, operand); } 2629 2630 void mrs(Condition cond, Register rd, SpecialRegister spec_reg); 2631 void mrs(Register rd, SpecialRegister spec_reg) { mrs(al, rd, spec_reg); } 2632 2633 void msr(Condition cond, 2634 MaskedSpecialRegister spec_reg, 2635 const Operand& operand); 2636 void msr(MaskedSpecialRegister spec_reg, const Operand& operand) { 2637 msr(al, spec_reg, operand); 2638 } 2639 2640 void mul( 2641 Condition cond, EncodingSize size, Register rd, Register rn, Register rm); 2642 void mul(Register rd, Register rn, Register rm) { mul(al, Best, rd, rn, rm); } 2643 void mul(Condition cond, Register rd, Register rn, Register rm) { 2644 mul(cond, Best, rd, rn, rm); 2645 } 2646 void mul(EncodingSize size, Register rd, Register rn, Register rm) { 2647 mul(al, size, rd, rn, rm); 2648 } 2649 2650 void muls(Condition cond, Register rd, Register rn, Register rm); 2651 void muls(Register rd, Register rn, Register rm) { muls(al, rd, rn, rm); } 2652 2653 void mvn(Condition cond, 2654 EncodingSize size, 2655 Register rd, 2656 const Operand& operand); 2657 void mvn(Register rd, const Operand& operand) { mvn(al, Best, rd, operand); } 2658 void mvn(Condition cond, Register rd, const Operand& operand) { 2659 mvn(cond, Best, rd, operand); 2660 } 2661 void mvn(EncodingSize size, Register rd, const Operand& operand) { 2662 mvn(al, size, rd, operand); 2663 } 2664 2665 void mvns(Condition cond, 2666 EncodingSize size, 2667 Register rd, 2668 const Operand& operand); 2669 void mvns(Register rd, const Operand& operand) { 2670 mvns(al, Best, rd, operand); 2671 } 2672 void mvns(Condition cond, Register rd, const Operand& operand) { 2673 mvns(cond, Best, rd, operand); 2674 } 2675 void mvns(EncodingSize size, Register rd, const Operand& operand) { 2676 mvns(al, size, rd, operand); 2677 } 2678 2679 void nop(Condition cond, EncodingSize size); 2680 void nop() { nop(al, Best); } 2681 void nop(Condition cond) { nop(cond, Best); } 2682 void nop(EncodingSize size) { nop(al, size); } 2683 2684 void orn(Condition cond, Register rd, Register rn, const Operand& operand); 2685 void orn(Register rd, Register rn, const Operand& operand) { 2686 orn(al, rd, rn, operand); 2687 } 2688 2689 void orns(Condition cond, Register rd, Register rn, const Operand& operand); 2690 void orns(Register rd, Register rn, const Operand& operand) { 2691 orns(al, rd, rn, operand); 2692 } 2693 2694 void orr(Condition cond, 2695 EncodingSize size, 2696 Register rd, 2697 Register rn, 2698 const Operand& operand); 2699 void orr(Register rd, Register rn, const Operand& operand) { 2700 orr(al, Best, rd, rn, operand); 2701 } 2702 void orr(Condition cond, Register rd, Register rn, const Operand& operand) { 2703 orr(cond, Best, rd, rn, operand); 2704 } 2705 void orr(EncodingSize size, 2706 Register rd, 2707 Register rn, 2708 const Operand& operand) { 2709 orr(al, size, rd, rn, operand); 2710 } 2711 2712 void orrs(Condition cond, 2713 EncodingSize size, 2714 Register rd, 2715 Register rn, 2716 const Operand& operand); 2717 void orrs(Register rd, Register rn, const Operand& operand) { 2718 orrs(al, Best, rd, rn, operand); 2719 } 2720 void orrs(Condition cond, Register rd, Register rn, const Operand& operand) { 2721 orrs(cond, Best, rd, rn, operand); 2722 } 2723 void orrs(EncodingSize size, 2724 Register rd, 2725 Register rn, 2726 const Operand& operand) { 2727 orrs(al, size, rd, rn, operand); 2728 } 2729 2730 void pkhbt(Condition cond, Register rd, Register rn, const Operand& operand); 2731 void pkhbt(Register rd, Register rn, const Operand& operand) { 2732 pkhbt(al, rd, rn, operand); 2733 } 2734 2735 void pkhtb(Condition cond, Register rd, Register rn, const Operand& operand); 2736 void pkhtb(Register rd, Register rn, const Operand& operand) { 2737 pkhtb(al, rd, rn, operand); 2738 } 2739 2740 void pld(Condition cond, Location* location); 2741 bool pld_info(Condition cond, 2742 Location* location, 2743 const struct ReferenceInfo** info); 2744 void pld(Location* location) { pld(al, location); } 2745 2746 void pld(Condition cond, const MemOperand& operand); 2747 void pld(const MemOperand& operand) { pld(al, operand); } 2748 2749 void pldw(Condition cond, const MemOperand& operand); 2750 void pldw(const MemOperand& operand) { pldw(al, operand); } 2751 2752 void pli(Condition cond, const MemOperand& operand); 2753 void pli(const MemOperand& operand) { pli(al, operand); } 2754 2755 void pli(Condition cond, Location* location); 2756 bool pli_info(Condition cond, 2757 Location* location, 2758 const struct ReferenceInfo** info); 2759 void pli(Location* location) { pli(al, location); } 2760 2761 void pop(Condition cond, EncodingSize size, RegisterList registers); 2762 void pop(RegisterList registers) { pop(al, Best, registers); } 2763 void pop(Condition cond, RegisterList registers) { 2764 pop(cond, Best, registers); 2765 } 2766 void pop(EncodingSize size, RegisterList registers) { 2767 pop(al, size, registers); 2768 } 2769 2770 void pop(Condition cond, EncodingSize size, Register rt); 2771 void pop(Register rt) { pop(al, Best, rt); } 2772 void pop(Condition cond, Register rt) { pop(cond, Best, rt); } 2773 void pop(EncodingSize size, Register rt) { pop(al, size, rt); } 2774 2775 void push(Condition cond, EncodingSize size, RegisterList registers); 2776 void push(RegisterList registers) { push(al, Best, registers); } 2777 void push(Condition cond, RegisterList registers) { 2778 push(cond, Best, registers); 2779 } 2780 void push(EncodingSize size, RegisterList registers) { 2781 push(al, size, registers); 2782 } 2783 2784 void push(Condition cond, EncodingSize size, Register rt); 2785 void push(Register rt) { push(al, Best, rt); } 2786 void push(Condition cond, Register rt) { push(cond, Best, rt); } 2787 void push(EncodingSize size, Register rt) { push(al, size, rt); } 2788 2789 void qadd(Condition cond, Register rd, Register rm, Register rn); 2790 void qadd(Register rd, Register rm, Register rn) { qadd(al, rd, rm, rn); } 2791 2792 void qadd16(Condition cond, Register rd, Register rn, Register rm); 2793 void qadd16(Register rd, Register rn, Register rm) { qadd16(al, rd, rn, rm); } 2794 2795 void qadd8(Condition cond, Register rd, Register rn, Register rm); 2796 void qadd8(Register rd, Register rn, Register rm) { qadd8(al, rd, rn, rm); } 2797 2798 void qasx(Condition cond, Register rd, Register rn, Register rm); 2799 void qasx(Register rd, Register rn, Register rm) { qasx(al, rd, rn, rm); } 2800 2801 void qdadd(Condition cond, Register rd, Register rm, Register rn); 2802 void qdadd(Register rd, Register rm, Register rn) { qdadd(al, rd, rm, rn); } 2803 2804 void qdsub(Condition cond, Register rd, Register rm, Register rn); 2805 void qdsub(Register rd, Register rm, Register rn) { qdsub(al, rd, rm, rn); } 2806 2807 void qsax(Condition cond, Register rd, Register rn, Register rm); 2808 void qsax(Register rd, Register rn, Register rm) { qsax(al, rd, rn, rm); } 2809 2810 void qsub(Condition cond, Register rd, Register rm, Register rn); 2811 void qsub(Register rd, Register rm, Register rn) { qsub(al, rd, rm, rn); } 2812 2813 void qsub16(Condition cond, Register rd, Register rn, Register rm); 2814 void qsub16(Register rd, Register rn, Register rm) { qsub16(al, rd, rn, rm); } 2815 2816 void qsub8(Condition cond, Register rd, Register rn, Register rm); 2817 void qsub8(Register rd, Register rn, Register rm) { qsub8(al, rd, rn, rm); } 2818 2819 void rbit(Condition cond, Register rd, Register rm); 2820 void rbit(Register rd, Register rm) { rbit(al, rd, rm); } 2821 2822 void rev(Condition cond, EncodingSize size, Register rd, Register rm); 2823 void rev(Register rd, Register rm) { rev(al, Best, rd, rm); } 2824 void rev(Condition cond, Register rd, Register rm) { 2825 rev(cond, Best, rd, rm); 2826 } 2827 void rev(EncodingSize size, Register rd, Register rm) { 2828 rev(al, size, rd, rm); 2829 } 2830 2831 void rev16(Condition cond, EncodingSize size, Register rd, Register rm); 2832 void rev16(Register rd, Register rm) { rev16(al, Best, rd, rm); } 2833 void rev16(Condition cond, Register rd, Register rm) { 2834 rev16(cond, Best, rd, rm); 2835 } 2836 void rev16(EncodingSize size, Register rd, Register rm) { 2837 rev16(al, size, rd, rm); 2838 } 2839 2840 void revsh(Condition cond, EncodingSize size, Register rd, Register rm); 2841 void revsh(Register rd, Register rm) { revsh(al, Best, rd, rm); } 2842 void revsh(Condition cond, Register rd, Register rm) { 2843 revsh(cond, Best, rd, rm); 2844 } 2845 void revsh(EncodingSize size, Register rd, Register rm) { 2846 revsh(al, size, rd, rm); 2847 } 2848 2849 void ror(Condition cond, 2850 EncodingSize size, 2851 Register rd, 2852 Register rm, 2853 const Operand& operand); 2854 void ror(Register rd, Register rm, const Operand& operand) { 2855 ror(al, Best, rd, rm, operand); 2856 } 2857 void ror(Condition cond, Register rd, Register rm, const Operand& operand) { 2858 ror(cond, Best, rd, rm, operand); 2859 } 2860 void ror(EncodingSize size, 2861 Register rd, 2862 Register rm, 2863 const Operand& operand) { 2864 ror(al, size, rd, rm, operand); 2865 } 2866 2867 void rors(Condition cond, 2868 EncodingSize size, 2869 Register rd, 2870 Register rm, 2871 const Operand& operand); 2872 void rors(Register rd, Register rm, const Operand& operand) { 2873 rors(al, Best, rd, rm, operand); 2874 } 2875 void rors(Condition cond, Register rd, Register rm, const Operand& operand) { 2876 rors(cond, Best, rd, rm, operand); 2877 } 2878 void rors(EncodingSize size, 2879 Register rd, 2880 Register rm, 2881 const Operand& operand) { 2882 rors(al, size, rd, rm, operand); 2883 } 2884 2885 void rrx(Condition cond, Register rd, Register rm); 2886 void rrx(Register rd, Register rm) { rrx(al, rd, rm); } 2887 2888 void rrxs(Condition cond, Register rd, Register rm); 2889 void rrxs(Register rd, Register rm) { rrxs(al, rd, rm); } 2890 2891 void rsb(Condition cond, 2892 EncodingSize size, 2893 Register rd, 2894 Register rn, 2895 const Operand& operand); 2896 void rsb(Register rd, Register rn, const Operand& operand) { 2897 rsb(al, Best, rd, rn, operand); 2898 } 2899 void rsb(Condition cond, Register rd, Register rn, const Operand& operand) { 2900 rsb(cond, Best, rd, rn, operand); 2901 } 2902 void rsb(EncodingSize size, 2903 Register rd, 2904 Register rn, 2905 const Operand& operand) { 2906 rsb(al, size, rd, rn, operand); 2907 } 2908 2909 void rsbs(Condition cond, 2910 EncodingSize size, 2911 Register rd, 2912 Register rn, 2913 const Operand& operand); 2914 void rsbs(Register rd, Register rn, const Operand& operand) { 2915 rsbs(al, Best, rd, rn, operand); 2916 } 2917 void rsbs(Condition cond, Register rd, Register rn, const Operand& operand) { 2918 rsbs(cond, Best, rd, rn, operand); 2919 } 2920 void rsbs(EncodingSize size, 2921 Register rd, 2922 Register rn, 2923 const Operand& operand) { 2924 rsbs(al, size, rd, rn, operand); 2925 } 2926 2927 void rsc(Condition cond, Register rd, Register rn, const Operand& operand); 2928 void rsc(Register rd, Register rn, const Operand& operand) { 2929 rsc(al, rd, rn, operand); 2930 } 2931 2932 void rscs(Condition cond, Register rd, Register rn, const Operand& operand); 2933 void rscs(Register rd, Register rn, const Operand& operand) { 2934 rscs(al, rd, rn, operand); 2935 } 2936 2937 void sadd16(Condition cond, Register rd, Register rn, Register rm); 2938 void sadd16(Register rd, Register rn, Register rm) { sadd16(al, rd, rn, rm); } 2939 2940 void sadd8(Condition cond, Register rd, Register rn, Register rm); 2941 void sadd8(Register rd, Register rn, Register rm) { sadd8(al, rd, rn, rm); } 2942 2943 void sasx(Condition cond, Register rd, Register rn, Register rm); 2944 void sasx(Register rd, Register rn, Register rm) { sasx(al, rd, rn, rm); } 2945 2946 void sbc(Condition cond, 2947 EncodingSize size, 2948 Register rd, 2949 Register rn, 2950 const Operand& operand); 2951 void sbc(Register rd, Register rn, const Operand& operand) { 2952 sbc(al, Best, rd, rn, operand); 2953 } 2954 void sbc(Condition cond, Register rd, Register rn, const Operand& operand) { 2955 sbc(cond, Best, rd, rn, operand); 2956 } 2957 void sbc(EncodingSize size, 2958 Register rd, 2959 Register rn, 2960 const Operand& operand) { 2961 sbc(al, size, rd, rn, operand); 2962 } 2963 2964 void sbcs(Condition cond, 2965 EncodingSize size, 2966 Register rd, 2967 Register rn, 2968 const Operand& operand); 2969 void sbcs(Register rd, Register rn, const Operand& operand) { 2970 sbcs(al, Best, rd, rn, operand); 2971 } 2972 void sbcs(Condition cond, Register rd, Register rn, const Operand& operand) { 2973 sbcs(cond, Best, rd, rn, operand); 2974 } 2975 void sbcs(EncodingSize size, 2976 Register rd, 2977 Register rn, 2978 const Operand& operand) { 2979 sbcs(al, size, rd, rn, operand); 2980 } 2981 2982 void sbfx( 2983 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 2984 void sbfx(Register rd, Register rn, uint32_t lsb, uint32_t width) { 2985 sbfx(al, rd, rn, lsb, width); 2986 } 2987 2988 void sdiv(Condition cond, Register rd, Register rn, Register rm); 2989 void sdiv(Register rd, Register rn, Register rm) { sdiv(al, rd, rn, rm); } 2990 2991 void sel(Condition cond, Register rd, Register rn, Register rm); 2992 void sel(Register rd, Register rn, Register rm) { sel(al, rd, rn, rm); } 2993 2994 void shadd16(Condition cond, Register rd, Register rn, Register rm); 2995 void shadd16(Register rd, Register rn, Register rm) { 2996 shadd16(al, rd, rn, rm); 2997 } 2998 2999 void shadd8(Condition cond, Register rd, Register rn, Register rm); 3000 void shadd8(Register rd, Register rn, Register rm) { shadd8(al, rd, rn, rm); } 3001 3002 void shasx(Condition cond, Register rd, Register rn, Register rm); 3003 void shasx(Register rd, Register rn, Register rm) { shasx(al, rd, rn, rm); } 3004 3005 void shsax(Condition cond, Register rd, Register rn, Register rm); 3006 void shsax(Register rd, Register rn, Register rm) { shsax(al, rd, rn, rm); } 3007 3008 void shsub16(Condition cond, Register rd, Register rn, Register rm); 3009 void shsub16(Register rd, Register rn, Register rm) { 3010 shsub16(al, rd, rn, rm); 3011 } 3012 3013 void shsub8(Condition cond, Register rd, Register rn, Register rm); 3014 void shsub8(Register rd, Register rn, Register rm) { shsub8(al, rd, rn, rm); } 3015 3016 void smlabb( 3017 Condition cond, Register rd, Register rn, Register rm, Register ra); 3018 void smlabb(Register rd, Register rn, Register rm, Register ra) { 3019 smlabb(al, rd, rn, rm, ra); 3020 } 3021 3022 void smlabt( 3023 Condition cond, Register rd, Register rn, Register rm, Register ra); 3024 void smlabt(Register rd, Register rn, Register rm, Register ra) { 3025 smlabt(al, rd, rn, rm, ra); 3026 } 3027 3028 void smlad( 3029 Condition cond, Register rd, Register rn, Register rm, Register ra); 3030 void smlad(Register rd, Register rn, Register rm, Register ra) { 3031 smlad(al, rd, rn, rm, ra); 3032 } 3033 3034 void smladx( 3035 Condition cond, Register rd, Register rn, Register rm, Register ra); 3036 void smladx(Register rd, Register rn, Register rm, Register ra) { 3037 smladx(al, rd, rn, rm, ra); 3038 } 3039 3040 void smlal( 3041 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3042 void smlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3043 smlal(al, rdlo, rdhi, rn, rm); 3044 } 3045 3046 void smlalbb( 3047 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3048 void smlalbb(Register rdlo, Register rdhi, Register rn, Register rm) { 3049 smlalbb(al, rdlo, rdhi, rn, rm); 3050 } 3051 3052 void smlalbt( 3053 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3054 void smlalbt(Register rdlo, Register rdhi, Register rn, Register rm) { 3055 smlalbt(al, rdlo, rdhi, rn, rm); 3056 } 3057 3058 void smlald( 3059 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3060 void smlald(Register rdlo, Register rdhi, Register rn, Register rm) { 3061 smlald(al, rdlo, rdhi, rn, rm); 3062 } 3063 3064 void smlaldx( 3065 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3066 void smlaldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3067 smlaldx(al, rdlo, rdhi, rn, rm); 3068 } 3069 3070 void smlals( 3071 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3072 void smlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3073 smlals(al, rdlo, rdhi, rn, rm); 3074 } 3075 3076 void smlaltb( 3077 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3078 void smlaltb(Register rdlo, Register rdhi, Register rn, Register rm) { 3079 smlaltb(al, rdlo, rdhi, rn, rm); 3080 } 3081 3082 void smlaltt( 3083 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3084 void smlaltt(Register rdlo, Register rdhi, Register rn, Register rm) { 3085 smlaltt(al, rdlo, rdhi, rn, rm); 3086 } 3087 3088 void smlatb( 3089 Condition cond, Register rd, Register rn, Register rm, Register ra); 3090 void smlatb(Register rd, Register rn, Register rm, Register ra) { 3091 smlatb(al, rd, rn, rm, ra); 3092 } 3093 3094 void smlatt( 3095 Condition cond, Register rd, Register rn, Register rm, Register ra); 3096 void smlatt(Register rd, Register rn, Register rm, Register ra) { 3097 smlatt(al, rd, rn, rm, ra); 3098 } 3099 3100 void smlawb( 3101 Condition cond, Register rd, Register rn, Register rm, Register ra); 3102 void smlawb(Register rd, Register rn, Register rm, Register ra) { 3103 smlawb(al, rd, rn, rm, ra); 3104 } 3105 3106 void smlawt( 3107 Condition cond, Register rd, Register rn, Register rm, Register ra); 3108 void smlawt(Register rd, Register rn, Register rm, Register ra) { 3109 smlawt(al, rd, rn, rm, ra); 3110 } 3111 3112 void smlsd( 3113 Condition cond, Register rd, Register rn, Register rm, Register ra); 3114 void smlsd(Register rd, Register rn, Register rm, Register ra) { 3115 smlsd(al, rd, rn, rm, ra); 3116 } 3117 3118 void smlsdx( 3119 Condition cond, Register rd, Register rn, Register rm, Register ra); 3120 void smlsdx(Register rd, Register rn, Register rm, Register ra) { 3121 smlsdx(al, rd, rn, rm, ra); 3122 } 3123 3124 void smlsld( 3125 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3126 void smlsld(Register rdlo, Register rdhi, Register rn, Register rm) { 3127 smlsld(al, rdlo, rdhi, rn, rm); 3128 } 3129 3130 void smlsldx( 3131 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3132 void smlsldx(Register rdlo, Register rdhi, Register rn, Register rm) { 3133 smlsldx(al, rdlo, rdhi, rn, rm); 3134 } 3135 3136 void smmla( 3137 Condition cond, Register rd, Register rn, Register rm, Register ra); 3138 void smmla(Register rd, Register rn, Register rm, Register ra) { 3139 smmla(al, rd, rn, rm, ra); 3140 } 3141 3142 void smmlar( 3143 Condition cond, Register rd, Register rn, Register rm, Register ra); 3144 void smmlar(Register rd, Register rn, Register rm, Register ra) { 3145 smmlar(al, rd, rn, rm, ra); 3146 } 3147 3148 void smmls( 3149 Condition cond, Register rd, Register rn, Register rm, Register ra); 3150 void smmls(Register rd, Register rn, Register rm, Register ra) { 3151 smmls(al, rd, rn, rm, ra); 3152 } 3153 3154 void smmlsr( 3155 Condition cond, Register rd, Register rn, Register rm, Register ra); 3156 void smmlsr(Register rd, Register rn, Register rm, Register ra) { 3157 smmlsr(al, rd, rn, rm, ra); 3158 } 3159 3160 void smmul(Condition cond, Register rd, Register rn, Register rm); 3161 void smmul(Register rd, Register rn, Register rm) { smmul(al, rd, rn, rm); } 3162 3163 void smmulr(Condition cond, Register rd, Register rn, Register rm); 3164 void smmulr(Register rd, Register rn, Register rm) { smmulr(al, rd, rn, rm); } 3165 3166 void smuad(Condition cond, Register rd, Register rn, Register rm); 3167 void smuad(Register rd, Register rn, Register rm) { smuad(al, rd, rn, rm); } 3168 3169 void smuadx(Condition cond, Register rd, Register rn, Register rm); 3170 void smuadx(Register rd, Register rn, Register rm) { smuadx(al, rd, rn, rm); } 3171 3172 void smulbb(Condition cond, Register rd, Register rn, Register rm); 3173 void smulbb(Register rd, Register rn, Register rm) { smulbb(al, rd, rn, rm); } 3174 3175 void smulbt(Condition cond, Register rd, Register rn, Register rm); 3176 void smulbt(Register rd, Register rn, Register rm) { smulbt(al, rd, rn, rm); } 3177 3178 void smull( 3179 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3180 void smull(Register rdlo, Register rdhi, Register rn, Register rm) { 3181 smull(al, rdlo, rdhi, rn, rm); 3182 } 3183 3184 void smulls( 3185 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3186 void smulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3187 smulls(al, rdlo, rdhi, rn, rm); 3188 } 3189 3190 void smultb(Condition cond, Register rd, Register rn, Register rm); 3191 void smultb(Register rd, Register rn, Register rm) { smultb(al, rd, rn, rm); } 3192 3193 void smultt(Condition cond, Register rd, Register rn, Register rm); 3194 void smultt(Register rd, Register rn, Register rm) { smultt(al, rd, rn, rm); } 3195 3196 void smulwb(Condition cond, Register rd, Register rn, Register rm); 3197 void smulwb(Register rd, Register rn, Register rm) { smulwb(al, rd, rn, rm); } 3198 3199 void smulwt(Condition cond, Register rd, Register rn, Register rm); 3200 void smulwt(Register rd, Register rn, Register rm) { smulwt(al, rd, rn, rm); } 3201 3202 void smusd(Condition cond, Register rd, Register rn, Register rm); 3203 void smusd(Register rd, Register rn, Register rm) { smusd(al, rd, rn, rm); } 3204 3205 void smusdx(Condition cond, Register rd, Register rn, Register rm); 3206 void smusdx(Register rd, Register rn, Register rm) { smusdx(al, rd, rn, rm); } 3207 3208 void ssat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 3209 void ssat(Register rd, uint32_t imm, const Operand& operand) { 3210 ssat(al, rd, imm, operand); 3211 } 3212 3213 void ssat16(Condition cond, Register rd, uint32_t imm, Register rn); 3214 void ssat16(Register rd, uint32_t imm, Register rn) { 3215 ssat16(al, rd, imm, rn); 3216 } 3217 3218 void ssax(Condition cond, Register rd, Register rn, Register rm); 3219 void ssax(Register rd, Register rn, Register rm) { ssax(al, rd, rn, rm); } 3220 3221 void ssub16(Condition cond, Register rd, Register rn, Register rm); 3222 void ssub16(Register rd, Register rn, Register rm) { ssub16(al, rd, rn, rm); } 3223 3224 void ssub8(Condition cond, Register rd, Register rn, Register rm); 3225 void ssub8(Register rd, Register rn, Register rm) { ssub8(al, rd, rn, rm); } 3226 3227 void stl(Condition cond, Register rt, const MemOperand& operand); 3228 void stl(Register rt, const MemOperand& operand) { stl(al, rt, operand); } 3229 3230 void stlb(Condition cond, Register rt, const MemOperand& operand); 3231 void stlb(Register rt, const MemOperand& operand) { stlb(al, rt, operand); } 3232 3233 void stlex(Condition cond, 3234 Register rd, 3235 Register rt, 3236 const MemOperand& operand); 3237 void stlex(Register rd, Register rt, const MemOperand& operand) { 3238 stlex(al, rd, rt, operand); 3239 } 3240 3241 void stlexb(Condition cond, 3242 Register rd, 3243 Register rt, 3244 const MemOperand& operand); 3245 void stlexb(Register rd, Register rt, const MemOperand& operand) { 3246 stlexb(al, rd, rt, operand); 3247 } 3248 3249 void stlexd(Condition cond, 3250 Register rd, 3251 Register rt, 3252 Register rt2, 3253 const MemOperand& operand); 3254 void stlexd(Register rd, 3255 Register rt, 3256 Register rt2, 3257 const MemOperand& operand) { 3258 stlexd(al, rd, rt, rt2, operand); 3259 } 3260 3261 void stlexh(Condition cond, 3262 Register rd, 3263 Register rt, 3264 const MemOperand& operand); 3265 void stlexh(Register rd, Register rt, const MemOperand& operand) { 3266 stlexh(al, rd, rt, operand); 3267 } 3268 3269 void stlh(Condition cond, Register rt, const MemOperand& operand); 3270 void stlh(Register rt, const MemOperand& operand) { stlh(al, rt, operand); } 3271 3272 void stm(Condition cond, 3273 EncodingSize size, 3274 Register rn, 3275 WriteBack write_back, 3276 RegisterList registers); 3277 void stm(Register rn, WriteBack write_back, RegisterList registers) { 3278 stm(al, Best, rn, write_back, registers); 3279 } 3280 void stm(Condition cond, 3281 Register rn, 3282 WriteBack write_back, 3283 RegisterList registers) { 3284 stm(cond, Best, rn, write_back, registers); 3285 } 3286 void stm(EncodingSize size, 3287 Register rn, 3288 WriteBack write_back, 3289 RegisterList registers) { 3290 stm(al, size, rn, write_back, registers); 3291 } 3292 3293 void stmda(Condition cond, 3294 Register rn, 3295 WriteBack write_back, 3296 RegisterList registers); 3297 void stmda(Register rn, WriteBack write_back, RegisterList registers) { 3298 stmda(al, rn, write_back, registers); 3299 } 3300 3301 void stmdb(Condition cond, 3302 EncodingSize size, 3303 Register rn, 3304 WriteBack write_back, 3305 RegisterList registers); 3306 void stmdb(Register rn, WriteBack write_back, RegisterList registers) { 3307 stmdb(al, Best, rn, write_back, registers); 3308 } 3309 void stmdb(Condition cond, 3310 Register rn, 3311 WriteBack write_back, 3312 RegisterList registers) { 3313 stmdb(cond, Best, rn, write_back, registers); 3314 } 3315 void stmdb(EncodingSize size, 3316 Register rn, 3317 WriteBack write_back, 3318 RegisterList registers) { 3319 stmdb(al, size, rn, write_back, registers); 3320 } 3321 3322 void stmea(Condition cond, 3323 EncodingSize size, 3324 Register rn, 3325 WriteBack write_back, 3326 RegisterList registers); 3327 void stmea(Register rn, WriteBack write_back, RegisterList registers) { 3328 stmea(al, Best, rn, write_back, registers); 3329 } 3330 void stmea(Condition cond, 3331 Register rn, 3332 WriteBack write_back, 3333 RegisterList registers) { 3334 stmea(cond, Best, rn, write_back, registers); 3335 } 3336 void stmea(EncodingSize size, 3337 Register rn, 3338 WriteBack write_back, 3339 RegisterList registers) { 3340 stmea(al, size, rn, write_back, registers); 3341 } 3342 3343 void stmed(Condition cond, 3344 Register rn, 3345 WriteBack write_back, 3346 RegisterList registers); 3347 void stmed(Register rn, WriteBack write_back, RegisterList registers) { 3348 stmed(al, rn, write_back, registers); 3349 } 3350 3351 void stmfa(Condition cond, 3352 Register rn, 3353 WriteBack write_back, 3354 RegisterList registers); 3355 void stmfa(Register rn, WriteBack write_back, RegisterList registers) { 3356 stmfa(al, rn, write_back, registers); 3357 } 3358 3359 void stmfd(Condition cond, 3360 Register rn, 3361 WriteBack write_back, 3362 RegisterList registers); 3363 void stmfd(Register rn, WriteBack write_back, RegisterList registers) { 3364 stmfd(al, rn, write_back, registers); 3365 } 3366 3367 void stmib(Condition cond, 3368 Register rn, 3369 WriteBack write_back, 3370 RegisterList registers); 3371 void stmib(Register rn, WriteBack write_back, RegisterList registers) { 3372 stmib(al, rn, write_back, registers); 3373 } 3374 3375 void str(Condition cond, 3376 EncodingSize size, 3377 Register rt, 3378 const MemOperand& operand); 3379 void str(Register rt, const MemOperand& operand) { 3380 str(al, Best, rt, operand); 3381 } 3382 void str(Condition cond, Register rt, const MemOperand& operand) { 3383 str(cond, Best, rt, operand); 3384 } 3385 void str(EncodingSize size, Register rt, const MemOperand& operand) { 3386 str(al, size, rt, operand); 3387 } 3388 3389 void strb(Condition cond, 3390 EncodingSize size, 3391 Register rt, 3392 const MemOperand& operand); 3393 void strb(Register rt, const MemOperand& operand) { 3394 strb(al, Best, rt, operand); 3395 } 3396 void strb(Condition cond, Register rt, const MemOperand& operand) { 3397 strb(cond, Best, rt, operand); 3398 } 3399 void strb(EncodingSize size, Register rt, const MemOperand& operand) { 3400 strb(al, size, rt, operand); 3401 } 3402 3403 void strd(Condition cond, 3404 Register rt, 3405 Register rt2, 3406 const MemOperand& operand); 3407 void strd(Register rt, Register rt2, const MemOperand& operand) { 3408 strd(al, rt, rt2, operand); 3409 } 3410 3411 void strex(Condition cond, 3412 Register rd, 3413 Register rt, 3414 const MemOperand& operand); 3415 void strex(Register rd, Register rt, const MemOperand& operand) { 3416 strex(al, rd, rt, operand); 3417 } 3418 3419 void strexb(Condition cond, 3420 Register rd, 3421 Register rt, 3422 const MemOperand& operand); 3423 void strexb(Register rd, Register rt, const MemOperand& operand) { 3424 strexb(al, rd, rt, operand); 3425 } 3426 3427 void strexd(Condition cond, 3428 Register rd, 3429 Register rt, 3430 Register rt2, 3431 const MemOperand& operand); 3432 void strexd(Register rd, 3433 Register rt, 3434 Register rt2, 3435 const MemOperand& operand) { 3436 strexd(al, rd, rt, rt2, operand); 3437 } 3438 3439 void strexh(Condition cond, 3440 Register rd, 3441 Register rt, 3442 const MemOperand& operand); 3443 void strexh(Register rd, Register rt, const MemOperand& operand) { 3444 strexh(al, rd, rt, operand); 3445 } 3446 3447 void strh(Condition cond, 3448 EncodingSize size, 3449 Register rt, 3450 const MemOperand& operand); 3451 void strh(Register rt, const MemOperand& operand) { 3452 strh(al, Best, rt, operand); 3453 } 3454 void strh(Condition cond, Register rt, const MemOperand& operand) { 3455 strh(cond, Best, rt, operand); 3456 } 3457 void strh(EncodingSize size, Register rt, const MemOperand& operand) { 3458 strh(al, size, rt, operand); 3459 } 3460 3461 void sub(Condition cond, 3462 EncodingSize size, 3463 Register rd, 3464 Register rn, 3465 const Operand& operand); 3466 void sub(Register rd, Register rn, const Operand& operand) { 3467 sub(al, Best, rd, rn, operand); 3468 } 3469 void sub(Condition cond, Register rd, Register rn, const Operand& operand) { 3470 sub(cond, Best, rd, rn, operand); 3471 } 3472 void sub(EncodingSize size, 3473 Register rd, 3474 Register rn, 3475 const Operand& operand) { 3476 sub(al, size, rd, rn, operand); 3477 } 3478 3479 void sub(Condition cond, Register rd, const Operand& operand); 3480 void sub(Register rd, const Operand& operand) { sub(al, rd, operand); } 3481 3482 void subs(Condition cond, 3483 EncodingSize size, 3484 Register rd, 3485 Register rn, 3486 const Operand& operand); 3487 void subs(Register rd, Register rn, const Operand& operand) { 3488 subs(al, Best, rd, rn, operand); 3489 } 3490 void subs(Condition cond, Register rd, Register rn, const Operand& operand) { 3491 subs(cond, Best, rd, rn, operand); 3492 } 3493 void subs(EncodingSize size, 3494 Register rd, 3495 Register rn, 3496 const Operand& operand) { 3497 subs(al, size, rd, rn, operand); 3498 } 3499 3500 void subs(Register rd, const Operand& operand); 3501 3502 void subw(Condition cond, Register rd, Register rn, const Operand& operand); 3503 void subw(Register rd, Register rn, const Operand& operand) { 3504 subw(al, rd, rn, operand); 3505 } 3506 3507 void svc(Condition cond, uint32_t imm); 3508 void svc(uint32_t imm) { svc(al, imm); } 3509 3510 void sxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3511 void sxtab(Register rd, Register rn, const Operand& operand) { 3512 sxtab(al, rd, rn, operand); 3513 } 3514 3515 void sxtab16(Condition cond, 3516 Register rd, 3517 Register rn, 3518 const Operand& operand); 3519 void sxtab16(Register rd, Register rn, const Operand& operand) { 3520 sxtab16(al, rd, rn, operand); 3521 } 3522 3523 void sxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3524 void sxtah(Register rd, Register rn, const Operand& operand) { 3525 sxtah(al, rd, rn, operand); 3526 } 3527 3528 void sxtb(Condition cond, 3529 EncodingSize size, 3530 Register rd, 3531 const Operand& operand); 3532 void sxtb(Register rd, const Operand& operand) { 3533 sxtb(al, Best, rd, operand); 3534 } 3535 void sxtb(Condition cond, Register rd, const Operand& operand) { 3536 sxtb(cond, Best, rd, operand); 3537 } 3538 void sxtb(EncodingSize size, Register rd, const Operand& operand) { 3539 sxtb(al, size, rd, operand); 3540 } 3541 3542 void sxtb16(Condition cond, Register rd, const Operand& operand); 3543 void sxtb16(Register rd, const Operand& operand) { sxtb16(al, rd, operand); } 3544 3545 void sxth(Condition cond, 3546 EncodingSize size, 3547 Register rd, 3548 const Operand& operand); 3549 void sxth(Register rd, const Operand& operand) { 3550 sxth(al, Best, rd, operand); 3551 } 3552 void sxth(Condition cond, Register rd, const Operand& operand) { 3553 sxth(cond, Best, rd, operand); 3554 } 3555 void sxth(EncodingSize size, Register rd, const Operand& operand) { 3556 sxth(al, size, rd, operand); 3557 } 3558 3559 void tbb(Condition cond, Register rn, Register rm); 3560 void tbb(Register rn, Register rm) { tbb(al, rn, rm); } 3561 3562 void tbh(Condition cond, Register rn, Register rm); 3563 void tbh(Register rn, Register rm) { tbh(al, rn, rm); } 3564 3565 void teq(Condition cond, Register rn, const Operand& operand); 3566 void teq(Register rn, const Operand& operand) { teq(al, rn, operand); } 3567 3568 void tst(Condition cond, 3569 EncodingSize size, 3570 Register rn, 3571 const Operand& operand); 3572 void tst(Register rn, const Operand& operand) { tst(al, Best, rn, operand); } 3573 void tst(Condition cond, Register rn, const Operand& operand) { 3574 tst(cond, Best, rn, operand); 3575 } 3576 void tst(EncodingSize size, Register rn, const Operand& operand) { 3577 tst(al, size, rn, operand); 3578 } 3579 3580 void uadd16(Condition cond, Register rd, Register rn, Register rm); 3581 void uadd16(Register rd, Register rn, Register rm) { uadd16(al, rd, rn, rm); } 3582 3583 void uadd8(Condition cond, Register rd, Register rn, Register rm); 3584 void uadd8(Register rd, Register rn, Register rm) { uadd8(al, rd, rn, rm); } 3585 3586 void uasx(Condition cond, Register rd, Register rn, Register rm); 3587 void uasx(Register rd, Register rn, Register rm) { uasx(al, rd, rn, rm); } 3588 3589 void ubfx( 3590 Condition cond, Register rd, Register rn, uint32_t lsb, uint32_t width); 3591 void ubfx(Register rd, Register rn, uint32_t lsb, uint32_t width) { 3592 ubfx(al, rd, rn, lsb, width); 3593 } 3594 3595 void udf(Condition cond, EncodingSize size, uint32_t imm); 3596 void udf(uint32_t imm) { udf(al, Best, imm); } 3597 void udf(Condition cond, uint32_t imm) { udf(cond, Best, imm); } 3598 void udf(EncodingSize size, uint32_t imm) { udf(al, size, imm); } 3599 3600 void udiv(Condition cond, Register rd, Register rn, Register rm); 3601 void udiv(Register rd, Register rn, Register rm) { udiv(al, rd, rn, rm); } 3602 3603 void uhadd16(Condition cond, Register rd, Register rn, Register rm); 3604 void uhadd16(Register rd, Register rn, Register rm) { 3605 uhadd16(al, rd, rn, rm); 3606 } 3607 3608 void uhadd8(Condition cond, Register rd, Register rn, Register rm); 3609 void uhadd8(Register rd, Register rn, Register rm) { uhadd8(al, rd, rn, rm); } 3610 3611 void uhasx(Condition cond, Register rd, Register rn, Register rm); 3612 void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); } 3613 3614 void uhsax(Condition cond, Register rd, Register rn, Register rm); 3615 void uhsax(Register rd, Register rn, Register rm) { uhsax(al, rd, rn, rm); } 3616 3617 void uhsub16(Condition cond, Register rd, Register rn, Register rm); 3618 void uhsub16(Register rd, Register rn, Register rm) { 3619 uhsub16(al, rd, rn, rm); 3620 } 3621 3622 void uhsub8(Condition cond, Register rd, Register rn, Register rm); 3623 void uhsub8(Register rd, Register rn, Register rm) { uhsub8(al, rd, rn, rm); } 3624 3625 void umaal( 3626 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3627 void umaal(Register rdlo, Register rdhi, Register rn, Register rm) { 3628 umaal(al, rdlo, rdhi, rn, rm); 3629 } 3630 3631 void umlal( 3632 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3633 void umlal(Register rdlo, Register rdhi, Register rn, Register rm) { 3634 umlal(al, rdlo, rdhi, rn, rm); 3635 } 3636 3637 void umlals( 3638 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3639 void umlals(Register rdlo, Register rdhi, Register rn, Register rm) { 3640 umlals(al, rdlo, rdhi, rn, rm); 3641 } 3642 3643 void umull( 3644 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3645 void umull(Register rdlo, Register rdhi, Register rn, Register rm) { 3646 umull(al, rdlo, rdhi, rn, rm); 3647 } 3648 3649 void umulls( 3650 Condition cond, Register rdlo, Register rdhi, Register rn, Register rm); 3651 void umulls(Register rdlo, Register rdhi, Register rn, Register rm) { 3652 umulls(al, rdlo, rdhi, rn, rm); 3653 } 3654 3655 void uqadd16(Condition cond, Register rd, Register rn, Register rm); 3656 void uqadd16(Register rd, Register rn, Register rm) { 3657 uqadd16(al, rd, rn, rm); 3658 } 3659 3660 void uqadd8(Condition cond, Register rd, Register rn, Register rm); 3661 void uqadd8(Register rd, Register rn, Register rm) { uqadd8(al, rd, rn, rm); } 3662 3663 void uqasx(Condition cond, Register rd, Register rn, Register rm); 3664 void uqasx(Register rd, Register rn, Register rm) { uqasx(al, rd, rn, rm); } 3665 3666 void uqsax(Condition cond, Register rd, Register rn, Register rm); 3667 void uqsax(Register rd, Register rn, Register rm) { uqsax(al, rd, rn, rm); } 3668 3669 void uqsub16(Condition cond, Register rd, Register rn, Register rm); 3670 void uqsub16(Register rd, Register rn, Register rm) { 3671 uqsub16(al, rd, rn, rm); 3672 } 3673 3674 void uqsub8(Condition cond, Register rd, Register rn, Register rm); 3675 void uqsub8(Register rd, Register rn, Register rm) { uqsub8(al, rd, rn, rm); } 3676 3677 void usad8(Condition cond, Register rd, Register rn, Register rm); 3678 void usad8(Register rd, Register rn, Register rm) { usad8(al, rd, rn, rm); } 3679 3680 void usada8( 3681 Condition cond, Register rd, Register rn, Register rm, Register ra); 3682 void usada8(Register rd, Register rn, Register rm, Register ra) { 3683 usada8(al, rd, rn, rm, ra); 3684 } 3685 3686 void usat(Condition cond, Register rd, uint32_t imm, const Operand& operand); 3687 void usat(Register rd, uint32_t imm, const Operand& operand) { 3688 usat(al, rd, imm, operand); 3689 } 3690 3691 void usat16(Condition cond, Register rd, uint32_t imm, Register rn); 3692 void usat16(Register rd, uint32_t imm, Register rn) { 3693 usat16(al, rd, imm, rn); 3694 } 3695 3696 void usax(Condition cond, Register rd, Register rn, Register rm); 3697 void usax(Register rd, Register rn, Register rm) { usax(al, rd, rn, rm); } 3698 3699 void usub16(Condition cond, Register rd, Register rn, Register rm); 3700 void usub16(Register rd, Register rn, Register rm) { usub16(al, rd, rn, rm); } 3701 3702 void usub8(Condition cond, Register rd, Register rn, Register rm); 3703 void usub8(Register rd, Register rn, Register rm) { usub8(al, rd, rn, rm); } 3704 3705 void uxtab(Condition cond, Register rd, Register rn, const Operand& operand); 3706 void uxtab(Register rd, Register rn, const Operand& operand) { 3707 uxtab(al, rd, rn, operand); 3708 } 3709 3710 void uxtab16(Condition cond, 3711 Register rd, 3712 Register rn, 3713 const Operand& operand); 3714 void uxtab16(Register rd, Register rn, const Operand& operand) { 3715 uxtab16(al, rd, rn, operand); 3716 } 3717 3718 void uxtah(Condition cond, Register rd, Register rn, const Operand& operand); 3719 void uxtah(Register rd, Register rn, const Operand& operand) { 3720 uxtah(al, rd, rn, operand); 3721 } 3722 3723 void uxtb(Condition cond, 3724 EncodingSize size, 3725 Register rd, 3726 const Operand& operand); 3727 void uxtb(Register rd, const Operand& operand) { 3728 uxtb(al, Best, rd, operand); 3729 } 3730 void uxtb(Condition cond, Register rd, const Operand& operand) { 3731 uxtb(cond, Best, rd, operand); 3732 } 3733 void uxtb(EncodingSize size, Register rd, const Operand& operand) { 3734 uxtb(al, size, rd, operand); 3735 } 3736 3737 void uxtb16(Condition cond, Register rd, const Operand& operand); 3738 void uxtb16(Register rd, const Operand& operand) { uxtb16(al, rd, operand); } 3739 3740 void uxth(Condition cond, 3741 EncodingSize size, 3742 Register rd, 3743 const Operand& operand); 3744 void uxth(Register rd, const Operand& operand) { 3745 uxth(al, Best, rd, operand); 3746 } 3747 void uxth(Condition cond, Register rd, const Operand& operand) { 3748 uxth(cond, Best, rd, operand); 3749 } 3750 void uxth(EncodingSize size, Register rd, const Operand& operand) { 3751 uxth(al, size, rd, operand); 3752 } 3753 3754 void vaba( 3755 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3756 void vaba(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3757 vaba(al, dt, rd, rn, rm); 3758 } 3759 3760 void vaba( 3761 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3762 void vaba(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3763 vaba(al, dt, rd, rn, rm); 3764 } 3765 3766 void vabal( 3767 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3768 void vabal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3769 vabal(al, dt, rd, rn, rm); 3770 } 3771 3772 void vabd( 3773 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3774 void vabd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3775 vabd(al, dt, rd, rn, rm); 3776 } 3777 3778 void vabd( 3779 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3780 void vabd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3781 vabd(al, dt, rd, rn, rm); 3782 } 3783 3784 void vabdl( 3785 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3786 void vabdl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3787 vabdl(al, dt, rd, rn, rm); 3788 } 3789 3790 void vabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 3791 void vabs(DataType dt, DRegister rd, DRegister rm) { vabs(al, dt, rd, rm); } 3792 3793 void vabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 3794 void vabs(DataType dt, QRegister rd, QRegister rm) { vabs(al, dt, rd, rm); } 3795 3796 void vabs(Condition cond, DataType dt, SRegister rd, SRegister rm); 3797 void vabs(DataType dt, SRegister rd, SRegister rm) { vabs(al, dt, rd, rm); } 3798 3799 void vacge( 3800 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3801 void vacge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3802 vacge(al, dt, rd, rn, rm); 3803 } 3804 3805 void vacge( 3806 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3807 void vacge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3808 vacge(al, dt, rd, rn, rm); 3809 } 3810 3811 void vacgt( 3812 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3813 void vacgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3814 vacgt(al, dt, rd, rn, rm); 3815 } 3816 3817 void vacgt( 3818 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3819 void vacgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3820 vacgt(al, dt, rd, rn, rm); 3821 } 3822 3823 void vacle( 3824 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3825 void vacle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3826 vacle(al, dt, rd, rn, rm); 3827 } 3828 3829 void vacle( 3830 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3831 void vacle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3832 vacle(al, dt, rd, rn, rm); 3833 } 3834 3835 void vaclt( 3836 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3837 void vaclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3838 vaclt(al, dt, rd, rn, rm); 3839 } 3840 3841 void vaclt( 3842 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3843 void vaclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3844 vaclt(al, dt, rd, rn, rm); 3845 } 3846 3847 void vadd( 3848 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3849 void vadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3850 vadd(al, dt, rd, rn, rm); 3851 } 3852 3853 void vadd( 3854 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3855 void vadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3856 vadd(al, dt, rd, rn, rm); 3857 } 3858 3859 void vadd( 3860 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 3861 void vadd(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 3862 vadd(al, dt, rd, rn, rm); 3863 } 3864 3865 void vaddhn( 3866 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 3867 void vaddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 3868 vaddhn(al, dt, rd, rn, rm); 3869 } 3870 3871 void vaddl( 3872 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 3873 void vaddl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 3874 vaddl(al, dt, rd, rn, rm); 3875 } 3876 3877 void vaddw( 3878 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 3879 void vaddw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 3880 vaddw(al, dt, rd, rn, rm); 3881 } 3882 3883 void vand(Condition cond, 3884 DataType dt, 3885 DRegister rd, 3886 DRegister rn, 3887 const DOperand& operand); 3888 void vand(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3889 vand(al, dt, rd, rn, operand); 3890 } 3891 3892 void vand(Condition cond, 3893 DataType dt, 3894 QRegister rd, 3895 QRegister rn, 3896 const QOperand& operand); 3897 void vand(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3898 vand(al, dt, rd, rn, operand); 3899 } 3900 3901 void vbic(Condition cond, 3902 DataType dt, 3903 DRegister rd, 3904 DRegister rn, 3905 const DOperand& operand); 3906 void vbic(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 3907 vbic(al, dt, rd, rn, operand); 3908 } 3909 3910 void vbic(Condition cond, 3911 DataType dt, 3912 QRegister rd, 3913 QRegister rn, 3914 const QOperand& operand); 3915 void vbic(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 3916 vbic(al, dt, rd, rn, operand); 3917 } 3918 3919 void vbif( 3920 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3921 void vbif(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3922 vbif(al, dt, rd, rn, rm); 3923 } 3924 void vbif(DRegister rd, DRegister rn, DRegister rm) { 3925 vbif(al, kDataTypeValueNone, rd, rn, rm); 3926 } 3927 void vbif(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3928 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3929 } 3930 3931 void vbif( 3932 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3933 void vbif(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3934 vbif(al, dt, rd, rn, rm); 3935 } 3936 void vbif(QRegister rd, QRegister rn, QRegister rm) { 3937 vbif(al, kDataTypeValueNone, rd, rn, rm); 3938 } 3939 void vbif(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3940 vbif(cond, kDataTypeValueNone, rd, rn, rm); 3941 } 3942 3943 void vbit( 3944 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3945 void vbit(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3946 vbit(al, dt, rd, rn, rm); 3947 } 3948 void vbit(DRegister rd, DRegister rn, DRegister rm) { 3949 vbit(al, kDataTypeValueNone, rd, rn, rm); 3950 } 3951 void vbit(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3952 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3953 } 3954 3955 void vbit( 3956 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3957 void vbit(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3958 vbit(al, dt, rd, rn, rm); 3959 } 3960 void vbit(QRegister rd, QRegister rn, QRegister rm) { 3961 vbit(al, kDataTypeValueNone, rd, rn, rm); 3962 } 3963 void vbit(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3964 vbit(cond, kDataTypeValueNone, rd, rn, rm); 3965 } 3966 3967 void vbsl( 3968 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 3969 void vbsl(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 3970 vbsl(al, dt, rd, rn, rm); 3971 } 3972 void vbsl(DRegister rd, DRegister rn, DRegister rm) { 3973 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3974 } 3975 void vbsl(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 3976 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3977 } 3978 3979 void vbsl( 3980 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 3981 void vbsl(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 3982 vbsl(al, dt, rd, rn, rm); 3983 } 3984 void vbsl(QRegister rd, QRegister rn, QRegister rm) { 3985 vbsl(al, kDataTypeValueNone, rd, rn, rm); 3986 } 3987 void vbsl(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 3988 vbsl(cond, kDataTypeValueNone, rd, rn, rm); 3989 } 3990 3991 void vceq(Condition cond, 3992 DataType dt, 3993 DRegister rd, 3994 DRegister rm, 3995 const DOperand& operand); 3996 void vceq(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 3997 vceq(al, dt, rd, rm, operand); 3998 } 3999 4000 void vceq(Condition cond, 4001 DataType dt, 4002 QRegister rd, 4003 QRegister rm, 4004 const QOperand& operand); 4005 void vceq(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4006 vceq(al, dt, rd, rm, operand); 4007 } 4008 4009 void vceq( 4010 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4011 void vceq(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4012 vceq(al, dt, rd, rn, rm); 4013 } 4014 4015 void vceq( 4016 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4017 void vceq(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4018 vceq(al, dt, rd, rn, rm); 4019 } 4020 4021 void vcge(Condition cond, 4022 DataType dt, 4023 DRegister rd, 4024 DRegister rm, 4025 const DOperand& operand); 4026 void vcge(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4027 vcge(al, dt, rd, rm, operand); 4028 } 4029 4030 void vcge(Condition cond, 4031 DataType dt, 4032 QRegister rd, 4033 QRegister rm, 4034 const QOperand& operand); 4035 void vcge(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4036 vcge(al, dt, rd, rm, operand); 4037 } 4038 4039 void vcge( 4040 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4041 void vcge(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4042 vcge(al, dt, rd, rn, rm); 4043 } 4044 4045 void vcge( 4046 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4047 void vcge(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4048 vcge(al, dt, rd, rn, rm); 4049 } 4050 4051 void vcgt(Condition cond, 4052 DataType dt, 4053 DRegister rd, 4054 DRegister rm, 4055 const DOperand& operand); 4056 void vcgt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4057 vcgt(al, dt, rd, rm, operand); 4058 } 4059 4060 void vcgt(Condition cond, 4061 DataType dt, 4062 QRegister rd, 4063 QRegister rm, 4064 const QOperand& operand); 4065 void vcgt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4066 vcgt(al, dt, rd, rm, operand); 4067 } 4068 4069 void vcgt( 4070 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4071 void vcgt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4072 vcgt(al, dt, rd, rn, rm); 4073 } 4074 4075 void vcgt( 4076 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4077 void vcgt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4078 vcgt(al, dt, rd, rn, rm); 4079 } 4080 4081 void vcle(Condition cond, 4082 DataType dt, 4083 DRegister rd, 4084 DRegister rm, 4085 const DOperand& operand); 4086 void vcle(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4087 vcle(al, dt, rd, rm, operand); 4088 } 4089 4090 void vcle(Condition cond, 4091 DataType dt, 4092 QRegister rd, 4093 QRegister rm, 4094 const QOperand& operand); 4095 void vcle(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4096 vcle(al, dt, rd, rm, operand); 4097 } 4098 4099 void vcle( 4100 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4101 void vcle(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4102 vcle(al, dt, rd, rn, rm); 4103 } 4104 4105 void vcle( 4106 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4107 void vcle(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4108 vcle(al, dt, rd, rn, rm); 4109 } 4110 4111 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm); 4112 void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); } 4113 4114 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm); 4115 void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); } 4116 4117 void vclt(Condition cond, 4118 DataType dt, 4119 DRegister rd, 4120 DRegister rm, 4121 const DOperand& operand); 4122 void vclt(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 4123 vclt(al, dt, rd, rm, operand); 4124 } 4125 4126 void vclt(Condition cond, 4127 DataType dt, 4128 QRegister rd, 4129 QRegister rm, 4130 const QOperand& operand); 4131 void vclt(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 4132 vclt(al, dt, rd, rm, operand); 4133 } 4134 4135 void vclt( 4136 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4137 void vclt(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4138 vclt(al, dt, rd, rn, rm); 4139 } 4140 4141 void vclt( 4142 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4143 void vclt(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4144 vclt(al, dt, rd, rn, rm); 4145 } 4146 4147 void vclz(Condition cond, DataType dt, DRegister rd, DRegister rm); 4148 void vclz(DataType dt, DRegister rd, DRegister rm) { vclz(al, dt, rd, rm); } 4149 4150 void vclz(Condition cond, DataType dt, QRegister rd, QRegister rm); 4151 void vclz(DataType dt, QRegister rd, QRegister rm) { vclz(al, dt, rd, rm); } 4152 4153 void vcmp(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 4154 void vcmp(DataType dt, SRegister rd, const SOperand& operand) { 4155 vcmp(al, dt, rd, operand); 4156 } 4157 4158 void vcmp(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4159 void vcmp(DataType dt, DRegister rd, const DOperand& operand) { 4160 vcmp(al, dt, rd, operand); 4161 } 4162 4163 void vcmpe(Condition cond, 4164 DataType dt, 4165 SRegister rd, 4166 const SOperand& operand); 4167 void vcmpe(DataType dt, SRegister rd, const SOperand& operand) { 4168 vcmpe(al, dt, rd, operand); 4169 } 4170 4171 void vcmpe(Condition cond, 4172 DataType dt, 4173 DRegister rd, 4174 const DOperand& operand); 4175 void vcmpe(DataType dt, DRegister rd, const DOperand& operand) { 4176 vcmpe(al, dt, rd, operand); 4177 } 4178 4179 void vcnt(Condition cond, DataType dt, DRegister rd, DRegister rm); 4180 void vcnt(DataType dt, DRegister rd, DRegister rm) { vcnt(al, dt, rd, rm); } 4181 4182 void vcnt(Condition cond, DataType dt, QRegister rd, QRegister rm); 4183 void vcnt(DataType dt, QRegister rd, QRegister rm) { vcnt(al, dt, rd, rm); } 4184 4185 void vcvt( 4186 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4187 void vcvt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4188 vcvt(al, dt1, dt2, rd, rm); 4189 } 4190 4191 void vcvt( 4192 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4193 void vcvt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4194 vcvt(al, dt1, dt2, rd, rm); 4195 } 4196 4197 void vcvt(Condition cond, 4198 DataType dt1, 4199 DataType dt2, 4200 DRegister rd, 4201 DRegister rm, 4202 int32_t fbits); 4203 void vcvt( 4204 DataType dt1, DataType dt2, DRegister rd, DRegister rm, int32_t fbits) { 4205 vcvt(al, dt1, dt2, rd, rm, fbits); 4206 } 4207 4208 void vcvt(Condition cond, 4209 DataType dt1, 4210 DataType dt2, 4211 QRegister rd, 4212 QRegister rm, 4213 int32_t fbits); 4214 void vcvt( 4215 DataType dt1, DataType dt2, QRegister rd, QRegister rm, int32_t fbits) { 4216 vcvt(al, dt1, dt2, rd, rm, fbits); 4217 } 4218 4219 void vcvt(Condition cond, 4220 DataType dt1, 4221 DataType dt2, 4222 SRegister rd, 4223 SRegister rm, 4224 int32_t fbits); 4225 void vcvt( 4226 DataType dt1, DataType dt2, SRegister rd, SRegister rm, int32_t fbits) { 4227 vcvt(al, dt1, dt2, rd, rm, fbits); 4228 } 4229 4230 void vcvt( 4231 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4232 void vcvt(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 4233 vcvt(al, dt1, dt2, rd, rm); 4234 } 4235 4236 void vcvt( 4237 Condition cond, DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4238 void vcvt(DataType dt1, DataType dt2, QRegister rd, QRegister rm) { 4239 vcvt(al, dt1, dt2, rd, rm); 4240 } 4241 4242 void vcvt( 4243 Condition cond, DataType dt1, DataType dt2, DRegister rd, QRegister rm); 4244 void vcvt(DataType dt1, DataType dt2, DRegister rd, QRegister rm) { 4245 vcvt(al, dt1, dt2, rd, rm); 4246 } 4247 4248 void vcvt( 4249 Condition cond, DataType dt1, DataType dt2, QRegister rd, DRegister rm); 4250 void vcvt(DataType dt1, DataType dt2, QRegister rd, DRegister rm) { 4251 vcvt(al, dt1, dt2, rd, rm); 4252 } 4253 4254 void vcvt( 4255 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4256 void vcvt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4257 vcvt(al, dt1, dt2, rd, rm); 4258 } 4259 4260 void vcvta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4261 4262 void vcvta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4263 4264 void vcvta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4265 4266 void vcvta(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4267 4268 void vcvtb( 4269 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4270 void vcvtb(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4271 vcvtb(al, dt1, dt2, rd, rm); 4272 } 4273 4274 void vcvtb( 4275 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4276 void vcvtb(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4277 vcvtb(al, dt1, dt2, rd, rm); 4278 } 4279 4280 void vcvtb( 4281 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4282 void vcvtb(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4283 vcvtb(al, dt1, dt2, rd, rm); 4284 } 4285 4286 void vcvtm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4287 4288 void vcvtm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4289 4290 void vcvtm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4291 4292 void vcvtm(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4293 4294 void vcvtn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4295 4296 void vcvtn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4297 4298 void vcvtn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4299 4300 void vcvtn(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4301 4302 void vcvtp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 4303 4304 void vcvtp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 4305 4306 void vcvtp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4307 4308 void vcvtp(DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4309 4310 void vcvtr( 4311 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4312 void vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4313 vcvtr(al, dt1, dt2, rd, rm); 4314 } 4315 4316 void vcvtr( 4317 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4318 void vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4319 vcvtr(al, dt1, dt2, rd, rm); 4320 } 4321 4322 void vcvtt( 4323 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 4324 void vcvtt(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 4325 vcvtt(al, dt1, dt2, rd, rm); 4326 } 4327 4328 void vcvtt( 4329 Condition cond, DataType dt1, DataType dt2, DRegister rd, SRegister rm); 4330 void vcvtt(DataType dt1, DataType dt2, DRegister rd, SRegister rm) { 4331 vcvtt(al, dt1, dt2, rd, rm); 4332 } 4333 4334 void vcvtt( 4335 Condition cond, DataType dt1, DataType dt2, SRegister rd, DRegister rm); 4336 void vcvtt(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { 4337 vcvtt(al, dt1, dt2, rd, rm); 4338 } 4339 4340 void vdiv( 4341 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4342 void vdiv(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4343 vdiv(al, dt, rd, rn, rm); 4344 } 4345 4346 void vdiv( 4347 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4348 void vdiv(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4349 vdiv(al, dt, rd, rn, rm); 4350 } 4351 4352 void vdup(Condition cond, DataType dt, QRegister rd, Register rt); 4353 void vdup(DataType dt, QRegister rd, Register rt) { vdup(al, dt, rd, rt); } 4354 4355 void vdup(Condition cond, DataType dt, DRegister rd, Register rt); 4356 void vdup(DataType dt, DRegister rd, Register rt) { vdup(al, dt, rd, rt); } 4357 4358 void vdup(Condition cond, DataType dt, DRegister rd, DRegisterLane rm); 4359 void vdup(DataType dt, DRegister rd, DRegisterLane rm) { 4360 vdup(al, dt, rd, rm); 4361 } 4362 4363 void vdup(Condition cond, DataType dt, QRegister rd, DRegisterLane rm); 4364 void vdup(DataType dt, QRegister rd, DRegisterLane rm) { 4365 vdup(al, dt, rd, rm); 4366 } 4367 4368 void veor( 4369 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4370 void veor(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4371 veor(al, dt, rd, rn, rm); 4372 } 4373 void veor(DRegister rd, DRegister rn, DRegister rm) { 4374 veor(al, kDataTypeValueNone, rd, rn, rm); 4375 } 4376 void veor(Condition cond, DRegister rd, DRegister rn, DRegister rm) { 4377 veor(cond, kDataTypeValueNone, rd, rn, rm); 4378 } 4379 4380 void veor( 4381 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4382 void veor(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4383 veor(al, dt, rd, rn, rm); 4384 } 4385 void veor(QRegister rd, QRegister rn, QRegister rm) { 4386 veor(al, kDataTypeValueNone, rd, rn, rm); 4387 } 4388 void veor(Condition cond, QRegister rd, QRegister rn, QRegister rm) { 4389 veor(cond, kDataTypeValueNone, rd, rn, rm); 4390 } 4391 4392 void vext(Condition cond, 4393 DataType dt, 4394 DRegister rd, 4395 DRegister rn, 4396 DRegister rm, 4397 const DOperand& operand); 4398 void vext(DataType dt, 4399 DRegister rd, 4400 DRegister rn, 4401 DRegister rm, 4402 const DOperand& operand) { 4403 vext(al, dt, rd, rn, rm, operand); 4404 } 4405 4406 void vext(Condition cond, 4407 DataType dt, 4408 QRegister rd, 4409 QRegister rn, 4410 QRegister rm, 4411 const QOperand& operand); 4412 void vext(DataType dt, 4413 QRegister rd, 4414 QRegister rn, 4415 QRegister rm, 4416 const QOperand& operand) { 4417 vext(al, dt, rd, rn, rm, operand); 4418 } 4419 4420 void vfma( 4421 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4422 void vfma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4423 vfma(al, dt, rd, rn, rm); 4424 } 4425 4426 void vfma( 4427 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4428 void vfma(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4429 vfma(al, dt, rd, rn, rm); 4430 } 4431 4432 void vfma( 4433 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4434 void vfma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4435 vfma(al, dt, rd, rn, rm); 4436 } 4437 4438 void vfms( 4439 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4440 void vfms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4441 vfms(al, dt, rd, rn, rm); 4442 } 4443 4444 void vfms( 4445 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4446 void vfms(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4447 vfms(al, dt, rd, rn, rm); 4448 } 4449 4450 void vfms( 4451 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4452 void vfms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4453 vfms(al, dt, rd, rn, rm); 4454 } 4455 4456 void vfnma( 4457 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4458 void vfnma(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4459 vfnma(al, dt, rd, rn, rm); 4460 } 4461 4462 void vfnma( 4463 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4464 void vfnma(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4465 vfnma(al, dt, rd, rn, rm); 4466 } 4467 4468 void vfnms( 4469 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4470 void vfnms(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4471 vfnms(al, dt, rd, rn, rm); 4472 } 4473 4474 void vfnms( 4475 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4476 void vfnms(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4477 vfnms(al, dt, rd, rn, rm); 4478 } 4479 4480 void vhadd( 4481 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4482 void vhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4483 vhadd(al, dt, rd, rn, rm); 4484 } 4485 4486 void vhadd( 4487 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4488 void vhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4489 vhadd(al, dt, rd, rn, rm); 4490 } 4491 4492 void vhsub( 4493 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4494 void vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4495 vhsub(al, dt, rd, rn, rm); 4496 } 4497 4498 void vhsub( 4499 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4500 void vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4501 vhsub(al, dt, rd, rn, rm); 4502 } 4503 4504 void vld1(Condition cond, 4505 DataType dt, 4506 const NeonRegisterList& nreglist, 4507 const AlignedMemOperand& operand); 4508 void vld1(DataType dt, 4509 const NeonRegisterList& nreglist, 4510 const AlignedMemOperand& operand) { 4511 vld1(al, dt, nreglist, operand); 4512 } 4513 4514 void vld2(Condition cond, 4515 DataType dt, 4516 const NeonRegisterList& nreglist, 4517 const AlignedMemOperand& operand); 4518 void vld2(DataType dt, 4519 const NeonRegisterList& nreglist, 4520 const AlignedMemOperand& operand) { 4521 vld2(al, dt, nreglist, operand); 4522 } 4523 4524 void vld3(Condition cond, 4525 DataType dt, 4526 const NeonRegisterList& nreglist, 4527 const AlignedMemOperand& operand); 4528 void vld3(DataType dt, 4529 const NeonRegisterList& nreglist, 4530 const AlignedMemOperand& operand) { 4531 vld3(al, dt, nreglist, operand); 4532 } 4533 4534 void vld3(Condition cond, 4535 DataType dt, 4536 const NeonRegisterList& nreglist, 4537 const MemOperand& operand); 4538 void vld3(DataType dt, 4539 const NeonRegisterList& nreglist, 4540 const MemOperand& operand) { 4541 vld3(al, dt, nreglist, operand); 4542 } 4543 4544 void vld4(Condition cond, 4545 DataType dt, 4546 const NeonRegisterList& nreglist, 4547 const AlignedMemOperand& operand); 4548 void vld4(DataType dt, 4549 const NeonRegisterList& nreglist, 4550 const AlignedMemOperand& operand) { 4551 vld4(al, dt, nreglist, operand); 4552 } 4553 4554 void vldm(Condition cond, 4555 DataType dt, 4556 Register rn, 4557 WriteBack write_back, 4558 DRegisterList dreglist); 4559 void vldm(DataType dt, 4560 Register rn, 4561 WriteBack write_back, 4562 DRegisterList dreglist) { 4563 vldm(al, dt, rn, write_back, dreglist); 4564 } 4565 void vldm(Register rn, WriteBack write_back, DRegisterList dreglist) { 4566 vldm(al, kDataTypeValueNone, rn, write_back, dreglist); 4567 } 4568 void vldm(Condition cond, 4569 Register rn, 4570 WriteBack write_back, 4571 DRegisterList dreglist) { 4572 vldm(cond, kDataTypeValueNone, rn, write_back, dreglist); 4573 } 4574 4575 void vldm(Condition cond, 4576 DataType dt, 4577 Register rn, 4578 WriteBack write_back, 4579 SRegisterList sreglist); 4580 void vldm(DataType dt, 4581 Register rn, 4582 WriteBack write_back, 4583 SRegisterList sreglist) { 4584 vldm(al, dt, rn, write_back, sreglist); 4585 } 4586 void vldm(Register rn, WriteBack write_back, SRegisterList sreglist) { 4587 vldm(al, kDataTypeValueNone, rn, write_back, sreglist); 4588 } 4589 void vldm(Condition cond, 4590 Register rn, 4591 WriteBack write_back, 4592 SRegisterList sreglist) { 4593 vldm(cond, kDataTypeValueNone, rn, write_back, sreglist); 4594 } 4595 4596 void vldmdb(Condition cond, 4597 DataType dt, 4598 Register rn, 4599 WriteBack write_back, 4600 DRegisterList dreglist); 4601 void vldmdb(DataType dt, 4602 Register rn, 4603 WriteBack write_back, 4604 DRegisterList dreglist) { 4605 vldmdb(al, dt, rn, write_back, dreglist); 4606 } 4607 void vldmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 4608 vldmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 4609 } 4610 void vldmdb(Condition cond, 4611 Register rn, 4612 WriteBack write_back, 4613 DRegisterList dreglist) { 4614 vldmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 4615 } 4616 4617 void vldmdb(Condition cond, 4618 DataType dt, 4619 Register rn, 4620 WriteBack write_back, 4621 SRegisterList sreglist); 4622 void vldmdb(DataType dt, 4623 Register rn, 4624 WriteBack write_back, 4625 SRegisterList sreglist) { 4626 vldmdb(al, dt, rn, write_back, sreglist); 4627 } 4628 void vldmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 4629 vldmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 4630 } 4631 void vldmdb(Condition cond, 4632 Register rn, 4633 WriteBack write_back, 4634 SRegisterList sreglist) { 4635 vldmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 4636 } 4637 4638 void vldmia(Condition cond, 4639 DataType dt, 4640 Register rn, 4641 WriteBack write_back, 4642 DRegisterList dreglist); 4643 void vldmia(DataType dt, 4644 Register rn, 4645 WriteBack write_back, 4646 DRegisterList dreglist) { 4647 vldmia(al, dt, rn, write_back, dreglist); 4648 } 4649 void vldmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 4650 vldmia(al, kDataTypeValueNone, rn, write_back, dreglist); 4651 } 4652 void vldmia(Condition cond, 4653 Register rn, 4654 WriteBack write_back, 4655 DRegisterList dreglist) { 4656 vldmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 4657 } 4658 4659 void vldmia(Condition cond, 4660 DataType dt, 4661 Register rn, 4662 WriteBack write_back, 4663 SRegisterList sreglist); 4664 void vldmia(DataType dt, 4665 Register rn, 4666 WriteBack write_back, 4667 SRegisterList sreglist) { 4668 vldmia(al, dt, rn, write_back, sreglist); 4669 } 4670 void vldmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 4671 vldmia(al, kDataTypeValueNone, rn, write_back, sreglist); 4672 } 4673 void vldmia(Condition cond, 4674 Register rn, 4675 WriteBack write_back, 4676 SRegisterList sreglist) { 4677 vldmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 4678 } 4679 4680 void vldr(Condition cond, DataType dt, DRegister rd, Location* location); 4681 bool vldr_info(Condition cond, 4682 DataType dt, 4683 DRegister rd, 4684 Location* location, 4685 const struct ReferenceInfo** info); 4686 void vldr(DataType dt, DRegister rd, Location* location) { 4687 vldr(al, dt, rd, location); 4688 } 4689 void vldr(DRegister rd, Location* location) { 4690 vldr(al, Untyped64, rd, location); 4691 } 4692 void vldr(Condition cond, DRegister rd, Location* location) { 4693 vldr(cond, Untyped64, rd, location); 4694 } 4695 4696 void vldr(Condition cond, 4697 DataType dt, 4698 DRegister rd, 4699 const MemOperand& operand); 4700 void vldr(DataType dt, DRegister rd, const MemOperand& operand) { 4701 vldr(al, dt, rd, operand); 4702 } 4703 void vldr(DRegister rd, const MemOperand& operand) { 4704 vldr(al, Untyped64, rd, operand); 4705 } 4706 void vldr(Condition cond, DRegister rd, const MemOperand& operand) { 4707 vldr(cond, Untyped64, rd, operand); 4708 } 4709 4710 void vldr(Condition cond, DataType dt, SRegister rd, Location* location); 4711 bool vldr_info(Condition cond, 4712 DataType dt, 4713 SRegister rd, 4714 Location* location, 4715 const struct ReferenceInfo** info); 4716 void vldr(DataType dt, SRegister rd, Location* location) { 4717 vldr(al, dt, rd, location); 4718 } 4719 void vldr(SRegister rd, Location* location) { 4720 vldr(al, Untyped32, rd, location); 4721 } 4722 void vldr(Condition cond, SRegister rd, Location* location) { 4723 vldr(cond, Untyped32, rd, location); 4724 } 4725 4726 void vldr(Condition cond, 4727 DataType dt, 4728 SRegister rd, 4729 const MemOperand& operand); 4730 void vldr(DataType dt, SRegister rd, const MemOperand& operand) { 4731 vldr(al, dt, rd, operand); 4732 } 4733 void vldr(SRegister rd, const MemOperand& operand) { 4734 vldr(al, Untyped32, rd, operand); 4735 } 4736 void vldr(Condition cond, SRegister rd, const MemOperand& operand) { 4737 vldr(cond, Untyped32, rd, operand); 4738 } 4739 4740 void vmax( 4741 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4742 void vmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4743 vmax(al, dt, rd, rn, rm); 4744 } 4745 4746 void vmax( 4747 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4748 void vmax(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4749 vmax(al, dt, rd, rn, rm); 4750 } 4751 4752 void vmaxnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4753 4754 void vmaxnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4755 4756 void vmaxnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4757 4758 void vmin( 4759 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4760 void vmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4761 vmin(al, dt, rd, rn, rm); 4762 } 4763 4764 void vmin( 4765 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4766 void vmin(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4767 vmin(al, dt, rd, rn, rm); 4768 } 4769 4770 void vminnm(DataType dt, DRegister rd, DRegister rn, DRegister rm); 4771 4772 void vminnm(DataType dt, QRegister rd, QRegister rn, QRegister rm); 4773 4774 void vminnm(DataType dt, SRegister rd, SRegister rn, SRegister rm); 4775 4776 void vmla(Condition cond, 4777 DataType dt, 4778 DRegister rd, 4779 DRegister rn, 4780 DRegisterLane rm); 4781 void vmla(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4782 vmla(al, dt, rd, rn, rm); 4783 } 4784 4785 void vmla(Condition cond, 4786 DataType dt, 4787 QRegister rd, 4788 QRegister rn, 4789 DRegisterLane rm); 4790 void vmla(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4791 vmla(al, dt, rd, rn, rm); 4792 } 4793 4794 void vmla( 4795 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4796 void vmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4797 vmla(al, dt, rd, rn, rm); 4798 } 4799 4800 void vmla( 4801 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4802 void vmla(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4803 vmla(al, dt, rd, rn, rm); 4804 } 4805 4806 void vmla( 4807 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4808 void vmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4809 vmla(al, dt, rd, rn, rm); 4810 } 4811 4812 void vmlal(Condition cond, 4813 DataType dt, 4814 QRegister rd, 4815 DRegister rn, 4816 DRegisterLane rm); 4817 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4818 vmlal(al, dt, rd, rn, rm); 4819 } 4820 4821 void vmlal( 4822 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4823 void vmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4824 vmlal(al, dt, rd, rn, rm); 4825 } 4826 4827 void vmls(Condition cond, 4828 DataType dt, 4829 DRegister rd, 4830 DRegister rn, 4831 DRegisterLane rm); 4832 void vmls(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 4833 vmls(al, dt, rd, rn, rm); 4834 } 4835 4836 void vmls(Condition cond, 4837 DataType dt, 4838 QRegister rd, 4839 QRegister rn, 4840 DRegisterLane rm); 4841 void vmls(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 4842 vmls(al, dt, rd, rn, rm); 4843 } 4844 4845 void vmls( 4846 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4847 void vmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4848 vmls(al, dt, rd, rn, rm); 4849 } 4850 4851 void vmls( 4852 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4853 void vmls(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4854 vmls(al, dt, rd, rn, rm); 4855 } 4856 4857 void vmls( 4858 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4859 void vmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4860 vmls(al, dt, rd, rn, rm); 4861 } 4862 4863 void vmlsl(Condition cond, 4864 DataType dt, 4865 QRegister rd, 4866 DRegister rn, 4867 DRegisterLane rm); 4868 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 4869 vmlsl(al, dt, rd, rn, rm); 4870 } 4871 4872 void vmlsl( 4873 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 4874 void vmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 4875 vmlsl(al, dt, rd, rn, rm); 4876 } 4877 4878 void vmov(Condition cond, Register rt, SRegister rn); 4879 void vmov(Register rt, SRegister rn) { vmov(al, rt, rn); } 4880 4881 void vmov(Condition cond, SRegister rn, Register rt); 4882 void vmov(SRegister rn, Register rt) { vmov(al, rn, rt); } 4883 4884 void vmov(Condition cond, Register rt, Register rt2, DRegister rm); 4885 void vmov(Register rt, Register rt2, DRegister rm) { vmov(al, rt, rt2, rm); } 4886 4887 void vmov(Condition cond, DRegister rm, Register rt, Register rt2); 4888 void vmov(DRegister rm, Register rt, Register rt2) { vmov(al, rm, rt, rt2); } 4889 4890 void vmov( 4891 Condition cond, Register rt, Register rt2, SRegister rm, SRegister rm1); 4892 void vmov(Register rt, Register rt2, SRegister rm, SRegister rm1) { 4893 vmov(al, rt, rt2, rm, rm1); 4894 } 4895 4896 void vmov( 4897 Condition cond, SRegister rm, SRegister rm1, Register rt, Register rt2); 4898 void vmov(SRegister rm, SRegister rm1, Register rt, Register rt2) { 4899 vmov(al, rm, rm1, rt, rt2); 4900 } 4901 4902 void vmov(Condition cond, DataType dt, DRegisterLane rd, Register rt); 4903 void vmov(DataType dt, DRegisterLane rd, Register rt) { 4904 vmov(al, dt, rd, rt); 4905 } 4906 void vmov(DRegisterLane rd, Register rt) { 4907 vmov(al, kDataTypeValueNone, rd, rt); 4908 } 4909 void vmov(Condition cond, DRegisterLane rd, Register rt) { 4910 vmov(cond, kDataTypeValueNone, rd, rt); 4911 } 4912 4913 void vmov(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 4914 void vmov(DataType dt, DRegister rd, const DOperand& operand) { 4915 vmov(al, dt, rd, operand); 4916 } 4917 4918 void vmov(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 4919 void vmov(DataType dt, QRegister rd, const QOperand& operand) { 4920 vmov(al, dt, rd, operand); 4921 } 4922 4923 void vmov(Condition cond, DataType dt, SRegister rd, const SOperand& operand); 4924 void vmov(DataType dt, SRegister rd, const SOperand& operand) { 4925 vmov(al, dt, rd, operand); 4926 } 4927 4928 void vmov(Condition cond, DataType dt, Register rt, DRegisterLane rn); 4929 void vmov(DataType dt, Register rt, DRegisterLane rn) { 4930 vmov(al, dt, rt, rn); 4931 } 4932 void vmov(Register rt, DRegisterLane rn) { 4933 vmov(al, kDataTypeValueNone, rt, rn); 4934 } 4935 void vmov(Condition cond, Register rt, DRegisterLane rn) { 4936 vmov(cond, kDataTypeValueNone, rt, rn); 4937 } 4938 4939 void vmovl(Condition cond, DataType dt, QRegister rd, DRegister rm); 4940 void vmovl(DataType dt, QRegister rd, DRegister rm) { vmovl(al, dt, rd, rm); } 4941 4942 void vmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 4943 void vmovn(DataType dt, DRegister rd, QRegister rm) { vmovn(al, dt, rd, rm); } 4944 4945 void vmrs(Condition cond, RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg); 4946 void vmrs(RegisterOrAPSR_nzcv rt, SpecialFPRegister spec_reg) { 4947 vmrs(al, rt, spec_reg); 4948 } 4949 4950 void vmsr(Condition cond, SpecialFPRegister spec_reg, Register rt); 4951 void vmsr(SpecialFPRegister spec_reg, Register rt) { vmsr(al, spec_reg, rt); } 4952 4953 void vmul(Condition cond, 4954 DataType dt, 4955 DRegister rd, 4956 DRegister rn, 4957 DRegister dm, 4958 unsigned index); 4959 void vmul( 4960 DataType dt, DRegister rd, DRegister rn, DRegister dm, unsigned index) { 4961 vmul(al, dt, rd, rn, dm, index); 4962 } 4963 4964 void vmul(Condition cond, 4965 DataType dt, 4966 QRegister rd, 4967 QRegister rn, 4968 DRegister dm, 4969 unsigned index); 4970 void vmul( 4971 DataType dt, QRegister rd, QRegister rn, DRegister dm, unsigned index) { 4972 vmul(al, dt, rd, rn, dm, index); 4973 } 4974 4975 void vmul( 4976 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 4977 void vmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 4978 vmul(al, dt, rd, rn, rm); 4979 } 4980 4981 void vmul( 4982 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 4983 void vmul(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 4984 vmul(al, dt, rd, rn, rm); 4985 } 4986 4987 void vmul( 4988 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 4989 void vmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 4990 vmul(al, dt, rd, rn, rm); 4991 } 4992 4993 void vmull(Condition cond, 4994 DataType dt, 4995 QRegister rd, 4996 DRegister rn, 4997 DRegister dm, 4998 unsigned index); 4999 void vmull( 5000 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 5001 vmull(al, dt, rd, rn, dm, index); 5002 } 5003 5004 void vmull( 5005 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5006 void vmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5007 vmull(al, dt, rd, rn, rm); 5008 } 5009 5010 void vmvn(Condition cond, DataType dt, DRegister rd, const DOperand& operand); 5011 void vmvn(DataType dt, DRegister rd, const DOperand& operand) { 5012 vmvn(al, dt, rd, operand); 5013 } 5014 5015 void vmvn(Condition cond, DataType dt, QRegister rd, const QOperand& operand); 5016 void vmvn(DataType dt, QRegister rd, const QOperand& operand) { 5017 vmvn(al, dt, rd, operand); 5018 } 5019 5020 void vneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 5021 void vneg(DataType dt, DRegister rd, DRegister rm) { vneg(al, dt, rd, rm); } 5022 5023 void vneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 5024 void vneg(DataType dt, QRegister rd, QRegister rm) { vneg(al, dt, rd, rm); } 5025 5026 void vneg(Condition cond, DataType dt, SRegister rd, SRegister rm); 5027 void vneg(DataType dt, SRegister rd, SRegister rm) { vneg(al, dt, rd, rm); } 5028 5029 void vnmla( 5030 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 5031 void vnmla(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5032 vnmla(al, dt, rd, rn, rm); 5033 } 5034 5035 void vnmla( 5036 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5037 void vnmla(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5038 vnmla(al, dt, rd, rn, rm); 5039 } 5040 5041 void vnmls( 5042 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 5043 void vnmls(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5044 vnmls(al, dt, rd, rn, rm); 5045 } 5046 5047 void vnmls( 5048 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5049 void vnmls(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5050 vnmls(al, dt, rd, rn, rm); 5051 } 5052 5053 void vnmul( 5054 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 5055 void vnmul(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 5056 vnmul(al, dt, rd, rn, rm); 5057 } 5058 5059 void vnmul( 5060 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5061 void vnmul(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5062 vnmul(al, dt, rd, rn, rm); 5063 } 5064 5065 void vorn(Condition cond, 5066 DataType dt, 5067 DRegister rd, 5068 DRegister rn, 5069 const DOperand& operand); 5070 void vorn(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5071 vorn(al, dt, rd, rn, operand); 5072 } 5073 5074 void vorn(Condition cond, 5075 DataType dt, 5076 QRegister rd, 5077 QRegister rn, 5078 const QOperand& operand); 5079 void vorn(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5080 vorn(al, dt, rd, rn, operand); 5081 } 5082 5083 void vorr(Condition cond, 5084 DataType dt, 5085 DRegister rd, 5086 DRegister rn, 5087 const DOperand& operand); 5088 void vorr(DataType dt, DRegister rd, DRegister rn, const DOperand& operand) { 5089 vorr(al, dt, rd, rn, operand); 5090 } 5091 void vorr(DRegister rd, DRegister rn, const DOperand& operand) { 5092 vorr(al, kDataTypeValueNone, rd, rn, operand); 5093 } 5094 void vorr(Condition cond, 5095 DRegister rd, 5096 DRegister rn, 5097 const DOperand& operand) { 5098 vorr(cond, kDataTypeValueNone, rd, rn, operand); 5099 } 5100 5101 void vorr(Condition cond, 5102 DataType dt, 5103 QRegister rd, 5104 QRegister rn, 5105 const QOperand& operand); 5106 void vorr(DataType dt, QRegister rd, QRegister rn, const QOperand& operand) { 5107 vorr(al, dt, rd, rn, operand); 5108 } 5109 void vorr(QRegister rd, QRegister rn, const QOperand& operand) { 5110 vorr(al, kDataTypeValueNone, rd, rn, operand); 5111 } 5112 void vorr(Condition cond, 5113 QRegister rd, 5114 QRegister rn, 5115 const QOperand& operand) { 5116 vorr(cond, kDataTypeValueNone, rd, rn, operand); 5117 } 5118 5119 void vpadal(Condition cond, DataType dt, DRegister rd, DRegister rm); 5120 void vpadal(DataType dt, DRegister rd, DRegister rm) { 5121 vpadal(al, dt, rd, rm); 5122 } 5123 5124 void vpadal(Condition cond, DataType dt, QRegister rd, QRegister rm); 5125 void vpadal(DataType dt, QRegister rd, QRegister rm) { 5126 vpadal(al, dt, rd, rm); 5127 } 5128 5129 void vpadd( 5130 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5131 void vpadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5132 vpadd(al, dt, rd, rn, rm); 5133 } 5134 5135 void vpaddl(Condition cond, DataType dt, DRegister rd, DRegister rm); 5136 void vpaddl(DataType dt, DRegister rd, DRegister rm) { 5137 vpaddl(al, dt, rd, rm); 5138 } 5139 5140 void vpaddl(Condition cond, DataType dt, QRegister rd, QRegister rm); 5141 void vpaddl(DataType dt, QRegister rd, QRegister rm) { 5142 vpaddl(al, dt, rd, rm); 5143 } 5144 5145 void vpmax( 5146 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5147 void vpmax(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5148 vpmax(al, dt, rd, rn, rm); 5149 } 5150 5151 void vpmin( 5152 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5153 void vpmin(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5154 vpmin(al, dt, rd, rn, rm); 5155 } 5156 5157 void vpop(Condition cond, DataType dt, DRegisterList dreglist); 5158 void vpop(DataType dt, DRegisterList dreglist) { vpop(al, dt, dreglist); } 5159 void vpop(DRegisterList dreglist) { vpop(al, kDataTypeValueNone, dreglist); } 5160 void vpop(Condition cond, DRegisterList dreglist) { 5161 vpop(cond, kDataTypeValueNone, dreglist); 5162 } 5163 5164 void vpop(Condition cond, DataType dt, SRegisterList sreglist); 5165 void vpop(DataType dt, SRegisterList sreglist) { vpop(al, dt, sreglist); } 5166 void vpop(SRegisterList sreglist) { vpop(al, kDataTypeValueNone, sreglist); } 5167 void vpop(Condition cond, SRegisterList sreglist) { 5168 vpop(cond, kDataTypeValueNone, sreglist); 5169 } 5170 5171 void vpush(Condition cond, DataType dt, DRegisterList dreglist); 5172 void vpush(DataType dt, DRegisterList dreglist) { vpush(al, dt, dreglist); } 5173 void vpush(DRegisterList dreglist) { 5174 vpush(al, kDataTypeValueNone, dreglist); 5175 } 5176 void vpush(Condition cond, DRegisterList dreglist) { 5177 vpush(cond, kDataTypeValueNone, dreglist); 5178 } 5179 5180 void vpush(Condition cond, DataType dt, SRegisterList sreglist); 5181 void vpush(DataType dt, SRegisterList sreglist) { vpush(al, dt, sreglist); } 5182 void vpush(SRegisterList sreglist) { 5183 vpush(al, kDataTypeValueNone, sreglist); 5184 } 5185 void vpush(Condition cond, SRegisterList sreglist) { 5186 vpush(cond, kDataTypeValueNone, sreglist); 5187 } 5188 5189 void vqabs(Condition cond, DataType dt, DRegister rd, DRegister rm); 5190 void vqabs(DataType dt, DRegister rd, DRegister rm) { vqabs(al, dt, rd, rm); } 5191 5192 void vqabs(Condition cond, DataType dt, QRegister rd, QRegister rm); 5193 void vqabs(DataType dt, QRegister rd, QRegister rm) { vqabs(al, dt, rd, rm); } 5194 5195 void vqadd( 5196 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5197 void vqadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5198 vqadd(al, dt, rd, rn, rm); 5199 } 5200 5201 void vqadd( 5202 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5203 void vqadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5204 vqadd(al, dt, rd, rn, rm); 5205 } 5206 5207 void vqdmlal( 5208 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5209 void vqdmlal(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5210 vqdmlal(al, dt, rd, rn, rm); 5211 } 5212 5213 void vqdmlal(Condition cond, 5214 DataType dt, 5215 QRegister rd, 5216 DRegister rn, 5217 DRegister dm, 5218 unsigned index); 5219 void vqdmlal( 5220 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 5221 vqdmlal(al, dt, rd, rn, dm, index); 5222 } 5223 5224 void vqdmlsl( 5225 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5226 void vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5227 vqdmlsl(al, dt, rd, rn, rm); 5228 } 5229 5230 void vqdmlsl(Condition cond, 5231 DataType dt, 5232 QRegister rd, 5233 DRegister rn, 5234 DRegister dm, 5235 unsigned index); 5236 void vqdmlsl( 5237 DataType dt, QRegister rd, DRegister rn, DRegister dm, unsigned index) { 5238 vqdmlsl(al, dt, rd, rn, dm, index); 5239 } 5240 5241 void vqdmulh( 5242 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5243 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5244 vqdmulh(al, dt, rd, rn, rm); 5245 } 5246 5247 void vqdmulh( 5248 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5249 void vqdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5250 vqdmulh(al, dt, rd, rn, rm); 5251 } 5252 5253 void vqdmulh(Condition cond, 5254 DataType dt, 5255 DRegister rd, 5256 DRegister rn, 5257 DRegisterLane rm); 5258 void vqdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 5259 vqdmulh(al, dt, rd, rn, rm); 5260 } 5261 5262 void vqdmulh(Condition cond, 5263 DataType dt, 5264 QRegister rd, 5265 QRegister rn, 5266 DRegisterLane rm); 5267 void vqdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 5268 vqdmulh(al, dt, rd, rn, rm); 5269 } 5270 5271 void vqdmull( 5272 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 5273 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 5274 vqdmull(al, dt, rd, rn, rm); 5275 } 5276 5277 void vqdmull(Condition cond, 5278 DataType dt, 5279 QRegister rd, 5280 DRegister rn, 5281 DRegisterLane rm); 5282 void vqdmull(DataType dt, QRegister rd, DRegister rn, DRegisterLane rm) { 5283 vqdmull(al, dt, rd, rn, rm); 5284 } 5285 5286 void vqmovn(Condition cond, DataType dt, DRegister rd, QRegister rm); 5287 void vqmovn(DataType dt, DRegister rd, QRegister rm) { 5288 vqmovn(al, dt, rd, rm); 5289 } 5290 5291 void vqmovun(Condition cond, DataType dt, DRegister rd, QRegister rm); 5292 void vqmovun(DataType dt, DRegister rd, QRegister rm) { 5293 vqmovun(al, dt, rd, rm); 5294 } 5295 5296 void vqneg(Condition cond, DataType dt, DRegister rd, DRegister rm); 5297 void vqneg(DataType dt, DRegister rd, DRegister rm) { vqneg(al, dt, rd, rm); } 5298 5299 void vqneg(Condition cond, DataType dt, QRegister rd, QRegister rm); 5300 void vqneg(DataType dt, QRegister rd, QRegister rm) { vqneg(al, dt, rd, rm); } 5301 5302 void vqrdmulh( 5303 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5304 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5305 vqrdmulh(al, dt, rd, rn, rm); 5306 } 5307 5308 void vqrdmulh( 5309 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5310 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5311 vqrdmulh(al, dt, rd, rn, rm); 5312 } 5313 5314 void vqrdmulh(Condition cond, 5315 DataType dt, 5316 DRegister rd, 5317 DRegister rn, 5318 DRegisterLane rm); 5319 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { 5320 vqrdmulh(al, dt, rd, rn, rm); 5321 } 5322 5323 void vqrdmulh(Condition cond, 5324 DataType dt, 5325 QRegister rd, 5326 QRegister rn, 5327 DRegisterLane rm); 5328 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, DRegisterLane rm) { 5329 vqrdmulh(al, dt, rd, rn, rm); 5330 } 5331 5332 void vqrshl( 5333 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 5334 void vqrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 5335 vqrshl(al, dt, rd, rm, rn); 5336 } 5337 5338 void vqrshl( 5339 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 5340 void vqrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 5341 vqrshl(al, dt, rd, rm, rn); 5342 } 5343 5344 void vqrshrn(Condition cond, 5345 DataType dt, 5346 DRegister rd, 5347 QRegister rm, 5348 const QOperand& operand); 5349 void vqrshrn(DataType dt, 5350 DRegister rd, 5351 QRegister rm, 5352 const QOperand& operand) { 5353 vqrshrn(al, dt, rd, rm, operand); 5354 } 5355 5356 void vqrshrun(Condition cond, 5357 DataType dt, 5358 DRegister rd, 5359 QRegister rm, 5360 const QOperand& operand); 5361 void vqrshrun(DataType dt, 5362 DRegister rd, 5363 QRegister rm, 5364 const QOperand& operand) { 5365 vqrshrun(al, dt, rd, rm, operand); 5366 } 5367 5368 void vqshl(Condition cond, 5369 DataType dt, 5370 DRegister rd, 5371 DRegister rm, 5372 const DOperand& operand); 5373 void vqshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5374 vqshl(al, dt, rd, rm, operand); 5375 } 5376 5377 void vqshl(Condition cond, 5378 DataType dt, 5379 QRegister rd, 5380 QRegister rm, 5381 const QOperand& operand); 5382 void vqshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5383 vqshl(al, dt, rd, rm, operand); 5384 } 5385 5386 void vqshlu(Condition cond, 5387 DataType dt, 5388 DRegister rd, 5389 DRegister rm, 5390 const DOperand& operand); 5391 void vqshlu(DataType dt, 5392 DRegister rd, 5393 DRegister rm, 5394 const DOperand& operand) { 5395 vqshlu(al, dt, rd, rm, operand); 5396 } 5397 5398 void vqshlu(Condition cond, 5399 DataType dt, 5400 QRegister rd, 5401 QRegister rm, 5402 const QOperand& operand); 5403 void vqshlu(DataType dt, 5404 QRegister rd, 5405 QRegister rm, 5406 const QOperand& operand) { 5407 vqshlu(al, dt, rd, rm, operand); 5408 } 5409 5410 void vqshrn(Condition cond, 5411 DataType dt, 5412 DRegister rd, 5413 QRegister rm, 5414 const QOperand& operand); 5415 void vqshrn(DataType dt, 5416 DRegister rd, 5417 QRegister rm, 5418 const QOperand& operand) { 5419 vqshrn(al, dt, rd, rm, operand); 5420 } 5421 5422 void vqshrun(Condition cond, 5423 DataType dt, 5424 DRegister rd, 5425 QRegister rm, 5426 const QOperand& operand); 5427 void vqshrun(DataType dt, 5428 DRegister rd, 5429 QRegister rm, 5430 const QOperand& operand) { 5431 vqshrun(al, dt, rd, rm, operand); 5432 } 5433 5434 void vqsub( 5435 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5436 void vqsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5437 vqsub(al, dt, rd, rn, rm); 5438 } 5439 5440 void vqsub( 5441 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5442 void vqsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5443 vqsub(al, dt, rd, rn, rm); 5444 } 5445 5446 void vraddhn( 5447 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5448 void vraddhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5449 vraddhn(al, dt, rd, rn, rm); 5450 } 5451 5452 void vrecpe(Condition cond, DataType dt, DRegister rd, DRegister rm); 5453 void vrecpe(DataType dt, DRegister rd, DRegister rm) { 5454 vrecpe(al, dt, rd, rm); 5455 } 5456 5457 void vrecpe(Condition cond, DataType dt, QRegister rd, QRegister rm); 5458 void vrecpe(DataType dt, QRegister rd, QRegister rm) { 5459 vrecpe(al, dt, rd, rm); 5460 } 5461 5462 void vrecps( 5463 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5464 void vrecps(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5465 vrecps(al, dt, rd, rn, rm); 5466 } 5467 5468 void vrecps( 5469 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5470 void vrecps(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5471 vrecps(al, dt, rd, rn, rm); 5472 } 5473 5474 void vrev16(Condition cond, DataType dt, DRegister rd, DRegister rm); 5475 void vrev16(DataType dt, DRegister rd, DRegister rm) { 5476 vrev16(al, dt, rd, rm); 5477 } 5478 5479 void vrev16(Condition cond, DataType dt, QRegister rd, QRegister rm); 5480 void vrev16(DataType dt, QRegister rd, QRegister rm) { 5481 vrev16(al, dt, rd, rm); 5482 } 5483 5484 void vrev32(Condition cond, DataType dt, DRegister rd, DRegister rm); 5485 void vrev32(DataType dt, DRegister rd, DRegister rm) { 5486 vrev32(al, dt, rd, rm); 5487 } 5488 5489 void vrev32(Condition cond, DataType dt, QRegister rd, QRegister rm); 5490 void vrev32(DataType dt, QRegister rd, QRegister rm) { 5491 vrev32(al, dt, rd, rm); 5492 } 5493 5494 void vrev64(Condition cond, DataType dt, DRegister rd, DRegister rm); 5495 void vrev64(DataType dt, DRegister rd, DRegister rm) { 5496 vrev64(al, dt, rd, rm); 5497 } 5498 5499 void vrev64(Condition cond, DataType dt, QRegister rd, QRegister rm); 5500 void vrev64(DataType dt, QRegister rd, QRegister rm) { 5501 vrev64(al, dt, rd, rm); 5502 } 5503 5504 void vrhadd( 5505 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5506 void vrhadd(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5507 vrhadd(al, dt, rd, rn, rm); 5508 } 5509 5510 void vrhadd( 5511 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5512 void vrhadd(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5513 vrhadd(al, dt, rd, rn, rm); 5514 } 5515 5516 void vrinta(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5517 5518 void vrinta(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5519 5520 void vrinta(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5521 5522 void vrintm(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5523 5524 void vrintm(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5525 5526 void vrintm(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5527 5528 void vrintn(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5529 5530 void vrintn(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5531 5532 void vrintn(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5533 5534 void vrintp(DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5535 5536 void vrintp(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5537 5538 void vrintp(DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5539 5540 void vrintr( 5541 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5542 void vrintr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5543 vrintr(al, dt1, dt2, rd, rm); 5544 } 5545 5546 void vrintr( 5547 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5548 void vrintr(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5549 vrintr(al, dt1, dt2, rd, rm); 5550 } 5551 5552 void vrintx( 5553 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5554 void vrintx(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5555 vrintx(al, dt1, dt2, rd, rm); 5556 } 5557 5558 void vrintx(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5559 5560 void vrintx( 5561 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5562 void vrintx(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5563 vrintx(al, dt1, dt2, rd, rm); 5564 } 5565 5566 void vrintz( 5567 Condition cond, DataType dt1, DataType dt2, DRegister rd, DRegister rm); 5568 void vrintz(DataType dt1, DataType dt2, DRegister rd, DRegister rm) { 5569 vrintz(al, dt1, dt2, rd, rm); 5570 } 5571 5572 void vrintz(DataType dt1, DataType dt2, QRegister rd, QRegister rm); 5573 5574 void vrintz( 5575 Condition cond, DataType dt1, DataType dt2, SRegister rd, SRegister rm); 5576 void vrintz(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { 5577 vrintz(al, dt1, dt2, rd, rm); 5578 } 5579 5580 void vrshl( 5581 Condition cond, DataType dt, DRegister rd, DRegister rm, DRegister rn); 5582 void vrshl(DataType dt, DRegister rd, DRegister rm, DRegister rn) { 5583 vrshl(al, dt, rd, rm, rn); 5584 } 5585 5586 void vrshl( 5587 Condition cond, DataType dt, QRegister rd, QRegister rm, QRegister rn); 5588 void vrshl(DataType dt, QRegister rd, QRegister rm, QRegister rn) { 5589 vrshl(al, dt, rd, rm, rn); 5590 } 5591 5592 void vrshr(Condition cond, 5593 DataType dt, 5594 DRegister rd, 5595 DRegister rm, 5596 const DOperand& operand); 5597 void vrshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5598 vrshr(al, dt, rd, rm, operand); 5599 } 5600 5601 void vrshr(Condition cond, 5602 DataType dt, 5603 QRegister rd, 5604 QRegister rm, 5605 const QOperand& operand); 5606 void vrshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5607 vrshr(al, dt, rd, rm, operand); 5608 } 5609 5610 void vrshrn(Condition cond, 5611 DataType dt, 5612 DRegister rd, 5613 QRegister rm, 5614 const QOperand& operand); 5615 void vrshrn(DataType dt, 5616 DRegister rd, 5617 QRegister rm, 5618 const QOperand& operand) { 5619 vrshrn(al, dt, rd, rm, operand); 5620 } 5621 5622 void vrsqrte(Condition cond, DataType dt, DRegister rd, DRegister rm); 5623 void vrsqrte(DataType dt, DRegister rd, DRegister rm) { 5624 vrsqrte(al, dt, rd, rm); 5625 } 5626 5627 void vrsqrte(Condition cond, DataType dt, QRegister rd, QRegister rm); 5628 void vrsqrte(DataType dt, QRegister rd, QRegister rm) { 5629 vrsqrte(al, dt, rd, rm); 5630 } 5631 5632 void vrsqrts( 5633 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 5634 void vrsqrts(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 5635 vrsqrts(al, dt, rd, rn, rm); 5636 } 5637 5638 void vrsqrts( 5639 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 5640 void vrsqrts(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 5641 vrsqrts(al, dt, rd, rn, rm); 5642 } 5643 5644 void vrsra(Condition cond, 5645 DataType dt, 5646 DRegister rd, 5647 DRegister rm, 5648 const DOperand& operand); 5649 void vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5650 vrsra(al, dt, rd, rm, operand); 5651 } 5652 5653 void vrsra(Condition cond, 5654 DataType dt, 5655 QRegister rd, 5656 QRegister rm, 5657 const QOperand& operand); 5658 void vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5659 vrsra(al, dt, rd, rm, operand); 5660 } 5661 5662 void vrsubhn( 5663 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 5664 void vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 5665 vrsubhn(al, dt, rd, rn, rm); 5666 } 5667 5668 void vseleq(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5669 5670 void vseleq(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5671 5672 void vselge(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5673 5674 void vselge(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5675 5676 void vselgt(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5677 5678 void vselgt(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5679 5680 void vselvs(DataType dt, DRegister rd, DRegister rn, DRegister rm); 5681 5682 void vselvs(DataType dt, SRegister rd, SRegister rn, SRegister rm); 5683 5684 void vshl(Condition cond, 5685 DataType dt, 5686 DRegister rd, 5687 DRegister rm, 5688 const DOperand& operand); 5689 void vshl(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5690 vshl(al, dt, rd, rm, operand); 5691 } 5692 5693 void vshl(Condition cond, 5694 DataType dt, 5695 QRegister rd, 5696 QRegister rm, 5697 const QOperand& operand); 5698 void vshl(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5699 vshl(al, dt, rd, rm, operand); 5700 } 5701 5702 void vshll(Condition cond, 5703 DataType dt, 5704 QRegister rd, 5705 DRegister rm, 5706 const DOperand& operand); 5707 void vshll(DataType dt, QRegister rd, DRegister rm, const DOperand& operand) { 5708 vshll(al, dt, rd, rm, operand); 5709 } 5710 5711 void vshr(Condition cond, 5712 DataType dt, 5713 DRegister rd, 5714 DRegister rm, 5715 const DOperand& operand); 5716 void vshr(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5717 vshr(al, dt, rd, rm, operand); 5718 } 5719 5720 void vshr(Condition cond, 5721 DataType dt, 5722 QRegister rd, 5723 QRegister rm, 5724 const QOperand& operand); 5725 void vshr(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5726 vshr(al, dt, rd, rm, operand); 5727 } 5728 5729 void vshrn(Condition cond, 5730 DataType dt, 5731 DRegister rd, 5732 QRegister rm, 5733 const QOperand& operand); 5734 void vshrn(DataType dt, DRegister rd, QRegister rm, const QOperand& operand) { 5735 vshrn(al, dt, rd, rm, operand); 5736 } 5737 5738 void vsli(Condition cond, 5739 DataType dt, 5740 DRegister rd, 5741 DRegister rm, 5742 const DOperand& operand); 5743 void vsli(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5744 vsli(al, dt, rd, rm, operand); 5745 } 5746 5747 void vsli(Condition cond, 5748 DataType dt, 5749 QRegister rd, 5750 QRegister rm, 5751 const QOperand& operand); 5752 void vsli(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5753 vsli(al, dt, rd, rm, operand); 5754 } 5755 5756 void vsqrt(Condition cond, DataType dt, SRegister rd, SRegister rm); 5757 void vsqrt(DataType dt, SRegister rd, SRegister rm) { vsqrt(al, dt, rd, rm); } 5758 5759 void vsqrt(Condition cond, DataType dt, DRegister rd, DRegister rm); 5760 void vsqrt(DataType dt, DRegister rd, DRegister rm) { vsqrt(al, dt, rd, rm); } 5761 5762 void vsra(Condition cond, 5763 DataType dt, 5764 DRegister rd, 5765 DRegister rm, 5766 const DOperand& operand); 5767 void vsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5768 vsra(al, dt, rd, rm, operand); 5769 } 5770 5771 void vsra(Condition cond, 5772 DataType dt, 5773 QRegister rd, 5774 QRegister rm, 5775 const QOperand& operand); 5776 void vsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5777 vsra(al, dt, rd, rm, operand); 5778 } 5779 5780 void vsri(Condition cond, 5781 DataType dt, 5782 DRegister rd, 5783 DRegister rm, 5784 const DOperand& operand); 5785 void vsri(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { 5786 vsri(al, dt, rd, rm, operand); 5787 } 5788 5789 void vsri(Condition cond, 5790 DataType dt, 5791 QRegister rd, 5792 QRegister rm, 5793 const QOperand& operand); 5794 void vsri(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { 5795 vsri(al, dt, rd, rm, operand); 5796 } 5797 5798 void vst1(Condition cond, 5799 DataType dt, 5800 const NeonRegisterList& nreglist, 5801 const AlignedMemOperand& operand); 5802 void vst1(DataType dt, 5803 const NeonRegisterList& nreglist, 5804 const AlignedMemOperand& operand) { 5805 vst1(al, dt, nreglist, operand); 5806 } 5807 5808 void vst2(Condition cond, 5809 DataType dt, 5810 const NeonRegisterList& nreglist, 5811 const AlignedMemOperand& operand); 5812 void vst2(DataType dt, 5813 const NeonRegisterList& nreglist, 5814 const AlignedMemOperand& operand) { 5815 vst2(al, dt, nreglist, operand); 5816 } 5817 5818 void vst3(Condition cond, 5819 DataType dt, 5820 const NeonRegisterList& nreglist, 5821 const AlignedMemOperand& operand); 5822 void vst3(DataType dt, 5823 const NeonRegisterList& nreglist, 5824 const AlignedMemOperand& operand) { 5825 vst3(al, dt, nreglist, operand); 5826 } 5827 5828 void vst3(Condition cond, 5829 DataType dt, 5830 const NeonRegisterList& nreglist, 5831 const MemOperand& operand); 5832 void vst3(DataType dt, 5833 const NeonRegisterList& nreglist, 5834 const MemOperand& operand) { 5835 vst3(al, dt, nreglist, operand); 5836 } 5837 5838 void vst4(Condition cond, 5839 DataType dt, 5840 const NeonRegisterList& nreglist, 5841 const AlignedMemOperand& operand); 5842 void vst4(DataType dt, 5843 const NeonRegisterList& nreglist, 5844 const AlignedMemOperand& operand) { 5845 vst4(al, dt, nreglist, operand); 5846 } 5847 5848 void vstm(Condition cond, 5849 DataType dt, 5850 Register rn, 5851 WriteBack write_back, 5852 DRegisterList dreglist); 5853 void vstm(DataType dt, 5854 Register rn, 5855 WriteBack write_back, 5856 DRegisterList dreglist) { 5857 vstm(al, dt, rn, write_back, dreglist); 5858 } 5859 void vstm(Register rn, WriteBack write_back, DRegisterList dreglist) { 5860 vstm(al, kDataTypeValueNone, rn, write_back, dreglist); 5861 } 5862 void vstm(Condition cond, 5863 Register rn, 5864 WriteBack write_back, 5865 DRegisterList dreglist) { 5866 vstm(cond, kDataTypeValueNone, rn, write_back, dreglist); 5867 } 5868 5869 void vstm(Condition cond, 5870 DataType dt, 5871 Register rn, 5872 WriteBack write_back, 5873 SRegisterList sreglist); 5874 void vstm(DataType dt, 5875 Register rn, 5876 WriteBack write_back, 5877 SRegisterList sreglist) { 5878 vstm(al, dt, rn, write_back, sreglist); 5879 } 5880 void vstm(Register rn, WriteBack write_back, SRegisterList sreglist) { 5881 vstm(al, kDataTypeValueNone, rn, write_back, sreglist); 5882 } 5883 void vstm(Condition cond, 5884 Register rn, 5885 WriteBack write_back, 5886 SRegisterList sreglist) { 5887 vstm(cond, kDataTypeValueNone, rn, write_back, sreglist); 5888 } 5889 5890 void vstmdb(Condition cond, 5891 DataType dt, 5892 Register rn, 5893 WriteBack write_back, 5894 DRegisterList dreglist); 5895 void vstmdb(DataType dt, 5896 Register rn, 5897 WriteBack write_back, 5898 DRegisterList dreglist) { 5899 vstmdb(al, dt, rn, write_back, dreglist); 5900 } 5901 void vstmdb(Register rn, WriteBack write_back, DRegisterList dreglist) { 5902 vstmdb(al, kDataTypeValueNone, rn, write_back, dreglist); 5903 } 5904 void vstmdb(Condition cond, 5905 Register rn, 5906 WriteBack write_back, 5907 DRegisterList dreglist) { 5908 vstmdb(cond, kDataTypeValueNone, rn, write_back, dreglist); 5909 } 5910 5911 void vstmdb(Condition cond, 5912 DataType dt, 5913 Register rn, 5914 WriteBack write_back, 5915 SRegisterList sreglist); 5916 void vstmdb(DataType dt, 5917 Register rn, 5918 WriteBack write_back, 5919 SRegisterList sreglist) { 5920 vstmdb(al, dt, rn, write_back, sreglist); 5921 } 5922 void vstmdb(Register rn, WriteBack write_back, SRegisterList sreglist) { 5923 vstmdb(al, kDataTypeValueNone, rn, write_back, sreglist); 5924 } 5925 void vstmdb(Condition cond, 5926 Register rn, 5927 WriteBack write_back, 5928 SRegisterList sreglist) { 5929 vstmdb(cond, kDataTypeValueNone, rn, write_back, sreglist); 5930 } 5931 5932 void vstmia(Condition cond, 5933 DataType dt, 5934 Register rn, 5935 WriteBack write_back, 5936 DRegisterList dreglist); 5937 void vstmia(DataType dt, 5938 Register rn, 5939 WriteBack write_back, 5940 DRegisterList dreglist) { 5941 vstmia(al, dt, rn, write_back, dreglist); 5942 } 5943 void vstmia(Register rn, WriteBack write_back, DRegisterList dreglist) { 5944 vstmia(al, kDataTypeValueNone, rn, write_back, dreglist); 5945 } 5946 void vstmia(Condition cond, 5947 Register rn, 5948 WriteBack write_back, 5949 DRegisterList dreglist) { 5950 vstmia(cond, kDataTypeValueNone, rn, write_back, dreglist); 5951 } 5952 5953 void vstmia(Condition cond, 5954 DataType dt, 5955 Register rn, 5956 WriteBack write_back, 5957 SRegisterList sreglist); 5958 void vstmia(DataType dt, 5959 Register rn, 5960 WriteBack write_back, 5961 SRegisterList sreglist) { 5962 vstmia(al, dt, rn, write_back, sreglist); 5963 } 5964 void vstmia(Register rn, WriteBack write_back, SRegisterList sreglist) { 5965 vstmia(al, kDataTypeValueNone, rn, write_back, sreglist); 5966 } 5967 void vstmia(Condition cond, 5968 Register rn, 5969 WriteBack write_back, 5970 SRegisterList sreglist) { 5971 vstmia(cond, kDataTypeValueNone, rn, write_back, sreglist); 5972 } 5973 5974 void vstr(Condition cond, 5975 DataType dt, 5976 DRegister rd, 5977 const MemOperand& operand); 5978 void vstr(DataType dt, DRegister rd, const MemOperand& operand) { 5979 vstr(al, dt, rd, operand); 5980 } 5981 void vstr(DRegister rd, const MemOperand& operand) { 5982 vstr(al, Untyped64, rd, operand); 5983 } 5984 void vstr(Condition cond, DRegister rd, const MemOperand& operand) { 5985 vstr(cond, Untyped64, rd, operand); 5986 } 5987 5988 void vstr(Condition cond, 5989 DataType dt, 5990 SRegister rd, 5991 const MemOperand& operand); 5992 void vstr(DataType dt, SRegister rd, const MemOperand& operand) { 5993 vstr(al, dt, rd, operand); 5994 } 5995 void vstr(SRegister rd, const MemOperand& operand) { 5996 vstr(al, Untyped32, rd, operand); 5997 } 5998 void vstr(Condition cond, SRegister rd, const MemOperand& operand) { 5999 vstr(cond, Untyped32, rd, operand); 6000 } 6001 6002 void vsub( 6003 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 6004 void vsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6005 vsub(al, dt, rd, rn, rm); 6006 } 6007 6008 void vsub( 6009 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 6010 void vsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6011 vsub(al, dt, rd, rn, rm); 6012 } 6013 6014 void vsub( 6015 Condition cond, DataType dt, SRegister rd, SRegister rn, SRegister rm); 6016 void vsub(DataType dt, SRegister rd, SRegister rn, SRegister rm) { 6017 vsub(al, dt, rd, rn, rm); 6018 } 6019 6020 void vsubhn( 6021 Condition cond, DataType dt, DRegister rd, QRegister rn, QRegister rm); 6022 void vsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { 6023 vsubhn(al, dt, rd, rn, rm); 6024 } 6025 6026 void vsubl( 6027 Condition cond, DataType dt, QRegister rd, DRegister rn, DRegister rm); 6028 void vsubl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { 6029 vsubl(al, dt, rd, rn, rm); 6030 } 6031 6032 void vsubw( 6033 Condition cond, DataType dt, QRegister rd, QRegister rn, DRegister rm); 6034 void vsubw(DataType dt, QRegister rd, QRegister rn, DRegister rm) { 6035 vsubw(al, dt, rd, rn, rm); 6036 } 6037 6038 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm); 6039 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } 6040 void vswp(DRegister rd, DRegister rm) { 6041 vswp(al, kDataTypeValueNone, rd, rm); 6042 } 6043 void vswp(Condition cond, DRegister rd, DRegister rm) { 6044 vswp(cond, kDataTypeValueNone, rd, rm); 6045 } 6046 6047 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm); 6048 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } 6049 void vswp(QRegister rd, QRegister rm) { 6050 vswp(al, kDataTypeValueNone, rd, rm); 6051 } 6052 void vswp(Condition cond, QRegister rd, QRegister rm) { 6053 vswp(cond, kDataTypeValueNone, rd, rm); 6054 } 6055 6056 void vtbl(Condition cond, 6057 DataType dt, 6058 DRegister rd, 6059 const NeonRegisterList& nreglist, 6060 DRegister rm); 6061 void vtbl(DataType dt, 6062 DRegister rd, 6063 const NeonRegisterList& nreglist, 6064 DRegister rm) { 6065 vtbl(al, dt, rd, nreglist, rm); 6066 } 6067 6068 void vtbx(Condition cond, 6069 DataType dt, 6070 DRegister rd, 6071 const NeonRegisterList& nreglist, 6072 DRegister rm); 6073 void vtbx(DataType dt, 6074 DRegister rd, 6075 const NeonRegisterList& nreglist, 6076 DRegister rm) { 6077 vtbx(al, dt, rd, nreglist, rm); 6078 } 6079 6080 void vtrn(Condition cond, DataType dt, DRegister rd, DRegister rm); 6081 void vtrn(DataType dt, DRegister rd, DRegister rm) { vtrn(al, dt, rd, rm); } 6082 6083 void vtrn(Condition cond, DataType dt, QRegister rd, QRegister rm); 6084 void vtrn(DataType dt, QRegister rd, QRegister rm) { vtrn(al, dt, rd, rm); } 6085 6086 void vtst( 6087 Condition cond, DataType dt, DRegister rd, DRegister rn, DRegister rm); 6088 void vtst(DataType dt, DRegister rd, DRegister rn, DRegister rm) { 6089 vtst(al, dt, rd, rn, rm); 6090 } 6091 6092 void vtst( 6093 Condition cond, DataType dt, QRegister rd, QRegister rn, QRegister rm); 6094 void vtst(DataType dt, QRegister rd, QRegister rn, QRegister rm) { 6095 vtst(al, dt, rd, rn, rm); 6096 } 6097 6098 void vuzp(Condition cond, DataType dt, DRegister rd, DRegister rm); 6099 void vuzp(DataType dt, DRegister rd, DRegister rm) { vuzp(al, dt, rd, rm); } 6100 6101 void vuzp(Condition cond, DataType dt, QRegister rd, QRegister rm); 6102 void vuzp(DataType dt, QRegister rd, QRegister rm) { vuzp(al, dt, rd, rm); } 6103 6104 void vzip(Condition cond, DataType dt, DRegister rd, DRegister rm); 6105 void vzip(DataType dt, DRegister rd, DRegister rm) { vzip(al, dt, rd, rm); } 6106 6107 void vzip(Condition cond, DataType dt, QRegister rd, QRegister rm); 6108 void vzip(DataType dt, QRegister rd, QRegister rm) { vzip(al, dt, rd, rm); } 6109 6110 void yield(Condition cond, EncodingSize size); 6111 void yield() { yield(al, Best); } 6112 void yield(Condition cond) { yield(cond, Best); } 6113 void yield(EncodingSize size) { yield(al, size); } 6114 // End of generated code. 6115 virtual void UnimplementedDelegate(InstructionType type) { 6116 std::string error_message(std::string("Ill-formed '") + 6117 std::string(ToCString(type)) + 6118 std::string("' instruction.\n")); 6119 VIXL_ABORT_WITH_MSG(error_message.c_str()); 6120 } 6121 virtual bool AllowUnpredictable() { return allow_unpredictable_; } 6122 virtual bool AllowStronglyDiscouraged() { 6123 return allow_strongly_discouraged_; 6124 } 6125 }; 6126 6127 } // namespace aarch32 6128 } // namespace vixl 6129 6130 #endif // VIXL_AARCH32_ASSEMBLER_AARCH32_H_ 6131
