1 //===-- SelectionDAGBuilder.cpp - Selection-DAG building ------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This implements routines for translating from LLVM IR into SelectionDAG IR. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #define DEBUG_TYPE "isel" 15 #include "SDNodeDbgValue.h" 16 #include "SelectionDAGBuilder.h" 17 #include "llvm/ADT/BitVector.h" 18 #include "llvm/ADT/PostOrderIterator.h" 19 #include "llvm/ADT/SmallSet.h" 20 #include "llvm/Analysis/AliasAnalysis.h" 21 #include "llvm/Analysis/ConstantFolding.h" 22 #include "llvm/Constants.h" 23 #include "llvm/CallingConv.h" 24 #include "llvm/DerivedTypes.h" 25 #include "llvm/Function.h" 26 #include "llvm/GlobalVariable.h" 27 #include "llvm/InlineAsm.h" 28 #include "llvm/Instructions.h" 29 #include "llvm/Intrinsics.h" 30 #include "llvm/IntrinsicInst.h" 31 #include "llvm/LLVMContext.h" 32 #include "llvm/Module.h" 33 #include "llvm/CodeGen/Analysis.h" 34 #include "llvm/CodeGen/FastISel.h" 35 #include "llvm/CodeGen/FunctionLoweringInfo.h" 36 #include "llvm/CodeGen/GCStrategy.h" 37 #include "llvm/CodeGen/GCMetadata.h" 38 #include "llvm/CodeGen/MachineFunction.h" 39 #include "llvm/CodeGen/MachineFrameInfo.h" 40 #include "llvm/CodeGen/MachineInstrBuilder.h" 41 #include "llvm/CodeGen/MachineJumpTableInfo.h" 42 #include "llvm/CodeGen/MachineModuleInfo.h" 43 #include "llvm/CodeGen/MachineRegisterInfo.h" 44 #include "llvm/CodeGen/PseudoSourceValue.h" 45 #include "llvm/CodeGen/SelectionDAG.h" 46 #include "llvm/Analysis/DebugInfo.h" 47 #include "llvm/Target/TargetData.h" 48 #include "llvm/Target/TargetFrameLowering.h" 49 #include "llvm/Target/TargetInstrInfo.h" 50 #include "llvm/Target/TargetIntrinsicInfo.h" 51 #include "llvm/Target/TargetLowering.h" 52 #include "llvm/Target/TargetOptions.h" 53 #include "llvm/Support/CommandLine.h" 54 #include "llvm/Support/Debug.h" 55 #include "llvm/Support/ErrorHandling.h" 56 #include "llvm/Support/MathExtras.h" 57 #include "llvm/Support/raw_ostream.h" 58 #include <algorithm> 59 using namespace llvm; 60 61 /// LimitFloatPrecision - Generate low-precision inline sequences for 62 /// some float libcalls (6, 8 or 12 bits). 63 static unsigned LimitFloatPrecision; 64 65 static cl::opt<unsigned, true> 66 LimitFPPrecision("limit-float-precision", 67 cl::desc("Generate low-precision inline sequences " 68 "for some float libcalls"), 69 cl::location(LimitFloatPrecision), 70 cl::init(0)); 71 72 // Limit the width of DAG chains. This is important in general to prevent 73 // prevent DAG-based analysis from blowing up. For example, alias analysis and 74 // load clustering may not complete in reasonable time. It is difficult to 75 // recognize and avoid this situation within each individual analysis, and 76 // future analyses are likely to have the same behavior. Limiting DAG width is 77 // the safe approach, and will be especially important with global DAGs. 78 // 79 // MaxParallelChains default is arbitrarily high to avoid affecting 80 // optimization, but could be lowered to improve compile time. Any ld-ld-st-st 81 // sequence over this should have been converted to llvm.memcpy by the 82 // frontend. It easy to induce this behavior with .ll code such as: 83 // %buffer = alloca [4096 x i8] 84 // %data = load [4096 x i8]* %argPtr 85 // store [4096 x i8] %data, [4096 x i8]* %buffer 86 static const unsigned MaxParallelChains = 64; 87 88 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 89 const SDValue *Parts, unsigned NumParts, 90 EVT PartVT, EVT ValueVT); 91 92 /// getCopyFromParts - Create a value that contains the specified legal parts 93 /// combined into the value they represent. If the parts combine to a type 94 /// larger then ValueVT then AssertOp can be used to specify whether the extra 95 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 96 /// (ISD::AssertSext). 97 static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc DL, 98 const SDValue *Parts, 99 unsigned NumParts, EVT PartVT, EVT ValueVT, 100 ISD::NodeType AssertOp = ISD::DELETED_NODE) { 101 if (ValueVT.isVector()) 102 return getCopyFromPartsVector(DAG, DL, Parts, NumParts, PartVT, ValueVT); 103 104 assert(NumParts > 0 && "No parts to assemble!"); 105 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 106 SDValue Val = Parts[0]; 107 108 if (NumParts > 1) { 109 // Assemble the value from multiple parts. 110 if (ValueVT.isInteger()) { 111 unsigned PartBits = PartVT.getSizeInBits(); 112 unsigned ValueBits = ValueVT.getSizeInBits(); 113 114 // Assemble the power of 2 part. 115 unsigned RoundParts = NumParts & (NumParts - 1) ? 116 1 << Log2_32(NumParts) : NumParts; 117 unsigned RoundBits = PartBits * RoundParts; 118 EVT RoundVT = RoundBits == ValueBits ? 119 ValueVT : EVT::getIntegerVT(*DAG.getContext(), RoundBits); 120 SDValue Lo, Hi; 121 122 EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), RoundBits/2); 123 124 if (RoundParts > 2) { 125 Lo = getCopyFromParts(DAG, DL, Parts, RoundParts / 2, 126 PartVT, HalfVT); 127 Hi = getCopyFromParts(DAG, DL, Parts + RoundParts / 2, 128 RoundParts / 2, PartVT, HalfVT); 129 } else { 130 Lo = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[0]); 131 Hi = DAG.getNode(ISD::BITCAST, DL, HalfVT, Parts[1]); 132 } 133 134 if (TLI.isBigEndian()) 135 std::swap(Lo, Hi); 136 137 Val = DAG.getNode(ISD::BUILD_PAIR, DL, RoundVT, Lo, Hi); 138 139 if (RoundParts < NumParts) { 140 // Assemble the trailing non-power-of-2 part. 141 unsigned OddParts = NumParts - RoundParts; 142 EVT OddVT = EVT::getIntegerVT(*DAG.getContext(), OddParts * PartBits); 143 Hi = getCopyFromParts(DAG, DL, 144 Parts + RoundParts, OddParts, PartVT, OddVT); 145 146 // Combine the round and odd parts. 147 Lo = Val; 148 if (TLI.isBigEndian()) 149 std::swap(Lo, Hi); 150 EVT TotalVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 151 Hi = DAG.getNode(ISD::ANY_EXTEND, DL, TotalVT, Hi); 152 Hi = DAG.getNode(ISD::SHL, DL, TotalVT, Hi, 153 DAG.getConstant(Lo.getValueType().getSizeInBits(), 154 TLI.getPointerTy())); 155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); 156 Val = DAG.getNode(ISD::OR, DL, TotalVT, Lo, Hi); 157 } 158 } else if (PartVT.isFloatingPoint()) { 159 // FP split into multiple FP parts (for ppcf128) 160 assert(ValueVT == EVT(MVT::ppcf128) && PartVT == EVT(MVT::f64) && 161 "Unexpected split"); 162 SDValue Lo, Hi; 163 Lo = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[0]); 164 Hi = DAG.getNode(ISD::BITCAST, DL, EVT(MVT::f64), Parts[1]); 165 if (TLI.isBigEndian()) 166 std::swap(Lo, Hi); 167 Val = DAG.getNode(ISD::BUILD_PAIR, DL, ValueVT, Lo, Hi); 168 } else { 169 // FP split into integer parts (soft fp) 170 assert(ValueVT.isFloatingPoint() && PartVT.isInteger() && 171 !PartVT.isVector() && "Unexpected split"); 172 EVT IntVT = EVT::getIntegerVT(*DAG.getContext(), ValueVT.getSizeInBits()); 173 Val = getCopyFromParts(DAG, DL, Parts, NumParts, PartVT, IntVT); 174 } 175 } 176 177 // There is now one part, held in Val. Correct it to match ValueVT. 178 PartVT = Val.getValueType(); 179 180 if (PartVT == ValueVT) 181 return Val; 182 183 if (PartVT.isInteger() && ValueVT.isInteger()) { 184 if (ValueVT.bitsLT(PartVT)) { 185 // For a truncate, see if we have any information to 186 // indicate whether the truncated bits will always be 187 // zero or sign-extension. 188 if (AssertOp != ISD::DELETED_NODE) 189 Val = DAG.getNode(AssertOp, DL, PartVT, Val, 190 DAG.getValueType(ValueVT)); 191 return DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 192 } 193 return DAG.getNode(ISD::ANY_EXTEND, DL, ValueVT, Val); 194 } 195 196 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 197 // FP_ROUND's are always exact here. 198 if (ValueVT.bitsLT(Val.getValueType())) 199 return DAG.getNode(ISD::FP_ROUND, DL, ValueVT, Val, 200 DAG.getIntPtrConstant(1)); 201 202 return DAG.getNode(ISD::FP_EXTEND, DL, ValueVT, Val); 203 } 204 205 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) 206 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 207 208 llvm_unreachable("Unknown mismatch!"); 209 return SDValue(); 210 } 211 212 /// getCopyFromParts - Create a value that contains the specified legal parts 213 /// combined into the value they represent. If the parts combine to a type 214 /// larger then ValueVT then AssertOp can be used to specify whether the extra 215 /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT 216 /// (ISD::AssertSext). 217 static SDValue getCopyFromPartsVector(SelectionDAG &DAG, DebugLoc DL, 218 const SDValue *Parts, unsigned NumParts, 219 EVT PartVT, EVT ValueVT) { 220 assert(ValueVT.isVector() && "Not a vector value"); 221 assert(NumParts > 0 && "No parts to assemble!"); 222 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 223 SDValue Val = Parts[0]; 224 225 // Handle a multi-element vector. 226 if (NumParts > 1) { 227 EVT IntermediateVT, RegisterVT; 228 unsigned NumIntermediates; 229 unsigned NumRegs = 230 TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, IntermediateVT, 231 NumIntermediates, RegisterVT); 232 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 233 NumParts = NumRegs; // Silence a compiler warning. 234 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 235 assert(RegisterVT == Parts[0].getValueType() && 236 "Part type doesn't match part!"); 237 238 // Assemble the parts into intermediate operands. 239 SmallVector<SDValue, 8> Ops(NumIntermediates); 240 if (NumIntermediates == NumParts) { 241 // If the register was not expanded, truncate or copy the value, 242 // as appropriate. 243 for (unsigned i = 0; i != NumParts; ++i) 244 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i], 1, 245 PartVT, IntermediateVT); 246 } else if (NumParts > 0) { 247 // If the intermediate type was expanded, build the intermediate 248 // operands from the parts. 249 assert(NumParts % NumIntermediates == 0 && 250 "Must expand into a divisible number of parts!"); 251 unsigned Factor = NumParts / NumIntermediates; 252 for (unsigned i = 0; i != NumIntermediates; ++i) 253 Ops[i] = getCopyFromParts(DAG, DL, &Parts[i * Factor], Factor, 254 PartVT, IntermediateVT); 255 } 256 257 // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the 258 // intermediate operands. 259 Val = DAG.getNode(IntermediateVT.isVector() ? 260 ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, DL, 261 ValueVT, &Ops[0], NumIntermediates); 262 } 263 264 // There is now one part, held in Val. Correct it to match ValueVT. 265 PartVT = Val.getValueType(); 266 267 if (PartVT == ValueVT) 268 return Val; 269 270 if (PartVT.isVector()) { 271 // If the element type of the source/dest vectors are the same, but the 272 // parts vector has more elements than the value vector, then we have a 273 // vector widening case (e.g. <2 x float> -> <4 x float>). Extract the 274 // elements we want. 275 if (PartVT.getVectorElementType() == ValueVT.getVectorElementType()) { 276 assert(PartVT.getVectorNumElements() > ValueVT.getVectorNumElements() && 277 "Cannot narrow, it would be a lossy transformation"); 278 return DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, ValueVT, Val, 279 DAG.getIntPtrConstant(0)); 280 } 281 282 // Vector/Vector bitcast. 283 if (ValueVT.getSizeInBits() == PartVT.getSizeInBits()) 284 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 285 286 assert(PartVT.getVectorNumElements() == ValueVT.getVectorNumElements() && 287 "Cannot handle this kind of promotion"); 288 // Promoted vector extract 289 bool Smaller = ValueVT.bitsLE(PartVT); 290 return DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 291 DL, ValueVT, Val); 292 293 } 294 295 // Trivial bitcast if the types are the same size and the destination 296 // vector type is legal. 297 if (PartVT.getSizeInBits() == ValueVT.getSizeInBits() && 298 TLI.isTypeLegal(ValueVT)) 299 return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val); 300 301 // Handle cases such as i8 -> <1 x i1> 302 assert(ValueVT.getVectorNumElements() == 1 && 303 "Only trivial scalar-to-vector conversions should get here!"); 304 305 if (ValueVT.getVectorNumElements() == 1 && 306 ValueVT.getVectorElementType() != PartVT) { 307 bool Smaller = ValueVT.bitsLE(PartVT); 308 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 309 DL, ValueVT.getScalarType(), Val); 310 } 311 312 return DAG.getNode(ISD::BUILD_VECTOR, DL, ValueVT, Val); 313 } 314 315 316 317 318 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc dl, 319 SDValue Val, SDValue *Parts, unsigned NumParts, 320 EVT PartVT); 321 322 /// getCopyToParts - Create a series of nodes that contain the specified value 323 /// split into legal parts. If the parts contain more bits than Val, then, for 324 /// integers, ExtendKind can be used to specify how to generate the extra bits. 325 static void getCopyToParts(SelectionDAG &DAG, DebugLoc DL, 326 SDValue Val, SDValue *Parts, unsigned NumParts, 327 EVT PartVT, 328 ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { 329 EVT ValueVT = Val.getValueType(); 330 331 // Handle the vector case separately. 332 if (ValueVT.isVector()) 333 return getCopyToPartsVector(DAG, DL, Val, Parts, NumParts, PartVT); 334 335 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 336 unsigned PartBits = PartVT.getSizeInBits(); 337 unsigned OrigNumParts = NumParts; 338 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); 339 340 if (NumParts == 0) 341 return; 342 343 assert(!ValueVT.isVector() && "Vector case handled elsewhere"); 344 if (PartVT == ValueVT) { 345 assert(NumParts == 1 && "No-op copy with multiple parts!"); 346 Parts[0] = Val; 347 return; 348 } 349 350 if (NumParts * PartBits > ValueVT.getSizeInBits()) { 351 // If the parts cover more bits than the value has, promote the value. 352 if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { 353 assert(NumParts == 1 && "Do not know what to promote to!"); 354 Val = DAG.getNode(ISD::FP_EXTEND, DL, PartVT, Val); 355 } else { 356 assert(PartVT.isInteger() && ValueVT.isInteger() && 357 "Unknown mismatch!"); 358 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 359 Val = DAG.getNode(ExtendKind, DL, ValueVT, Val); 360 } 361 } else if (PartBits == ValueVT.getSizeInBits()) { 362 // Different types of the same size. 363 assert(NumParts == 1 && PartVT != ValueVT); 364 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 365 } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { 366 // If the parts cover less bits than value has, truncate the value. 367 assert(PartVT.isInteger() && ValueVT.isInteger() && 368 "Unknown mismatch!"); 369 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 370 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 371 } 372 373 // The value may have changed - recompute ValueVT. 374 ValueVT = Val.getValueType(); 375 assert(NumParts * PartBits == ValueVT.getSizeInBits() && 376 "Failed to tile the value with PartVT!"); 377 378 if (NumParts == 1) { 379 assert(PartVT == ValueVT && "Type conversion failed!"); 380 Parts[0] = Val; 381 return; 382 } 383 384 // Expand the value into multiple parts. 385 if (NumParts & (NumParts - 1)) { 386 // The number of parts is not a power of 2. Split off and copy the tail. 387 assert(PartVT.isInteger() && ValueVT.isInteger() && 388 "Do not know what to expand to!"); 389 unsigned RoundParts = 1 << Log2_32(NumParts); 390 unsigned RoundBits = RoundParts * PartBits; 391 unsigned OddParts = NumParts - RoundParts; 392 SDValue OddVal = DAG.getNode(ISD::SRL, DL, ValueVT, Val, 393 DAG.getIntPtrConstant(RoundBits)); 394 getCopyToParts(DAG, DL, OddVal, Parts + RoundParts, OddParts, PartVT); 395 396 if (TLI.isBigEndian()) 397 // The odd parts were reversed by getCopyToParts - unreverse them. 398 std::reverse(Parts + RoundParts, Parts + NumParts); 399 400 NumParts = RoundParts; 401 ValueVT = EVT::getIntegerVT(*DAG.getContext(), NumParts * PartBits); 402 Val = DAG.getNode(ISD::TRUNCATE, DL, ValueVT, Val); 403 } 404 405 // The number of parts is a power of 2. Repeatedly bisect the value using 406 // EXTRACT_ELEMENT. 407 Parts[0] = DAG.getNode(ISD::BITCAST, DL, 408 EVT::getIntegerVT(*DAG.getContext(), 409 ValueVT.getSizeInBits()), 410 Val); 411 412 for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { 413 for (unsigned i = 0; i < NumParts; i += StepSize) { 414 unsigned ThisBits = StepSize * PartBits / 2; 415 EVT ThisVT = EVT::getIntegerVT(*DAG.getContext(), ThisBits); 416 SDValue &Part0 = Parts[i]; 417 SDValue &Part1 = Parts[i+StepSize/2]; 418 419 Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 420 ThisVT, Part0, DAG.getIntPtrConstant(1)); 421 Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, 422 ThisVT, Part0, DAG.getIntPtrConstant(0)); 423 424 if (ThisBits == PartBits && ThisVT != PartVT) { 425 Part0 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part0); 426 Part1 = DAG.getNode(ISD::BITCAST, DL, PartVT, Part1); 427 } 428 } 429 } 430 431 if (TLI.isBigEndian()) 432 std::reverse(Parts, Parts + OrigNumParts); 433 } 434 435 436 /// getCopyToPartsVector - Create a series of nodes that contain the specified 437 /// value split into legal parts. 438 static void getCopyToPartsVector(SelectionDAG &DAG, DebugLoc DL, 439 SDValue Val, SDValue *Parts, unsigned NumParts, 440 EVT PartVT) { 441 EVT ValueVT = Val.getValueType(); 442 assert(ValueVT.isVector() && "Not a vector"); 443 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 444 445 if (NumParts == 1) { 446 if (PartVT == ValueVT) { 447 // Nothing to do. 448 } else if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) { 449 // Bitconvert vector->vector case. 450 Val = DAG.getNode(ISD::BITCAST, DL, PartVT, Val); 451 } else if (PartVT.isVector() && 452 PartVT.getVectorElementType() == ValueVT.getVectorElementType() && 453 PartVT.getVectorNumElements() > ValueVT.getVectorNumElements()) { 454 EVT ElementVT = PartVT.getVectorElementType(); 455 // Vector widening case, e.g. <2 x float> -> <4 x float>. Shuffle in 456 // undef elements. 457 SmallVector<SDValue, 16> Ops; 458 for (unsigned i = 0, e = ValueVT.getVectorNumElements(); i != e; ++i) 459 Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 460 ElementVT, Val, DAG.getIntPtrConstant(i))); 461 462 for (unsigned i = ValueVT.getVectorNumElements(), 463 e = PartVT.getVectorNumElements(); i != e; ++i) 464 Ops.push_back(DAG.getUNDEF(ElementVT)); 465 466 Val = DAG.getNode(ISD::BUILD_VECTOR, DL, PartVT, &Ops[0], Ops.size()); 467 468 // FIXME: Use CONCAT for 2x -> 4x. 469 470 //SDValue UndefElts = DAG.getUNDEF(VectorTy); 471 //Val = DAG.getNode(ISD::CONCAT_VECTORS, DL, PartVT, Val, UndefElts); 472 } else if (PartVT.isVector() && 473 PartVT.getVectorElementType().bitsGE( 474 ValueVT.getVectorElementType()) && 475 PartVT.getVectorNumElements() == ValueVT.getVectorNumElements()) { 476 477 // Promoted vector extract 478 bool Smaller = PartVT.bitsLE(ValueVT); 479 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 480 DL, PartVT, Val); 481 } else{ 482 // Vector -> scalar conversion. 483 assert(ValueVT.getVectorNumElements() == 1 && 484 "Only trivial vector-to-scalar conversions should get here!"); 485 Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 486 PartVT, Val, DAG.getIntPtrConstant(0)); 487 488 bool Smaller = ValueVT.bitsLE(PartVT); 489 Val = DAG.getNode((Smaller ? ISD::TRUNCATE : ISD::ANY_EXTEND), 490 DL, PartVT, Val); 491 } 492 493 Parts[0] = Val; 494 return; 495 } 496 497 // Handle a multi-element vector. 498 EVT IntermediateVT, RegisterVT; 499 unsigned NumIntermediates; 500 unsigned NumRegs = TLI.getVectorTypeBreakdown(*DAG.getContext(), ValueVT, 501 IntermediateVT, 502 NumIntermediates, RegisterVT); 503 unsigned NumElements = ValueVT.getVectorNumElements(); 504 505 assert(NumRegs == NumParts && "Part count doesn't match vector breakdown!"); 506 NumParts = NumRegs; // Silence a compiler warning. 507 assert(RegisterVT == PartVT && "Part type doesn't match vector breakdown!"); 508 509 // Split the vector into intermediate operands. 510 SmallVector<SDValue, 8> Ops(NumIntermediates); 511 for (unsigned i = 0; i != NumIntermediates; ++i) { 512 if (IntermediateVT.isVector()) 513 Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, 514 IntermediateVT, Val, 515 DAG.getIntPtrConstant(i * (NumElements / NumIntermediates))); 516 else 517 Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, 518 IntermediateVT, Val, DAG.getIntPtrConstant(i)); 519 } 520 521 // Split the intermediate operands into legal parts. 522 if (NumParts == NumIntermediates) { 523 // If the register was not expanded, promote or copy the value, 524 // as appropriate. 525 for (unsigned i = 0; i != NumParts; ++i) 526 getCopyToParts(DAG, DL, Ops[i], &Parts[i], 1, PartVT); 527 } else if (NumParts > 0) { 528 // If the intermediate type was expanded, split each the value into 529 // legal parts. 530 assert(NumParts % NumIntermediates == 0 && 531 "Must expand into a divisible number of parts!"); 532 unsigned Factor = NumParts / NumIntermediates; 533 for (unsigned i = 0; i != NumIntermediates; ++i) 534 getCopyToParts(DAG, DL, Ops[i], &Parts[i*Factor], Factor, PartVT); 535 } 536 } 537 538 539 540 541 namespace { 542 /// RegsForValue - This struct represents the registers (physical or virtual) 543 /// that a particular set of values is assigned, and the type information 544 /// about the value. The most common situation is to represent one value at a 545 /// time, but struct or array values are handled element-wise as multiple 546 /// values. The splitting of aggregates is performed recursively, so that we 547 /// never have aggregate-typed registers. The values at this point do not 548 /// necessarily have legal types, so each value may require one or more 549 /// registers of some legal type. 550 /// 551 struct RegsForValue { 552 /// ValueVTs - The value types of the values, which may not be legal, and 553 /// may need be promoted or synthesized from one or more registers. 554 /// 555 SmallVector<EVT, 4> ValueVTs; 556 557 /// RegVTs - The value types of the registers. This is the same size as 558 /// ValueVTs and it records, for each value, what the type of the assigned 559 /// register or registers are. (Individual values are never synthesized 560 /// from more than one type of register.) 561 /// 562 /// With virtual registers, the contents of RegVTs is redundant with TLI's 563 /// getRegisterType member function, however when with physical registers 564 /// it is necessary to have a separate record of the types. 565 /// 566 SmallVector<EVT, 4> RegVTs; 567 568 /// Regs - This list holds the registers assigned to the values. 569 /// Each legal or promoted value requires one register, and each 570 /// expanded value requires multiple registers. 571 /// 572 SmallVector<unsigned, 4> Regs; 573 574 RegsForValue() {} 575 576 RegsForValue(const SmallVector<unsigned, 4> ®s, 577 EVT regvt, EVT valuevt) 578 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {} 579 580 RegsForValue(LLVMContext &Context, const TargetLowering &tli, 581 unsigned Reg, Type *Ty) { 582 ComputeValueVTs(tli, Ty, ValueVTs); 583 584 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 585 EVT ValueVT = ValueVTs[Value]; 586 unsigned NumRegs = tli.getNumRegisters(Context, ValueVT); 587 EVT RegisterVT = tli.getRegisterType(Context, ValueVT); 588 for (unsigned i = 0; i != NumRegs; ++i) 589 Regs.push_back(Reg + i); 590 RegVTs.push_back(RegisterVT); 591 Reg += NumRegs; 592 } 593 } 594 595 /// areValueTypesLegal - Return true if types of all the values are legal. 596 bool areValueTypesLegal(const TargetLowering &TLI) { 597 for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) { 598 EVT RegisterVT = RegVTs[Value]; 599 if (!TLI.isTypeLegal(RegisterVT)) 600 return false; 601 } 602 return true; 603 } 604 605 /// append - Add the specified values to this one. 606 void append(const RegsForValue &RHS) { 607 ValueVTs.append(RHS.ValueVTs.begin(), RHS.ValueVTs.end()); 608 RegVTs.append(RHS.RegVTs.begin(), RHS.RegVTs.end()); 609 Regs.append(RHS.Regs.begin(), RHS.Regs.end()); 610 } 611 612 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 613 /// this value and returns the result as a ValueVTs value. This uses 614 /// Chain/Flag as the input and updates them for the output Chain/Flag. 615 /// If the Flag pointer is NULL, no flag is used. 616 SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, 617 DebugLoc dl, 618 SDValue &Chain, SDValue *Flag) const; 619 620 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 621 /// specified value into the registers specified by this object. This uses 622 /// Chain/Flag as the input and updates them for the output Chain/Flag. 623 /// If the Flag pointer is NULL, no flag is used. 624 void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 625 SDValue &Chain, SDValue *Flag) const; 626 627 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 628 /// operand list. This adds the code marker, matching input operand index 629 /// (if applicable), and includes the number of values added into it. 630 void AddInlineAsmOperands(unsigned Kind, 631 bool HasMatching, unsigned MatchingIdx, 632 SelectionDAG &DAG, 633 std::vector<SDValue> &Ops) const; 634 }; 635 } 636 637 /// getCopyFromRegs - Emit a series of CopyFromReg nodes that copies from 638 /// this value and returns the result as a ValueVT value. This uses 639 /// Chain/Flag as the input and updates them for the output Chain/Flag. 640 /// If the Flag pointer is NULL, no flag is used. 641 SDValue RegsForValue::getCopyFromRegs(SelectionDAG &DAG, 642 FunctionLoweringInfo &FuncInfo, 643 DebugLoc dl, 644 SDValue &Chain, SDValue *Flag) const { 645 // A Value with type {} or [0 x %t] needs no registers. 646 if (ValueVTs.empty()) 647 return SDValue(); 648 649 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 650 651 // Assemble the legal parts into the final values. 652 SmallVector<SDValue, 4> Values(ValueVTs.size()); 653 SmallVector<SDValue, 8> Parts; 654 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 655 // Copy the legal parts from the registers. 656 EVT ValueVT = ValueVTs[Value]; 657 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 658 EVT RegisterVT = RegVTs[Value]; 659 660 Parts.resize(NumRegs); 661 for (unsigned i = 0; i != NumRegs; ++i) { 662 SDValue P; 663 if (Flag == 0) { 664 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT); 665 } else { 666 P = DAG.getCopyFromReg(Chain, dl, Regs[Part+i], RegisterVT, *Flag); 667 *Flag = P.getValue(2); 668 } 669 670 Chain = P.getValue(1); 671 Parts[i] = P; 672 673 // If the source register was virtual and if we know something about it, 674 // add an assert node. 675 if (!TargetRegisterInfo::isVirtualRegister(Regs[Part+i]) || 676 !RegisterVT.isInteger() || RegisterVT.isVector()) 677 continue; 678 679 const FunctionLoweringInfo::LiveOutInfo *LOI = 680 FuncInfo.GetLiveOutRegInfo(Regs[Part+i]); 681 if (!LOI) 682 continue; 683 684 unsigned RegSize = RegisterVT.getSizeInBits(); 685 unsigned NumSignBits = LOI->NumSignBits; 686 unsigned NumZeroBits = LOI->KnownZero.countLeadingOnes(); 687 688 // FIXME: We capture more information than the dag can represent. For 689 // now, just use the tightest assertzext/assertsext possible. 690 bool isSExt = true; 691 EVT FromVT(MVT::Other); 692 if (NumSignBits == RegSize) 693 isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1 694 else if (NumZeroBits >= RegSize-1) 695 isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1 696 else if (NumSignBits > RegSize-8) 697 isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8 698 else if (NumZeroBits >= RegSize-8) 699 isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8 700 else if (NumSignBits > RegSize-16) 701 isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16 702 else if (NumZeroBits >= RegSize-16) 703 isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16 704 else if (NumSignBits > RegSize-32) 705 isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32 706 else if (NumZeroBits >= RegSize-32) 707 isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32 708 else 709 continue; 710 711 // Add an assertion node. 712 assert(FromVT != MVT::Other); 713 Parts[i] = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl, 714 RegisterVT, P, DAG.getValueType(FromVT)); 715 } 716 717 Values[Value] = getCopyFromParts(DAG, dl, Parts.begin(), 718 NumRegs, RegisterVT, ValueVT); 719 Part += NumRegs; 720 Parts.clear(); 721 } 722 723 return DAG.getNode(ISD::MERGE_VALUES, dl, 724 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 725 &Values[0], ValueVTs.size()); 726 } 727 728 /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the 729 /// specified value into the registers specified by this object. This uses 730 /// Chain/Flag as the input and updates them for the output Chain/Flag. 731 /// If the Flag pointer is NULL, no flag is used. 732 void RegsForValue::getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, 733 SDValue &Chain, SDValue *Flag) const { 734 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 735 736 // Get the list of the values's legal parts. 737 unsigned NumRegs = Regs.size(); 738 SmallVector<SDValue, 8> Parts(NumRegs); 739 for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) { 740 EVT ValueVT = ValueVTs[Value]; 741 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), ValueVT); 742 EVT RegisterVT = RegVTs[Value]; 743 744 getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value), 745 &Parts[Part], NumParts, RegisterVT); 746 Part += NumParts; 747 } 748 749 // Copy the parts into the registers. 750 SmallVector<SDValue, 8> Chains(NumRegs); 751 for (unsigned i = 0; i != NumRegs; ++i) { 752 SDValue Part; 753 if (Flag == 0) { 754 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i]); 755 } else { 756 Part = DAG.getCopyToReg(Chain, dl, Regs[i], Parts[i], *Flag); 757 *Flag = Part.getValue(1); 758 } 759 760 Chains[i] = Part.getValue(0); 761 } 762 763 if (NumRegs == 1 || Flag) 764 // If NumRegs > 1 && Flag is used then the use of the last CopyToReg is 765 // flagged to it. That is the CopyToReg nodes and the user are considered 766 // a single scheduling unit. If we create a TokenFactor and return it as 767 // chain, then the TokenFactor is both a predecessor (operand) of the 768 // user as well as a successor (the TF operands are flagged to the user). 769 // c1, f1 = CopyToReg 770 // c2, f2 = CopyToReg 771 // c3 = TokenFactor c1, c2 772 // ... 773 // = op c3, ..., f2 774 Chain = Chains[NumRegs-1]; 775 else 776 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs); 777 } 778 779 /// AddInlineAsmOperands - Add this value to the specified inlineasm node 780 /// operand list. This adds the code marker and includes the number of 781 /// values added into it. 782 void RegsForValue::AddInlineAsmOperands(unsigned Code, bool HasMatching, 783 unsigned MatchingIdx, 784 SelectionDAG &DAG, 785 std::vector<SDValue> &Ops) const { 786 const TargetLowering &TLI = DAG.getTargetLoweringInfo(); 787 788 unsigned Flag = InlineAsm::getFlagWord(Code, Regs.size()); 789 if (HasMatching) 790 Flag = InlineAsm::getFlagWordForMatchingOp(Flag, MatchingIdx); 791 else if (!Regs.empty() && 792 TargetRegisterInfo::isVirtualRegister(Regs.front())) { 793 // Put the register class of the virtual registers in the flag word. That 794 // way, later passes can recompute register class constraints for inline 795 // assembly as well as normal instructions. 796 // Don't do this for tied operands that can use the regclass information 797 // from the def. 798 const MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo(); 799 const TargetRegisterClass *RC = MRI.getRegClass(Regs.front()); 800 Flag = InlineAsm::getFlagWordForRegClass(Flag, RC->getID()); 801 } 802 803 SDValue Res = DAG.getTargetConstant(Flag, MVT::i32); 804 Ops.push_back(Res); 805 806 for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) { 807 unsigned NumRegs = TLI.getNumRegisters(*DAG.getContext(), ValueVTs[Value]); 808 EVT RegisterVT = RegVTs[Value]; 809 for (unsigned i = 0; i != NumRegs; ++i) { 810 assert(Reg < Regs.size() && "Mismatch in # registers expected"); 811 Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT)); 812 } 813 } 814 } 815 816 void SelectionDAGBuilder::init(GCFunctionInfo *gfi, AliasAnalysis &aa) { 817 AA = &aa; 818 GFI = gfi; 819 TD = DAG.getTarget().getTargetData(); 820 LPadToCallSiteMap.clear(); 821 } 822 823 /// clear - Clear out the current SelectionDAG and the associated 824 /// state and prepare this SelectionDAGBuilder object to be used 825 /// for a new block. This doesn't clear out information about 826 /// additional blocks that are needed to complete switch lowering 827 /// or PHI node updating; that information is cleared out as it is 828 /// consumed. 829 void SelectionDAGBuilder::clear() { 830 NodeMap.clear(); 831 UnusedArgNodeMap.clear(); 832 PendingLoads.clear(); 833 PendingExports.clear(); 834 CurDebugLoc = DebugLoc(); 835 HasTailCall = false; 836 } 837 838 /// clearDanglingDebugInfo - Clear the dangling debug information 839 /// map. This function is seperated from the clear so that debug 840 /// information that is dangling in a basic block can be properly 841 /// resolved in a different basic block. This allows the 842 /// SelectionDAG to resolve dangling debug information attached 843 /// to PHI nodes. 844 void SelectionDAGBuilder::clearDanglingDebugInfo() { 845 DanglingDebugInfoMap.clear(); 846 } 847 848 /// getRoot - Return the current virtual root of the Selection DAG, 849 /// flushing any PendingLoad items. This must be done before emitting 850 /// a store or any other node that may need to be ordered after any 851 /// prior load instructions. 852 /// 853 SDValue SelectionDAGBuilder::getRoot() { 854 if (PendingLoads.empty()) 855 return DAG.getRoot(); 856 857 if (PendingLoads.size() == 1) { 858 SDValue Root = PendingLoads[0]; 859 DAG.setRoot(Root); 860 PendingLoads.clear(); 861 return Root; 862 } 863 864 // Otherwise, we have to make a token factor node. 865 SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 866 &PendingLoads[0], PendingLoads.size()); 867 PendingLoads.clear(); 868 DAG.setRoot(Root); 869 return Root; 870 } 871 872 /// getControlRoot - Similar to getRoot, but instead of flushing all the 873 /// PendingLoad items, flush all the PendingExports items. It is necessary 874 /// to do this before emitting a terminator instruction. 875 /// 876 SDValue SelectionDAGBuilder::getControlRoot() { 877 SDValue Root = DAG.getRoot(); 878 879 if (PendingExports.empty()) 880 return Root; 881 882 // Turn all of the CopyToReg chains into one factored node. 883 if (Root.getOpcode() != ISD::EntryToken) { 884 unsigned i = 0, e = PendingExports.size(); 885 for (; i != e; ++i) { 886 assert(PendingExports[i].getNode()->getNumOperands() > 1); 887 if (PendingExports[i].getNode()->getOperand(0) == Root) 888 break; // Don't add the root if we already indirectly depend on it. 889 } 890 891 if (i == e) 892 PendingExports.push_back(Root); 893 } 894 895 Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 896 &PendingExports[0], 897 PendingExports.size()); 898 PendingExports.clear(); 899 DAG.setRoot(Root); 900 return Root; 901 } 902 903 void SelectionDAGBuilder::AssignOrderingToNode(const SDNode *Node) { 904 if (DAG.GetOrdering(Node) != 0) return; // Already has ordering. 905 DAG.AssignOrdering(Node, SDNodeOrder); 906 907 for (unsigned I = 0, E = Node->getNumOperands(); I != E; ++I) 908 AssignOrderingToNode(Node->getOperand(I).getNode()); 909 } 910 911 void SelectionDAGBuilder::visit(const Instruction &I) { 912 // Set up outgoing PHI node register values before emitting the terminator. 913 if (isa<TerminatorInst>(&I)) 914 HandlePHINodesInSuccessorBlocks(I.getParent()); 915 916 CurDebugLoc = I.getDebugLoc(); 917 918 visit(I.getOpcode(), I); 919 920 if (!isa<TerminatorInst>(&I) && !HasTailCall) 921 CopyToExportRegsIfNeeded(&I); 922 923 CurDebugLoc = DebugLoc(); 924 } 925 926 void SelectionDAGBuilder::visitPHI(const PHINode &) { 927 llvm_unreachable("SelectionDAGBuilder shouldn't visit PHI nodes!"); 928 } 929 930 void SelectionDAGBuilder::visit(unsigned Opcode, const User &I) { 931 // Note: this doesn't use InstVisitor, because it has to work with 932 // ConstantExpr's in addition to instructions. 933 switch (Opcode) { 934 default: llvm_unreachable("Unknown instruction type encountered!"); 935 // Build the switch statement using the Instruction.def file. 936 #define HANDLE_INST(NUM, OPCODE, CLASS) \ 937 case Instruction::OPCODE: visit##OPCODE((CLASS&)I); break; 938 #include "llvm/Instruction.def" 939 } 940 941 // Assign the ordering to the freshly created DAG nodes. 942 if (NodeMap.count(&I)) { 943 ++SDNodeOrder; 944 AssignOrderingToNode(getValue(&I).getNode()); 945 } 946 } 947 948 // resolveDanglingDebugInfo - if we saw an earlier dbg_value referring to V, 949 // generate the debug data structures now that we've seen its definition. 950 void SelectionDAGBuilder::resolveDanglingDebugInfo(const Value *V, 951 SDValue Val) { 952 DanglingDebugInfo &DDI = DanglingDebugInfoMap[V]; 953 if (DDI.getDI()) { 954 const DbgValueInst *DI = DDI.getDI(); 955 DebugLoc dl = DDI.getdl(); 956 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder(); 957 MDNode *Variable = DI->getVariable(); 958 uint64_t Offset = DI->getOffset(); 959 SDDbgValue *SDV; 960 if (Val.getNode()) { 961 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, Val)) { 962 SDV = DAG.getDbgValue(Variable, Val.getNode(), 963 Val.getResNo(), Offset, dl, DbgSDNodeOrder); 964 DAG.AddDbgValue(SDV, Val.getNode(), false); 965 } 966 } else 967 DEBUG(dbgs() << "Dropping debug info for " << DI); 968 DanglingDebugInfoMap[V] = DanglingDebugInfo(); 969 } 970 } 971 972 /// getValue - Return an SDValue for the given Value. 973 SDValue SelectionDAGBuilder::getValue(const Value *V) { 974 // If we already have an SDValue for this value, use it. It's important 975 // to do this first, so that we don't create a CopyFromReg if we already 976 // have a regular SDValue. 977 SDValue &N = NodeMap[V]; 978 if (N.getNode()) return N; 979 980 // If there's a virtual register allocated and initialized for this 981 // value, use it. 982 DenseMap<const Value *, unsigned>::iterator It = FuncInfo.ValueMap.find(V); 983 if (It != FuncInfo.ValueMap.end()) { 984 unsigned InReg = It->second; 985 RegsForValue RFV(*DAG.getContext(), TLI, InReg, V->getType()); 986 SDValue Chain = DAG.getEntryNode(); 987 N = RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 988 resolveDanglingDebugInfo(V, N); 989 return N; 990 } 991 992 // Otherwise create a new SDValue and remember it. 993 SDValue Val = getValueImpl(V); 994 NodeMap[V] = Val; 995 resolveDanglingDebugInfo(V, Val); 996 return Val; 997 } 998 999 /// getNonRegisterValue - Return an SDValue for the given Value, but 1000 /// don't look in FuncInfo.ValueMap for a virtual register. 1001 SDValue SelectionDAGBuilder::getNonRegisterValue(const Value *V) { 1002 // If we already have an SDValue for this value, use it. 1003 SDValue &N = NodeMap[V]; 1004 if (N.getNode()) return N; 1005 1006 // Otherwise create a new SDValue and remember it. 1007 SDValue Val = getValueImpl(V); 1008 NodeMap[V] = Val; 1009 resolveDanglingDebugInfo(V, Val); 1010 return Val; 1011 } 1012 1013 /// getValueImpl - Helper function for getValue and getNonRegisterValue. 1014 /// Create an SDValue for the given value. 1015 SDValue SelectionDAGBuilder::getValueImpl(const Value *V) { 1016 if (const Constant *C = dyn_cast<Constant>(V)) { 1017 EVT VT = TLI.getValueType(V->getType(), true); 1018 1019 if (const ConstantInt *CI = dyn_cast<ConstantInt>(C)) 1020 return DAG.getConstant(*CI, VT); 1021 1022 if (const GlobalValue *GV = dyn_cast<GlobalValue>(C)) 1023 return DAG.getGlobalAddress(GV, getCurDebugLoc(), VT); 1024 1025 if (isa<ConstantPointerNull>(C)) 1026 return DAG.getConstant(0, TLI.getPointerTy()); 1027 1028 if (const ConstantFP *CFP = dyn_cast<ConstantFP>(C)) 1029 return DAG.getConstantFP(*CFP, VT); 1030 1031 if (isa<UndefValue>(C) && !V->getType()->isAggregateType()) 1032 return DAG.getUNDEF(VT); 1033 1034 if (const ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { 1035 visit(CE->getOpcode(), *CE); 1036 SDValue N1 = NodeMap[V]; 1037 assert(N1.getNode() && "visit didn't populate the NodeMap!"); 1038 return N1; 1039 } 1040 1041 if (isa<ConstantStruct>(C) || isa<ConstantArray>(C)) { 1042 SmallVector<SDValue, 4> Constants; 1043 for (User::const_op_iterator OI = C->op_begin(), OE = C->op_end(); 1044 OI != OE; ++OI) { 1045 SDNode *Val = getValue(*OI).getNode(); 1046 // If the operand is an empty aggregate, there are no values. 1047 if (!Val) continue; 1048 // Add each leaf value from the operand to the Constants list 1049 // to form a flattened list of all the values. 1050 for (unsigned i = 0, e = Val->getNumValues(); i != e; ++i) 1051 Constants.push_back(SDValue(Val, i)); 1052 } 1053 1054 return DAG.getMergeValues(&Constants[0], Constants.size(), 1055 getCurDebugLoc()); 1056 } 1057 1058 if (C->getType()->isStructTy() || C->getType()->isArrayTy()) { 1059 assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) && 1060 "Unknown struct or array constant!"); 1061 1062 SmallVector<EVT, 4> ValueVTs; 1063 ComputeValueVTs(TLI, C->getType(), ValueVTs); 1064 unsigned NumElts = ValueVTs.size(); 1065 if (NumElts == 0) 1066 return SDValue(); // empty struct 1067 SmallVector<SDValue, 4> Constants(NumElts); 1068 for (unsigned i = 0; i != NumElts; ++i) { 1069 EVT EltVT = ValueVTs[i]; 1070 if (isa<UndefValue>(C)) 1071 Constants[i] = DAG.getUNDEF(EltVT); 1072 else if (EltVT.isFloatingPoint()) 1073 Constants[i] = DAG.getConstantFP(0, EltVT); 1074 else 1075 Constants[i] = DAG.getConstant(0, EltVT); 1076 } 1077 1078 return DAG.getMergeValues(&Constants[0], NumElts, 1079 getCurDebugLoc()); 1080 } 1081 1082 if (const BlockAddress *BA = dyn_cast<BlockAddress>(C)) 1083 return DAG.getBlockAddress(BA, VT); 1084 1085 VectorType *VecTy = cast<VectorType>(V->getType()); 1086 unsigned NumElements = VecTy->getNumElements(); 1087 1088 // Now that we know the number and type of the elements, get that number of 1089 // elements into the Ops array based on what kind of constant it is. 1090 SmallVector<SDValue, 16> Ops; 1091 if (const ConstantVector *CP = dyn_cast<ConstantVector>(C)) { 1092 for (unsigned i = 0; i != NumElements; ++i) 1093 Ops.push_back(getValue(CP->getOperand(i))); 1094 } else { 1095 assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!"); 1096 EVT EltVT = TLI.getValueType(VecTy->getElementType()); 1097 1098 SDValue Op; 1099 if (EltVT.isFloatingPoint()) 1100 Op = DAG.getConstantFP(0, EltVT); 1101 else 1102 Op = DAG.getConstant(0, EltVT); 1103 Ops.assign(NumElements, Op); 1104 } 1105 1106 // Create a BUILD_VECTOR node. 1107 return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 1108 VT, &Ops[0], Ops.size()); 1109 } 1110 1111 // If this is a static alloca, generate it as the frameindex instead of 1112 // computation. 1113 if (const AllocaInst *AI = dyn_cast<AllocaInst>(V)) { 1114 DenseMap<const AllocaInst*, int>::iterator SI = 1115 FuncInfo.StaticAllocaMap.find(AI); 1116 if (SI != FuncInfo.StaticAllocaMap.end()) 1117 return DAG.getFrameIndex(SI->second, TLI.getPointerTy()); 1118 } 1119 1120 // If this is an instruction which fast-isel has deferred, select it now. 1121 if (const Instruction *Inst = dyn_cast<Instruction>(V)) { 1122 unsigned InReg = FuncInfo.InitializeRegForValue(Inst); 1123 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType()); 1124 SDValue Chain = DAG.getEntryNode(); 1125 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL); 1126 } 1127 1128 llvm_unreachable("Can't get register for value!"); 1129 return SDValue(); 1130 } 1131 1132 void SelectionDAGBuilder::visitRet(const ReturnInst &I) { 1133 SDValue Chain = getControlRoot(); 1134 SmallVector<ISD::OutputArg, 8> Outs; 1135 SmallVector<SDValue, 8> OutVals; 1136 1137 if (!FuncInfo.CanLowerReturn) { 1138 unsigned DemoteReg = FuncInfo.DemoteRegister; 1139 const Function *F = I.getParent()->getParent(); 1140 1141 // Emit a store of the return value through the virtual register. 1142 // Leave Outs empty so that LowerReturn won't try to load return 1143 // registers the usual way. 1144 SmallVector<EVT, 1> PtrValueVTs; 1145 ComputeValueVTs(TLI, PointerType::getUnqual(F->getReturnType()), 1146 PtrValueVTs); 1147 1148 SDValue RetPtr = DAG.getRegister(DemoteReg, PtrValueVTs[0]); 1149 SDValue RetOp = getValue(I.getOperand(0)); 1150 1151 SmallVector<EVT, 4> ValueVTs; 1152 SmallVector<uint64_t, 4> Offsets; 1153 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs, &Offsets); 1154 unsigned NumValues = ValueVTs.size(); 1155 1156 SmallVector<SDValue, 4> Chains(NumValues); 1157 for (unsigned i = 0; i != NumValues; ++i) { 1158 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), 1159 RetPtr.getValueType(), RetPtr, 1160 DAG.getIntPtrConstant(Offsets[i])); 1161 Chains[i] = 1162 DAG.getStore(Chain, getCurDebugLoc(), 1163 SDValue(RetOp.getNode(), RetOp.getResNo() + i), 1164 // FIXME: better loc info would be nice. 1165 Add, MachinePointerInfo(), false, false, 0); 1166 } 1167 1168 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 1169 MVT::Other, &Chains[0], NumValues); 1170 } else if (I.getNumOperands() != 0) { 1171 SmallVector<EVT, 4> ValueVTs; 1172 ComputeValueVTs(TLI, I.getOperand(0)->getType(), ValueVTs); 1173 unsigned NumValues = ValueVTs.size(); 1174 if (NumValues) { 1175 SDValue RetOp = getValue(I.getOperand(0)); 1176 for (unsigned j = 0, f = NumValues; j != f; ++j) { 1177 EVT VT = ValueVTs[j]; 1178 1179 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 1180 1181 const Function *F = I.getParent()->getParent(); 1182 if (F->paramHasAttr(0, Attribute::SExt)) 1183 ExtendKind = ISD::SIGN_EXTEND; 1184 else if (F->paramHasAttr(0, Attribute::ZExt)) 1185 ExtendKind = ISD::ZERO_EXTEND; 1186 1187 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) 1188 VT = TLI.getTypeForExtArgOrReturn(*DAG.getContext(), VT, ExtendKind); 1189 1190 unsigned NumParts = TLI.getNumRegisters(*DAG.getContext(), VT); 1191 EVT PartVT = TLI.getRegisterType(*DAG.getContext(), VT); 1192 SmallVector<SDValue, 4> Parts(NumParts); 1193 getCopyToParts(DAG, getCurDebugLoc(), 1194 SDValue(RetOp.getNode(), RetOp.getResNo() + j), 1195 &Parts[0], NumParts, PartVT, ExtendKind); 1196 1197 // 'inreg' on function refers to return value 1198 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy(); 1199 if (F->paramHasAttr(0, Attribute::InReg)) 1200 Flags.setInReg(); 1201 1202 // Propagate extension type if any 1203 if (ExtendKind == ISD::SIGN_EXTEND) 1204 Flags.setSExt(); 1205 else if (ExtendKind == ISD::ZERO_EXTEND) 1206 Flags.setZExt(); 1207 1208 for (unsigned i = 0; i < NumParts; ++i) { 1209 Outs.push_back(ISD::OutputArg(Flags, Parts[i].getValueType(), 1210 /*isfixed=*/true)); 1211 OutVals.push_back(Parts[i]); 1212 } 1213 } 1214 } 1215 } 1216 1217 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg(); 1218 CallingConv::ID CallConv = 1219 DAG.getMachineFunction().getFunction()->getCallingConv(); 1220 Chain = TLI.LowerReturn(Chain, CallConv, isVarArg, 1221 Outs, OutVals, getCurDebugLoc(), DAG); 1222 1223 // Verify that the target's LowerReturn behaved as expected. 1224 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 1225 "LowerReturn didn't return a valid chain!"); 1226 1227 // Update the DAG with the new chain value resulting from return lowering. 1228 DAG.setRoot(Chain); 1229 } 1230 1231 /// CopyToExportRegsIfNeeded - If the given value has virtual registers 1232 /// created for it, emit nodes to copy the value into the virtual 1233 /// registers. 1234 void SelectionDAGBuilder::CopyToExportRegsIfNeeded(const Value *V) { 1235 // Skip empty types 1236 if (V->getType()->isEmptyTy()) 1237 return; 1238 1239 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 1240 if (VMI != FuncInfo.ValueMap.end()) { 1241 assert(!V->use_empty() && "Unused value assigned virtual registers!"); 1242 CopyValueToVirtualRegister(V, VMI->second); 1243 } 1244 } 1245 1246 /// ExportFromCurrentBlock - If this condition isn't known to be exported from 1247 /// the current basic block, add it to ValueMap now so that we'll get a 1248 /// CopyTo/FromReg. 1249 void SelectionDAGBuilder::ExportFromCurrentBlock(const Value *V) { 1250 // No need to export constants. 1251 if (!isa<Instruction>(V) && !isa<Argument>(V)) return; 1252 1253 // Already exported? 1254 if (FuncInfo.isExportedInst(V)) return; 1255 1256 unsigned Reg = FuncInfo.InitializeRegForValue(V); 1257 CopyValueToVirtualRegister(V, Reg); 1258 } 1259 1260 bool SelectionDAGBuilder::isExportableFromCurrentBlock(const Value *V, 1261 const BasicBlock *FromBB) { 1262 // The operands of the setcc have to be in this block. We don't know 1263 // how to export them from some other block. 1264 if (const Instruction *VI = dyn_cast<Instruction>(V)) { 1265 // Can export from current BB. 1266 if (VI->getParent() == FromBB) 1267 return true; 1268 1269 // Is already exported, noop. 1270 return FuncInfo.isExportedInst(V); 1271 } 1272 1273 // If this is an argument, we can export it if the BB is the entry block or 1274 // if it is already exported. 1275 if (isa<Argument>(V)) { 1276 if (FromBB == &FromBB->getParent()->getEntryBlock()) 1277 return true; 1278 1279 // Otherwise, can only export this if it is already exported. 1280 return FuncInfo.isExportedInst(V); 1281 } 1282 1283 // Otherwise, constants can always be exported. 1284 return true; 1285 } 1286 1287 /// Return branch probability calculated by BranchProbabilityInfo for IR blocks. 1288 uint32_t SelectionDAGBuilder::getEdgeWeight(MachineBasicBlock *Src, 1289 MachineBasicBlock *Dst) { 1290 BranchProbabilityInfo *BPI = FuncInfo.BPI; 1291 if (!BPI) 1292 return 0; 1293 const BasicBlock *SrcBB = Src->getBasicBlock(); 1294 const BasicBlock *DstBB = Dst->getBasicBlock(); 1295 return BPI->getEdgeWeight(SrcBB, DstBB); 1296 } 1297 1298 void SelectionDAGBuilder:: 1299 addSuccessorWithWeight(MachineBasicBlock *Src, MachineBasicBlock *Dst, 1300 uint32_t Weight /* = 0 */) { 1301 if (!Weight) 1302 Weight = getEdgeWeight(Src, Dst); 1303 Src->addSuccessor(Dst, Weight); 1304 } 1305 1306 1307 static bool InBlock(const Value *V, const BasicBlock *BB) { 1308 if (const Instruction *I = dyn_cast<Instruction>(V)) 1309 return I->getParent() == BB; 1310 return true; 1311 } 1312 1313 /// EmitBranchForMergedCondition - Helper method for FindMergedConditions. 1314 /// This function emits a branch and is used at the leaves of an OR or an 1315 /// AND operator tree. 1316 /// 1317 void 1318 SelectionDAGBuilder::EmitBranchForMergedCondition(const Value *Cond, 1319 MachineBasicBlock *TBB, 1320 MachineBasicBlock *FBB, 1321 MachineBasicBlock *CurBB, 1322 MachineBasicBlock *SwitchBB) { 1323 const BasicBlock *BB = CurBB->getBasicBlock(); 1324 1325 // If the leaf of the tree is a comparison, merge the condition into 1326 // the caseblock. 1327 if (const CmpInst *BOp = dyn_cast<CmpInst>(Cond)) { 1328 // The operands of the cmp have to be in this block. We don't know 1329 // how to export them from some other block. If this is the first block 1330 // of the sequence, no exporting is needed. 1331 if (CurBB == SwitchBB || 1332 (isExportableFromCurrentBlock(BOp->getOperand(0), BB) && 1333 isExportableFromCurrentBlock(BOp->getOperand(1), BB))) { 1334 ISD::CondCode Condition; 1335 if (const ICmpInst *IC = dyn_cast<ICmpInst>(Cond)) { 1336 Condition = getICmpCondCode(IC->getPredicate()); 1337 } else if (const FCmpInst *FC = dyn_cast<FCmpInst>(Cond)) { 1338 Condition = getFCmpCondCode(FC->getPredicate()); 1339 } else { 1340 Condition = ISD::SETEQ; // silence warning. 1341 llvm_unreachable("Unknown compare instruction"); 1342 } 1343 1344 CaseBlock CB(Condition, BOp->getOperand(0), 1345 BOp->getOperand(1), NULL, TBB, FBB, CurBB); 1346 SwitchCases.push_back(CB); 1347 return; 1348 } 1349 } 1350 1351 // Create a CaseBlock record representing this branch. 1352 CaseBlock CB(ISD::SETEQ, Cond, ConstantInt::getTrue(*DAG.getContext()), 1353 NULL, TBB, FBB, CurBB); 1354 SwitchCases.push_back(CB); 1355 } 1356 1357 /// FindMergedConditions - If Cond is an expression like 1358 void SelectionDAGBuilder::FindMergedConditions(const Value *Cond, 1359 MachineBasicBlock *TBB, 1360 MachineBasicBlock *FBB, 1361 MachineBasicBlock *CurBB, 1362 MachineBasicBlock *SwitchBB, 1363 unsigned Opc) { 1364 // If this node is not part of the or/and tree, emit it as a branch. 1365 const Instruction *BOp = dyn_cast<Instruction>(Cond); 1366 if (!BOp || !(isa<BinaryOperator>(BOp) || isa<CmpInst>(BOp)) || 1367 (unsigned)BOp->getOpcode() != Opc || !BOp->hasOneUse() || 1368 BOp->getParent() != CurBB->getBasicBlock() || 1369 !InBlock(BOp->getOperand(0), CurBB->getBasicBlock()) || 1370 !InBlock(BOp->getOperand(1), CurBB->getBasicBlock())) { 1371 EmitBranchForMergedCondition(Cond, TBB, FBB, CurBB, SwitchBB); 1372 return; 1373 } 1374 1375 // Create TmpBB after CurBB. 1376 MachineFunction::iterator BBI = CurBB; 1377 MachineFunction &MF = DAG.getMachineFunction(); 1378 MachineBasicBlock *TmpBB = MF.CreateMachineBasicBlock(CurBB->getBasicBlock()); 1379 CurBB->getParent()->insert(++BBI, TmpBB); 1380 1381 if (Opc == Instruction::Or) { 1382 // Codegen X | Y as: 1383 // jmp_if_X TBB 1384 // jmp TmpBB 1385 // TmpBB: 1386 // jmp_if_Y TBB 1387 // jmp FBB 1388 // 1389 1390 // Emit the LHS condition. 1391 FindMergedConditions(BOp->getOperand(0), TBB, TmpBB, CurBB, SwitchBB, Opc); 1392 1393 // Emit the RHS condition into TmpBB. 1394 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1395 } else { 1396 assert(Opc == Instruction::And && "Unknown merge op!"); 1397 // Codegen X & Y as: 1398 // jmp_if_X TmpBB 1399 // jmp FBB 1400 // TmpBB: 1401 // jmp_if_Y TBB 1402 // jmp FBB 1403 // 1404 // This requires creation of TmpBB after CurBB. 1405 1406 // Emit the LHS condition. 1407 FindMergedConditions(BOp->getOperand(0), TmpBB, FBB, CurBB, SwitchBB, Opc); 1408 1409 // Emit the RHS condition into TmpBB. 1410 FindMergedConditions(BOp->getOperand(1), TBB, FBB, TmpBB, SwitchBB, Opc); 1411 } 1412 } 1413 1414 /// If the set of cases should be emitted as a series of branches, return true. 1415 /// If we should emit this as a bunch of and/or'd together conditions, return 1416 /// false. 1417 bool 1418 SelectionDAGBuilder::ShouldEmitAsBranches(const std::vector<CaseBlock> &Cases){ 1419 if (Cases.size() != 2) return true; 1420 1421 // If this is two comparisons of the same values or'd or and'd together, they 1422 // will get folded into a single comparison, so don't emit two blocks. 1423 if ((Cases[0].CmpLHS == Cases[1].CmpLHS && 1424 Cases[0].CmpRHS == Cases[1].CmpRHS) || 1425 (Cases[0].CmpRHS == Cases[1].CmpLHS && 1426 Cases[0].CmpLHS == Cases[1].CmpRHS)) { 1427 return false; 1428 } 1429 1430 // Handle: (X != null) | (Y != null) --> (X|Y) != 0 1431 // Handle: (X == null) & (Y == null) --> (X|Y) == 0 1432 if (Cases[0].CmpRHS == Cases[1].CmpRHS && 1433 Cases[0].CC == Cases[1].CC && 1434 isa<Constant>(Cases[0].CmpRHS) && 1435 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) { 1436 if (Cases[0].CC == ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB) 1437 return false; 1438 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) 1439 return false; 1440 } 1441 1442 return true; 1443 } 1444 1445 void SelectionDAGBuilder::visitBr(const BranchInst &I) { 1446 MachineBasicBlock *BrMBB = FuncInfo.MBB; 1447 1448 // Update machine-CFG edges. 1449 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)]; 1450 1451 // Figure out which block is immediately after the current one. 1452 MachineBasicBlock *NextBlock = 0; 1453 MachineFunction::iterator BBI = BrMBB; 1454 if (++BBI != FuncInfo.MF->end()) 1455 NextBlock = BBI; 1456 1457 if (I.isUnconditional()) { 1458 // Update machine-CFG edges. 1459 BrMBB->addSuccessor(Succ0MBB); 1460 1461 // If this is not a fall-through branch, emit the branch. 1462 if (Succ0MBB != NextBlock) 1463 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1464 MVT::Other, getControlRoot(), 1465 DAG.getBasicBlock(Succ0MBB))); 1466 1467 return; 1468 } 1469 1470 // If this condition is one of the special cases we handle, do special stuff 1471 // now. 1472 const Value *CondVal = I.getCondition(); 1473 MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)]; 1474 1475 // If this is a series of conditions that are or'd or and'd together, emit 1476 // this as a sequence of branches instead of setcc's with and/or operations. 1477 // As long as jumps are not expensive, this should improve performance. 1478 // For example, instead of something like: 1479 // cmp A, B 1480 // C = seteq 1481 // cmp D, E 1482 // F = setle 1483 // or C, F 1484 // jnz foo 1485 // Emit: 1486 // cmp A, B 1487 // je foo 1488 // cmp D, E 1489 // jle foo 1490 // 1491 if (const BinaryOperator *BOp = dyn_cast<BinaryOperator>(CondVal)) { 1492 if (!TLI.isJumpExpensive() && 1493 BOp->hasOneUse() && 1494 (BOp->getOpcode() == Instruction::And || 1495 BOp->getOpcode() == Instruction::Or)) { 1496 FindMergedConditions(BOp, Succ0MBB, Succ1MBB, BrMBB, BrMBB, 1497 BOp->getOpcode()); 1498 // If the compares in later blocks need to use values not currently 1499 // exported from this block, export them now. This block should always 1500 // be the first entry. 1501 assert(SwitchCases[0].ThisBB == BrMBB && "Unexpected lowering!"); 1502 1503 // Allow some cases to be rejected. 1504 if (ShouldEmitAsBranches(SwitchCases)) { 1505 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) { 1506 ExportFromCurrentBlock(SwitchCases[i].CmpLHS); 1507 ExportFromCurrentBlock(SwitchCases[i].CmpRHS); 1508 } 1509 1510 // Emit the branch for this block. 1511 visitSwitchCase(SwitchCases[0], BrMBB); 1512 SwitchCases.erase(SwitchCases.begin()); 1513 return; 1514 } 1515 1516 // Okay, we decided not to do this, remove any inserted MBB's and clear 1517 // SwitchCases. 1518 for (unsigned i = 1, e = SwitchCases.size(); i != e; ++i) 1519 FuncInfo.MF->erase(SwitchCases[i].ThisBB); 1520 1521 SwitchCases.clear(); 1522 } 1523 } 1524 1525 // Create a CaseBlock record representing this branch. 1526 CaseBlock CB(ISD::SETEQ, CondVal, ConstantInt::getTrue(*DAG.getContext()), 1527 NULL, Succ0MBB, Succ1MBB, BrMBB); 1528 1529 // Use visitSwitchCase to actually insert the fast branch sequence for this 1530 // cond branch. 1531 visitSwitchCase(CB, BrMBB); 1532 } 1533 1534 /// visitSwitchCase - Emits the necessary code to represent a single node in 1535 /// the binary search tree resulting from lowering a switch instruction. 1536 void SelectionDAGBuilder::visitSwitchCase(CaseBlock &CB, 1537 MachineBasicBlock *SwitchBB) { 1538 SDValue Cond; 1539 SDValue CondLHS = getValue(CB.CmpLHS); 1540 DebugLoc dl = getCurDebugLoc(); 1541 1542 // Build the setcc now. 1543 if (CB.CmpMHS == NULL) { 1544 // Fold "(X == true)" to X and "(X == false)" to !X to 1545 // handle common cases produced by branch lowering. 1546 if (CB.CmpRHS == ConstantInt::getTrue(*DAG.getContext()) && 1547 CB.CC == ISD::SETEQ) 1548 Cond = CondLHS; 1549 else if (CB.CmpRHS == ConstantInt::getFalse(*DAG.getContext()) && 1550 CB.CC == ISD::SETEQ) { 1551 SDValue True = DAG.getConstant(1, CondLHS.getValueType()); 1552 Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True); 1553 } else 1554 Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); 1555 } else { 1556 assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now"); 1557 1558 const APInt& Low = cast<ConstantInt>(CB.CmpLHS)->getValue(); 1559 const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue(); 1560 1561 SDValue CmpOp = getValue(CB.CmpMHS); 1562 EVT VT = CmpOp.getValueType(); 1563 1564 if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { 1565 Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT), 1566 ISD::SETLE); 1567 } else { 1568 SDValue SUB = DAG.getNode(ISD::SUB, dl, 1569 VT, CmpOp, DAG.getConstant(Low, VT)); 1570 Cond = DAG.getSetCC(dl, MVT::i1, SUB, 1571 DAG.getConstant(High-Low, VT), ISD::SETULE); 1572 } 1573 } 1574 1575 // Update successor info 1576 addSuccessorWithWeight(SwitchBB, CB.TrueBB, CB.TrueWeight); 1577 addSuccessorWithWeight(SwitchBB, CB.FalseBB, CB.FalseWeight); 1578 1579 // Set NextBlock to be the MBB immediately after the current one, if any. 1580 // This is used to avoid emitting unnecessary branches to the next block. 1581 MachineBasicBlock *NextBlock = 0; 1582 MachineFunction::iterator BBI = SwitchBB; 1583 if (++BBI != FuncInfo.MF->end()) 1584 NextBlock = BBI; 1585 1586 // If the lhs block is the next block, invert the condition so that we can 1587 // fall through to the lhs instead of the rhs block. 1588 if (CB.TrueBB == NextBlock) { 1589 std::swap(CB.TrueBB, CB.FalseBB); 1590 SDValue True = DAG.getConstant(1, Cond.getValueType()); 1591 Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True); 1592 } 1593 1594 SDValue BrCond = DAG.getNode(ISD::BRCOND, dl, 1595 MVT::Other, getControlRoot(), Cond, 1596 DAG.getBasicBlock(CB.TrueBB)); 1597 1598 // Insert the false branch. Do this even if it's a fall through branch, 1599 // this makes it easier to do DAG optimizations which require inverting 1600 // the branch condition. 1601 BrCond = DAG.getNode(ISD::BR, dl, MVT::Other, BrCond, 1602 DAG.getBasicBlock(CB.FalseBB)); 1603 1604 DAG.setRoot(BrCond); 1605 } 1606 1607 /// visitJumpTable - Emit JumpTable node in the current MBB 1608 void SelectionDAGBuilder::visitJumpTable(JumpTable &JT) { 1609 // Emit the code for the jump table 1610 assert(JT.Reg != -1U && "Should lower JT Header first!"); 1611 EVT PTy = TLI.getPointerTy(); 1612 SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1613 JT.Reg, PTy); 1614 SDValue Table = DAG.getJumpTable(JT.JTI, PTy); 1615 SDValue BrJumpTable = DAG.getNode(ISD::BR_JT, getCurDebugLoc(), 1616 MVT::Other, Index.getValue(1), 1617 Table, Index); 1618 DAG.setRoot(BrJumpTable); 1619 } 1620 1621 /// visitJumpTableHeader - This function emits necessary code to produce index 1622 /// in the JumpTable from switch case. 1623 void SelectionDAGBuilder::visitJumpTableHeader(JumpTable &JT, 1624 JumpTableHeader &JTH, 1625 MachineBasicBlock *SwitchBB) { 1626 // Subtract the lowest switch case value from the value being switched on and 1627 // conditional branch to default mbb if the result is greater than the 1628 // difference between smallest and largest cases. 1629 SDValue SwitchOp = getValue(JTH.SValue); 1630 EVT VT = SwitchOp.getValueType(); 1631 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1632 DAG.getConstant(JTH.First, VT)); 1633 1634 // The SDNode we just created, which holds the value being switched on minus 1635 // the smallest case value, needs to be copied to a virtual register so it 1636 // can be used as an index into the jump table in a subsequent basic block. 1637 // This value may be smaller or larger than the target's pointer type, and 1638 // therefore require extension or truncating. 1639 SwitchOp = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), TLI.getPointerTy()); 1640 1641 unsigned JumpTableReg = FuncInfo.CreateReg(TLI.getPointerTy()); 1642 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1643 JumpTableReg, SwitchOp); 1644 JT.Reg = JumpTableReg; 1645 1646 // Emit the range check for the jump table, and branch to the default block 1647 // for the switch statement if the value being switched on exceeds the largest 1648 // case in the switch. 1649 SDValue CMP = DAG.getSetCC(getCurDebugLoc(), 1650 TLI.getSetCCResultType(Sub.getValueType()), Sub, 1651 DAG.getConstant(JTH.Last-JTH.First,VT), 1652 ISD::SETUGT); 1653 1654 // Set NextBlock to be the MBB immediately after the current one, if any. 1655 // This is used to avoid emitting unnecessary branches to the next block. 1656 MachineBasicBlock *NextBlock = 0; 1657 MachineFunction::iterator BBI = SwitchBB; 1658 1659 if (++BBI != FuncInfo.MF->end()) 1660 NextBlock = BBI; 1661 1662 SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1663 MVT::Other, CopyTo, CMP, 1664 DAG.getBasicBlock(JT.Default)); 1665 1666 if (JT.MBB != NextBlock) 1667 BrCond = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, 1668 DAG.getBasicBlock(JT.MBB)); 1669 1670 DAG.setRoot(BrCond); 1671 } 1672 1673 /// visitBitTestHeader - This function emits necessary code to produce value 1674 /// suitable for "bit tests" 1675 void SelectionDAGBuilder::visitBitTestHeader(BitTestBlock &B, 1676 MachineBasicBlock *SwitchBB) { 1677 // Subtract the minimum value 1678 SDValue SwitchOp = getValue(B.SValue); 1679 EVT VT = SwitchOp.getValueType(); 1680 SDValue Sub = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, 1681 DAG.getConstant(B.First, VT)); 1682 1683 // Check range 1684 SDValue RangeCmp = DAG.getSetCC(getCurDebugLoc(), 1685 TLI.getSetCCResultType(Sub.getValueType()), 1686 Sub, DAG.getConstant(B.Range, VT), 1687 ISD::SETUGT); 1688 1689 // Determine the type of the test operands. 1690 bool UsePtrType = false; 1691 if (!TLI.isTypeLegal(VT)) 1692 UsePtrType = true; 1693 else { 1694 for (unsigned i = 0, e = B.Cases.size(); i != e; ++i) 1695 if (!isUIntN(VT.getSizeInBits(), B.Cases[i].Mask)) { 1696 // Switch table case range are encoded into series of masks. 1697 // Just use pointer type, it's guaranteed to fit. 1698 UsePtrType = true; 1699 break; 1700 } 1701 } 1702 if (UsePtrType) { 1703 VT = TLI.getPointerTy(); 1704 Sub = DAG.getZExtOrTrunc(Sub, getCurDebugLoc(), VT); 1705 } 1706 1707 B.RegVT = VT; 1708 B.Reg = FuncInfo.CreateReg(VT); 1709 SDValue CopyTo = DAG.getCopyToReg(getControlRoot(), getCurDebugLoc(), 1710 B.Reg, Sub); 1711 1712 // Set NextBlock to be the MBB immediately after the current one, if any. 1713 // This is used to avoid emitting unnecessary branches to the next block. 1714 MachineBasicBlock *NextBlock = 0; 1715 MachineFunction::iterator BBI = SwitchBB; 1716 if (++BBI != FuncInfo.MF->end()) 1717 NextBlock = BBI; 1718 1719 MachineBasicBlock* MBB = B.Cases[0].ThisBB; 1720 1721 addSuccessorWithWeight(SwitchBB, B.Default); 1722 addSuccessorWithWeight(SwitchBB, MBB); 1723 1724 SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1725 MVT::Other, CopyTo, RangeCmp, 1726 DAG.getBasicBlock(B.Default)); 1727 1728 if (MBB != NextBlock) 1729 BrRange = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, 1730 DAG.getBasicBlock(MBB)); 1731 1732 DAG.setRoot(BrRange); 1733 } 1734 1735 /// visitBitTestCase - this function produces one "bit test" 1736 void SelectionDAGBuilder::visitBitTestCase(BitTestBlock &BB, 1737 MachineBasicBlock* NextMBB, 1738 unsigned Reg, 1739 BitTestCase &B, 1740 MachineBasicBlock *SwitchBB) { 1741 EVT VT = BB.RegVT; 1742 SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(), 1743 Reg, VT); 1744 SDValue Cmp; 1745 unsigned PopCount = CountPopulation_64(B.Mask); 1746 if (PopCount == 1) { 1747 // Testing for a single bit; just compare the shift count with what it 1748 // would need to be to shift a 1 bit in that position. 1749 Cmp = DAG.getSetCC(getCurDebugLoc(), 1750 TLI.getSetCCResultType(VT), 1751 ShiftOp, 1752 DAG.getConstant(CountTrailingZeros_64(B.Mask), VT), 1753 ISD::SETEQ); 1754 } else if (PopCount == BB.Range) { 1755 // There is only one zero bit in the range, test for it directly. 1756 Cmp = DAG.getSetCC(getCurDebugLoc(), 1757 TLI.getSetCCResultType(VT), 1758 ShiftOp, 1759 DAG.getConstant(CountTrailingOnes_64(B.Mask), VT), 1760 ISD::SETNE); 1761 } else { 1762 // Make desired shift 1763 SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), VT, 1764 DAG.getConstant(1, VT), ShiftOp); 1765 1766 // Emit bit tests and jumps 1767 SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), 1768 VT, SwitchVal, DAG.getConstant(B.Mask, VT)); 1769 Cmp = DAG.getSetCC(getCurDebugLoc(), 1770 TLI.getSetCCResultType(VT), 1771 AndOp, DAG.getConstant(0, VT), 1772 ISD::SETNE); 1773 } 1774 1775 addSuccessorWithWeight(SwitchBB, B.TargetBB); 1776 addSuccessorWithWeight(SwitchBB, NextMBB); 1777 1778 SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), 1779 MVT::Other, getControlRoot(), 1780 Cmp, DAG.getBasicBlock(B.TargetBB)); 1781 1782 // Set NextBlock to be the MBB immediately after the current one, if any. 1783 // This is used to avoid emitting unnecessary branches to the next block. 1784 MachineBasicBlock *NextBlock = 0; 1785 MachineFunction::iterator BBI = SwitchBB; 1786 if (++BBI != FuncInfo.MF->end()) 1787 NextBlock = BBI; 1788 1789 if (NextMBB != NextBlock) 1790 BrAnd = DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, 1791 DAG.getBasicBlock(NextMBB)); 1792 1793 DAG.setRoot(BrAnd); 1794 } 1795 1796 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) { 1797 MachineBasicBlock *InvokeMBB = FuncInfo.MBB; 1798 1799 // Retrieve successors. 1800 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)]; 1801 MachineBasicBlock *LandingPad = FuncInfo.MBBMap[I.getSuccessor(1)]; 1802 1803 const Value *Callee(I.getCalledValue()); 1804 if (isa<InlineAsm>(Callee)) 1805 visitInlineAsm(&I); 1806 else 1807 LowerCallTo(&I, getValue(Callee), false, LandingPad); 1808 1809 // If the value of the invoke is used outside of its defining block, make it 1810 // available as a virtual register. 1811 CopyToExportRegsIfNeeded(&I); 1812 1813 // Update successor info 1814 InvokeMBB->addSuccessor(Return); 1815 InvokeMBB->addSuccessor(LandingPad); 1816 1817 // Drop into normal successor. 1818 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 1819 MVT::Other, getControlRoot(), 1820 DAG.getBasicBlock(Return))); 1821 } 1822 1823 void SelectionDAGBuilder::visitUnwind(const UnwindInst &I) { 1824 } 1825 1826 void SelectionDAGBuilder::visitResume(const ResumeInst &RI) { 1827 llvm_unreachable("SelectionDAGBuilder shouldn't visit resume instructions!"); 1828 } 1829 1830 void SelectionDAGBuilder::visitLandingPad(const LandingPadInst &LP) { 1831 assert(FuncInfo.MBB->isLandingPad() && 1832 "Call to landingpad not in landing pad!"); 1833 1834 MachineBasicBlock *MBB = FuncInfo.MBB; 1835 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 1836 AddLandingPadInfo(LP, MMI, MBB); 1837 1838 SmallVector<EVT, 2> ValueVTs; 1839 ComputeValueVTs(TLI, LP.getType(), ValueVTs); 1840 1841 // Insert the EXCEPTIONADDR instruction. 1842 assert(FuncInfo.MBB->isLandingPad() && 1843 "Call to eh.exception not in landing pad!"); 1844 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1845 SDValue Ops[2]; 1846 Ops[0] = DAG.getRoot(); 1847 SDValue Op1 = DAG.getNode(ISD::EXCEPTIONADDR, getCurDebugLoc(), VTs, Ops, 1); 1848 SDValue Chain = Op1.getValue(1); 1849 1850 // Insert the EHSELECTION instruction. 1851 VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 1852 Ops[0] = Op1; 1853 Ops[1] = Chain; 1854 SDValue Op2 = DAG.getNode(ISD::EHSELECTION, getCurDebugLoc(), VTs, Ops, 2); 1855 Chain = Op2.getValue(1); 1856 Op2 = DAG.getSExtOrTrunc(Op2, getCurDebugLoc(), MVT::i32); 1857 1858 Ops[0] = Op1; 1859 Ops[1] = Op2; 1860 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 1861 DAG.getVTList(&ValueVTs[0], ValueVTs.size()), 1862 &Ops[0], 2); 1863 1864 std::pair<SDValue, SDValue> RetPair = std::make_pair(Res, Chain); 1865 setValue(&LP, RetPair.first); 1866 DAG.setRoot(RetPair.second); 1867 } 1868 1869 /// handleSmallSwitchCaseRange - Emit a series of specific tests (suitable for 1870 /// small case ranges). 1871 bool SelectionDAGBuilder::handleSmallSwitchRange(CaseRec& CR, 1872 CaseRecVector& WorkList, 1873 const Value* SV, 1874 MachineBasicBlock *Default, 1875 MachineBasicBlock *SwitchBB) { 1876 Case& BackCase = *(CR.Range.second-1); 1877 1878 // Size is the number of Cases represented by this range. 1879 size_t Size = CR.Range.second - CR.Range.first; 1880 if (Size > 3) 1881 return false; 1882 1883 // Get the MachineFunction which holds the current MBB. This is used when 1884 // inserting any additional MBBs necessary to represent the switch. 1885 MachineFunction *CurMF = FuncInfo.MF; 1886 1887 // Figure out which block is immediately after the current one. 1888 MachineBasicBlock *NextBlock = 0; 1889 MachineFunction::iterator BBI = CR.CaseBB; 1890 1891 if (++BBI != FuncInfo.MF->end()) 1892 NextBlock = BBI; 1893 1894 // If any two of the cases has the same destination, and if one value 1895 // is the same as the other, but has one bit unset that the other has set, 1896 // use bit manipulation to do two compares at once. For example: 1897 // "if (X == 6 || X == 4)" -> "if ((X|2) == 6)" 1898 // TODO: This could be extended to merge any 2 cases in switches with 3 cases. 1899 // TODO: Handle cases where CR.CaseBB != SwitchBB. 1900 if (Size == 2 && CR.CaseBB == SwitchBB) { 1901 Case &Small = *CR.Range.first; 1902 Case &Big = *(CR.Range.second-1); 1903 1904 if (Small.Low == Small.High && Big.Low == Big.High && Small.BB == Big.BB) { 1905 const APInt& SmallValue = cast<ConstantInt>(Small.Low)->getValue(); 1906 const APInt& BigValue = cast<ConstantInt>(Big.Low)->getValue(); 1907 1908 // Check that there is only one bit different. 1909 if (BigValue.countPopulation() == SmallValue.countPopulation() + 1 && 1910 (SmallValue | BigValue) == BigValue) { 1911 // Isolate the common bit. 1912 APInt CommonBit = BigValue & ~SmallValue; 1913 assert((SmallValue | CommonBit) == BigValue && 1914 CommonBit.countPopulation() == 1 && "Not a common bit?"); 1915 1916 SDValue CondLHS = getValue(SV); 1917 EVT VT = CondLHS.getValueType(); 1918 DebugLoc DL = getCurDebugLoc(); 1919 1920 SDValue Or = DAG.getNode(ISD::OR, DL, VT, CondLHS, 1921 DAG.getConstant(CommonBit, VT)); 1922 SDValue Cond = DAG.getSetCC(DL, MVT::i1, 1923 Or, DAG.getConstant(BigValue, VT), 1924 ISD::SETEQ); 1925 1926 // Update successor info. 1927 addSuccessorWithWeight(SwitchBB, Small.BB); 1928 addSuccessorWithWeight(SwitchBB, Default); 1929 1930 // Insert the true branch. 1931 SDValue BrCond = DAG.getNode(ISD::BRCOND, DL, MVT::Other, 1932 getControlRoot(), Cond, 1933 DAG.getBasicBlock(Small.BB)); 1934 1935 // Insert the false branch. 1936 BrCond = DAG.getNode(ISD::BR, DL, MVT::Other, BrCond, 1937 DAG.getBasicBlock(Default)); 1938 1939 DAG.setRoot(BrCond); 1940 return true; 1941 } 1942 } 1943 } 1944 1945 // Rearrange the case blocks so that the last one falls through if possible. 1946 if (NextBlock && Default != NextBlock && BackCase.BB != NextBlock) { 1947 // The last case block won't fall through into 'NextBlock' if we emit the 1948 // branches in this order. See if rearranging a case value would help. 1949 for (CaseItr I = CR.Range.first, E = CR.Range.second-1; I != E; ++I) { 1950 if (I->BB == NextBlock) { 1951 std::swap(*I, BackCase); 1952 break; 1953 } 1954 } 1955 } 1956 1957 // Create a CaseBlock record representing a conditional branch to 1958 // the Case's target mbb if the value being switched on SV is equal 1959 // to C. 1960 MachineBasicBlock *CurBlock = CR.CaseBB; 1961 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) { 1962 MachineBasicBlock *FallThrough; 1963 if (I != E-1) { 1964 FallThrough = CurMF->CreateMachineBasicBlock(CurBlock->getBasicBlock()); 1965 CurMF->insert(BBI, FallThrough); 1966 1967 // Put SV in a virtual register to make it available from the new blocks. 1968 ExportFromCurrentBlock(SV); 1969 } else { 1970 // If the last case doesn't match, go to the default block. 1971 FallThrough = Default; 1972 } 1973 1974 const Value *RHS, *LHS, *MHS; 1975 ISD::CondCode CC; 1976 if (I->High == I->Low) { 1977 // This is just small small case range :) containing exactly 1 case 1978 CC = ISD::SETEQ; 1979 LHS = SV; RHS = I->High; MHS = NULL; 1980 } else { 1981 CC = ISD::SETLE; 1982 LHS = I->Low; MHS = SV; RHS = I->High; 1983 } 1984 1985 uint32_t ExtraWeight = I->ExtraWeight; 1986 CaseBlock CB(CC, LHS, RHS, MHS, /* truebb */ I->BB, /* falsebb */ FallThrough, 1987 /* me */ CurBlock, 1988 /* trueweight */ ExtraWeight / 2, /* falseweight */ ExtraWeight / 2); 1989 1990 // If emitting the first comparison, just call visitSwitchCase to emit the 1991 // code into the current block. Otherwise, push the CaseBlock onto the 1992 // vector to be later processed by SDISel, and insert the node's MBB 1993 // before the next MBB. 1994 if (CurBlock == SwitchBB) 1995 visitSwitchCase(CB, SwitchBB); 1996 else 1997 SwitchCases.push_back(CB); 1998 1999 CurBlock = FallThrough; 2000 } 2001 2002 return true; 2003 } 2004 2005 static inline bool areJTsAllowed(const TargetLowering &TLI) { 2006 return !DisableJumpTables && 2007 (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || 2008 TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); 2009 } 2010 2011 static APInt ComputeRange(const APInt &First, const APInt &Last) { 2012 uint32_t BitWidth = std::max(Last.getBitWidth(), First.getBitWidth()) + 1; 2013 APInt LastExt = Last.sext(BitWidth), FirstExt = First.sext(BitWidth); 2014 return (LastExt - FirstExt + 1ULL); 2015 } 2016 2017 /// handleJTSwitchCase - Emit jumptable for current switch case range 2018 bool SelectionDAGBuilder::handleJTSwitchCase(CaseRec &CR, 2019 CaseRecVector &WorkList, 2020 const Value *SV, 2021 MachineBasicBlock *Default, 2022 MachineBasicBlock *SwitchBB) { 2023 Case& FrontCase = *CR.Range.first; 2024 Case& BackCase = *(CR.Range.second-1); 2025 2026 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2027 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2028 2029 APInt TSize(First.getBitWidth(), 0); 2030 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++I) 2031 TSize += I->size(); 2032 2033 if (!areJTsAllowed(TLI) || TSize.ult(4)) 2034 return false; 2035 2036 APInt Range = ComputeRange(First, Last); 2037 double Density = TSize.roundToDouble() / Range.roundToDouble(); 2038 if (Density < 0.4) 2039 return false; 2040 2041 DEBUG(dbgs() << "Lowering jump table\n" 2042 << "First entry: " << First << ". Last entry: " << Last << '\n' 2043 << "Range: " << Range 2044 << ". Size: " << TSize << ". Density: " << Density << "\n\n"); 2045 2046 // Get the MachineFunction which holds the current MBB. This is used when 2047 // inserting any additional MBBs necessary to represent the switch. 2048 MachineFunction *CurMF = FuncInfo.MF; 2049 2050 // Figure out which block is immediately after the current one. 2051 MachineFunction::iterator BBI = CR.CaseBB; 2052 ++BBI; 2053 2054 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2055 2056 // Create a new basic block to hold the code for loading the address 2057 // of the jump table, and jumping to it. Update successor information; 2058 // we will either branch to the default case for the switch, or the jump 2059 // table. 2060 MachineBasicBlock *JumpTableBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2061 CurMF->insert(BBI, JumpTableBB); 2062 2063 addSuccessorWithWeight(CR.CaseBB, Default); 2064 addSuccessorWithWeight(CR.CaseBB, JumpTableBB); 2065 2066 // Build a vector of destination BBs, corresponding to each target 2067 // of the jump table. If the value of the jump table slot corresponds to 2068 // a case statement, push the case's BB onto the vector, otherwise, push 2069 // the default BB. 2070 std::vector<MachineBasicBlock*> DestBBs; 2071 APInt TEI = First; 2072 for (CaseItr I = CR.Range.first, E = CR.Range.second; I != E; ++TEI) { 2073 const APInt &Low = cast<ConstantInt>(I->Low)->getValue(); 2074 const APInt &High = cast<ConstantInt>(I->High)->getValue(); 2075 2076 if (Low.sle(TEI) && TEI.sle(High)) { 2077 DestBBs.push_back(I->BB); 2078 if (TEI==High) 2079 ++I; 2080 } else { 2081 DestBBs.push_back(Default); 2082 } 2083 } 2084 2085 // Update successor info. Add one edge to each unique successor. 2086 BitVector SuccsHandled(CR.CaseBB->getParent()->getNumBlockIDs()); 2087 for (std::vector<MachineBasicBlock*>::iterator I = DestBBs.begin(), 2088 E = DestBBs.end(); I != E; ++I) { 2089 if (!SuccsHandled[(*I)->getNumber()]) { 2090 SuccsHandled[(*I)->getNumber()] = true; 2091 addSuccessorWithWeight(JumpTableBB, *I); 2092 } 2093 } 2094 2095 // Create a jump table index for this jump table. 2096 unsigned JTEncoding = TLI.getJumpTableEncoding(); 2097 unsigned JTI = CurMF->getOrCreateJumpTableInfo(JTEncoding) 2098 ->createJumpTableIndex(DestBBs); 2099 2100 // Set the jump table information so that we can codegen it as a second 2101 // MachineBasicBlock 2102 JumpTable JT(-1U, JTI, JumpTableBB, Default); 2103 JumpTableHeader JTH(First, Last, SV, CR.CaseBB, (CR.CaseBB == SwitchBB)); 2104 if (CR.CaseBB == SwitchBB) 2105 visitJumpTableHeader(JT, JTH, SwitchBB); 2106 2107 JTCases.push_back(JumpTableBlock(JTH, JT)); 2108 return true; 2109 } 2110 2111 /// handleBTSplitSwitchCase - emit comparison and split binary search tree into 2112 /// 2 subtrees. 2113 bool SelectionDAGBuilder::handleBTSplitSwitchCase(CaseRec& CR, 2114 CaseRecVector& WorkList, 2115 const Value* SV, 2116 MachineBasicBlock *Default, 2117 MachineBasicBlock *SwitchBB) { 2118 // Get the MachineFunction which holds the current MBB. This is used when 2119 // inserting any additional MBBs necessary to represent the switch. 2120 MachineFunction *CurMF = FuncInfo.MF; 2121 2122 // Figure out which block is immediately after the current one. 2123 MachineFunction::iterator BBI = CR.CaseBB; 2124 ++BBI; 2125 2126 Case& FrontCase = *CR.Range.first; 2127 Case& BackCase = *(CR.Range.second-1); 2128 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2129 2130 // Size is the number of Cases represented by this range. 2131 unsigned Size = CR.Range.second - CR.Range.first; 2132 2133 const APInt &First = cast<ConstantInt>(FrontCase.Low)->getValue(); 2134 const APInt &Last = cast<ConstantInt>(BackCase.High)->getValue(); 2135 double FMetric = 0; 2136 CaseItr Pivot = CR.Range.first + Size/2; 2137 2138 // Select optimal pivot, maximizing sum density of LHS and RHS. This will 2139 // (heuristically) allow us to emit JumpTable's later. 2140 APInt TSize(First.getBitWidth(), 0); 2141 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2142 I!=E; ++I) 2143 TSize += I->size(); 2144 2145 APInt LSize = FrontCase.size(); 2146 APInt RSize = TSize-LSize; 2147 DEBUG(dbgs() << "Selecting best pivot: \n" 2148 << "First: " << First << ", Last: " << Last <<'\n' 2149 << "LSize: " << LSize << ", RSize: " << RSize << '\n'); 2150 for (CaseItr I = CR.Range.first, J=I+1, E = CR.Range.second; 2151 J!=E; ++I, ++J) { 2152 const APInt &LEnd = cast<ConstantInt>(I->High)->getValue(); 2153 const APInt &RBegin = cast<ConstantInt>(J->Low)->getValue(); 2154 APInt Range = ComputeRange(LEnd, RBegin); 2155 assert((Range - 2ULL).isNonNegative() && 2156 "Invalid case distance"); 2157 // Use volatile double here to avoid excess precision issues on some hosts, 2158 // e.g. that use 80-bit X87 registers. 2159 volatile double LDensity = 2160 (double)LSize.roundToDouble() / 2161 (LEnd - First + 1ULL).roundToDouble(); 2162 volatile double RDensity = 2163 (double)RSize.roundToDouble() / 2164 (Last - RBegin + 1ULL).roundToDouble(); 2165 double Metric = Range.logBase2()*(LDensity+RDensity); 2166 // Should always split in some non-trivial place 2167 DEBUG(dbgs() <<"=>Step\n" 2168 << "LEnd: " << LEnd << ", RBegin: " << RBegin << '\n' 2169 << "LDensity: " << LDensity 2170 << ", RDensity: " << RDensity << '\n' 2171 << "Metric: " << Metric << '\n'); 2172 if (FMetric < Metric) { 2173 Pivot = J; 2174 FMetric = Metric; 2175 DEBUG(dbgs() << "Current metric set to: " << FMetric << '\n'); 2176 } 2177 2178 LSize += J->size(); 2179 RSize -= J->size(); 2180 } 2181 if (areJTsAllowed(TLI)) { 2182 // If our case is dense we *really* should handle it earlier! 2183 assert((FMetric > 0) && "Should handle dense range earlier!"); 2184 } else { 2185 Pivot = CR.Range.first + Size/2; 2186 } 2187 2188 CaseRange LHSR(CR.Range.first, Pivot); 2189 CaseRange RHSR(Pivot, CR.Range.second); 2190 Constant *C = Pivot->Low; 2191 MachineBasicBlock *FalseBB = 0, *TrueBB = 0; 2192 2193 // We know that we branch to the LHS if the Value being switched on is 2194 // less than the Pivot value, C. We use this to optimize our binary 2195 // tree a bit, by recognizing that if SV is greater than or equal to the 2196 // LHS's Case Value, and that Case Value is exactly one less than the 2197 // Pivot's Value, then we can branch directly to the LHS's Target, 2198 // rather than creating a leaf node for it. 2199 if ((LHSR.second - LHSR.first) == 1 && 2200 LHSR.first->High == CR.GE && 2201 cast<ConstantInt>(C)->getValue() == 2202 (cast<ConstantInt>(CR.GE)->getValue() + 1LL)) { 2203 TrueBB = LHSR.first->BB; 2204 } else { 2205 TrueBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2206 CurMF->insert(BBI, TrueBB); 2207 WorkList.push_back(CaseRec(TrueBB, C, CR.GE, LHSR)); 2208 2209 // Put SV in a virtual register to make it available from the new blocks. 2210 ExportFromCurrentBlock(SV); 2211 } 2212 2213 // Similar to the optimization above, if the Value being switched on is 2214 // known to be less than the Constant CR.LT, and the current Case Value 2215 // is CR.LT - 1, then we can branch directly to the target block for 2216 // the current Case Value, rather than emitting a RHS leaf node for it. 2217 if ((RHSR.second - RHSR.first) == 1 && CR.LT && 2218 cast<ConstantInt>(RHSR.first->Low)->getValue() == 2219 (cast<ConstantInt>(CR.LT)->getValue() - 1LL)) { 2220 FalseBB = RHSR.first->BB; 2221 } else { 2222 FalseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2223 CurMF->insert(BBI, FalseBB); 2224 WorkList.push_back(CaseRec(FalseBB,CR.LT,C,RHSR)); 2225 2226 // Put SV in a virtual register to make it available from the new blocks. 2227 ExportFromCurrentBlock(SV); 2228 } 2229 2230 // Create a CaseBlock record representing a conditional branch to 2231 // the LHS node if the value being switched on SV is less than C. 2232 // Otherwise, branch to LHS. 2233 CaseBlock CB(ISD::SETLT, SV, C, NULL, TrueBB, FalseBB, CR.CaseBB); 2234 2235 if (CR.CaseBB == SwitchBB) 2236 visitSwitchCase(CB, SwitchBB); 2237 else 2238 SwitchCases.push_back(CB); 2239 2240 return true; 2241 } 2242 2243 /// handleBitTestsSwitchCase - if current case range has few destination and 2244 /// range span less, than machine word bitwidth, encode case range into series 2245 /// of masks and emit bit tests with these masks. 2246 bool SelectionDAGBuilder::handleBitTestsSwitchCase(CaseRec& CR, 2247 CaseRecVector& WorkList, 2248 const Value* SV, 2249 MachineBasicBlock* Default, 2250 MachineBasicBlock *SwitchBB){ 2251 EVT PTy = TLI.getPointerTy(); 2252 unsigned IntPtrBits = PTy.getSizeInBits(); 2253 2254 Case& FrontCase = *CR.Range.first; 2255 Case& BackCase = *(CR.Range.second-1); 2256 2257 // Get the MachineFunction which holds the current MBB. This is used when 2258 // inserting any additional MBBs necessary to represent the switch. 2259 MachineFunction *CurMF = FuncInfo.MF; 2260 2261 // If target does not have legal shift left, do not emit bit tests at all. 2262 if (!TLI.isOperationLegal(ISD::SHL, TLI.getPointerTy())) 2263 return false; 2264 2265 size_t numCmps = 0; 2266 for (CaseItr I = CR.Range.first, E = CR.Range.second; 2267 I!=E; ++I) { 2268 // Single case counts one, case range - two. 2269 numCmps += (I->Low == I->High ? 1 : 2); 2270 } 2271 2272 // Count unique destinations 2273 SmallSet<MachineBasicBlock*, 4> Dests; 2274 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2275 Dests.insert(I->BB); 2276 if (Dests.size() > 3) 2277 // Don't bother the code below, if there are too much unique destinations 2278 return false; 2279 } 2280 DEBUG(dbgs() << "Total number of unique destinations: " 2281 << Dests.size() << '\n' 2282 << "Total number of comparisons: " << numCmps << '\n'); 2283 2284 // Compute span of values. 2285 const APInt& minValue = cast<ConstantInt>(FrontCase.Low)->getValue(); 2286 const APInt& maxValue = cast<ConstantInt>(BackCase.High)->getValue(); 2287 APInt cmpRange = maxValue - minValue; 2288 2289 DEBUG(dbgs() << "Compare range: " << cmpRange << '\n' 2290 << "Low bound: " << minValue << '\n' 2291 << "High bound: " << maxValue << '\n'); 2292 2293 if (cmpRange.uge(IntPtrBits) || 2294 (!(Dests.size() == 1 && numCmps >= 3) && 2295 !(Dests.size() == 2 && numCmps >= 5) && 2296 !(Dests.size() >= 3 && numCmps >= 6))) 2297 return false; 2298 2299 DEBUG(dbgs() << "Emitting bit tests\n"); 2300 APInt lowBound = APInt::getNullValue(cmpRange.getBitWidth()); 2301 2302 // Optimize the case where all the case values fit in a 2303 // word without having to subtract minValue. In this case, 2304 // we can optimize away the subtraction. 2305 if (minValue.isNonNegative() && maxValue.slt(IntPtrBits)) { 2306 cmpRange = maxValue; 2307 } else { 2308 lowBound = minValue; 2309 } 2310 2311 CaseBitsVector CasesBits; 2312 unsigned i, count = 0; 2313 2314 for (CaseItr I = CR.Range.first, E = CR.Range.second; I!=E; ++I) { 2315 MachineBasicBlock* Dest = I->BB; 2316 for (i = 0; i < count; ++i) 2317 if (Dest == CasesBits[i].BB) 2318 break; 2319 2320 if (i == count) { 2321 assert((count < 3) && "Too much destinations to test!"); 2322 CasesBits.push_back(CaseBits(0, Dest, 0)); 2323 count++; 2324 } 2325 2326 const APInt& lowValue = cast<ConstantInt>(I->Low)->getValue(); 2327 const APInt& highValue = cast<ConstantInt>(I->High)->getValue(); 2328 2329 uint64_t lo = (lowValue - lowBound).getZExtValue(); 2330 uint64_t hi = (highValue - lowBound).getZExtValue(); 2331 2332 for (uint64_t j = lo; j <= hi; j++) { 2333 CasesBits[i].Mask |= 1ULL << j; 2334 CasesBits[i].Bits++; 2335 } 2336 2337 } 2338 std::sort(CasesBits.begin(), CasesBits.end(), CaseBitsCmp()); 2339 2340 BitTestInfo BTC; 2341 2342 // Figure out which block is immediately after the current one. 2343 MachineFunction::iterator BBI = CR.CaseBB; 2344 ++BBI; 2345 2346 const BasicBlock *LLVMBB = CR.CaseBB->getBasicBlock(); 2347 2348 DEBUG(dbgs() << "Cases:\n"); 2349 for (unsigned i = 0, e = CasesBits.size(); i!=e; ++i) { 2350 DEBUG(dbgs() << "Mask: " << CasesBits[i].Mask 2351 << ", Bits: " << CasesBits[i].Bits 2352 << ", BB: " << CasesBits[i].BB << '\n'); 2353 2354 MachineBasicBlock *CaseBB = CurMF->CreateMachineBasicBlock(LLVMBB); 2355 CurMF->insert(BBI, CaseBB); 2356 BTC.push_back(BitTestCase(CasesBits[i].Mask, 2357 CaseBB, 2358 CasesBits[i].BB)); 2359 2360 // Put SV in a virtual register to make it available from the new blocks. 2361 ExportFromCurrentBlock(SV); 2362 } 2363 2364 BitTestBlock BTB(lowBound, cmpRange, SV, 2365 -1U, MVT::Other, (CR.CaseBB == SwitchBB), 2366 CR.CaseBB, Default, BTC); 2367 2368 if (CR.CaseBB == SwitchBB) 2369 visitBitTestHeader(BTB, SwitchBB); 2370 2371 BitTestCases.push_back(BTB); 2372 2373 return true; 2374 } 2375 2376 /// Clusterify - Transform simple list of Cases into list of CaseRange's 2377 size_t SelectionDAGBuilder::Clusterify(CaseVector& Cases, 2378 const SwitchInst& SI) { 2379 size_t numCmps = 0; 2380 2381 BranchProbabilityInfo *BPI = FuncInfo.BPI; 2382 // Start with "simple" cases 2383 for (size_t i = 1; i < SI.getNumSuccessors(); ++i) { 2384 BasicBlock *SuccBB = SI.getSuccessor(i); 2385 MachineBasicBlock *SMBB = FuncInfo.MBBMap[SuccBB]; 2386 2387 uint32_t ExtraWeight = BPI ? BPI->getEdgeWeight(SI.getParent(), SuccBB) : 0; 2388 2389 Cases.push_back(Case(SI.getSuccessorValue(i), 2390 SI.getSuccessorValue(i), 2391 SMBB, ExtraWeight)); 2392 } 2393 std::sort(Cases.begin(), Cases.end(), CaseCmp()); 2394 2395 // Merge case into clusters 2396 if (Cases.size() >= 2) 2397 // Must recompute end() each iteration because it may be 2398 // invalidated by erase if we hold on to it 2399 for (CaseItr I = Cases.begin(), J = llvm::next(Cases.begin()); 2400 J != Cases.end(); ) { 2401 const APInt& nextValue = cast<ConstantInt>(J->Low)->getValue(); 2402 const APInt& currentValue = cast<ConstantInt>(I->High)->getValue(); 2403 MachineBasicBlock* nextBB = J->BB; 2404 MachineBasicBlock* currentBB = I->BB; 2405 2406 // If the two neighboring cases go to the same destination, merge them 2407 // into a single case. 2408 if ((nextValue - currentValue == 1) && (currentBB == nextBB)) { 2409 I->High = J->High; 2410 J = Cases.erase(J); 2411 2412 if (BranchProbabilityInfo *BPI = FuncInfo.BPI) { 2413 uint32_t CurWeight = currentBB->getBasicBlock() ? 2414 BPI->getEdgeWeight(SI.getParent(), currentBB->getBasicBlock()) : 16; 2415 uint32_t NextWeight = nextBB->getBasicBlock() ? 2416 BPI->getEdgeWeight(SI.getParent(), nextBB->getBasicBlock()) : 16; 2417 2418 BPI->setEdgeWeight(SI.getParent(), currentBB->getBasicBlock(), 2419 CurWeight + NextWeight); 2420 } 2421 } else { 2422 I = J++; 2423 } 2424 } 2425 2426 for (CaseItr I=Cases.begin(), E=Cases.end(); I!=E; ++I, ++numCmps) { 2427 if (I->Low != I->High) 2428 // A range counts double, since it requires two compares. 2429 ++numCmps; 2430 } 2431 2432 return numCmps; 2433 } 2434 2435 void SelectionDAGBuilder::UpdateSplitBlock(MachineBasicBlock *First, 2436 MachineBasicBlock *Last) { 2437 // Update JTCases. 2438 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) 2439 if (JTCases[i].first.HeaderBB == First) 2440 JTCases[i].first.HeaderBB = Last; 2441 2442 // Update BitTestCases. 2443 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) 2444 if (BitTestCases[i].Parent == First) 2445 BitTestCases[i].Parent = Last; 2446 } 2447 2448 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) { 2449 MachineBasicBlock *SwitchMBB = FuncInfo.MBB; 2450 2451 // Figure out which block is immediately after the current one. 2452 MachineBasicBlock *NextBlock = 0; 2453 MachineBasicBlock *Default = FuncInfo.MBBMap[SI.getDefaultDest()]; 2454 2455 // If there is only the default destination, branch to it if it is not the 2456 // next basic block. Otherwise, just fall through. 2457 if (SI.getNumCases() == 1) { 2458 // Update machine-CFG edges. 2459 2460 // If this is not a fall-through branch, emit the branch. 2461 SwitchMBB->addSuccessor(Default); 2462 if (Default != NextBlock) 2463 DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), 2464 MVT::Other, getControlRoot(), 2465 DAG.getBasicBlock(Default))); 2466 2467 return; 2468 } 2469 2470 // If there are any non-default case statements, create a vector of Cases 2471 // representing each one, and sort the vector so that we can efficiently 2472 // create a binary search tree from them. 2473 CaseVector Cases; 2474 size_t numCmps = Clusterify(Cases, SI); 2475 DEBUG(dbgs() << "Clusterify finished. Total clusters: " << Cases.size() 2476 << ". Total compares: " << numCmps << '\n'); 2477 (void)numCmps; 2478 2479 // Get the Value to be switched on and default basic blocks, which will be 2480 // inserted into CaseBlock records, representing basic blocks in the binary 2481 // search tree. 2482 const Value *SV = SI.getCondition(); 2483 2484 // Push the initial CaseRec onto the worklist 2485 CaseRecVector WorkList; 2486 WorkList.push_back(CaseRec(SwitchMBB,0,0, 2487 CaseRange(Cases.begin(),Cases.end()))); 2488 2489 while (!WorkList.empty()) { 2490 // Grab a record representing a case range to process off the worklist 2491 CaseRec CR = WorkList.back(); 2492 WorkList.pop_back(); 2493 2494 if (handleBitTestsSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2495 continue; 2496 2497 // If the range has few cases (two or less) emit a series of specific 2498 // tests. 2499 if (handleSmallSwitchRange(CR, WorkList, SV, Default, SwitchMBB)) 2500 continue; 2501 2502 // If the switch has more than 5 blocks, and at least 40% dense, and the 2503 // target supports indirect branches, then emit a jump table rather than 2504 // lowering the switch to a binary tree of conditional branches. 2505 if (handleJTSwitchCase(CR, WorkList, SV, Default, SwitchMBB)) 2506 continue; 2507 2508 // Emit binary tree. We need to pick a pivot, and push left and right ranges 2509 // onto the worklist. Leafs are handled via handleSmallSwitchRange() call. 2510 handleBTSplitSwitchCase(CR, WorkList, SV, Default, SwitchMBB); 2511 } 2512 } 2513 2514 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) { 2515 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB; 2516 2517 // Update machine-CFG edges with unique successors. 2518 SmallVector<BasicBlock*, 32> succs; 2519 succs.reserve(I.getNumSuccessors()); 2520 for (unsigned i = 0, e = I.getNumSuccessors(); i != e; ++i) 2521 succs.push_back(I.getSuccessor(i)); 2522 array_pod_sort(succs.begin(), succs.end()); 2523 succs.erase(std::unique(succs.begin(), succs.end()), succs.end()); 2524 for (unsigned i = 0, e = succs.size(); i != e; ++i) { 2525 MachineBasicBlock *Succ = FuncInfo.MBBMap[succs[i]]; 2526 addSuccessorWithWeight(IndirectBrMBB, Succ); 2527 } 2528 2529 DAG.setRoot(DAG.getNode(ISD::BRIND, getCurDebugLoc(), 2530 MVT::Other, getControlRoot(), 2531 getValue(I.getAddress()))); 2532 } 2533 2534 void SelectionDAGBuilder::visitFSub(const User &I) { 2535 // -0.0 - X --> fneg 2536 Type *Ty = I.getType(); 2537 if (isa<Constant>(I.getOperand(0)) && 2538 I.getOperand(0) == ConstantFP::getZeroValueForNegation(Ty)) { 2539 SDValue Op2 = getValue(I.getOperand(1)); 2540 setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), 2541 Op2.getValueType(), Op2)); 2542 return; 2543 } 2544 2545 visitBinary(I, ISD::FSUB); 2546 } 2547 2548 void SelectionDAGBuilder::visitBinary(const User &I, unsigned OpCode) { 2549 SDValue Op1 = getValue(I.getOperand(0)); 2550 SDValue Op2 = getValue(I.getOperand(1)); 2551 setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), 2552 Op1.getValueType(), Op1, Op2)); 2553 } 2554 2555 void SelectionDAGBuilder::visitShift(const User &I, unsigned Opcode) { 2556 SDValue Op1 = getValue(I.getOperand(0)); 2557 SDValue Op2 = getValue(I.getOperand(1)); 2558 2559 MVT ShiftTy = TLI.getShiftAmountTy(Op2.getValueType()); 2560 2561 // Coerce the shift amount to the right type if we can. 2562 if (!I.getType()->isVectorTy() && Op2.getValueType() != ShiftTy) { 2563 unsigned ShiftSize = ShiftTy.getSizeInBits(); 2564 unsigned Op2Size = Op2.getValueType().getSizeInBits(); 2565 DebugLoc DL = getCurDebugLoc(); 2566 2567 // If the operand is smaller than the shift count type, promote it. 2568 if (ShiftSize > Op2Size) 2569 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); 2570 2571 // If the operand is larger than the shift count type but the shift 2572 // count type has enough bits to represent any shift value, truncate 2573 // it now. This is a common case and it exposes the truncate to 2574 // optimization early. 2575 else if (ShiftSize >= Log2_32_Ceil(Op2.getValueType().getSizeInBits())) 2576 Op2 = DAG.getNode(ISD::TRUNCATE, DL, ShiftTy, Op2); 2577 // Otherwise we'll need to temporarily settle for some other convenient 2578 // type. Type legalization will make adjustments once the shiftee is split. 2579 else 2580 Op2 = DAG.getZExtOrTrunc(Op2, DL, MVT::i32); 2581 } 2582 2583 setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), 2584 Op1.getValueType(), Op1, Op2)); 2585 } 2586 2587 void SelectionDAGBuilder::visitSDiv(const User &I) { 2588 SDValue Op1 = getValue(I.getOperand(0)); 2589 SDValue Op2 = getValue(I.getOperand(1)); 2590 2591 // Turn exact SDivs into multiplications. 2592 // FIXME: This should be in DAGCombiner, but it doesn't have access to the 2593 // exact bit. 2594 if (isa<BinaryOperator>(&I) && cast<BinaryOperator>(&I)->isExact() && 2595 !isa<ConstantSDNode>(Op1) && 2596 isa<ConstantSDNode>(Op2) && !cast<ConstantSDNode>(Op2)->isNullValue()) 2597 setValue(&I, TLI.BuildExactSDIV(Op1, Op2, getCurDebugLoc(), DAG)); 2598 else 2599 setValue(&I, DAG.getNode(ISD::SDIV, getCurDebugLoc(), Op1.getValueType(), 2600 Op1, Op2)); 2601 } 2602 2603 void SelectionDAGBuilder::visitICmp(const User &I) { 2604 ICmpInst::Predicate predicate = ICmpInst::BAD_ICMP_PREDICATE; 2605 if (const ICmpInst *IC = dyn_cast<ICmpInst>(&I)) 2606 predicate = IC->getPredicate(); 2607 else if (const ConstantExpr *IC = dyn_cast<ConstantExpr>(&I)) 2608 predicate = ICmpInst::Predicate(IC->getPredicate()); 2609 SDValue Op1 = getValue(I.getOperand(0)); 2610 SDValue Op2 = getValue(I.getOperand(1)); 2611 ISD::CondCode Opcode = getICmpCondCode(predicate); 2612 2613 EVT DestVT = TLI.getValueType(I.getType()); 2614 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode)); 2615 } 2616 2617 void SelectionDAGBuilder::visitFCmp(const User &I) { 2618 FCmpInst::Predicate predicate = FCmpInst::BAD_FCMP_PREDICATE; 2619 if (const FCmpInst *FC = dyn_cast<FCmpInst>(&I)) 2620 predicate = FC->getPredicate(); 2621 else if (const ConstantExpr *FC = dyn_cast<ConstantExpr>(&I)) 2622 predicate = FCmpInst::Predicate(FC->getPredicate()); 2623 SDValue Op1 = getValue(I.getOperand(0)); 2624 SDValue Op2 = getValue(I.getOperand(1)); 2625 ISD::CondCode Condition = getFCmpCondCode(predicate); 2626 EVT DestVT = TLI.getValueType(I.getType()); 2627 setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition)); 2628 } 2629 2630 void SelectionDAGBuilder::visitSelect(const User &I) { 2631 SmallVector<EVT, 4> ValueVTs; 2632 ComputeValueVTs(TLI, I.getType(), ValueVTs); 2633 unsigned NumValues = ValueVTs.size(); 2634 if (NumValues == 0) return; 2635 2636 SmallVector<SDValue, 4> Values(NumValues); 2637 SDValue Cond = getValue(I.getOperand(0)); 2638 SDValue TrueVal = getValue(I.getOperand(1)); 2639 SDValue FalseVal = getValue(I.getOperand(2)); 2640 ISD::NodeType OpCode = Cond.getValueType().isVector() ? 2641 ISD::VSELECT : ISD::SELECT; 2642 2643 for (unsigned i = 0; i != NumValues; ++i) 2644 Values[i] = DAG.getNode(OpCode, getCurDebugLoc(), 2645 TrueVal.getNode()->getValueType(TrueVal.getResNo()+i), 2646 Cond, 2647 SDValue(TrueVal.getNode(), 2648 TrueVal.getResNo() + i), 2649 SDValue(FalseVal.getNode(), 2650 FalseVal.getResNo() + i)); 2651 2652 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 2653 DAG.getVTList(&ValueVTs[0], NumValues), 2654 &Values[0], NumValues)); 2655 } 2656 2657 void SelectionDAGBuilder::visitTrunc(const User &I) { 2658 // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). 2659 SDValue N = getValue(I.getOperand(0)); 2660 EVT DestVT = TLI.getValueType(I.getType()); 2661 setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); 2662 } 2663 2664 void SelectionDAGBuilder::visitZExt(const User &I) { 2665 // ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2666 // ZExt also can't be a cast to bool for same reason. So, nothing much to do 2667 SDValue N = getValue(I.getOperand(0)); 2668 EVT DestVT = TLI.getValueType(I.getType()); 2669 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); 2670 } 2671 2672 void SelectionDAGBuilder::visitSExt(const User &I) { 2673 // SExt cannot be a no-op cast because sizeof(src) < sizeof(dest). 2674 // SExt also can't be a cast to bool for same reason. So, nothing much to do 2675 SDValue N = getValue(I.getOperand(0)); 2676 EVT DestVT = TLI.getValueType(I.getType()); 2677 setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); 2678 } 2679 2680 void SelectionDAGBuilder::visitFPTrunc(const User &I) { 2681 // FPTrunc is never a no-op cast, no need to check 2682 SDValue N = getValue(I.getOperand(0)); 2683 EVT DestVT = TLI.getValueType(I.getType()); 2684 setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), 2685 DestVT, N, DAG.getIntPtrConstant(0))); 2686 } 2687 2688 void SelectionDAGBuilder::visitFPExt(const User &I){ 2689 // FPExt is never a no-op cast, no need to check 2690 SDValue N = getValue(I.getOperand(0)); 2691 EVT DestVT = TLI.getValueType(I.getType()); 2692 setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); 2693 } 2694 2695 void SelectionDAGBuilder::visitFPToUI(const User &I) { 2696 // FPToUI is never a no-op cast, no need to check 2697 SDValue N = getValue(I.getOperand(0)); 2698 EVT DestVT = TLI.getValueType(I.getType()); 2699 setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); 2700 } 2701 2702 void SelectionDAGBuilder::visitFPToSI(const User &I) { 2703 // FPToSI is never a no-op cast, no need to check 2704 SDValue N = getValue(I.getOperand(0)); 2705 EVT DestVT = TLI.getValueType(I.getType()); 2706 setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); 2707 } 2708 2709 void SelectionDAGBuilder::visitUIToFP(const User &I) { 2710 // UIToFP is never a no-op cast, no need to check 2711 SDValue N = getValue(I.getOperand(0)); 2712 EVT DestVT = TLI.getValueType(I.getType()); 2713 setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2714 } 2715 2716 void SelectionDAGBuilder::visitSIToFP(const User &I){ 2717 // SIToFP is never a no-op cast, no need to check 2718 SDValue N = getValue(I.getOperand(0)); 2719 EVT DestVT = TLI.getValueType(I.getType()); 2720 setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); 2721 } 2722 2723 void SelectionDAGBuilder::visitPtrToInt(const User &I) { 2724 // What to do depends on the size of the integer and the size of the pointer. 2725 // We can either truncate, zero extend, or no-op, accordingly. 2726 SDValue N = getValue(I.getOperand(0)); 2727 EVT DestVT = TLI.getValueType(I.getType()); 2728 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2729 } 2730 2731 void SelectionDAGBuilder::visitIntToPtr(const User &I) { 2732 // What to do depends on the size of the integer and the size of the pointer. 2733 // We can either truncate, zero extend, or no-op, accordingly. 2734 SDValue N = getValue(I.getOperand(0)); 2735 EVT DestVT = TLI.getValueType(I.getType()); 2736 setValue(&I, DAG.getZExtOrTrunc(N, getCurDebugLoc(), DestVT)); 2737 } 2738 2739 void SelectionDAGBuilder::visitBitCast(const User &I) { 2740 SDValue N = getValue(I.getOperand(0)); 2741 EVT DestVT = TLI.getValueType(I.getType()); 2742 2743 // BitCast assures us that source and destination are the same size so this is 2744 // either a BITCAST or a no-op. 2745 if (DestVT != N.getValueType()) 2746 setValue(&I, DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 2747 DestVT, N)); // convert types. 2748 else 2749 setValue(&I, N); // noop cast. 2750 } 2751 2752 void SelectionDAGBuilder::visitInsertElement(const User &I) { 2753 SDValue InVec = getValue(I.getOperand(0)); 2754 SDValue InVal = getValue(I.getOperand(1)); 2755 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2756 TLI.getPointerTy(), 2757 getValue(I.getOperand(2))); 2758 setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), 2759 TLI.getValueType(I.getType()), 2760 InVec, InVal, InIdx)); 2761 } 2762 2763 void SelectionDAGBuilder::visitExtractElement(const User &I) { 2764 SDValue InVec = getValue(I.getOperand(0)); 2765 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), 2766 TLI.getPointerTy(), 2767 getValue(I.getOperand(1))); 2768 setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2769 TLI.getValueType(I.getType()), InVec, InIdx)); 2770 } 2771 2772 // Utility for visitShuffleVector - Returns true if the mask is mask starting 2773 // from SIndx and increasing to the element length (undefs are allowed). 2774 static bool SequentialMask(SmallVectorImpl<int> &Mask, unsigned SIndx) { 2775 unsigned MaskNumElts = Mask.size(); 2776 for (unsigned i = 0; i != MaskNumElts; ++i) 2777 if ((Mask[i] >= 0) && (Mask[i] != (int)(i + SIndx))) 2778 return false; 2779 return true; 2780 } 2781 2782 void SelectionDAGBuilder::visitShuffleVector(const User &I) { 2783 SmallVector<int, 8> Mask; 2784 SDValue Src1 = getValue(I.getOperand(0)); 2785 SDValue Src2 = getValue(I.getOperand(1)); 2786 2787 // Convert the ConstantVector mask operand into an array of ints, with -1 2788 // representing undef values. 2789 SmallVector<Constant*, 8> MaskElts; 2790 cast<Constant>(I.getOperand(2))->getVectorElements(MaskElts); 2791 unsigned MaskNumElts = MaskElts.size(); 2792 for (unsigned i = 0; i != MaskNumElts; ++i) { 2793 if (isa<UndefValue>(MaskElts[i])) 2794 Mask.push_back(-1); 2795 else 2796 Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue()); 2797 } 2798 2799 EVT VT = TLI.getValueType(I.getType()); 2800 EVT SrcVT = Src1.getValueType(); 2801 unsigned SrcNumElts = SrcVT.getVectorNumElements(); 2802 2803 if (SrcNumElts == MaskNumElts) { 2804 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2805 &Mask[0])); 2806 return; 2807 } 2808 2809 // Normalize the shuffle vector since mask and vector length don't match. 2810 if (SrcNumElts < MaskNumElts && MaskNumElts % SrcNumElts == 0) { 2811 // Mask is longer than the source vectors and is a multiple of the source 2812 // vectors. We can use concatenate vector to make the mask and vectors 2813 // lengths match. 2814 if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { 2815 // The shuffle is concatenating two vectors together. 2816 setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), 2817 VT, Src1, Src2)); 2818 return; 2819 } 2820 2821 // Pad both vectors with undefs to make them the same length as the mask. 2822 unsigned NumConcat = MaskNumElts / SrcNumElts; 2823 bool Src1U = Src1.getOpcode() == ISD::UNDEF; 2824 bool Src2U = Src2.getOpcode() == ISD::UNDEF; 2825 SDValue UndefVal = DAG.getUNDEF(SrcVT); 2826 2827 SmallVector<SDValue, 8> MOps1(NumConcat, UndefVal); 2828 SmallVector<SDValue, 8> MOps2(NumConcat, UndefVal); 2829 MOps1[0] = Src1; 2830 MOps2[0] = Src2; 2831 2832 Src1 = Src1U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2833 getCurDebugLoc(), VT, 2834 &MOps1[0], NumConcat); 2835 Src2 = Src2U ? DAG.getUNDEF(VT) : DAG.getNode(ISD::CONCAT_VECTORS, 2836 getCurDebugLoc(), VT, 2837 &MOps2[0], NumConcat); 2838 2839 // Readjust mask for new input vector length. 2840 SmallVector<int, 8> MappedOps; 2841 for (unsigned i = 0; i != MaskNumElts; ++i) { 2842 int Idx = Mask[i]; 2843 if (Idx < (int)SrcNumElts) 2844 MappedOps.push_back(Idx); 2845 else 2846 MappedOps.push_back(Idx + MaskNumElts - SrcNumElts); 2847 } 2848 2849 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2850 &MappedOps[0])); 2851 return; 2852 } 2853 2854 if (SrcNumElts > MaskNumElts) { 2855 // Analyze the access pattern of the vector to see if we can extract 2856 // two subvectors and do the shuffle. The analysis is done by calculating 2857 // the range of elements the mask access on both vectors. 2858 int MinRange[2] = { static_cast<int>(SrcNumElts+1), 2859 static_cast<int>(SrcNumElts+1)}; 2860 int MaxRange[2] = {-1, -1}; 2861 2862 for (unsigned i = 0; i != MaskNumElts; ++i) { 2863 int Idx = Mask[i]; 2864 int Input = 0; 2865 if (Idx < 0) 2866 continue; 2867 2868 if (Idx >= (int)SrcNumElts) { 2869 Input = 1; 2870 Idx -= SrcNumElts; 2871 } 2872 if (Idx > MaxRange[Input]) 2873 MaxRange[Input] = Idx; 2874 if (Idx < MinRange[Input]) 2875 MinRange[Input] = Idx; 2876 } 2877 2878 // Check if the access is smaller than the vector size and can we find 2879 // a reasonable extract index. 2880 int RangeUse[2] = { 2, 2 }; // 0 = Unused, 1 = Extract, 2 = Can not 2881 // Extract. 2882 int StartIdx[2]; // StartIdx to extract from 2883 for (int Input=0; Input < 2; ++Input) { 2884 if (MinRange[Input] == (int)(SrcNumElts+1) && MaxRange[Input] == -1) { 2885 RangeUse[Input] = 0; // Unused 2886 StartIdx[Input] = 0; 2887 } else if (MaxRange[Input] - MinRange[Input] < (int)MaskNumElts) { 2888 // Fits within range but we should see if we can find a good 2889 // start index that is a multiple of the mask length. 2890 if (MaxRange[Input] < (int)MaskNumElts) { 2891 RangeUse[Input] = 1; // Extract from beginning of the vector 2892 StartIdx[Input] = 0; 2893 } else { 2894 StartIdx[Input] = (MinRange[Input]/MaskNumElts)*MaskNumElts; 2895 if (MaxRange[Input] - StartIdx[Input] < (int)MaskNumElts && 2896 StartIdx[Input] + MaskNumElts <= SrcNumElts) 2897 RangeUse[Input] = 1; // Extract from a multiple of the mask length. 2898 } 2899 } 2900 } 2901 2902 if (RangeUse[0] == 0 && RangeUse[1] == 0) { 2903 setValue(&I, DAG.getUNDEF(VT)); // Vectors are not used. 2904 return; 2905 } 2906 else if (RangeUse[0] < 2 && RangeUse[1] < 2) { 2907 // Extract appropriate subvector and generate a vector shuffle 2908 for (int Input=0; Input < 2; ++Input) { 2909 SDValue &Src = Input == 0 ? Src1 : Src2; 2910 if (RangeUse[Input] == 0) 2911 Src = DAG.getUNDEF(VT); 2912 else 2913 Src = DAG.getNode(ISD::EXTRACT_SUBVECTOR, getCurDebugLoc(), VT, 2914 Src, DAG.getIntPtrConstant(StartIdx[Input])); 2915 } 2916 2917 // Calculate new mask. 2918 SmallVector<int, 8> MappedOps; 2919 for (unsigned i = 0; i != MaskNumElts; ++i) { 2920 int Idx = Mask[i]; 2921 if (Idx < 0) 2922 MappedOps.push_back(Idx); 2923 else if (Idx < (int)SrcNumElts) 2924 MappedOps.push_back(Idx - StartIdx[0]); 2925 else 2926 MappedOps.push_back(Idx - SrcNumElts - StartIdx[1] + MaskNumElts); 2927 } 2928 2929 setValue(&I, DAG.getVectorShuffle(VT, getCurDebugLoc(), Src1, Src2, 2930 &MappedOps[0])); 2931 return; 2932 } 2933 } 2934 2935 // We can't use either concat vectors or extract subvectors so fall back to 2936 // replacing the shuffle with extract and build vector. 2937 // to insert and build vector. 2938 EVT EltVT = VT.getVectorElementType(); 2939 EVT PtrVT = TLI.getPointerTy(); 2940 SmallVector<SDValue,8> Ops; 2941 for (unsigned i = 0; i != MaskNumElts; ++i) { 2942 if (Mask[i] < 0) { 2943 Ops.push_back(DAG.getUNDEF(EltVT)); 2944 } else { 2945 int Idx = Mask[i]; 2946 SDValue Res; 2947 2948 if (Idx < (int)SrcNumElts) 2949 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2950 EltVT, Src1, DAG.getConstant(Idx, PtrVT)); 2951 else 2952 Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), 2953 EltVT, Src2, 2954 DAG.getConstant(Idx - SrcNumElts, PtrVT)); 2955 2956 Ops.push_back(Res); 2957 } 2958 } 2959 2960 setValue(&I, DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), 2961 VT, &Ops[0], Ops.size())); 2962 } 2963 2964 void SelectionDAGBuilder::visitInsertValue(const InsertValueInst &I) { 2965 const Value *Op0 = I.getOperand(0); 2966 const Value *Op1 = I.getOperand(1); 2967 Type *AggTy = I.getType(); 2968 Type *ValTy = Op1->getType(); 2969 bool IntoUndef = isa<UndefValue>(Op0); 2970 bool FromUndef = isa<UndefValue>(Op1); 2971 2972 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 2973 2974 SmallVector<EVT, 4> AggValueVTs; 2975 ComputeValueVTs(TLI, AggTy, AggValueVTs); 2976 SmallVector<EVT, 4> ValValueVTs; 2977 ComputeValueVTs(TLI, ValTy, ValValueVTs); 2978 2979 unsigned NumAggValues = AggValueVTs.size(); 2980 unsigned NumValValues = ValValueVTs.size(); 2981 SmallVector<SDValue, 4> Values(NumAggValues); 2982 2983 SDValue Agg = getValue(Op0); 2984 unsigned i = 0; 2985 // Copy the beginning value(s) from the original aggregate. 2986 for (; i != LinearIndex; ++i) 2987 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2988 SDValue(Agg.getNode(), Agg.getResNo() + i); 2989 // Copy values from the inserted value(s). 2990 if (NumValValues) { 2991 SDValue Val = getValue(Op1); 2992 for (; i != LinearIndex + NumValValues; ++i) 2993 Values[i] = FromUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2994 SDValue(Val.getNode(), Val.getResNo() + i - LinearIndex); 2995 } 2996 // Copy remaining value(s) from the original aggregate. 2997 for (; i != NumAggValues; ++i) 2998 Values[i] = IntoUndef ? DAG.getUNDEF(AggValueVTs[i]) : 2999 SDValue(Agg.getNode(), Agg.getResNo() + i); 3000 3001 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3002 DAG.getVTList(&AggValueVTs[0], NumAggValues), 3003 &Values[0], NumAggValues)); 3004 } 3005 3006 void SelectionDAGBuilder::visitExtractValue(const ExtractValueInst &I) { 3007 const Value *Op0 = I.getOperand(0); 3008 Type *AggTy = Op0->getType(); 3009 Type *ValTy = I.getType(); 3010 bool OutOfUndef = isa<UndefValue>(Op0); 3011 3012 unsigned LinearIndex = ComputeLinearIndex(AggTy, I.getIndices()); 3013 3014 SmallVector<EVT, 4> ValValueVTs; 3015 ComputeValueVTs(TLI, ValTy, ValValueVTs); 3016 3017 unsigned NumValValues = ValValueVTs.size(); 3018 3019 // Ignore a extractvalue that produces an empty object 3020 if (!NumValValues) { 3021 setValue(&I, DAG.getUNDEF(MVT(MVT::Other))); 3022 return; 3023 } 3024 3025 SmallVector<SDValue, 4> Values(NumValValues); 3026 3027 SDValue Agg = getValue(Op0); 3028 // Copy out the selected value(s). 3029 for (unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i) 3030 Values[i - LinearIndex] = 3031 OutOfUndef ? 3032 DAG.getUNDEF(Agg.getNode()->getValueType(Agg.getResNo() + i)) : 3033 SDValue(Agg.getNode(), Agg.getResNo() + i); 3034 3035 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3036 DAG.getVTList(&ValValueVTs[0], NumValValues), 3037 &Values[0], NumValValues)); 3038 } 3039 3040 void SelectionDAGBuilder::visitGetElementPtr(const User &I) { 3041 SDValue N = getValue(I.getOperand(0)); 3042 Type *Ty = I.getOperand(0)->getType(); 3043 3044 for (GetElementPtrInst::const_op_iterator OI = I.op_begin()+1, E = I.op_end(); 3045 OI != E; ++OI) { 3046 const Value *Idx = *OI; 3047 if (StructType *StTy = dyn_cast<StructType>(Ty)) { 3048 unsigned Field = cast<ConstantInt>(Idx)->getZExtValue(); 3049 if (Field) { 3050 // N = N + Offset 3051 uint64_t Offset = TD->getStructLayout(StTy)->getElementOffset(Field); 3052 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3053 DAG.getIntPtrConstant(Offset)); 3054 } 3055 3056 Ty = StTy->getElementType(Field); 3057 } else { 3058 Ty = cast<SequentialType>(Ty)->getElementType(); 3059 3060 // If this is a constant subscript, handle it quickly. 3061 if (const ConstantInt *CI = dyn_cast<ConstantInt>(Idx)) { 3062 if (CI->isZero()) continue; 3063 uint64_t Offs = 3064 TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue(); 3065 SDValue OffsVal; 3066 EVT PTy = TLI.getPointerTy(); 3067 unsigned PtrBits = PTy.getSizeInBits(); 3068 if (PtrBits < 64) 3069 OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), 3070 TLI.getPointerTy(), 3071 DAG.getConstant(Offs, MVT::i64)); 3072 else 3073 OffsVal = DAG.getIntPtrConstant(Offs); 3074 3075 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N, 3076 OffsVal); 3077 continue; 3078 } 3079 3080 // N = N + Idx * ElementSize; 3081 APInt ElementSize = APInt(TLI.getPointerTy().getSizeInBits(), 3082 TD->getTypeAllocSize(Ty)); 3083 SDValue IdxN = getValue(Idx); 3084 3085 // If the index is smaller or larger than intptr_t, truncate or extend 3086 // it. 3087 IdxN = DAG.getSExtOrTrunc(IdxN, getCurDebugLoc(), N.getValueType()); 3088 3089 // If this is a multiply by a power of two, turn it into a shl 3090 // immediately. This is a very common case. 3091 if (ElementSize != 1) { 3092 if (ElementSize.isPowerOf2()) { 3093 unsigned Amt = ElementSize.logBase2(); 3094 IdxN = DAG.getNode(ISD::SHL, getCurDebugLoc(), 3095 N.getValueType(), IdxN, 3096 DAG.getConstant(Amt, TLI.getPointerTy())); 3097 } else { 3098 SDValue Scale = DAG.getConstant(ElementSize, TLI.getPointerTy()); 3099 IdxN = DAG.getNode(ISD::MUL, getCurDebugLoc(), 3100 N.getValueType(), IdxN, Scale); 3101 } 3102 } 3103 3104 N = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3105 N.getValueType(), N, IdxN); 3106 } 3107 } 3108 3109 setValue(&I, N); 3110 } 3111 3112 void SelectionDAGBuilder::visitAlloca(const AllocaInst &I) { 3113 // If this is a fixed sized alloca in the entry block of the function, 3114 // allocate it statically on the stack. 3115 if (FuncInfo.StaticAllocaMap.count(&I)) 3116 return; // getValue will auto-populate this. 3117 3118 Type *Ty = I.getAllocatedType(); 3119 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 3120 unsigned Align = 3121 std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), 3122 I.getAlignment()); 3123 3124 SDValue AllocSize = getValue(I.getArraySize()); 3125 3126 EVT IntPtr = TLI.getPointerTy(); 3127 if (AllocSize.getValueType() != IntPtr) 3128 AllocSize = DAG.getZExtOrTrunc(AllocSize, getCurDebugLoc(), IntPtr); 3129 3130 AllocSize = DAG.getNode(ISD::MUL, getCurDebugLoc(), IntPtr, 3131 AllocSize, 3132 DAG.getConstant(TySize, IntPtr)); 3133 3134 // Handle alignment. If the requested alignment is less than or equal to 3135 // the stack alignment, ignore it. If the size is greater than or equal to 3136 // the stack alignment, we note this in the DYNAMIC_STACKALLOC node. 3137 unsigned StackAlign = TM.getFrameLowering()->getStackAlignment(); 3138 if (Align <= StackAlign) 3139 Align = 0; 3140 3141 // Round the size of the allocation up to the stack alignment size 3142 // by add SA-1 to the size. 3143 AllocSize = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3144 AllocSize.getValueType(), AllocSize, 3145 DAG.getIntPtrConstant(StackAlign-1)); 3146 3147 // Mask out the low bits for alignment purposes. 3148 AllocSize = DAG.getNode(ISD::AND, getCurDebugLoc(), 3149 AllocSize.getValueType(), AllocSize, 3150 DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1))); 3151 3152 SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) }; 3153 SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other); 3154 SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(), 3155 VTs, Ops, 3); 3156 setValue(&I, DSA); 3157 DAG.setRoot(DSA.getValue(1)); 3158 3159 // Inform the Frame Information that we have just allocated a variable-sized 3160 // object. 3161 FuncInfo.MF->getFrameInfo()->CreateVariableSizedObject(Align ? Align : 1); 3162 } 3163 3164 void SelectionDAGBuilder::visitLoad(const LoadInst &I) { 3165 if (I.isAtomic()) 3166 return visitAtomicLoad(I); 3167 3168 const Value *SV = I.getOperand(0); 3169 SDValue Ptr = getValue(SV); 3170 3171 Type *Ty = I.getType(); 3172 3173 bool isVolatile = I.isVolatile(); 3174 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3175 unsigned Alignment = I.getAlignment(); 3176 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3177 3178 SmallVector<EVT, 4> ValueVTs; 3179 SmallVector<uint64_t, 4> Offsets; 3180 ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets); 3181 unsigned NumValues = ValueVTs.size(); 3182 if (NumValues == 0) 3183 return; 3184 3185 SDValue Root; 3186 bool ConstantMemory = false; 3187 if (I.isVolatile() || NumValues > MaxParallelChains) 3188 // Serialize volatile loads with other side effects. 3189 Root = getRoot(); 3190 else if (AA->pointsToConstantMemory( 3191 AliasAnalysis::Location(SV, AA->getTypeStoreSize(Ty), TBAAInfo))) { 3192 // Do not serialize (non-volatile) loads of constant memory with anything. 3193 Root = DAG.getEntryNode(); 3194 ConstantMemory = true; 3195 } else { 3196 // Do not serialize non-volatile loads against each other. 3197 Root = DAG.getRoot(); 3198 } 3199 3200 SmallVector<SDValue, 4> Values(NumValues); 3201 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3202 NumValues)); 3203 EVT PtrVT = Ptr.getValueType(); 3204 unsigned ChainI = 0; 3205 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3206 // Serializing loads here may result in excessive register pressure, and 3207 // TokenFactor places arbitrary choke points on the scheduler. SD scheduling 3208 // could recover a bit by hoisting nodes upward in the chain by recognizing 3209 // they are side-effect free or do not alias. The optimizer should really 3210 // avoid this case by converting large object/array copies to llvm.memcpy 3211 // (MaxParallelChains should always remain as failsafe). 3212 if (ChainI == MaxParallelChains) { 3213 assert(PendingLoads.empty() && "PendingLoads must be serialized first"); 3214 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3215 MVT::Other, &Chains[0], ChainI); 3216 Root = Chain; 3217 ChainI = 0; 3218 } 3219 SDValue A = DAG.getNode(ISD::ADD, getCurDebugLoc(), 3220 PtrVT, Ptr, 3221 DAG.getConstant(Offsets[i], PtrVT)); 3222 SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root, 3223 A, MachinePointerInfo(SV, Offsets[i]), isVolatile, 3224 isNonTemporal, Alignment, TBAAInfo); 3225 3226 Values[i] = L; 3227 Chains[ChainI] = L.getValue(1); 3228 } 3229 3230 if (!ConstantMemory) { 3231 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3232 MVT::Other, &Chains[0], ChainI); 3233 if (isVolatile) 3234 DAG.setRoot(Chain); 3235 else 3236 PendingLoads.push_back(Chain); 3237 } 3238 3239 setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 3240 DAG.getVTList(&ValueVTs[0], NumValues), 3241 &Values[0], NumValues)); 3242 } 3243 3244 void SelectionDAGBuilder::visitStore(const StoreInst &I) { 3245 if (I.isAtomic()) 3246 return visitAtomicStore(I); 3247 3248 const Value *SrcV = I.getOperand(0); 3249 const Value *PtrV = I.getOperand(1); 3250 3251 SmallVector<EVT, 4> ValueVTs; 3252 SmallVector<uint64_t, 4> Offsets; 3253 ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets); 3254 unsigned NumValues = ValueVTs.size(); 3255 if (NumValues == 0) 3256 return; 3257 3258 // Get the lowered operands. Note that we do this after 3259 // checking if NumResults is zero, because with zero results 3260 // the operands won't have values in the map. 3261 SDValue Src = getValue(SrcV); 3262 SDValue Ptr = getValue(PtrV); 3263 3264 SDValue Root = getRoot(); 3265 SmallVector<SDValue, 4> Chains(std::min(unsigned(MaxParallelChains), 3266 NumValues)); 3267 EVT PtrVT = Ptr.getValueType(); 3268 bool isVolatile = I.isVolatile(); 3269 bool isNonTemporal = I.getMetadata("nontemporal") != 0; 3270 unsigned Alignment = I.getAlignment(); 3271 const MDNode *TBAAInfo = I.getMetadata(LLVMContext::MD_tbaa); 3272 3273 unsigned ChainI = 0; 3274 for (unsigned i = 0; i != NumValues; ++i, ++ChainI) { 3275 // See visitLoad comments. 3276 if (ChainI == MaxParallelChains) { 3277 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3278 MVT::Other, &Chains[0], ChainI); 3279 Root = Chain; 3280 ChainI = 0; 3281 } 3282 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, Ptr, 3283 DAG.getConstant(Offsets[i], PtrVT)); 3284 SDValue St = DAG.getStore(Root, getCurDebugLoc(), 3285 SDValue(Src.getNode(), Src.getResNo() + i), 3286 Add, MachinePointerInfo(PtrV, Offsets[i]), 3287 isVolatile, isNonTemporal, Alignment, TBAAInfo); 3288 Chains[ChainI] = St; 3289 } 3290 3291 SDValue StoreNode = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 3292 MVT::Other, &Chains[0], ChainI); 3293 ++SDNodeOrder; 3294 AssignOrderingToNode(StoreNode.getNode()); 3295 DAG.setRoot(StoreNode); 3296 } 3297 3298 static SDValue InsertFenceForAtomic(SDValue Chain, AtomicOrdering Order, 3299 SynchronizationScope Scope, 3300 bool Before, DebugLoc dl, 3301 SelectionDAG &DAG, 3302 const TargetLowering &TLI) { 3303 // Fence, if necessary 3304 if (Before) { 3305 if (Order == AcquireRelease || Order == SequentiallyConsistent) 3306 Order = Release; 3307 else if (Order == Acquire || Order == Monotonic) 3308 return Chain; 3309 } else { 3310 if (Order == AcquireRelease) 3311 Order = Acquire; 3312 else if (Order == Release || Order == Monotonic) 3313 return Chain; 3314 } 3315 SDValue Ops[3]; 3316 Ops[0] = Chain; 3317 Ops[1] = DAG.getConstant(Order, TLI.getPointerTy()); 3318 Ops[2] = DAG.getConstant(Scope, TLI.getPointerTy()); 3319 return DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3); 3320 } 3321 3322 void SelectionDAGBuilder::visitAtomicCmpXchg(const AtomicCmpXchgInst &I) { 3323 DebugLoc dl = getCurDebugLoc(); 3324 AtomicOrdering Order = I.getOrdering(); 3325 SynchronizationScope Scope = I.getSynchScope(); 3326 3327 SDValue InChain = getRoot(); 3328 3329 if (TLI.getInsertFencesForAtomic()) 3330 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3331 DAG, TLI); 3332 3333 SDValue L = 3334 DAG.getAtomic(ISD::ATOMIC_CMP_SWAP, dl, 3335 getValue(I.getCompareOperand()).getValueType().getSimpleVT(), 3336 InChain, 3337 getValue(I.getPointerOperand()), 3338 getValue(I.getCompareOperand()), 3339 getValue(I.getNewValOperand()), 3340 MachinePointerInfo(I.getPointerOperand()), 0 /* Alignment */, 3341 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3342 Scope); 3343 3344 SDValue OutChain = L.getValue(1); 3345 3346 if (TLI.getInsertFencesForAtomic()) 3347 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3348 DAG, TLI); 3349 3350 setValue(&I, L); 3351 DAG.setRoot(OutChain); 3352 } 3353 3354 void SelectionDAGBuilder::visitAtomicRMW(const AtomicRMWInst &I) { 3355 DebugLoc dl = getCurDebugLoc(); 3356 ISD::NodeType NT; 3357 switch (I.getOperation()) { 3358 default: llvm_unreachable("Unknown atomicrmw operation"); return; 3359 case AtomicRMWInst::Xchg: NT = ISD::ATOMIC_SWAP; break; 3360 case AtomicRMWInst::Add: NT = ISD::ATOMIC_LOAD_ADD; break; 3361 case AtomicRMWInst::Sub: NT = ISD::ATOMIC_LOAD_SUB; break; 3362 case AtomicRMWInst::And: NT = ISD::ATOMIC_LOAD_AND; break; 3363 case AtomicRMWInst::Nand: NT = ISD::ATOMIC_LOAD_NAND; break; 3364 case AtomicRMWInst::Or: NT = ISD::ATOMIC_LOAD_OR; break; 3365 case AtomicRMWInst::Xor: NT = ISD::ATOMIC_LOAD_XOR; break; 3366 case AtomicRMWInst::Max: NT = ISD::ATOMIC_LOAD_MAX; break; 3367 case AtomicRMWInst::Min: NT = ISD::ATOMIC_LOAD_MIN; break; 3368 case AtomicRMWInst::UMax: NT = ISD::ATOMIC_LOAD_UMAX; break; 3369 case AtomicRMWInst::UMin: NT = ISD::ATOMIC_LOAD_UMIN; break; 3370 } 3371 AtomicOrdering Order = I.getOrdering(); 3372 SynchronizationScope Scope = I.getSynchScope(); 3373 3374 SDValue InChain = getRoot(); 3375 3376 if (TLI.getInsertFencesForAtomic()) 3377 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3378 DAG, TLI); 3379 3380 SDValue L = 3381 DAG.getAtomic(NT, dl, 3382 getValue(I.getValOperand()).getValueType().getSimpleVT(), 3383 InChain, 3384 getValue(I.getPointerOperand()), 3385 getValue(I.getValOperand()), 3386 I.getPointerOperand(), 0 /* Alignment */, 3387 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3388 Scope); 3389 3390 SDValue OutChain = L.getValue(1); 3391 3392 if (TLI.getInsertFencesForAtomic()) 3393 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3394 DAG, TLI); 3395 3396 setValue(&I, L); 3397 DAG.setRoot(OutChain); 3398 } 3399 3400 void SelectionDAGBuilder::visitFence(const FenceInst &I) { 3401 DebugLoc dl = getCurDebugLoc(); 3402 SDValue Ops[3]; 3403 Ops[0] = getRoot(); 3404 Ops[1] = DAG.getConstant(I.getOrdering(), TLI.getPointerTy()); 3405 Ops[2] = DAG.getConstant(I.getSynchScope(), TLI.getPointerTy()); 3406 DAG.setRoot(DAG.getNode(ISD::ATOMIC_FENCE, dl, MVT::Other, Ops, 3)); 3407 } 3408 3409 void SelectionDAGBuilder::visitAtomicLoad(const LoadInst &I) { 3410 DebugLoc dl = getCurDebugLoc(); 3411 AtomicOrdering Order = I.getOrdering(); 3412 SynchronizationScope Scope = I.getSynchScope(); 3413 3414 SDValue InChain = getRoot(); 3415 3416 EVT VT = EVT::getEVT(I.getType()); 3417 3418 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3419 report_fatal_error("Cannot generate unaligned atomic load"); 3420 3421 SDValue L = 3422 DAG.getAtomic(ISD::ATOMIC_LOAD, dl, VT, VT, InChain, 3423 getValue(I.getPointerOperand()), 3424 I.getPointerOperand(), I.getAlignment(), 3425 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3426 Scope); 3427 3428 SDValue OutChain = L.getValue(1); 3429 3430 if (TLI.getInsertFencesForAtomic()) 3431 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3432 DAG, TLI); 3433 3434 setValue(&I, L); 3435 DAG.setRoot(OutChain); 3436 } 3437 3438 void SelectionDAGBuilder::visitAtomicStore(const StoreInst &I) { 3439 DebugLoc dl = getCurDebugLoc(); 3440 3441 AtomicOrdering Order = I.getOrdering(); 3442 SynchronizationScope Scope = I.getSynchScope(); 3443 3444 SDValue InChain = getRoot(); 3445 3446 EVT VT = EVT::getEVT(I.getValueOperand()->getType()); 3447 3448 if (I.getAlignment() * 8 < VT.getSizeInBits()) 3449 report_fatal_error("Cannot generate unaligned atomic store"); 3450 3451 if (TLI.getInsertFencesForAtomic()) 3452 InChain = InsertFenceForAtomic(InChain, Order, Scope, true, dl, 3453 DAG, TLI); 3454 3455 SDValue OutChain = 3456 DAG.getAtomic(ISD::ATOMIC_STORE, dl, VT, 3457 InChain, 3458 getValue(I.getPointerOperand()), 3459 getValue(I.getValueOperand()), 3460 I.getPointerOperand(), I.getAlignment(), 3461 TLI.getInsertFencesForAtomic() ? Monotonic : Order, 3462 Scope); 3463 3464 if (TLI.getInsertFencesForAtomic()) 3465 OutChain = InsertFenceForAtomic(OutChain, Order, Scope, false, dl, 3466 DAG, TLI); 3467 3468 DAG.setRoot(OutChain); 3469 } 3470 3471 /// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC 3472 /// node. 3473 void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, 3474 unsigned Intrinsic) { 3475 bool HasChain = !I.doesNotAccessMemory(); 3476 bool OnlyLoad = HasChain && I.onlyReadsMemory(); 3477 3478 // Build the operand list. 3479 SmallVector<SDValue, 8> Ops; 3480 if (HasChain) { // If this intrinsic has side-effects, chainify it. 3481 if (OnlyLoad) { 3482 // We don't need to serialize loads against other loads. 3483 Ops.push_back(DAG.getRoot()); 3484 } else { 3485 Ops.push_back(getRoot()); 3486 } 3487 } 3488 3489 // Info is set by getTgtMemInstrinsic 3490 TargetLowering::IntrinsicInfo Info; 3491 bool IsTgtIntrinsic = TLI.getTgtMemIntrinsic(Info, I, Intrinsic); 3492 3493 // Add the intrinsic ID as an integer operand if it's not a target intrinsic. 3494 if (!IsTgtIntrinsic || Info.opc == ISD::INTRINSIC_VOID || 3495 Info.opc == ISD::INTRINSIC_W_CHAIN) 3496 Ops.push_back(DAG.getConstant(Intrinsic, TLI.getPointerTy())); 3497 3498 // Add all operands of the call to the operand list. 3499 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 3500 SDValue Op = getValue(I.getArgOperand(i)); 3501 assert(TLI.isTypeLegal(Op.getValueType()) && 3502 "Intrinsic uses a non-legal type?"); 3503 Ops.push_back(Op); 3504 } 3505 3506 SmallVector<EVT, 4> ValueVTs; 3507 ComputeValueVTs(TLI, I.getType(), ValueVTs); 3508 #ifndef NDEBUG 3509 for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) { 3510 assert(TLI.isTypeLegal(ValueVTs[Val]) && 3511 "Intrinsic uses a non-legal type?"); 3512 } 3513 #endif // NDEBUG 3514 3515 if (HasChain) 3516 ValueVTs.push_back(MVT::Other); 3517 3518 SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size()); 3519 3520 // Create the node. 3521 SDValue Result; 3522 if (IsTgtIntrinsic) { 3523 // This is target intrinsic that touches memory 3524 Result = DAG.getMemIntrinsicNode(Info.opc, getCurDebugLoc(), 3525 VTs, &Ops[0], Ops.size(), 3526 Info.memVT, 3527 MachinePointerInfo(Info.ptrVal, Info.offset), 3528 Info.align, Info.vol, 3529 Info.readMem, Info.writeMem); 3530 } else if (!HasChain) { 3531 Result = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, getCurDebugLoc(), 3532 VTs, &Ops[0], Ops.size()); 3533 } else if (!I.getType()->isVoidTy()) { 3534 Result = DAG.getNode(ISD::INTRINSIC_W_CHAIN, getCurDebugLoc(), 3535 VTs, &Ops[0], Ops.size()); 3536 } else { 3537 Result = DAG.getNode(ISD::INTRINSIC_VOID, getCurDebugLoc(), 3538 VTs, &Ops[0], Ops.size()); 3539 } 3540 3541 if (HasChain) { 3542 SDValue Chain = Result.getValue(Result.getNode()->getNumValues()-1); 3543 if (OnlyLoad) 3544 PendingLoads.push_back(Chain); 3545 else 3546 DAG.setRoot(Chain); 3547 } 3548 3549 if (!I.getType()->isVoidTy()) { 3550 if (VectorType *PTy = dyn_cast<VectorType>(I.getType())) { 3551 EVT VT = TLI.getValueType(PTy); 3552 Result = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), VT, Result); 3553 } 3554 3555 setValue(&I, Result); 3556 } 3557 } 3558 3559 /// GetSignificand - Get the significand and build it into a floating-point 3560 /// number with exponent of 1: 3561 /// 3562 /// Op = (Op & 0x007fffff) | 0x3f800000; 3563 /// 3564 /// where Op is the hexidecimal representation of floating point value. 3565 static SDValue 3566 GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) { 3567 SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3568 DAG.getConstant(0x007fffff, MVT::i32)); 3569 SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1, 3570 DAG.getConstant(0x3f800000, MVT::i32)); 3571 return DAG.getNode(ISD::BITCAST, dl, MVT::f32, t2); 3572 } 3573 3574 /// GetExponent - Get the exponent: 3575 /// 3576 /// (float)(int)(((Op & 0x7f800000) >> 23) - 127); 3577 /// 3578 /// where Op is the hexidecimal representation of floating point value. 3579 static SDValue 3580 GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, 3581 DebugLoc dl) { 3582 SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op, 3583 DAG.getConstant(0x7f800000, MVT::i32)); 3584 SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0, 3585 DAG.getConstant(23, TLI.getPointerTy())); 3586 SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1, 3587 DAG.getConstant(127, MVT::i32)); 3588 return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2); 3589 } 3590 3591 /// getF32Constant - Get 32-bit floating point constant. 3592 static SDValue 3593 getF32Constant(SelectionDAG &DAG, unsigned Flt) { 3594 return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32); 3595 } 3596 3597 // implVisitAluOverflow - Lower arithmetic overflow instrinsics. 3598 const char * 3599 SelectionDAGBuilder::implVisitAluOverflow(const CallInst &I, ISD::NodeType Op) { 3600 SDValue Op1 = getValue(I.getArgOperand(0)); 3601 SDValue Op2 = getValue(I.getArgOperand(1)); 3602 3603 SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1); 3604 setValue(&I, DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2)); 3605 return 0; 3606 } 3607 3608 /// visitExp - Lower an exp intrinsic. Handles the special sequences for 3609 /// limited-precision mode. 3610 void 3611 SelectionDAGBuilder::visitExp(const CallInst &I) { 3612 SDValue result; 3613 DebugLoc dl = getCurDebugLoc(); 3614 3615 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3616 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3617 SDValue Op = getValue(I.getArgOperand(0)); 3618 3619 // Put the exponent in the right bit position for later addition to the 3620 // final result: 3621 // 3622 // #define LOG2OFe 1.4426950f 3623 // IntegerPartOfX = ((int32_t)(X * LOG2OFe)); 3624 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 3625 getF32Constant(DAG, 0x3fb8aa3b)); 3626 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 3627 3628 // FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX; 3629 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 3630 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 3631 3632 // IntegerPartOfX <<= 23; 3633 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 3634 DAG.getConstant(23, TLI.getPointerTy())); 3635 3636 if (LimitFloatPrecision <= 6) { 3637 // For floating-point precision of 6: 3638 // 3639 // TwoToFractionalPartOfX = 3640 // 0.997535578f + 3641 // (0.735607626f + 0.252464424f * x) * x; 3642 // 3643 // error 0.0144103317, which is 6 bits 3644 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3645 getF32Constant(DAG, 0x3e814304)); 3646 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3647 getF32Constant(DAG, 0x3f3c50c8)); 3648 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3649 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3650 getF32Constant(DAG, 0x3f7f5e7e)); 3651 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t5); 3652 3653 // Add the exponent into the result in integer domain. 3654 SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3655 TwoToFracPartOfX, IntegerPartOfX); 3656 3657 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t6); 3658 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3659 // For floating-point precision of 12: 3660 // 3661 // TwoToFractionalPartOfX = 3662 // 0.999892986f + 3663 // (0.696457318f + 3664 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 3665 // 3666 // 0.000107046256 error, which is 13 to 14 bits 3667 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3668 getF32Constant(DAG, 0x3da235e3)); 3669 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3670 getF32Constant(DAG, 0x3e65b8f3)); 3671 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3672 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3673 getF32Constant(DAG, 0x3f324b07)); 3674 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3675 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3676 getF32Constant(DAG, 0x3f7ff8fd)); 3677 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl,MVT::i32, t7); 3678 3679 // Add the exponent into the result in integer domain. 3680 SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3681 TwoToFracPartOfX, IntegerPartOfX); 3682 3683 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t8); 3684 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3685 // For floating-point precision of 18: 3686 // 3687 // TwoToFractionalPartOfX = 3688 // 0.999999982f + 3689 // (0.693148872f + 3690 // (0.240227044f + 3691 // (0.554906021e-1f + 3692 // (0.961591928e-2f + 3693 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 3694 // 3695 // error 2.47208000*10^(-7), which is better than 18 bits 3696 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3697 getF32Constant(DAG, 0x3924b03e)); 3698 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 3699 getF32Constant(DAG, 0x3ab24b87)); 3700 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3701 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3702 getF32Constant(DAG, 0x3c1d8c17)); 3703 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3704 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 3705 getF32Constant(DAG, 0x3d634a1d)); 3706 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3707 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3708 getF32Constant(DAG, 0x3e75fe14)); 3709 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3710 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 3711 getF32Constant(DAG, 0x3f317234)); 3712 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 3713 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 3714 getF32Constant(DAG, 0x3f800000)); 3715 SDValue TwoToFracPartOfX = DAG.getNode(ISD::BITCAST, dl, 3716 MVT::i32, t13); 3717 3718 // Add the exponent into the result in integer domain. 3719 SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32, 3720 TwoToFracPartOfX, IntegerPartOfX); 3721 3722 result = DAG.getNode(ISD::BITCAST, dl, MVT::f32, t14); 3723 } 3724 } else { 3725 // No special expansion. 3726 result = DAG.getNode(ISD::FEXP, dl, 3727 getValue(I.getArgOperand(0)).getValueType(), 3728 getValue(I.getArgOperand(0))); 3729 } 3730 3731 setValue(&I, result); 3732 } 3733 3734 /// visitLog - Lower a log intrinsic. Handles the special sequences for 3735 /// limited-precision mode. 3736 void 3737 SelectionDAGBuilder::visitLog(const CallInst &I) { 3738 SDValue result; 3739 DebugLoc dl = getCurDebugLoc(); 3740 3741 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3742 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3743 SDValue Op = getValue(I.getArgOperand(0)); 3744 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3745 3746 // Scale the exponent by log(2) [0.69314718f]. 3747 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3748 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3749 getF32Constant(DAG, 0x3f317218)); 3750 3751 // Get the significand and build it into a floating-point number with 3752 // exponent of 1. 3753 SDValue X = GetSignificand(DAG, Op1, dl); 3754 3755 if (LimitFloatPrecision <= 6) { 3756 // For floating-point precision of 6: 3757 // 3758 // LogofMantissa = 3759 // -1.1609546f + 3760 // (1.4034025f - 0.23903021f * x) * x; 3761 // 3762 // error 0.0034276066, which is better than 8 bits 3763 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3764 getF32Constant(DAG, 0xbe74c456)); 3765 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3766 getF32Constant(DAG, 0x3fb3a2b1)); 3767 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3768 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3769 getF32Constant(DAG, 0x3f949a29)); 3770 3771 result = DAG.getNode(ISD::FADD, dl, 3772 MVT::f32, LogOfExponent, LogOfMantissa); 3773 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3774 // For floating-point precision of 12: 3775 // 3776 // LogOfMantissa = 3777 // -1.7417939f + 3778 // (2.8212026f + 3779 // (-1.4699568f + 3780 // (0.44717955f - 0.56570851e-1f * x) * x) * x) * x; 3781 // 3782 // error 0.000061011436, which is 14 bits 3783 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3784 getF32Constant(DAG, 0xbd67b6d6)); 3785 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3786 getF32Constant(DAG, 0x3ee4f4b8)); 3787 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3788 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3789 getF32Constant(DAG, 0x3fbc278b)); 3790 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3791 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3792 getF32Constant(DAG, 0x40348e95)); 3793 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3794 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3795 getF32Constant(DAG, 0x3fdef31a)); 3796 3797 result = DAG.getNode(ISD::FADD, dl, 3798 MVT::f32, LogOfExponent, LogOfMantissa); 3799 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3800 // For floating-point precision of 18: 3801 // 3802 // LogOfMantissa = 3803 // -2.1072184f + 3804 // (4.2372794f + 3805 // (-3.7029485f + 3806 // (2.2781945f + 3807 // (-0.87823314f + 3808 // (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x; 3809 // 3810 // error 0.0000023660568, which is better than 18 bits 3811 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3812 getF32Constant(DAG, 0xbc91e5ac)); 3813 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3814 getF32Constant(DAG, 0x3e4350aa)); 3815 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3816 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3817 getF32Constant(DAG, 0x3f60d3e3)); 3818 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3819 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3820 getF32Constant(DAG, 0x4011cdf0)); 3821 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3822 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3823 getF32Constant(DAG, 0x406cfd1c)); 3824 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3825 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3826 getF32Constant(DAG, 0x408797cb)); 3827 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3828 SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3829 getF32Constant(DAG, 0x4006dcab)); 3830 3831 result = DAG.getNode(ISD::FADD, dl, 3832 MVT::f32, LogOfExponent, LogOfMantissa); 3833 } 3834 } else { 3835 // No special expansion. 3836 result = DAG.getNode(ISD::FLOG, dl, 3837 getValue(I.getArgOperand(0)).getValueType(), 3838 getValue(I.getArgOperand(0))); 3839 } 3840 3841 setValue(&I, result); 3842 } 3843 3844 /// visitLog2 - Lower a log2 intrinsic. Handles the special sequences for 3845 /// limited-precision mode. 3846 void 3847 SelectionDAGBuilder::visitLog2(const CallInst &I) { 3848 SDValue result; 3849 DebugLoc dl = getCurDebugLoc(); 3850 3851 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3852 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3853 SDValue Op = getValue(I.getArgOperand(0)); 3854 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3855 3856 // Get the exponent. 3857 SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl); 3858 3859 // Get the significand and build it into a floating-point number with 3860 // exponent of 1. 3861 SDValue X = GetSignificand(DAG, Op1, dl); 3862 3863 // Different possible minimax approximations of significand in 3864 // floating-point for various degrees of accuracy over [1,2]. 3865 if (LimitFloatPrecision <= 6) { 3866 // For floating-point precision of 6: 3867 // 3868 // Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x; 3869 // 3870 // error 0.0049451742, which is more than 7 bits 3871 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3872 getF32Constant(DAG, 0xbeb08fe0)); 3873 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3874 getF32Constant(DAG, 0x40019463)); 3875 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3876 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3877 getF32Constant(DAG, 0x3fd6633d)); 3878 3879 result = DAG.getNode(ISD::FADD, dl, 3880 MVT::f32, LogOfExponent, Log2ofMantissa); 3881 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3882 // For floating-point precision of 12: 3883 // 3884 // Log2ofMantissa = 3885 // -2.51285454f + 3886 // (4.07009056f + 3887 // (-2.12067489f + 3888 // (.645142248f - 0.816157886e-1f * x) * x) * x) * x; 3889 // 3890 // error 0.0000876136000, which is better than 13 bits 3891 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3892 getF32Constant(DAG, 0xbda7262e)); 3893 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3894 getF32Constant(DAG, 0x3f25280b)); 3895 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3896 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3897 getF32Constant(DAG, 0x4007b923)); 3898 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3899 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3900 getF32Constant(DAG, 0x40823e2f)); 3901 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3902 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3903 getF32Constant(DAG, 0x4020d29c)); 3904 3905 result = DAG.getNode(ISD::FADD, dl, 3906 MVT::f32, LogOfExponent, Log2ofMantissa); 3907 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 3908 // For floating-point precision of 18: 3909 // 3910 // Log2ofMantissa = 3911 // -3.0400495f + 3912 // (6.1129976f + 3913 // (-5.3420409f + 3914 // (3.2865683f + 3915 // (-1.2669343f + 3916 // (0.27515199f - 3917 // 0.25691327e-1f * x) * x) * x) * x) * x) * x; 3918 // 3919 // error 0.0000018516, which is better than 18 bits 3920 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3921 getF32Constant(DAG, 0xbcd2769e)); 3922 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3923 getF32Constant(DAG, 0x3e8ce0b9)); 3924 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3925 SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3926 getF32Constant(DAG, 0x3fa22ae7)); 3927 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 3928 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 3929 getF32Constant(DAG, 0x40525723)); 3930 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 3931 SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6, 3932 getF32Constant(DAG, 0x40aaf200)); 3933 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 3934 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 3935 getF32Constant(DAG, 0x40c39dad)); 3936 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 3937 SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10, 3938 getF32Constant(DAG, 0x4042902c)); 3939 3940 result = DAG.getNode(ISD::FADD, dl, 3941 MVT::f32, LogOfExponent, Log2ofMantissa); 3942 } 3943 } else { 3944 // No special expansion. 3945 result = DAG.getNode(ISD::FLOG2, dl, 3946 getValue(I.getArgOperand(0)).getValueType(), 3947 getValue(I.getArgOperand(0))); 3948 } 3949 3950 setValue(&I, result); 3951 } 3952 3953 /// visitLog10 - Lower a log10 intrinsic. Handles the special sequences for 3954 /// limited-precision mode. 3955 void 3956 SelectionDAGBuilder::visitLog10(const CallInst &I) { 3957 SDValue result; 3958 DebugLoc dl = getCurDebugLoc(); 3959 3960 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 3961 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 3962 SDValue Op = getValue(I.getArgOperand(0)); 3963 SDValue Op1 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Op); 3964 3965 // Scale the exponent by log10(2) [0.30102999f]. 3966 SDValue Exp = GetExponent(DAG, Op1, TLI, dl); 3967 SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp, 3968 getF32Constant(DAG, 0x3e9a209a)); 3969 3970 // Get the significand and build it into a floating-point number with 3971 // exponent of 1. 3972 SDValue X = GetSignificand(DAG, Op1, dl); 3973 3974 if (LimitFloatPrecision <= 6) { 3975 // For floating-point precision of 6: 3976 // 3977 // Log10ofMantissa = 3978 // -0.50419619f + 3979 // (0.60948995f - 0.10380950f * x) * x; 3980 // 3981 // error 0.0014886165, which is 6 bits 3982 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 3983 getF32Constant(DAG, 0xbdd49a13)); 3984 SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0, 3985 getF32Constant(DAG, 0x3f1c0789)); 3986 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 3987 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2, 3988 getF32Constant(DAG, 0x3f011300)); 3989 3990 result = DAG.getNode(ISD::FADD, dl, 3991 MVT::f32, LogOfExponent, Log10ofMantissa); 3992 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 3993 // For floating-point precision of 12: 3994 // 3995 // Log10ofMantissa = 3996 // -0.64831180f + 3997 // (0.91751397f + 3998 // (-0.31664806f + 0.47637168e-1f * x) * x) * x; 3999 // 4000 // error 0.00019228036, which is better than 12 bits 4001 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4002 getF32Constant(DAG, 0x3d431f31)); 4003 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4004 getF32Constant(DAG, 0x3ea21fb2)); 4005 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4006 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4007 getF32Constant(DAG, 0x3f6ae232)); 4008 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4009 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4010 getF32Constant(DAG, 0x3f25f7c3)); 4011 4012 result = DAG.getNode(ISD::FADD, dl, 4013 MVT::f32, LogOfExponent, Log10ofMantissa); 4014 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4015 // For floating-point precision of 18: 4016 // 4017 // Log10ofMantissa = 4018 // -0.84299375f + 4019 // (1.5327582f + 4020 // (-1.0688956f + 4021 // (0.49102474f + 4022 // (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x; 4023 // 4024 // error 0.0000037995730, which is better than 18 bits 4025 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4026 getF32Constant(DAG, 0x3c5d51ce)); 4027 SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, 4028 getF32Constant(DAG, 0x3e00685a)); 4029 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X); 4030 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4031 getF32Constant(DAG, 0x3efb6798)); 4032 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4033 SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4, 4034 getF32Constant(DAG, 0x3f88d192)); 4035 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4036 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4037 getF32Constant(DAG, 0x3fc4316c)); 4038 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4039 SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8, 4040 getF32Constant(DAG, 0x3f57ce70)); 4041 4042 result = DAG.getNode(ISD::FADD, dl, 4043 MVT::f32, LogOfExponent, Log10ofMantissa); 4044 } 4045 } else { 4046 // No special expansion. 4047 result = DAG.getNode(ISD::FLOG10, dl, 4048 getValue(I.getArgOperand(0)).getValueType(), 4049 getValue(I.getArgOperand(0))); 4050 } 4051 4052 setValue(&I, result); 4053 } 4054 4055 /// visitExp2 - Lower an exp2 intrinsic. Handles the special sequences for 4056 /// limited-precision mode. 4057 void 4058 SelectionDAGBuilder::visitExp2(const CallInst &I) { 4059 SDValue result; 4060 DebugLoc dl = getCurDebugLoc(); 4061 4062 if (getValue(I.getArgOperand(0)).getValueType() == MVT::f32 && 4063 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4064 SDValue Op = getValue(I.getArgOperand(0)); 4065 4066 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op); 4067 4068 // FractionalPartOfX = x - (float)IntegerPartOfX; 4069 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4070 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1); 4071 4072 // IntegerPartOfX <<= 23; 4073 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4074 DAG.getConstant(23, TLI.getPointerTy())); 4075 4076 if (LimitFloatPrecision <= 6) { 4077 // For floating-point precision of 6: 4078 // 4079 // TwoToFractionalPartOfX = 4080 // 0.997535578f + 4081 // (0.735607626f + 0.252464424f * x) * x; 4082 // 4083 // error 0.0144103317, which is 6 bits 4084 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4085 getF32Constant(DAG, 0x3e814304)); 4086 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4087 getF32Constant(DAG, 0x3f3c50c8)); 4088 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4089 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4090 getF32Constant(DAG, 0x3f7f5e7e)); 4091 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4092 SDValue TwoToFractionalPartOfX = 4093 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4094 4095 result = DAG.getNode(ISD::BITCAST, dl, 4096 MVT::f32, TwoToFractionalPartOfX); 4097 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4098 // For floating-point precision of 12: 4099 // 4100 // TwoToFractionalPartOfX = 4101 // 0.999892986f + 4102 // (0.696457318f + 4103 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4104 // 4105 // error 0.000107046256, which is 13 to 14 bits 4106 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4107 getF32Constant(DAG, 0x3da235e3)); 4108 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4109 getF32Constant(DAG, 0x3e65b8f3)); 4110 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4111 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4112 getF32Constant(DAG, 0x3f324b07)); 4113 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4114 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4115 getF32Constant(DAG, 0x3f7ff8fd)); 4116 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4117 SDValue TwoToFractionalPartOfX = 4118 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4119 4120 result = DAG.getNode(ISD::BITCAST, dl, 4121 MVT::f32, TwoToFractionalPartOfX); 4122 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4123 // For floating-point precision of 18: 4124 // 4125 // TwoToFractionalPartOfX = 4126 // 0.999999982f + 4127 // (0.693148872f + 4128 // (0.240227044f + 4129 // (0.554906021e-1f + 4130 // (0.961591928e-2f + 4131 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4132 // error 2.47208000*10^(-7), which is better than 18 bits 4133 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4134 getF32Constant(DAG, 0x3924b03e)); 4135 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4136 getF32Constant(DAG, 0x3ab24b87)); 4137 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4138 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4139 getF32Constant(DAG, 0x3c1d8c17)); 4140 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4141 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4142 getF32Constant(DAG, 0x3d634a1d)); 4143 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4144 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4145 getF32Constant(DAG, 0x3e75fe14)); 4146 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4147 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4148 getF32Constant(DAG, 0x3f317234)); 4149 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4150 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4151 getF32Constant(DAG, 0x3f800000)); 4152 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4153 SDValue TwoToFractionalPartOfX = 4154 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4155 4156 result = DAG.getNode(ISD::BITCAST, dl, 4157 MVT::f32, TwoToFractionalPartOfX); 4158 } 4159 } else { 4160 // No special expansion. 4161 result = DAG.getNode(ISD::FEXP2, dl, 4162 getValue(I.getArgOperand(0)).getValueType(), 4163 getValue(I.getArgOperand(0))); 4164 } 4165 4166 setValue(&I, result); 4167 } 4168 4169 /// visitPow - Lower a pow intrinsic. Handles the special sequences for 4170 /// limited-precision mode with x == 10.0f. 4171 void 4172 SelectionDAGBuilder::visitPow(const CallInst &I) { 4173 SDValue result; 4174 const Value *Val = I.getArgOperand(0); 4175 DebugLoc dl = getCurDebugLoc(); 4176 bool IsExp10 = false; 4177 4178 if (getValue(Val).getValueType() == MVT::f32 && 4179 getValue(I.getArgOperand(1)).getValueType() == MVT::f32 && 4180 LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4181 if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) { 4182 if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) { 4183 APFloat Ten(10.0f); 4184 IsExp10 = CFP->getValueAPF().bitwiseIsEqual(Ten); 4185 } 4186 } 4187 } 4188 4189 if (IsExp10 && LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) { 4190 SDValue Op = getValue(I.getArgOperand(1)); 4191 4192 // Put the exponent in the right bit position for later addition to the 4193 // final result: 4194 // 4195 // #define LOG2OF10 3.3219281f 4196 // IntegerPartOfX = (int32_t)(x * LOG2OF10); 4197 SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op, 4198 getF32Constant(DAG, 0x40549a78)); 4199 SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0); 4200 4201 // FractionalPartOfX = x - (float)IntegerPartOfX; 4202 SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX); 4203 SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1); 4204 4205 // IntegerPartOfX <<= 23; 4206 IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX, 4207 DAG.getConstant(23, TLI.getPointerTy())); 4208 4209 if (LimitFloatPrecision <= 6) { 4210 // For floating-point precision of 6: 4211 // 4212 // twoToFractionalPartOfX = 4213 // 0.997535578f + 4214 // (0.735607626f + 0.252464424f * x) * x; 4215 // 4216 // error 0.0144103317, which is 6 bits 4217 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4218 getF32Constant(DAG, 0x3e814304)); 4219 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4220 getF32Constant(DAG, 0x3f3c50c8)); 4221 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4222 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4223 getF32Constant(DAG, 0x3f7f5e7e)); 4224 SDValue t6 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t5); 4225 SDValue TwoToFractionalPartOfX = 4226 DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX); 4227 4228 result = DAG.getNode(ISD::BITCAST, dl, 4229 MVT::f32, TwoToFractionalPartOfX); 4230 } else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) { 4231 // For floating-point precision of 12: 4232 // 4233 // TwoToFractionalPartOfX = 4234 // 0.999892986f + 4235 // (0.696457318f + 4236 // (0.224338339f + 0.792043434e-1f * x) * x) * x; 4237 // 4238 // error 0.000107046256, which is 13 to 14 bits 4239 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4240 getF32Constant(DAG, 0x3da235e3)); 4241 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4242 getF32Constant(DAG, 0x3e65b8f3)); 4243 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4244 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4245 getF32Constant(DAG, 0x3f324b07)); 4246 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4247 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4248 getF32Constant(DAG, 0x3f7ff8fd)); 4249 SDValue t8 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t7); 4250 SDValue TwoToFractionalPartOfX = 4251 DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX); 4252 4253 result = DAG.getNode(ISD::BITCAST, dl, 4254 MVT::f32, TwoToFractionalPartOfX); 4255 } else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18 4256 // For floating-point precision of 18: 4257 // 4258 // TwoToFractionalPartOfX = 4259 // 0.999999982f + 4260 // (0.693148872f + 4261 // (0.240227044f + 4262 // (0.554906021e-1f + 4263 // (0.961591928e-2f + 4264 // (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x; 4265 // error 2.47208000*10^(-7), which is better than 18 bits 4266 SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X, 4267 getF32Constant(DAG, 0x3924b03e)); 4268 SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2, 4269 getF32Constant(DAG, 0x3ab24b87)); 4270 SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X); 4271 SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4, 4272 getF32Constant(DAG, 0x3c1d8c17)); 4273 SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X); 4274 SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6, 4275 getF32Constant(DAG, 0x3d634a1d)); 4276 SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X); 4277 SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8, 4278 getF32Constant(DAG, 0x3e75fe14)); 4279 SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X); 4280 SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10, 4281 getF32Constant(DAG, 0x3f317234)); 4282 SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X); 4283 SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12, 4284 getF32Constant(DAG, 0x3f800000)); 4285 SDValue t14 = DAG.getNode(ISD::BITCAST, dl, MVT::i32, t13); 4286 SDValue TwoToFractionalPartOfX = 4287 DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX); 4288 4289 result = DAG.getNode(ISD::BITCAST, dl, 4290 MVT::f32, TwoToFractionalPartOfX); 4291 } 4292 } else { 4293 // No special expansion. 4294 result = DAG.getNode(ISD::FPOW, dl, 4295 getValue(I.getArgOperand(0)).getValueType(), 4296 getValue(I.getArgOperand(0)), 4297 getValue(I.getArgOperand(1))); 4298 } 4299 4300 setValue(&I, result); 4301 } 4302 4303 4304 /// ExpandPowI - Expand a llvm.powi intrinsic. 4305 static SDValue ExpandPowI(DebugLoc DL, SDValue LHS, SDValue RHS, 4306 SelectionDAG &DAG) { 4307 // If RHS is a constant, we can expand this out to a multiplication tree, 4308 // otherwise we end up lowering to a call to __powidf2 (for example). When 4309 // optimizing for size, we only want to do this if the expansion would produce 4310 // a small number of multiplies, otherwise we do the full expansion. 4311 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS)) { 4312 // Get the exponent as a positive value. 4313 unsigned Val = RHSC->getSExtValue(); 4314 if ((int)Val < 0) Val = -Val; 4315 4316 // powi(x, 0) -> 1.0 4317 if (Val == 0) 4318 return DAG.getConstantFP(1.0, LHS.getValueType()); 4319 4320 const Function *F = DAG.getMachineFunction().getFunction(); 4321 if (!F->hasFnAttr(Attribute::OptimizeForSize) || 4322 // If optimizing for size, don't insert too many multiplies. This 4323 // inserts up to 5 multiplies. 4324 CountPopulation_32(Val)+Log2_32(Val) < 7) { 4325 // We use the simple binary decomposition method to generate the multiply 4326 // sequence. There are more optimal ways to do this (for example, 4327 // powi(x,15) generates one more multiply than it should), but this has 4328 // the benefit of being both really simple and much better than a libcall. 4329 SDValue Res; // Logically starts equal to 1.0 4330 SDValue CurSquare = LHS; 4331 while (Val) { 4332 if (Val & 1) { 4333 if (Res.getNode()) 4334 Res = DAG.getNode(ISD::FMUL, DL,Res.getValueType(), Res, CurSquare); 4335 else 4336 Res = CurSquare; // 1.0*CurSquare. 4337 } 4338 4339 CurSquare = DAG.getNode(ISD::FMUL, DL, CurSquare.getValueType(), 4340 CurSquare, CurSquare); 4341 Val >>= 1; 4342 } 4343 4344 // If the original was negative, invert the result, producing 1/(x*x*x). 4345 if (RHSC->getSExtValue() < 0) 4346 Res = DAG.getNode(ISD::FDIV, DL, LHS.getValueType(), 4347 DAG.getConstantFP(1.0, LHS.getValueType()), Res); 4348 return Res; 4349 } 4350 } 4351 4352 // Otherwise, expand to a libcall. 4353 return DAG.getNode(ISD::FPOWI, DL, LHS.getValueType(), LHS, RHS); 4354 } 4355 4356 // getTruncatedArgReg - Find underlying register used for an truncated 4357 // argument. 4358 static unsigned getTruncatedArgReg(const SDValue &N) { 4359 if (N.getOpcode() != ISD::TRUNCATE) 4360 return 0; 4361 4362 const SDValue &Ext = N.getOperand(0); 4363 if (Ext.getOpcode() == ISD::AssertZext || Ext.getOpcode() == ISD::AssertSext){ 4364 const SDValue &CFR = Ext.getOperand(0); 4365 if (CFR.getOpcode() == ISD::CopyFromReg) 4366 return cast<RegisterSDNode>(CFR.getOperand(1))->getReg(); 4367 else 4368 if (CFR.getOpcode() == ISD::TRUNCATE) 4369 return getTruncatedArgReg(CFR); 4370 } 4371 return 0; 4372 } 4373 4374 /// EmitFuncArgumentDbgValue - If the DbgValueInst is a dbg_value of a function 4375 /// argument, create the corresponding DBG_VALUE machine instruction for it now. 4376 /// At the end of instruction selection, they will be inserted to the entry BB. 4377 bool 4378 SelectionDAGBuilder::EmitFuncArgumentDbgValue(const Value *V, MDNode *Variable, 4379 int64_t Offset, 4380 const SDValue &N) { 4381 const Argument *Arg = dyn_cast<Argument>(V); 4382 if (!Arg) 4383 return false; 4384 4385 MachineFunction &MF = DAG.getMachineFunction(); 4386 const TargetInstrInfo *TII = DAG.getTarget().getInstrInfo(); 4387 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 4388 4389 // Ignore inlined function arguments here. 4390 DIVariable DV(Variable); 4391 if (DV.isInlinedFnArgument(MF.getFunction())) 4392 return false; 4393 4394 unsigned Reg = 0; 4395 // Some arguments' frame index is recorded during argument lowering. 4396 Offset = FuncInfo.getArgumentFrameIndex(Arg); 4397 if (Offset) 4398 Reg = TRI->getFrameRegister(MF); 4399 4400 if (!Reg && N.getNode()) { 4401 if (N.getOpcode() == ISD::CopyFromReg) 4402 Reg = cast<RegisterSDNode>(N.getOperand(1))->getReg(); 4403 else 4404 Reg = getTruncatedArgReg(N); 4405 if (Reg && TargetRegisterInfo::isVirtualRegister(Reg)) { 4406 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 4407 unsigned PR = RegInfo.getLiveInPhysReg(Reg); 4408 if (PR) 4409 Reg = PR; 4410 } 4411 } 4412 4413 if (!Reg) { 4414 // Check if ValueMap has reg number. 4415 DenseMap<const Value *, unsigned>::iterator VMI = FuncInfo.ValueMap.find(V); 4416 if (VMI != FuncInfo.ValueMap.end()) 4417 Reg = VMI->second; 4418 } 4419 4420 if (!Reg && N.getNode()) { 4421 // Check if frame index is available. 4422 if (LoadSDNode *LNode = dyn_cast<LoadSDNode>(N.getNode())) 4423 if (FrameIndexSDNode *FINode = 4424 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) { 4425 Reg = TRI->getFrameRegister(MF); 4426 Offset = FINode->getIndex(); 4427 } 4428 } 4429 4430 if (!Reg) 4431 return false; 4432 4433 MachineInstrBuilder MIB = BuildMI(MF, getCurDebugLoc(), 4434 TII->get(TargetOpcode::DBG_VALUE)) 4435 .addReg(Reg, RegState::Debug).addImm(Offset).addMetadata(Variable); 4436 FuncInfo.ArgDbgValues.push_back(&*MIB); 4437 return true; 4438 } 4439 4440 // VisualStudio defines setjmp as _setjmp 4441 #if defined(_MSC_VER) && defined(setjmp) && \ 4442 !defined(setjmp_undefined_for_msvc) 4443 # pragma push_macro("setjmp") 4444 # undef setjmp 4445 # define setjmp_undefined_for_msvc 4446 #endif 4447 4448 /// visitIntrinsicCall - Lower the call to the specified intrinsic function. If 4449 /// we want to emit this as a call to a named external function, return the name 4450 /// otherwise lower it and return null. 4451 const char * 4452 SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) { 4453 DebugLoc dl = getCurDebugLoc(); 4454 SDValue Res; 4455 4456 switch (Intrinsic) { 4457 default: 4458 // By default, turn this into a target intrinsic node. 4459 visitTargetIntrinsic(I, Intrinsic); 4460 return 0; 4461 case Intrinsic::vastart: visitVAStart(I); return 0; 4462 case Intrinsic::vaend: visitVAEnd(I); return 0; 4463 case Intrinsic::vacopy: visitVACopy(I); return 0; 4464 case Intrinsic::returnaddress: 4465 setValue(&I, DAG.getNode(ISD::RETURNADDR, dl, TLI.getPointerTy(), 4466 getValue(I.getArgOperand(0)))); 4467 return 0; 4468 case Intrinsic::frameaddress: 4469 setValue(&I, DAG.getNode(ISD::FRAMEADDR, dl, TLI.getPointerTy(), 4470 getValue(I.getArgOperand(0)))); 4471 return 0; 4472 case Intrinsic::setjmp: 4473 return "_setjmp"+!TLI.usesUnderscoreSetJmp(); 4474 case Intrinsic::longjmp: 4475 return "_longjmp"+!TLI.usesUnderscoreLongJmp(); 4476 case Intrinsic::memcpy: { 4477 // Assert for address < 256 since we support only user defined address 4478 // spaces. 4479 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4480 < 256 && 4481 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4482 < 256 && 4483 "Unknown address space"); 4484 SDValue Op1 = getValue(I.getArgOperand(0)); 4485 SDValue Op2 = getValue(I.getArgOperand(1)); 4486 SDValue Op3 = getValue(I.getArgOperand(2)); 4487 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4488 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4489 DAG.setRoot(DAG.getMemcpy(getRoot(), dl, Op1, Op2, Op3, Align, isVol, false, 4490 MachinePointerInfo(I.getArgOperand(0)), 4491 MachinePointerInfo(I.getArgOperand(1)))); 4492 return 0; 4493 } 4494 case Intrinsic::memset: { 4495 // Assert for address < 256 since we support only user defined address 4496 // spaces. 4497 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4498 < 256 && 4499 "Unknown address space"); 4500 SDValue Op1 = getValue(I.getArgOperand(0)); 4501 SDValue Op2 = getValue(I.getArgOperand(1)); 4502 SDValue Op3 = getValue(I.getArgOperand(2)); 4503 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4504 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4505 DAG.setRoot(DAG.getMemset(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4506 MachinePointerInfo(I.getArgOperand(0)))); 4507 return 0; 4508 } 4509 case Intrinsic::memmove: { 4510 // Assert for address < 256 since we support only user defined address 4511 // spaces. 4512 assert(cast<PointerType>(I.getArgOperand(0)->getType())->getAddressSpace() 4513 < 256 && 4514 cast<PointerType>(I.getArgOperand(1)->getType())->getAddressSpace() 4515 < 256 && 4516 "Unknown address space"); 4517 SDValue Op1 = getValue(I.getArgOperand(0)); 4518 SDValue Op2 = getValue(I.getArgOperand(1)); 4519 SDValue Op3 = getValue(I.getArgOperand(2)); 4520 unsigned Align = cast<ConstantInt>(I.getArgOperand(3))->getZExtValue(); 4521 bool isVol = cast<ConstantInt>(I.getArgOperand(4))->getZExtValue(); 4522 DAG.setRoot(DAG.getMemmove(getRoot(), dl, Op1, Op2, Op3, Align, isVol, 4523 MachinePointerInfo(I.getArgOperand(0)), 4524 MachinePointerInfo(I.getArgOperand(1)))); 4525 return 0; 4526 } 4527 case Intrinsic::dbg_declare: { 4528 const DbgDeclareInst &DI = cast<DbgDeclareInst>(I); 4529 MDNode *Variable = DI.getVariable(); 4530 const Value *Address = DI.getAddress(); 4531 if (!Address || !DIVariable(Variable).Verify()) 4532 return 0; 4533 4534 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4535 // but do not always have a corresponding SDNode built. The SDNodeOrder 4536 // absolute, but not relative, values are different depending on whether 4537 // debug info exists. 4538 ++SDNodeOrder; 4539 4540 // Check if address has undef value. 4541 if (isa<UndefValue>(Address) || 4542 (Address->use_empty() && !isa<Argument>(Address))) { 4543 DEBUG(dbgs() << "Dropping debug info for " << DI); 4544 return 0; 4545 } 4546 4547 SDValue &N = NodeMap[Address]; 4548 if (!N.getNode() && isa<Argument>(Address)) 4549 // Check unused arguments map. 4550 N = UnusedArgNodeMap[Address]; 4551 SDDbgValue *SDV; 4552 if (N.getNode()) { 4553 // Parameters are handled specially. 4554 bool isParameter = 4555 DIVariable(Variable).getTag() == dwarf::DW_TAG_arg_variable; 4556 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(Address)) 4557 Address = BCI->getOperand(0); 4558 const AllocaInst *AI = dyn_cast<AllocaInst>(Address); 4559 4560 if (isParameter && !AI) { 4561 FrameIndexSDNode *FINode = dyn_cast<FrameIndexSDNode>(N.getNode()); 4562 if (FINode) 4563 // Byval parameter. We have a frame index at this point. 4564 SDV = DAG.getDbgValue(Variable, FINode->getIndex(), 4565 0, dl, SDNodeOrder); 4566 else { 4567 // Address is an argument, so try to emit its dbg value using 4568 // virtual register info from the FuncInfo.ValueMap. 4569 EmitFuncArgumentDbgValue(Address, Variable, 0, N); 4570 return 0; 4571 } 4572 } else if (AI) 4573 SDV = DAG.getDbgValue(Variable, N.getNode(), N.getResNo(), 4574 0, dl, SDNodeOrder); 4575 else { 4576 // Can't do anything with other non-AI cases yet. 4577 DEBUG(dbgs() << "Dropping debug info for " << DI); 4578 return 0; 4579 } 4580 DAG.AddDbgValue(SDV, N.getNode(), isParameter); 4581 } else { 4582 // If Address is an argument then try to emit its dbg value using 4583 // virtual register info from the FuncInfo.ValueMap. 4584 if (!EmitFuncArgumentDbgValue(Address, Variable, 0, N)) { 4585 // If variable is pinned by a alloca in dominating bb then 4586 // use StaticAllocaMap. 4587 if (const AllocaInst *AI = dyn_cast<AllocaInst>(Address)) { 4588 if (AI->getParent() != DI.getParent()) { 4589 DenseMap<const AllocaInst*, int>::iterator SI = 4590 FuncInfo.StaticAllocaMap.find(AI); 4591 if (SI != FuncInfo.StaticAllocaMap.end()) { 4592 SDV = DAG.getDbgValue(Variable, SI->second, 4593 0, dl, SDNodeOrder); 4594 DAG.AddDbgValue(SDV, 0, false); 4595 return 0; 4596 } 4597 } 4598 } 4599 DEBUG(dbgs() << "Dropping debug info for " << DI); 4600 } 4601 } 4602 return 0; 4603 } 4604 case Intrinsic::dbg_value: { 4605 const DbgValueInst &DI = cast<DbgValueInst>(I); 4606 if (!DIVariable(DI.getVariable()).Verify()) 4607 return 0; 4608 4609 MDNode *Variable = DI.getVariable(); 4610 uint64_t Offset = DI.getOffset(); 4611 const Value *V = DI.getValue(); 4612 if (!V) 4613 return 0; 4614 4615 // Build an entry in DbgOrdering. Debug info input nodes get an SDNodeOrder 4616 // but do not always have a corresponding SDNode built. The SDNodeOrder 4617 // absolute, but not relative, values are different depending on whether 4618 // debug info exists. 4619 ++SDNodeOrder; 4620 SDDbgValue *SDV; 4621 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V)) { 4622 SDV = DAG.getDbgValue(Variable, V, Offset, dl, SDNodeOrder); 4623 DAG.AddDbgValue(SDV, 0, false); 4624 } else { 4625 // Do not use getValue() in here; we don't want to generate code at 4626 // this point if it hasn't been done yet. 4627 SDValue N = NodeMap[V]; 4628 if (!N.getNode() && isa<Argument>(V)) 4629 // Check unused arguments map. 4630 N = UnusedArgNodeMap[V]; 4631 if (N.getNode()) { 4632 if (!EmitFuncArgumentDbgValue(V, Variable, Offset, N)) { 4633 SDV = DAG.getDbgValue(Variable, N.getNode(), 4634 N.getResNo(), Offset, dl, SDNodeOrder); 4635 DAG.AddDbgValue(SDV, N.getNode(), false); 4636 } 4637 } else if (!V->use_empty() ) { 4638 // Do not call getValue(V) yet, as we don't want to generate code. 4639 // Remember it for later. 4640 DanglingDebugInfo DDI(&DI, dl, SDNodeOrder); 4641 DanglingDebugInfoMap[V] = DDI; 4642 } else { 4643 // We may expand this to cover more cases. One case where we have no 4644 // data available is an unreferenced parameter. 4645 DEBUG(dbgs() << "Dropping debug info for " << DI); 4646 } 4647 } 4648 4649 // Build a debug info table entry. 4650 if (const BitCastInst *BCI = dyn_cast<BitCastInst>(V)) 4651 V = BCI->getOperand(0); 4652 const AllocaInst *AI = dyn_cast<AllocaInst>(V); 4653 // Don't handle byval struct arguments or VLAs, for example. 4654 if (!AI) 4655 return 0; 4656 DenseMap<const AllocaInst*, int>::iterator SI = 4657 FuncInfo.StaticAllocaMap.find(AI); 4658 if (SI == FuncInfo.StaticAllocaMap.end()) 4659 return 0; // VLAs. 4660 int FI = SI->second; 4661 4662 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4663 if (!DI.getDebugLoc().isUnknown() && MMI.hasDebugInfo()) 4664 MMI.setVariableDbgInfo(Variable, FI, DI.getDebugLoc()); 4665 return 0; 4666 } 4667 case Intrinsic::eh_exception: { 4668 // Insert the EXCEPTIONADDR instruction. 4669 assert(FuncInfo.MBB->isLandingPad() && 4670 "Call to eh.exception not in landing pad!"); 4671 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4672 SDValue Ops[1]; 4673 Ops[0] = DAG.getRoot(); 4674 SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1); 4675 setValue(&I, Op); 4676 DAG.setRoot(Op.getValue(1)); 4677 return 0; 4678 } 4679 4680 case Intrinsic::eh_selector: { 4681 MachineBasicBlock *CallMBB = FuncInfo.MBB; 4682 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4683 if (CallMBB->isLandingPad()) 4684 AddCatchInfo(I, &MMI, CallMBB); 4685 else { 4686 #ifndef NDEBUG 4687 FuncInfo.CatchInfoLost.insert(&I); 4688 #endif 4689 // FIXME: Mark exception selector register as live in. Hack for PR1508. 4690 unsigned Reg = TLI.getExceptionSelectorRegister(); 4691 if (Reg) FuncInfo.MBB->addLiveIn(Reg); 4692 } 4693 4694 // Insert the EHSELECTION instruction. 4695 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other); 4696 SDValue Ops[2]; 4697 Ops[0] = getValue(I.getArgOperand(0)); 4698 Ops[1] = getRoot(); 4699 SDValue Op = DAG.getNode(ISD::EHSELECTION, dl, VTs, Ops, 2); 4700 DAG.setRoot(Op.getValue(1)); 4701 setValue(&I, DAG.getSExtOrTrunc(Op, dl, MVT::i32)); 4702 return 0; 4703 } 4704 4705 case Intrinsic::eh_typeid_for: { 4706 // Find the type id for the given typeinfo. 4707 GlobalVariable *GV = ExtractTypeInfo(I.getArgOperand(0)); 4708 unsigned TypeID = DAG.getMachineFunction().getMMI().getTypeIDFor(GV); 4709 Res = DAG.getConstant(TypeID, MVT::i32); 4710 setValue(&I, Res); 4711 return 0; 4712 } 4713 4714 case Intrinsic::eh_return_i32: 4715 case Intrinsic::eh_return_i64: 4716 DAG.getMachineFunction().getMMI().setCallsEHReturn(true); 4717 DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl, 4718 MVT::Other, 4719 getControlRoot(), 4720 getValue(I.getArgOperand(0)), 4721 getValue(I.getArgOperand(1)))); 4722 return 0; 4723 case Intrinsic::eh_unwind_init: 4724 DAG.getMachineFunction().getMMI().setCallsUnwindInit(true); 4725 return 0; 4726 case Intrinsic::eh_dwarf_cfa: { 4727 SDValue CfaArg = DAG.getSExtOrTrunc(getValue(I.getArgOperand(0)), dl, 4728 TLI.getPointerTy()); 4729 SDValue Offset = DAG.getNode(ISD::ADD, dl, 4730 TLI.getPointerTy(), 4731 DAG.getNode(ISD::FRAME_TO_ARGS_OFFSET, dl, 4732 TLI.getPointerTy()), 4733 CfaArg); 4734 SDValue FA = DAG.getNode(ISD::FRAMEADDR, dl, 4735 TLI.getPointerTy(), 4736 DAG.getConstant(0, TLI.getPointerTy())); 4737 setValue(&I, DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), 4738 FA, Offset)); 4739 return 0; 4740 } 4741 case Intrinsic::eh_sjlj_callsite: { 4742 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 4743 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(0)); 4744 assert(CI && "Non-constant call site value in eh.sjlj.callsite!"); 4745 assert(MMI.getCurrentCallSite() == 0 && "Overlapping call sites!"); 4746 4747 MMI.setCurrentCallSite(CI->getZExtValue()); 4748 return 0; 4749 } 4750 case Intrinsic::eh_sjlj_functioncontext: { 4751 // Get and store the index of the function context. 4752 MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo(); 4753 AllocaInst *FnCtx = 4754 cast<AllocaInst>(I.getArgOperand(0)->stripPointerCasts()); 4755 int FI = FuncInfo.StaticAllocaMap[FnCtx]; 4756 MFI->setFunctionContextIndex(FI); 4757 return 0; 4758 } 4759 case Intrinsic::eh_sjlj_setjmp: { 4760 SDValue Ops[2]; 4761 Ops[0] = getRoot(); 4762 Ops[1] = getValue(I.getArgOperand(0)); 4763 SDValue Op = DAG.getNode(ISD::EH_SJLJ_SETJMP, dl, 4764 DAG.getVTList(MVT::i32, MVT::Other), 4765 Ops, 2); 4766 setValue(&I, Op.getValue(0)); 4767 DAG.setRoot(Op.getValue(1)); 4768 return 0; 4769 } 4770 case Intrinsic::eh_sjlj_longjmp: { 4771 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_LONGJMP, dl, MVT::Other, 4772 getRoot(), getValue(I.getArgOperand(0)))); 4773 return 0; 4774 } 4775 case Intrinsic::eh_sjlj_dispatch_setup: { 4776 DAG.setRoot(DAG.getNode(ISD::EH_SJLJ_DISPATCHSETUP, dl, MVT::Other, 4777 getRoot(), getValue(I.getArgOperand(0)))); 4778 return 0; 4779 } 4780 4781 case Intrinsic::x86_mmx_pslli_w: 4782 case Intrinsic::x86_mmx_pslli_d: 4783 case Intrinsic::x86_mmx_pslli_q: 4784 case Intrinsic::x86_mmx_psrli_w: 4785 case Intrinsic::x86_mmx_psrli_d: 4786 case Intrinsic::x86_mmx_psrli_q: 4787 case Intrinsic::x86_mmx_psrai_w: 4788 case Intrinsic::x86_mmx_psrai_d: { 4789 SDValue ShAmt = getValue(I.getArgOperand(1)); 4790 if (isa<ConstantSDNode>(ShAmt)) { 4791 visitTargetIntrinsic(I, Intrinsic); 4792 return 0; 4793 } 4794 unsigned NewIntrinsic = 0; 4795 EVT ShAmtVT = MVT::v2i32; 4796 switch (Intrinsic) { 4797 case Intrinsic::x86_mmx_pslli_w: 4798 NewIntrinsic = Intrinsic::x86_mmx_psll_w; 4799 break; 4800 case Intrinsic::x86_mmx_pslli_d: 4801 NewIntrinsic = Intrinsic::x86_mmx_psll_d; 4802 break; 4803 case Intrinsic::x86_mmx_pslli_q: 4804 NewIntrinsic = Intrinsic::x86_mmx_psll_q; 4805 break; 4806 case Intrinsic::x86_mmx_psrli_w: 4807 NewIntrinsic = Intrinsic::x86_mmx_psrl_w; 4808 break; 4809 case Intrinsic::x86_mmx_psrli_d: 4810 NewIntrinsic = Intrinsic::x86_mmx_psrl_d; 4811 break; 4812 case Intrinsic::x86_mmx_psrli_q: 4813 NewIntrinsic = Intrinsic::x86_mmx_psrl_q; 4814 break; 4815 case Intrinsic::x86_mmx_psrai_w: 4816 NewIntrinsic = Intrinsic::x86_mmx_psra_w; 4817 break; 4818 case Intrinsic::x86_mmx_psrai_d: 4819 NewIntrinsic = Intrinsic::x86_mmx_psra_d; 4820 break; 4821 default: llvm_unreachable("Impossible intrinsic"); // Can't reach here. 4822 } 4823 4824 // The vector shift intrinsics with scalars uses 32b shift amounts but 4825 // the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits 4826 // to be zero. 4827 // We must do this early because v2i32 is not a legal type. 4828 DebugLoc dl = getCurDebugLoc(); 4829 SDValue ShOps[2]; 4830 ShOps[0] = ShAmt; 4831 ShOps[1] = DAG.getConstant(0, MVT::i32); 4832 ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2); 4833 EVT DestVT = TLI.getValueType(I.getType()); 4834 ShAmt = DAG.getNode(ISD::BITCAST, dl, DestVT, ShAmt); 4835 Res = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, DestVT, 4836 DAG.getConstant(NewIntrinsic, MVT::i32), 4837 getValue(I.getArgOperand(0)), ShAmt); 4838 setValue(&I, Res); 4839 return 0; 4840 } 4841 case Intrinsic::convertff: 4842 case Intrinsic::convertfsi: 4843 case Intrinsic::convertfui: 4844 case Intrinsic::convertsif: 4845 case Intrinsic::convertuif: 4846 case Intrinsic::convertss: 4847 case Intrinsic::convertsu: 4848 case Intrinsic::convertus: 4849 case Intrinsic::convertuu: { 4850 ISD::CvtCode Code = ISD::CVT_INVALID; 4851 switch (Intrinsic) { 4852 case Intrinsic::convertff: Code = ISD::CVT_FF; break; 4853 case Intrinsic::convertfsi: Code = ISD::CVT_FS; break; 4854 case Intrinsic::convertfui: Code = ISD::CVT_FU; break; 4855 case Intrinsic::convertsif: Code = ISD::CVT_SF; break; 4856 case Intrinsic::convertuif: Code = ISD::CVT_UF; break; 4857 case Intrinsic::convertss: Code = ISD::CVT_SS; break; 4858 case Intrinsic::convertsu: Code = ISD::CVT_SU; break; 4859 case Intrinsic::convertus: Code = ISD::CVT_US; break; 4860 case Intrinsic::convertuu: Code = ISD::CVT_UU; break; 4861 } 4862 EVT DestVT = TLI.getValueType(I.getType()); 4863 const Value *Op1 = I.getArgOperand(0); 4864 Res = DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1), 4865 DAG.getValueType(DestVT), 4866 DAG.getValueType(getValue(Op1).getValueType()), 4867 getValue(I.getArgOperand(1)), 4868 getValue(I.getArgOperand(2)), 4869 Code); 4870 setValue(&I, Res); 4871 return 0; 4872 } 4873 case Intrinsic::sqrt: 4874 setValue(&I, DAG.getNode(ISD::FSQRT, dl, 4875 getValue(I.getArgOperand(0)).getValueType(), 4876 getValue(I.getArgOperand(0)))); 4877 return 0; 4878 case Intrinsic::powi: 4879 setValue(&I, ExpandPowI(dl, getValue(I.getArgOperand(0)), 4880 getValue(I.getArgOperand(1)), DAG)); 4881 return 0; 4882 case Intrinsic::sin: 4883 setValue(&I, DAG.getNode(ISD::FSIN, dl, 4884 getValue(I.getArgOperand(0)).getValueType(), 4885 getValue(I.getArgOperand(0)))); 4886 return 0; 4887 case Intrinsic::cos: 4888 setValue(&I, DAG.getNode(ISD::FCOS, dl, 4889 getValue(I.getArgOperand(0)).getValueType(), 4890 getValue(I.getArgOperand(0)))); 4891 return 0; 4892 case Intrinsic::log: 4893 visitLog(I); 4894 return 0; 4895 case Intrinsic::log2: 4896 visitLog2(I); 4897 return 0; 4898 case Intrinsic::log10: 4899 visitLog10(I); 4900 return 0; 4901 case Intrinsic::exp: 4902 visitExp(I); 4903 return 0; 4904 case Intrinsic::exp2: 4905 visitExp2(I); 4906 return 0; 4907 case Intrinsic::pow: 4908 visitPow(I); 4909 return 0; 4910 case Intrinsic::fma: 4911 setValue(&I, DAG.getNode(ISD::FMA, dl, 4912 getValue(I.getArgOperand(0)).getValueType(), 4913 getValue(I.getArgOperand(0)), 4914 getValue(I.getArgOperand(1)), 4915 getValue(I.getArgOperand(2)))); 4916 return 0; 4917 case Intrinsic::convert_to_fp16: 4918 setValue(&I, DAG.getNode(ISD::FP32_TO_FP16, dl, 4919 MVT::i16, getValue(I.getArgOperand(0)))); 4920 return 0; 4921 case Intrinsic::convert_from_fp16: 4922 setValue(&I, DAG.getNode(ISD::FP16_TO_FP32, dl, 4923 MVT::f32, getValue(I.getArgOperand(0)))); 4924 return 0; 4925 case Intrinsic::pcmarker: { 4926 SDValue Tmp = getValue(I.getArgOperand(0)); 4927 DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp)); 4928 return 0; 4929 } 4930 case Intrinsic::readcyclecounter: { 4931 SDValue Op = getRoot(); 4932 Res = DAG.getNode(ISD::READCYCLECOUNTER, dl, 4933 DAG.getVTList(MVT::i64, MVT::Other), 4934 &Op, 1); 4935 setValue(&I, Res); 4936 DAG.setRoot(Res.getValue(1)); 4937 return 0; 4938 } 4939 case Intrinsic::bswap: 4940 setValue(&I, DAG.getNode(ISD::BSWAP, dl, 4941 getValue(I.getArgOperand(0)).getValueType(), 4942 getValue(I.getArgOperand(0)))); 4943 return 0; 4944 case Intrinsic::cttz: { 4945 SDValue Arg = getValue(I.getArgOperand(0)); 4946 EVT Ty = Arg.getValueType(); 4947 setValue(&I, DAG.getNode(ISD::CTTZ, dl, Ty, Arg)); 4948 return 0; 4949 } 4950 case Intrinsic::ctlz: { 4951 SDValue Arg = getValue(I.getArgOperand(0)); 4952 EVT Ty = Arg.getValueType(); 4953 setValue(&I, DAG.getNode(ISD::CTLZ, dl, Ty, Arg)); 4954 return 0; 4955 } 4956 case Intrinsic::ctpop: { 4957 SDValue Arg = getValue(I.getArgOperand(0)); 4958 EVT Ty = Arg.getValueType(); 4959 setValue(&I, DAG.getNode(ISD::CTPOP, dl, Ty, Arg)); 4960 return 0; 4961 } 4962 case Intrinsic::stacksave: { 4963 SDValue Op = getRoot(); 4964 Res = DAG.getNode(ISD::STACKSAVE, dl, 4965 DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1); 4966 setValue(&I, Res); 4967 DAG.setRoot(Res.getValue(1)); 4968 return 0; 4969 } 4970 case Intrinsic::stackrestore: { 4971 Res = getValue(I.getArgOperand(0)); 4972 DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Res)); 4973 return 0; 4974 } 4975 case Intrinsic::stackprotector: { 4976 // Emit code into the DAG to store the stack guard onto the stack. 4977 MachineFunction &MF = DAG.getMachineFunction(); 4978 MachineFrameInfo *MFI = MF.getFrameInfo(); 4979 EVT PtrTy = TLI.getPointerTy(); 4980 4981 SDValue Src = getValue(I.getArgOperand(0)); // The guard's value. 4982 AllocaInst *Slot = cast<AllocaInst>(I.getArgOperand(1)); 4983 4984 int FI = FuncInfo.StaticAllocaMap[Slot]; 4985 MFI->setStackProtectorIndex(FI); 4986 4987 SDValue FIN = DAG.getFrameIndex(FI, PtrTy); 4988 4989 // Store the stack protector onto the stack. 4990 Res = DAG.getStore(getRoot(), getCurDebugLoc(), Src, FIN, 4991 MachinePointerInfo::getFixedStack(FI), 4992 true, false, 0); 4993 setValue(&I, Res); 4994 DAG.setRoot(Res); 4995 return 0; 4996 } 4997 case Intrinsic::objectsize: { 4998 // If we don't know by now, we're never going to know. 4999 ConstantInt *CI = dyn_cast<ConstantInt>(I.getArgOperand(1)); 5000 5001 assert(CI && "Non-constant type in __builtin_object_size?"); 5002 5003 SDValue Arg = getValue(I.getCalledValue()); 5004 EVT Ty = Arg.getValueType(); 5005 5006 if (CI->isZero()) 5007 Res = DAG.getConstant(-1ULL, Ty); 5008 else 5009 Res = DAG.getConstant(0, Ty); 5010 5011 setValue(&I, Res); 5012 return 0; 5013 } 5014 case Intrinsic::var_annotation: 5015 // Discard annotate attributes 5016 return 0; 5017 5018 case Intrinsic::init_trampoline: { 5019 const Function *F = cast<Function>(I.getArgOperand(1)->stripPointerCasts()); 5020 5021 SDValue Ops[6]; 5022 Ops[0] = getRoot(); 5023 Ops[1] = getValue(I.getArgOperand(0)); 5024 Ops[2] = getValue(I.getArgOperand(1)); 5025 Ops[3] = getValue(I.getArgOperand(2)); 5026 Ops[4] = DAG.getSrcValue(I.getArgOperand(0)); 5027 Ops[5] = DAG.getSrcValue(F); 5028 5029 Res = DAG.getNode(ISD::INIT_TRAMPOLINE, dl, MVT::Other, Ops, 6); 5030 5031 DAG.setRoot(Res); 5032 return 0; 5033 } 5034 case Intrinsic::adjust_trampoline: { 5035 setValue(&I, DAG.getNode(ISD::ADJUST_TRAMPOLINE, dl, 5036 TLI.getPointerTy(), 5037 getValue(I.getArgOperand(0)))); 5038 return 0; 5039 } 5040 case Intrinsic::gcroot: 5041 if (GFI) { 5042 const Value *Alloca = I.getArgOperand(0); 5043 const Constant *TypeMap = cast<Constant>(I.getArgOperand(1)); 5044 5045 FrameIndexSDNode *FI = cast<FrameIndexSDNode>(getValue(Alloca).getNode()); 5046 GFI->addStackRoot(FI->getIndex(), TypeMap); 5047 } 5048 return 0; 5049 case Intrinsic::gcread: 5050 case Intrinsic::gcwrite: 5051 llvm_unreachable("GC failed to lower gcread/gcwrite intrinsics!"); 5052 return 0; 5053 case Intrinsic::flt_rounds: 5054 setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32)); 5055 return 0; 5056 5057 case Intrinsic::expect: { 5058 // Just replace __builtin_expect(exp, c) with EXP. 5059 setValue(&I, getValue(I.getArgOperand(0))); 5060 return 0; 5061 } 5062 5063 case Intrinsic::trap: { 5064 StringRef TrapFuncName = getTrapFunctionName(); 5065 if (TrapFuncName.empty()) { 5066 DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot())); 5067 return 0; 5068 } 5069 TargetLowering::ArgListTy Args; 5070 std::pair<SDValue, SDValue> Result = 5071 TLI.LowerCallTo(getRoot(), I.getType(), 5072 false, false, false, false, 0, CallingConv::C, 5073 /*isTailCall=*/false, /*isReturnValueUsed=*/true, 5074 DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()), 5075 Args, DAG, getCurDebugLoc()); 5076 DAG.setRoot(Result.second); 5077 return 0; 5078 } 5079 case Intrinsic::uadd_with_overflow: 5080 return implVisitAluOverflow(I, ISD::UADDO); 5081 case Intrinsic::sadd_with_overflow: 5082 return implVisitAluOverflow(I, ISD::SADDO); 5083 case Intrinsic::usub_with_overflow: 5084 return implVisitAluOverflow(I, ISD::USUBO); 5085 case Intrinsic::ssub_with_overflow: 5086 return implVisitAluOverflow(I, ISD::SSUBO); 5087 case Intrinsic::umul_with_overflow: 5088 return implVisitAluOverflow(I, ISD::UMULO); 5089 case Intrinsic::smul_with_overflow: 5090 return implVisitAluOverflow(I, ISD::SMULO); 5091 5092 case Intrinsic::prefetch: { 5093 SDValue Ops[5]; 5094 unsigned rw = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue(); 5095 Ops[0] = getRoot(); 5096 Ops[1] = getValue(I.getArgOperand(0)); 5097 Ops[2] = getValue(I.getArgOperand(1)); 5098 Ops[3] = getValue(I.getArgOperand(2)); 5099 Ops[4] = getValue(I.getArgOperand(3)); 5100 DAG.setRoot(DAG.getMemIntrinsicNode(ISD::PREFETCH, dl, 5101 DAG.getVTList(MVT::Other), 5102 &Ops[0], 5, 5103 EVT::getIntegerVT(*Context, 8), 5104 MachinePointerInfo(I.getArgOperand(0)), 5105 0, /* align */ 5106 false, /* volatile */ 5107 rw==0, /* read */ 5108 rw==1)); /* write */ 5109 return 0; 5110 } 5111 5112 case Intrinsic::invariant_start: 5113 case Intrinsic::lifetime_start: 5114 // Discard region information. 5115 setValue(&I, DAG.getUNDEF(TLI.getPointerTy())); 5116 return 0; 5117 case Intrinsic::invariant_end: 5118 case Intrinsic::lifetime_end: 5119 // Discard region information. 5120 return 0; 5121 } 5122 } 5123 5124 void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee, 5125 bool isTailCall, 5126 MachineBasicBlock *LandingPad) { 5127 PointerType *PT = cast<PointerType>(CS.getCalledValue()->getType()); 5128 FunctionType *FTy = cast<FunctionType>(PT->getElementType()); 5129 Type *RetTy = FTy->getReturnType(); 5130 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5131 MCSymbol *BeginLabel = 0; 5132 5133 TargetLowering::ArgListTy Args; 5134 TargetLowering::ArgListEntry Entry; 5135 Args.reserve(CS.arg_size()); 5136 5137 // Check whether the function can return without sret-demotion. 5138 SmallVector<ISD::OutputArg, 4> Outs; 5139 SmallVector<uint64_t, 4> Offsets; 5140 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(), 5141 Outs, TLI, &Offsets); 5142 5143 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(), 5144 DAG.getMachineFunction(), 5145 FTy->isVarArg(), Outs, 5146 FTy->getContext()); 5147 5148 SDValue DemoteStackSlot; 5149 int DemoteStackIdx = -100; 5150 5151 if (!CanLowerReturn) { 5152 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize( 5153 FTy->getReturnType()); 5154 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment( 5155 FTy->getReturnType()); 5156 MachineFunction &MF = DAG.getMachineFunction(); 5157 DemoteStackIdx = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5158 Type *StackSlotPtrType = PointerType::getUnqual(FTy->getReturnType()); 5159 5160 DemoteStackSlot = DAG.getFrameIndex(DemoteStackIdx, TLI.getPointerTy()); 5161 Entry.Node = DemoteStackSlot; 5162 Entry.Ty = StackSlotPtrType; 5163 Entry.isSExt = false; 5164 Entry.isZExt = false; 5165 Entry.isInReg = false; 5166 Entry.isSRet = true; 5167 Entry.isNest = false; 5168 Entry.isByVal = false; 5169 Entry.Alignment = Align; 5170 Args.push_back(Entry); 5171 RetTy = Type::getVoidTy(FTy->getContext()); 5172 } 5173 5174 for (ImmutableCallSite::arg_iterator i = CS.arg_begin(), e = CS.arg_end(); 5175 i != e; ++i) { 5176 const Value *V = *i; 5177 5178 // Skip empty types 5179 if (V->getType()->isEmptyTy()) 5180 continue; 5181 5182 SDValue ArgNode = getValue(V); 5183 Entry.Node = ArgNode; Entry.Ty = V->getType(); 5184 5185 unsigned attrInd = i - CS.arg_begin() + 1; 5186 Entry.isSExt = CS.paramHasAttr(attrInd, Attribute::SExt); 5187 Entry.isZExt = CS.paramHasAttr(attrInd, Attribute::ZExt); 5188 Entry.isInReg = CS.paramHasAttr(attrInd, Attribute::InReg); 5189 Entry.isSRet = CS.paramHasAttr(attrInd, Attribute::StructRet); 5190 Entry.isNest = CS.paramHasAttr(attrInd, Attribute::Nest); 5191 Entry.isByVal = CS.paramHasAttr(attrInd, Attribute::ByVal); 5192 Entry.Alignment = CS.getParamAlignment(attrInd); 5193 Args.push_back(Entry); 5194 } 5195 5196 if (LandingPad) { 5197 // Insert a label before the invoke call to mark the try range. This can be 5198 // used to detect deletion of the invoke via the MachineModuleInfo. 5199 BeginLabel = MMI.getContext().CreateTempSymbol(); 5200 5201 // For SjLj, keep track of which landing pads go with which invokes 5202 // so as to maintain the ordering of pads in the LSDA. 5203 unsigned CallSiteIndex = MMI.getCurrentCallSite(); 5204 if (CallSiteIndex) { 5205 MMI.setCallSiteBeginLabel(BeginLabel, CallSiteIndex); 5206 LPadToCallSiteMap[LandingPad].push_back(CallSiteIndex); 5207 5208 // Now that the call site is handled, stop tracking it. 5209 MMI.setCurrentCallSite(0); 5210 } 5211 5212 // Both PendingLoads and PendingExports must be flushed here; 5213 // this call might not return. 5214 (void)getRoot(); 5215 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getControlRoot(), BeginLabel)); 5216 } 5217 5218 // Check if target-independent constraints permit a tail call here. 5219 // Target-dependent constraints are checked within TLI.LowerCallTo. 5220 if (isTailCall && 5221 !isInTailCallPosition(CS, CS.getAttributes().getRetAttributes(), TLI)) 5222 isTailCall = false; 5223 5224 // If there's a possibility that fast-isel has already selected some amount 5225 // of the current basic block, don't emit a tail call. 5226 if (isTailCall && EnableFastISel) 5227 isTailCall = false; 5228 5229 std::pair<SDValue,SDValue> Result = 5230 TLI.LowerCallTo(getRoot(), RetTy, 5231 CS.paramHasAttr(0, Attribute::SExt), 5232 CS.paramHasAttr(0, Attribute::ZExt), FTy->isVarArg(), 5233 CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(), 5234 CS.getCallingConv(), 5235 isTailCall, 5236 !CS.getInstruction()->use_empty(), 5237 Callee, Args, DAG, getCurDebugLoc()); 5238 assert((isTailCall || Result.second.getNode()) && 5239 "Non-null chain expected with non-tail call!"); 5240 assert((Result.second.getNode() || !Result.first.getNode()) && 5241 "Null value expected with tail call!"); 5242 if (Result.first.getNode()) { 5243 setValue(CS.getInstruction(), Result.first); 5244 } else if (!CanLowerReturn && Result.second.getNode()) { 5245 // The instruction result is the result of loading from the 5246 // hidden sret parameter. 5247 SmallVector<EVT, 1> PVTs; 5248 Type *PtrRetTy = PointerType::getUnqual(FTy->getReturnType()); 5249 5250 ComputeValueVTs(TLI, PtrRetTy, PVTs); 5251 assert(PVTs.size() == 1 && "Pointers should fit in one register"); 5252 EVT PtrVT = PVTs[0]; 5253 unsigned NumValues = Outs.size(); 5254 SmallVector<SDValue, 4> Values(NumValues); 5255 SmallVector<SDValue, 4> Chains(NumValues); 5256 5257 for (unsigned i = 0; i < NumValues; ++i) { 5258 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT, 5259 DemoteStackSlot, 5260 DAG.getConstant(Offsets[i], PtrVT)); 5261 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second, 5262 Add, 5263 MachinePointerInfo::getFixedStack(DemoteStackIdx, Offsets[i]), 5264 false, false, 1); 5265 Values[i] = L; 5266 Chains[i] = L.getValue(1); 5267 } 5268 5269 SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), 5270 MVT::Other, &Chains[0], NumValues); 5271 PendingLoads.push_back(Chain); 5272 5273 // Collect the legal value parts into potentially illegal values 5274 // that correspond to the original function's return values. 5275 SmallVector<EVT, 4> RetTys; 5276 RetTy = FTy->getReturnType(); 5277 ComputeValueVTs(TLI, RetTy, RetTys); 5278 ISD::NodeType AssertOp = ISD::DELETED_NODE; 5279 SmallVector<SDValue, 4> ReturnValues; 5280 unsigned CurReg = 0; 5281 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 5282 EVT VT = RetTys[I]; 5283 EVT RegisterVT = TLI.getRegisterType(RetTy->getContext(), VT); 5284 unsigned NumRegs = TLI.getNumRegisters(RetTy->getContext(), VT); 5285 5286 SDValue ReturnValue = 5287 getCopyFromParts(DAG, getCurDebugLoc(), &Values[CurReg], NumRegs, 5288 RegisterVT, VT, AssertOp); 5289 ReturnValues.push_back(ReturnValue); 5290 CurReg += NumRegs; 5291 } 5292 5293 setValue(CS.getInstruction(), 5294 DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), 5295 DAG.getVTList(&RetTys[0], RetTys.size()), 5296 &ReturnValues[0], ReturnValues.size())); 5297 } 5298 5299 // Assign order to nodes here. If the call does not produce a result, it won't 5300 // be mapped to a SDNode and visit() will not assign it an order number. 5301 if (!Result.second.getNode()) { 5302 // As a special case, a null chain means that a tail call has been emitted and 5303 // the DAG root is already updated. 5304 HasTailCall = true; 5305 ++SDNodeOrder; 5306 AssignOrderingToNode(DAG.getRoot().getNode()); 5307 } else { 5308 DAG.setRoot(Result.second); 5309 ++SDNodeOrder; 5310 AssignOrderingToNode(Result.second.getNode()); 5311 } 5312 5313 if (LandingPad) { 5314 // Insert a label at the end of the invoke call to mark the try range. This 5315 // can be used to detect deletion of the invoke via the MachineModuleInfo. 5316 MCSymbol *EndLabel = MMI.getContext().CreateTempSymbol(); 5317 DAG.setRoot(DAG.getEHLabel(getCurDebugLoc(), getRoot(), EndLabel)); 5318 5319 // Inform MachineModuleInfo of range. 5320 MMI.addInvoke(LandingPad, BeginLabel, EndLabel); 5321 } 5322 } 5323 5324 /// IsOnlyUsedInZeroEqualityComparison - Return true if it only matters that the 5325 /// value is equal or not-equal to zero. 5326 static bool IsOnlyUsedInZeroEqualityComparison(const Value *V) { 5327 for (Value::const_use_iterator UI = V->use_begin(), E = V->use_end(); 5328 UI != E; ++UI) { 5329 if (const ICmpInst *IC = dyn_cast<ICmpInst>(*UI)) 5330 if (IC->isEquality()) 5331 if (const Constant *C = dyn_cast<Constant>(IC->getOperand(1))) 5332 if (C->isNullValue()) 5333 continue; 5334 // Unknown instruction. 5335 return false; 5336 } 5337 return true; 5338 } 5339 5340 static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, 5341 Type *LoadTy, 5342 SelectionDAGBuilder &Builder) { 5343 5344 // Check to see if this load can be trivially constant folded, e.g. if the 5345 // input is from a string literal. 5346 if (const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) { 5347 // Cast pointer to the type we really want to load. 5348 LoadInput = ConstantExpr::getBitCast(const_cast<Constant *>(LoadInput), 5349 PointerType::getUnqual(LoadTy)); 5350 5351 if (const Constant *LoadCst = 5352 ConstantFoldLoadFromConstPtr(const_cast<Constant *>(LoadInput), 5353 Builder.TD)) 5354 return Builder.getValue(LoadCst); 5355 } 5356 5357 // Otherwise, we have to emit the load. If the pointer is to unfoldable but 5358 // still constant memory, the input chain can be the entry node. 5359 SDValue Root; 5360 bool ConstantMemory = false; 5361 5362 // Do not serialize (non-volatile) loads of constant memory with anything. 5363 if (Builder.AA->pointsToConstantMemory(PtrVal)) { 5364 Root = Builder.DAG.getEntryNode(); 5365 ConstantMemory = true; 5366 } else { 5367 // Do not serialize non-volatile loads against each other. 5368 Root = Builder.DAG.getRoot(); 5369 } 5370 5371 SDValue Ptr = Builder.getValue(PtrVal); 5372 SDValue LoadVal = Builder.DAG.getLoad(LoadVT, Builder.getCurDebugLoc(), Root, 5373 Ptr, MachinePointerInfo(PtrVal), 5374 false /*volatile*/, 5375 false /*nontemporal*/, 1 /* align=1 */); 5376 5377 if (!ConstantMemory) 5378 Builder.PendingLoads.push_back(LoadVal.getValue(1)); 5379 return LoadVal; 5380 } 5381 5382 5383 /// visitMemCmpCall - See if we can lower a call to memcmp in an optimized form. 5384 /// If so, return true and lower it, otherwise return false and it will be 5385 /// lowered like a normal call. 5386 bool SelectionDAGBuilder::visitMemCmpCall(const CallInst &I) { 5387 // Verify that the prototype makes sense. int memcmp(void*,void*,size_t) 5388 if (I.getNumArgOperands() != 3) 5389 return false; 5390 5391 const Value *LHS = I.getArgOperand(0), *RHS = I.getArgOperand(1); 5392 if (!LHS->getType()->isPointerTy() || !RHS->getType()->isPointerTy() || 5393 !I.getArgOperand(2)->getType()->isIntegerTy() || 5394 !I.getType()->isIntegerTy()) 5395 return false; 5396 5397 const ConstantInt *Size = dyn_cast<ConstantInt>(I.getArgOperand(2)); 5398 5399 // memcmp(S1,S2,2) != 0 -> (*(short*)LHS != *(short*)RHS) != 0 5400 // memcmp(S1,S2,4) != 0 -> (*(int*)LHS != *(int*)RHS) != 0 5401 if (Size && IsOnlyUsedInZeroEqualityComparison(&I)) { 5402 bool ActuallyDoIt = true; 5403 MVT LoadVT; 5404 Type *LoadTy; 5405 switch (Size->getZExtValue()) { 5406 default: 5407 LoadVT = MVT::Other; 5408 LoadTy = 0; 5409 ActuallyDoIt = false; 5410 break; 5411 case 2: 5412 LoadVT = MVT::i16; 5413 LoadTy = Type::getInt16Ty(Size->getContext()); 5414 break; 5415 case 4: 5416 LoadVT = MVT::i32; 5417 LoadTy = Type::getInt32Ty(Size->getContext()); 5418 break; 5419 case 8: 5420 LoadVT = MVT::i64; 5421 LoadTy = Type::getInt64Ty(Size->getContext()); 5422 break; 5423 /* 5424 case 16: 5425 LoadVT = MVT::v4i32; 5426 LoadTy = Type::getInt32Ty(Size->getContext()); 5427 LoadTy = VectorType::get(LoadTy, 4); 5428 break; 5429 */ 5430 } 5431 5432 // This turns into unaligned loads. We only do this if the target natively 5433 // supports the MVT we'll be loading or if it is small enough (<= 4) that 5434 // we'll only produce a small number of byte loads. 5435 5436 // Require that we can find a legal MVT, and only do this if the target 5437 // supports unaligned loads of that type. Expanding into byte loads would 5438 // bloat the code. 5439 if (ActuallyDoIt && Size->getZExtValue() > 4) { 5440 // TODO: Handle 5 byte compare as 4-byte + 1 byte. 5441 // TODO: Handle 8 byte compare on x86-32 as two 32-bit loads. 5442 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) 5443 ActuallyDoIt = false; 5444 } 5445 5446 if (ActuallyDoIt) { 5447 SDValue LHSVal = getMemCmpLoad(LHS, LoadVT, LoadTy, *this); 5448 SDValue RHSVal = getMemCmpLoad(RHS, LoadVT, LoadTy, *this); 5449 5450 SDValue Res = DAG.getSetCC(getCurDebugLoc(), MVT::i1, LHSVal, RHSVal, 5451 ISD::SETNE); 5452 EVT CallVT = TLI.getValueType(I.getType(), true); 5453 setValue(&I, DAG.getZExtOrTrunc(Res, getCurDebugLoc(), CallVT)); 5454 return true; 5455 } 5456 } 5457 5458 5459 return false; 5460 } 5461 5462 5463 void SelectionDAGBuilder::visitCall(const CallInst &I) { 5464 // Handle inline assembly differently. 5465 if (isa<InlineAsm>(I.getCalledValue())) { 5466 visitInlineAsm(&I); 5467 return; 5468 } 5469 5470 // See if any floating point values are being passed to this function. This is 5471 // used to emit an undefined reference to fltused on Windows. 5472 FunctionType *FT = 5473 cast<FunctionType>(I.getCalledValue()->getType()->getContainedType(0)); 5474 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI(); 5475 if (FT->isVarArg() && 5476 !MMI.callsExternalVAFunctionWithFloatingPointArguments()) { 5477 for (unsigned i = 0, e = I.getNumArgOperands(); i != e; ++i) { 5478 Type* T = I.getArgOperand(i)->getType(); 5479 for (po_iterator<Type*> i = po_begin(T), e = po_end(T); 5480 i != e; ++i) { 5481 if (!i->isFloatingPointTy()) continue; 5482 MMI.setCallsExternalVAFunctionWithFloatingPointArguments(true); 5483 break; 5484 } 5485 } 5486 } 5487 5488 const char *RenameFn = 0; 5489 if (Function *F = I.getCalledFunction()) { 5490 if (F->isDeclaration()) { 5491 if (const TargetIntrinsicInfo *II = TM.getIntrinsicInfo()) { 5492 if (unsigned IID = II->getIntrinsicID(F)) { 5493 RenameFn = visitIntrinsicCall(I, IID); 5494 if (!RenameFn) 5495 return; 5496 } 5497 } 5498 if (unsigned IID = F->getIntrinsicID()) { 5499 RenameFn = visitIntrinsicCall(I, IID); 5500 if (!RenameFn) 5501 return; 5502 } 5503 } 5504 5505 // Check for well-known libc/libm calls. If the function is internal, it 5506 // can't be a library call. 5507 if (!F->hasLocalLinkage() && F->hasName()) { 5508 StringRef Name = F->getName(); 5509 if (Name == "copysign" || Name == "copysignf" || Name == "copysignl") { 5510 if (I.getNumArgOperands() == 2 && // Basic sanity checks. 5511 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5512 I.getType() == I.getArgOperand(0)->getType() && 5513 I.getType() == I.getArgOperand(1)->getType()) { 5514 SDValue LHS = getValue(I.getArgOperand(0)); 5515 SDValue RHS = getValue(I.getArgOperand(1)); 5516 setValue(&I, DAG.getNode(ISD::FCOPYSIGN, getCurDebugLoc(), 5517 LHS.getValueType(), LHS, RHS)); 5518 return; 5519 } 5520 } else if (Name == "fabs" || Name == "fabsf" || Name == "fabsl") { 5521 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5522 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5523 I.getType() == I.getArgOperand(0)->getType()) { 5524 SDValue Tmp = getValue(I.getArgOperand(0)); 5525 setValue(&I, DAG.getNode(ISD::FABS, getCurDebugLoc(), 5526 Tmp.getValueType(), Tmp)); 5527 return; 5528 } 5529 } else if (Name == "sin" || Name == "sinf" || Name == "sinl") { 5530 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5531 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5532 I.getType() == I.getArgOperand(0)->getType() && 5533 I.onlyReadsMemory()) { 5534 SDValue Tmp = getValue(I.getArgOperand(0)); 5535 setValue(&I, DAG.getNode(ISD::FSIN, getCurDebugLoc(), 5536 Tmp.getValueType(), Tmp)); 5537 return; 5538 } 5539 } else if (Name == "cos" || Name == "cosf" || Name == "cosl") { 5540 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5541 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5542 I.getType() == I.getArgOperand(0)->getType() && 5543 I.onlyReadsMemory()) { 5544 SDValue Tmp = getValue(I.getArgOperand(0)); 5545 setValue(&I, DAG.getNode(ISD::FCOS, getCurDebugLoc(), 5546 Tmp.getValueType(), Tmp)); 5547 return; 5548 } 5549 } else if (Name == "sqrt" || Name == "sqrtf" || Name == "sqrtl") { 5550 if (I.getNumArgOperands() == 1 && // Basic sanity checks. 5551 I.getArgOperand(0)->getType()->isFloatingPointTy() && 5552 I.getType() == I.getArgOperand(0)->getType() && 5553 I.onlyReadsMemory()) { 5554 SDValue Tmp = getValue(I.getArgOperand(0)); 5555 setValue(&I, DAG.getNode(ISD::FSQRT, getCurDebugLoc(), 5556 Tmp.getValueType(), Tmp)); 5557 return; 5558 } 5559 } else if (Name == "memcmp") { 5560 if (visitMemCmpCall(I)) 5561 return; 5562 } 5563 } 5564 } 5565 5566 SDValue Callee; 5567 if (!RenameFn) 5568 Callee = getValue(I.getCalledValue()); 5569 else 5570 Callee = DAG.getExternalSymbol(RenameFn, TLI.getPointerTy()); 5571 5572 // Check if we can potentially perform a tail call. More detailed checking is 5573 // be done within LowerCallTo, after more information about the call is known. 5574 LowerCallTo(&I, Callee, I.isTailCall()); 5575 } 5576 5577 namespace { 5578 5579 /// AsmOperandInfo - This contains information for each constraint that we are 5580 /// lowering. 5581 class SDISelAsmOperandInfo : public TargetLowering::AsmOperandInfo { 5582 public: 5583 /// CallOperand - If this is the result output operand or a clobber 5584 /// this is null, otherwise it is the incoming operand to the CallInst. 5585 /// This gets modified as the asm is processed. 5586 SDValue CallOperand; 5587 5588 /// AssignedRegs - If this is a register or register class operand, this 5589 /// contains the set of register corresponding to the operand. 5590 RegsForValue AssignedRegs; 5591 5592 explicit SDISelAsmOperandInfo(const TargetLowering::AsmOperandInfo &info) 5593 : TargetLowering::AsmOperandInfo(info), CallOperand(0,0) { 5594 } 5595 5596 /// MarkAllocatedRegs - Once AssignedRegs is set, mark the assigned registers 5597 /// busy in OutputRegs/InputRegs. 5598 void MarkAllocatedRegs(bool isOutReg, bool isInReg, 5599 std::set<unsigned> &OutputRegs, 5600 std::set<unsigned> &InputRegs, 5601 const TargetRegisterInfo &TRI) const { 5602 if (isOutReg) { 5603 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5604 MarkRegAndAliases(AssignedRegs.Regs[i], OutputRegs, TRI); 5605 } 5606 if (isInReg) { 5607 for (unsigned i = 0, e = AssignedRegs.Regs.size(); i != e; ++i) 5608 MarkRegAndAliases(AssignedRegs.Regs[i], InputRegs, TRI); 5609 } 5610 } 5611 5612 /// getCallOperandValEVT - Return the EVT of the Value* that this operand 5613 /// corresponds to. If there is no Value* for this operand, it returns 5614 /// MVT::Other. 5615 EVT getCallOperandValEVT(LLVMContext &Context, 5616 const TargetLowering &TLI, 5617 const TargetData *TD) const { 5618 if (CallOperandVal == 0) return MVT::Other; 5619 5620 if (isa<BasicBlock>(CallOperandVal)) 5621 return TLI.getPointerTy(); 5622 5623 llvm::Type *OpTy = CallOperandVal->getType(); 5624 5625 // FIXME: code duplicated from TargetLowering::ParseConstraints(). 5626 // If this is an indirect operand, the operand is a pointer to the 5627 // accessed type. 5628 if (isIndirect) { 5629 llvm::PointerType *PtrTy = dyn_cast<PointerType>(OpTy); 5630 if (!PtrTy) 5631 report_fatal_error("Indirect operand for inline asm not a pointer!"); 5632 OpTy = PtrTy->getElementType(); 5633 } 5634 5635 // Look for vector wrapped in a struct. e.g. { <16 x i8> }. 5636 if (StructType *STy = dyn_cast<StructType>(OpTy)) 5637 if (STy->getNumElements() == 1) 5638 OpTy = STy->getElementType(0); 5639 5640 // If OpTy is not a single value, it may be a struct/union that we 5641 // can tile with integers. 5642 if (!OpTy->isSingleValueType() && OpTy->isSized()) { 5643 unsigned BitSize = TD->getTypeSizeInBits(OpTy); 5644 switch (BitSize) { 5645 default: break; 5646 case 1: 5647 case 8: 5648 case 16: 5649 case 32: 5650 case 64: 5651 case 128: 5652 OpTy = IntegerType::get(Context, BitSize); 5653 break; 5654 } 5655 } 5656 5657 return TLI.getValueType(OpTy, true); 5658 } 5659 5660 private: 5661 /// MarkRegAndAliases - Mark the specified register and all aliases in the 5662 /// specified set. 5663 static void MarkRegAndAliases(unsigned Reg, std::set<unsigned> &Regs, 5664 const TargetRegisterInfo &TRI) { 5665 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && "Isn't a physreg"); 5666 Regs.insert(Reg); 5667 if (const unsigned *Aliases = TRI.getAliasSet(Reg)) 5668 for (; *Aliases; ++Aliases) 5669 Regs.insert(*Aliases); 5670 } 5671 }; 5672 5673 typedef SmallVector<SDISelAsmOperandInfo,16> SDISelAsmOperandInfoVector; 5674 5675 } // end anonymous namespace 5676 5677 /// GetRegistersForValue - Assign registers (virtual or physical) for the 5678 /// specified operand. We prefer to assign virtual registers, to allow the 5679 /// register allocator to handle the assignment process. However, if the asm 5680 /// uses features that we can't model on machineinstrs, we have SDISel do the 5681 /// allocation. This produces generally horrible, but correct, code. 5682 /// 5683 /// OpInfo describes the operand. 5684 /// Input and OutputRegs are the set of already allocated physical registers. 5685 /// 5686 static void GetRegistersForValue(SelectionDAG &DAG, 5687 const TargetLowering &TLI, 5688 DebugLoc DL, 5689 SDISelAsmOperandInfo &OpInfo, 5690 std::set<unsigned> &OutputRegs, 5691 std::set<unsigned> &InputRegs) { 5692 LLVMContext &Context = *DAG.getContext(); 5693 5694 // Compute whether this value requires an input register, an output register, 5695 // or both. 5696 bool isOutReg = false; 5697 bool isInReg = false; 5698 switch (OpInfo.Type) { 5699 case InlineAsm::isOutput: 5700 isOutReg = true; 5701 5702 // If there is an input constraint that matches this, we need to reserve 5703 // the input register so no other inputs allocate to it. 5704 isInReg = OpInfo.hasMatchingInput(); 5705 break; 5706 case InlineAsm::isInput: 5707 isInReg = true; 5708 isOutReg = false; 5709 break; 5710 case InlineAsm::isClobber: 5711 isOutReg = true; 5712 isInReg = true; 5713 break; 5714 } 5715 5716 5717 MachineFunction &MF = DAG.getMachineFunction(); 5718 SmallVector<unsigned, 4> Regs; 5719 5720 // If this is a constraint for a single physreg, or a constraint for a 5721 // register class, find it. 5722 std::pair<unsigned, const TargetRegisterClass*> PhysReg = 5723 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5724 OpInfo.ConstraintVT); 5725 5726 unsigned NumRegs = 1; 5727 if (OpInfo.ConstraintVT != MVT::Other) { 5728 // If this is a FP input in an integer register (or visa versa) insert a bit 5729 // cast of the input value. More generally, handle any case where the input 5730 // value disagrees with the register class we plan to stick this in. 5731 if (OpInfo.Type == InlineAsm::isInput && 5732 PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) { 5733 // Try to convert to the first EVT that the reg class contains. If the 5734 // types are identical size, use a bitcast to convert (e.g. two differing 5735 // vector types). 5736 EVT RegVT = *PhysReg.second->vt_begin(); 5737 if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) { 5738 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5739 RegVT, OpInfo.CallOperand); 5740 OpInfo.ConstraintVT = RegVT; 5741 } else if (RegVT.isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) { 5742 // If the input is a FP value and we want it in FP registers, do a 5743 // bitcast to the corresponding integer type. This turns an f64 value 5744 // into i64, which can be passed with two i32 values on a 32-bit 5745 // machine. 5746 RegVT = EVT::getIntegerVT(Context, 5747 OpInfo.ConstraintVT.getSizeInBits()); 5748 OpInfo.CallOperand = DAG.getNode(ISD::BITCAST, DL, 5749 RegVT, OpInfo.CallOperand); 5750 OpInfo.ConstraintVT = RegVT; 5751 } 5752 } 5753 5754 NumRegs = TLI.getNumRegisters(Context, OpInfo.ConstraintVT); 5755 } 5756 5757 EVT RegVT; 5758 EVT ValueVT = OpInfo.ConstraintVT; 5759 5760 // If this is a constraint for a specific physical register, like {r17}, 5761 // assign it now. 5762 if (unsigned AssignedReg = PhysReg.first) { 5763 const TargetRegisterClass *RC = PhysReg.second; 5764 if (OpInfo.ConstraintVT == MVT::Other) 5765 ValueVT = *RC->vt_begin(); 5766 5767 // Get the actual register value type. This is important, because the user 5768 // may have asked for (e.g.) the AX register in i32 type. We need to 5769 // remember that AX is actually i16 to get the right extension. 5770 RegVT = *RC->vt_begin(); 5771 5772 // This is a explicit reference to a physical register. 5773 Regs.push_back(AssignedReg); 5774 5775 // If this is an expanded reference, add the rest of the regs to Regs. 5776 if (NumRegs != 1) { 5777 TargetRegisterClass::iterator I = RC->begin(); 5778 for (; *I != AssignedReg; ++I) 5779 assert(I != RC->end() && "Didn't find reg!"); 5780 5781 // Already added the first reg. 5782 --NumRegs; ++I; 5783 for (; NumRegs; --NumRegs, ++I) { 5784 assert(I != RC->end() && "Ran out of registers to allocate!"); 5785 Regs.push_back(*I); 5786 } 5787 } 5788 5789 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5790 const TargetRegisterInfo *TRI = DAG.getTarget().getRegisterInfo(); 5791 OpInfo.MarkAllocatedRegs(isOutReg, isInReg, OutputRegs, InputRegs, *TRI); 5792 return; 5793 } 5794 5795 // Otherwise, if this was a reference to an LLVM register class, create vregs 5796 // for this reference. 5797 if (const TargetRegisterClass *RC = PhysReg.second) { 5798 RegVT = *RC->vt_begin(); 5799 if (OpInfo.ConstraintVT == MVT::Other) 5800 ValueVT = RegVT; 5801 5802 // Create the appropriate number of virtual registers. 5803 MachineRegisterInfo &RegInfo = MF.getRegInfo(); 5804 for (; NumRegs; --NumRegs) 5805 Regs.push_back(RegInfo.createVirtualRegister(RC)); 5806 5807 OpInfo.AssignedRegs = RegsForValue(Regs, RegVT, ValueVT); 5808 return; 5809 } 5810 5811 // Otherwise, we couldn't allocate enough registers for this. 5812 } 5813 5814 /// visitInlineAsm - Handle a call to an InlineAsm object. 5815 /// 5816 void SelectionDAGBuilder::visitInlineAsm(ImmutableCallSite CS) { 5817 const InlineAsm *IA = cast<InlineAsm>(CS.getCalledValue()); 5818 5819 /// ConstraintOperands - Information about all of the constraints. 5820 SDISelAsmOperandInfoVector ConstraintOperands; 5821 5822 std::set<unsigned> OutputRegs, InputRegs; 5823 5824 TargetLowering::AsmOperandInfoVector 5825 TargetConstraints = TLI.ParseConstraints(CS); 5826 5827 bool hasMemory = false; 5828 5829 unsigned ArgNo = 0; // ArgNo - The argument of the CallInst. 5830 unsigned ResNo = 0; // ResNo - The result number of the next output. 5831 for (unsigned i = 0, e = TargetConstraints.size(); i != e; ++i) { 5832 ConstraintOperands.push_back(SDISelAsmOperandInfo(TargetConstraints[i])); 5833 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back(); 5834 5835 EVT OpVT = MVT::Other; 5836 5837 // Compute the value type for each operand. 5838 switch (OpInfo.Type) { 5839 case InlineAsm::isOutput: 5840 // Indirect outputs just consume an argument. 5841 if (OpInfo.isIndirect) { 5842 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5843 break; 5844 } 5845 5846 // The return value of the call is this value. As such, there is no 5847 // corresponding argument. 5848 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 5849 if (StructType *STy = dyn_cast<StructType>(CS.getType())) { 5850 OpVT = TLI.getValueType(STy->getElementType(ResNo)); 5851 } else { 5852 assert(ResNo == 0 && "Asm only has one result!"); 5853 OpVT = TLI.getValueType(CS.getType()); 5854 } 5855 ++ResNo; 5856 break; 5857 case InlineAsm::isInput: 5858 OpInfo.CallOperandVal = const_cast<Value *>(CS.getArgument(ArgNo++)); 5859 break; 5860 case InlineAsm::isClobber: 5861 // Nothing to do. 5862 break; 5863 } 5864 5865 // If this is an input or an indirect output, process the call argument. 5866 // BasicBlocks are labels, currently appearing only in asm's. 5867 if (OpInfo.CallOperandVal) { 5868 if (const BasicBlock *BB = dyn_cast<BasicBlock>(OpInfo.CallOperandVal)) { 5869 OpInfo.CallOperand = DAG.getBasicBlock(FuncInfo.MBBMap[BB]); 5870 } else { 5871 OpInfo.CallOperand = getValue(OpInfo.CallOperandVal); 5872 } 5873 5874 OpVT = OpInfo.getCallOperandValEVT(*DAG.getContext(), TLI, TD); 5875 } 5876 5877 OpInfo.ConstraintVT = OpVT; 5878 5879 // Indirect operand accesses access memory. 5880 if (OpInfo.isIndirect) 5881 hasMemory = true; 5882 else { 5883 for (unsigned j = 0, ee = OpInfo.Codes.size(); j != ee; ++j) { 5884 TargetLowering::ConstraintType 5885 CType = TLI.getConstraintType(OpInfo.Codes[j]); 5886 if (CType == TargetLowering::C_Memory) { 5887 hasMemory = true; 5888 break; 5889 } 5890 } 5891 } 5892 } 5893 5894 SDValue Chain, Flag; 5895 5896 // We won't need to flush pending loads if this asm doesn't touch 5897 // memory and is nonvolatile. 5898 if (hasMemory || IA->hasSideEffects()) 5899 Chain = getRoot(); 5900 else 5901 Chain = DAG.getRoot(); 5902 5903 // Second pass over the constraints: compute which constraint option to use 5904 // and assign registers to constraints that want a specific physreg. 5905 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5906 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5907 5908 // If this is an output operand with a matching input operand, look up the 5909 // matching input. If their types mismatch, e.g. one is an integer, the 5910 // other is floating point, or their sizes are different, flag it as an 5911 // error. 5912 if (OpInfo.hasMatchingInput()) { 5913 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput]; 5914 5915 if (OpInfo.ConstraintVT != Input.ConstraintVT) { 5916 std::pair<unsigned, const TargetRegisterClass*> MatchRC = 5917 TLI.getRegForInlineAsmConstraint(OpInfo.ConstraintCode, 5918 OpInfo.ConstraintVT); 5919 std::pair<unsigned, const TargetRegisterClass*> InputRC = 5920 TLI.getRegForInlineAsmConstraint(Input.ConstraintCode, 5921 Input.ConstraintVT); 5922 if ((OpInfo.ConstraintVT.isInteger() != 5923 Input.ConstraintVT.isInteger()) || 5924 (MatchRC.second != InputRC.second)) { 5925 report_fatal_error("Unsupported asm: input constraint" 5926 " with a matching output constraint of" 5927 " incompatible type!"); 5928 } 5929 Input.ConstraintVT = OpInfo.ConstraintVT; 5930 } 5931 } 5932 5933 // Compute the constraint code and ConstraintType to use. 5934 TLI.ComputeConstraintToUse(OpInfo, OpInfo.CallOperand, &DAG); 5935 5936 // If this is a memory input, and if the operand is not indirect, do what we 5937 // need to to provide an address for the memory input. 5938 if (OpInfo.ConstraintType == TargetLowering::C_Memory && 5939 !OpInfo.isIndirect) { 5940 assert((OpInfo.isMultipleAlternative || 5941 (OpInfo.Type == InlineAsm::isInput)) && 5942 "Can only indirectify direct input operands!"); 5943 5944 // Memory operands really want the address of the value. If we don't have 5945 // an indirect input, put it in the constpool if we can, otherwise spill 5946 // it to a stack slot. 5947 // TODO: This isn't quite right. We need to handle these according to 5948 // the addressing mode that the constraint wants. Also, this may take 5949 // an additional register for the computation and we don't want that 5950 // either. 5951 5952 // If the operand is a float, integer, or vector constant, spill to a 5953 // constant pool entry to get its address. 5954 const Value *OpVal = OpInfo.CallOperandVal; 5955 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) || 5956 isa<ConstantVector>(OpVal)) { 5957 OpInfo.CallOperand = DAG.getConstantPool(cast<Constant>(OpVal), 5958 TLI.getPointerTy()); 5959 } else { 5960 // Otherwise, create a stack slot and emit a store to it before the 5961 // asm. 5962 Type *Ty = OpVal->getType(); 5963 uint64_t TySize = TLI.getTargetData()->getTypeAllocSize(Ty); 5964 unsigned Align = TLI.getTargetData()->getPrefTypeAlignment(Ty); 5965 MachineFunction &MF = DAG.getMachineFunction(); 5966 int SSFI = MF.getFrameInfo()->CreateStackObject(TySize, Align, false); 5967 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getPointerTy()); 5968 Chain = DAG.getStore(Chain, getCurDebugLoc(), 5969 OpInfo.CallOperand, StackSlot, 5970 MachinePointerInfo::getFixedStack(SSFI), 5971 false, false, 0); 5972 OpInfo.CallOperand = StackSlot; 5973 } 5974 5975 // There is no longer a Value* corresponding to this operand. 5976 OpInfo.CallOperandVal = 0; 5977 5978 // It is now an indirect operand. 5979 OpInfo.isIndirect = true; 5980 } 5981 5982 // If this constraint is for a specific register, allocate it before 5983 // anything else. 5984 if (OpInfo.ConstraintType == TargetLowering::C_Register) 5985 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5986 InputRegs); 5987 } 5988 5989 // Second pass - Loop over all of the operands, assigning virtual or physregs 5990 // to register class operands. 5991 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 5992 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 5993 5994 // C_Register operands have already been allocated, Other/Memory don't need 5995 // to be. 5996 if (OpInfo.ConstraintType == TargetLowering::C_RegisterClass) 5997 GetRegistersForValue(DAG, TLI, getCurDebugLoc(), OpInfo, OutputRegs, 5998 InputRegs); 5999 } 6000 6001 // AsmNodeOperands - The operands for the ISD::INLINEASM node. 6002 std::vector<SDValue> AsmNodeOperands; 6003 AsmNodeOperands.push_back(SDValue()); // reserve space for input chain 6004 AsmNodeOperands.push_back( 6005 DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), 6006 TLI.getPointerTy())); 6007 6008 // If we have a !srcloc metadata node associated with it, we want to attach 6009 // this to the ultimately generated inline asm machineinstr. To do this, we 6010 // pass in the third operand as this (potentially null) inline asm MDNode. 6011 const MDNode *SrcLoc = CS.getInstruction()->getMetadata("srcloc"); 6012 AsmNodeOperands.push_back(DAG.getMDNode(SrcLoc)); 6013 6014 // Remember the HasSideEffect and AlignStack bits as operand 3. 6015 unsigned ExtraInfo = 0; 6016 if (IA->hasSideEffects()) 6017 ExtraInfo |= InlineAsm::Extra_HasSideEffects; 6018 if (IA->isAlignStack()) 6019 ExtraInfo |= InlineAsm::Extra_IsAlignStack; 6020 AsmNodeOperands.push_back(DAG.getTargetConstant(ExtraInfo, 6021 TLI.getPointerTy())); 6022 6023 // Loop over all of the inputs, copying the operand values into the 6024 // appropriate registers and processing the output regs. 6025 RegsForValue RetValRegs; 6026 6027 // IndirectStoresToEmit - The set of stores to emit after the inline asm node. 6028 std::vector<std::pair<RegsForValue, Value*> > IndirectStoresToEmit; 6029 6030 for (unsigned i = 0, e = ConstraintOperands.size(); i != e; ++i) { 6031 SDISelAsmOperandInfo &OpInfo = ConstraintOperands[i]; 6032 6033 switch (OpInfo.Type) { 6034 case InlineAsm::isOutput: { 6035 if (OpInfo.ConstraintType != TargetLowering::C_RegisterClass && 6036 OpInfo.ConstraintType != TargetLowering::C_Register) { 6037 // Memory output, or 'other' output (e.g. 'X' constraint). 6038 assert(OpInfo.isIndirect && "Memory output must be indirect operand"); 6039 6040 // Add information to the INLINEASM node to know about this output. 6041 unsigned OpFlags = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6042 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlags, 6043 TLI.getPointerTy())); 6044 AsmNodeOperands.push_back(OpInfo.CallOperand); 6045 break; 6046 } 6047 6048 // Otherwise, this is a register or register class output. 6049 6050 // Copy the output from the appropriate register. Find a register that 6051 // we can use. 6052 if (OpInfo.AssignedRegs.Regs.empty()) 6053 report_fatal_error("Couldn't allocate output reg for constraint '" + 6054 Twine(OpInfo.ConstraintCode) + "'!"); 6055 6056 // If this is an indirect operand, store through the pointer after the 6057 // asm. 6058 if (OpInfo.isIndirect) { 6059 IndirectStoresToEmit.push_back(std::make_pair(OpInfo.AssignedRegs, 6060 OpInfo.CallOperandVal)); 6061 } else { 6062 // This is the result value of the call. 6063 assert(!CS.getType()->isVoidTy() && "Bad inline asm!"); 6064 // Concatenate this output onto the outputs list. 6065 RetValRegs.append(OpInfo.AssignedRegs); 6066 } 6067 6068 // Add information to the INLINEASM node to know that this register is 6069 // set. 6070 OpInfo.AssignedRegs.AddInlineAsmOperands(OpInfo.isEarlyClobber ? 6071 InlineAsm::Kind_RegDefEarlyClobber : 6072 InlineAsm::Kind_RegDef, 6073 false, 6074 0, 6075 DAG, 6076 AsmNodeOperands); 6077 break; 6078 } 6079 case InlineAsm::isInput: { 6080 SDValue InOperandVal = OpInfo.CallOperand; 6081 6082 if (OpInfo.isMatchingInputConstraint()) { // Matching constraint? 6083 // If this is required to match an output register we have already set, 6084 // just use its register. 6085 unsigned OperandNo = OpInfo.getMatchedOperand(); 6086 6087 // Scan until we find the definition we already emitted of this operand. 6088 // When we find it, create a RegsForValue operand. 6089 unsigned CurOp = InlineAsm::Op_FirstOperand; 6090 for (; OperandNo; --OperandNo) { 6091 // Advance to the next operand. 6092 unsigned OpFlag = 6093 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6094 assert((InlineAsm::isRegDefKind(OpFlag) || 6095 InlineAsm::isRegDefEarlyClobberKind(OpFlag) || 6096 InlineAsm::isMemKind(OpFlag)) && "Skipped past definitions?"); 6097 CurOp += InlineAsm::getNumOperandRegisters(OpFlag)+1; 6098 } 6099 6100 unsigned OpFlag = 6101 cast<ConstantSDNode>(AsmNodeOperands[CurOp])->getZExtValue(); 6102 if (InlineAsm::isRegDefKind(OpFlag) || 6103 InlineAsm::isRegDefEarlyClobberKind(OpFlag)) { 6104 // Add (OpFlag&0xffff)>>3 registers to MatchedRegs. 6105 if (OpInfo.isIndirect) { 6106 // This happens on gcc/testsuite/gcc.dg/pr8788-1.c 6107 LLVMContext &Ctx = *DAG.getContext(); 6108 Ctx.emitError(CS.getInstruction(), "inline asm not supported yet:" 6109 " don't know how to handle tied " 6110 "indirect register inputs"); 6111 } 6112 6113 RegsForValue MatchedRegs; 6114 MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType()); 6115 EVT RegVT = AsmNodeOperands[CurOp+1].getValueType(); 6116 MatchedRegs.RegVTs.push_back(RegVT); 6117 MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo(); 6118 for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag); 6119 i != e; ++i) 6120 MatchedRegs.Regs.push_back 6121 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); 6122 6123 // Use the produced MatchedRegs object to 6124 MatchedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6125 Chain, &Flag); 6126 MatchedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, 6127 true, OpInfo.getMatchedOperand(), 6128 DAG, AsmNodeOperands); 6129 break; 6130 } 6131 6132 assert(InlineAsm::isMemKind(OpFlag) && "Unknown matching constraint!"); 6133 assert(InlineAsm::getNumOperandRegisters(OpFlag) == 1 && 6134 "Unexpected number of operands"); 6135 // Add information to the INLINEASM node to know about this input. 6136 // See InlineAsm.h isUseOperandTiedToDef. 6137 OpFlag = InlineAsm::getFlagWordForMatchingOp(OpFlag, 6138 OpInfo.getMatchedOperand()); 6139 AsmNodeOperands.push_back(DAG.getTargetConstant(OpFlag, 6140 TLI.getPointerTy())); 6141 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]); 6142 break; 6143 } 6144 6145 // Treat indirect 'X' constraint as memory. 6146 if (OpInfo.ConstraintType == TargetLowering::C_Other && 6147 OpInfo.isIndirect) 6148 OpInfo.ConstraintType = TargetLowering::C_Memory; 6149 6150 if (OpInfo.ConstraintType == TargetLowering::C_Other) { 6151 std::vector<SDValue> Ops; 6152 TLI.LowerAsmOperandForConstraint(InOperandVal, OpInfo.ConstraintCode, 6153 Ops, DAG); 6154 if (Ops.empty()) 6155 report_fatal_error("Invalid operand for inline asm constraint '" + 6156 Twine(OpInfo.ConstraintCode) + "'!"); 6157 6158 // Add information to the INLINEASM node to know about this input. 6159 unsigned ResOpType = 6160 InlineAsm::getFlagWord(InlineAsm::Kind_Imm, Ops.size()); 6161 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6162 TLI.getPointerTy())); 6163 AsmNodeOperands.insert(AsmNodeOperands.end(), Ops.begin(), Ops.end()); 6164 break; 6165 } 6166 6167 if (OpInfo.ConstraintType == TargetLowering::C_Memory) { 6168 assert(OpInfo.isIndirect && "Operand must be indirect to be a mem!"); 6169 assert(InOperandVal.getValueType() == TLI.getPointerTy() && 6170 "Memory operands expect pointer values"); 6171 6172 // Add information to the INLINEASM node to know about this input. 6173 unsigned ResOpType = InlineAsm::getFlagWord(InlineAsm::Kind_Mem, 1); 6174 AsmNodeOperands.push_back(DAG.getTargetConstant(ResOpType, 6175 TLI.getPointerTy())); 6176 AsmNodeOperands.push_back(InOperandVal); 6177 break; 6178 } 6179 6180 assert((OpInfo.ConstraintType == TargetLowering::C_RegisterClass || 6181 OpInfo.ConstraintType == TargetLowering::C_Register) && 6182 "Unknown constraint type!"); 6183 assert(!OpInfo.isIndirect && 6184 "Don't know how to handle indirect register inputs yet!"); 6185 6186 // Copy the input into the appropriate registers. 6187 if (OpInfo.AssignedRegs.Regs.empty()) 6188 report_fatal_error("Couldn't allocate input reg for constraint '" + 6189 Twine(OpInfo.ConstraintCode) + "'!"); 6190 6191 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal, DAG, getCurDebugLoc(), 6192 Chain, &Flag); 6193 6194 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_RegUse, false, 0, 6195 DAG, AsmNodeOperands); 6196 break; 6197 } 6198 case InlineAsm::isClobber: { 6199 // Add the clobbered value to the operand list, so that the register 6200 // allocator is aware that the physreg got clobbered. 6201 if (!OpInfo.AssignedRegs.Regs.empty()) 6202 OpInfo.AssignedRegs.AddInlineAsmOperands(InlineAsm::Kind_Clobber, 6203 false, 0, DAG, 6204 AsmNodeOperands); 6205 break; 6206 } 6207 } 6208 } 6209 6210 // Finish up input operands. Set the input chain and add the flag last. 6211 AsmNodeOperands[InlineAsm::Op_InputChain] = Chain; 6212 if (Flag.getNode()) AsmNodeOperands.push_back(Flag); 6213 6214 Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(), 6215 DAG.getVTList(MVT::Other, MVT::Glue), 6216 &AsmNodeOperands[0], AsmNodeOperands.size()); 6217 Flag = Chain.getValue(1); 6218 6219 // If this asm returns a register value, copy the result from that register 6220 // and set it as the value of the call. 6221 if (!RetValRegs.Regs.empty()) { 6222 SDValue Val = RetValRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6223 Chain, &Flag); 6224 6225 // FIXME: Why don't we do this for inline asms with MRVs? 6226 if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) { 6227 EVT ResultType = TLI.getValueType(CS.getType()); 6228 6229 // If any of the results of the inline asm is a vector, it may have the 6230 // wrong width/num elts. This can happen for register classes that can 6231 // contain multiple different value types. The preg or vreg allocated may 6232 // not have the same VT as was expected. Convert it to the right type 6233 // with bit_convert. 6234 if (ResultType != Val.getValueType() && Val.getValueType().isVector()) { 6235 Val = DAG.getNode(ISD::BITCAST, getCurDebugLoc(), 6236 ResultType, Val); 6237 6238 } else if (ResultType != Val.getValueType() && 6239 ResultType.isInteger() && Val.getValueType().isInteger()) { 6240 // If a result value was tied to an input value, the computed result may 6241 // have a wider width than the expected result. Extract the relevant 6242 // portion. 6243 Val = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), ResultType, Val); 6244 } 6245 6246 assert(ResultType == Val.getValueType() && "Asm result value mismatch!"); 6247 } 6248 6249 setValue(CS.getInstruction(), Val); 6250 // Don't need to use this as a chain in this case. 6251 if (!IA->hasSideEffects() && !hasMemory && IndirectStoresToEmit.empty()) 6252 return; 6253 } 6254 6255 std::vector<std::pair<SDValue, const Value *> > StoresToEmit; 6256 6257 // Process indirect outputs, first output all of the flagged copies out of 6258 // physregs. 6259 for (unsigned i = 0, e = IndirectStoresToEmit.size(); i != e; ++i) { 6260 RegsForValue &OutRegs = IndirectStoresToEmit[i].first; 6261 const Value *Ptr = IndirectStoresToEmit[i].second; 6262 SDValue OutVal = OutRegs.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), 6263 Chain, &Flag); 6264 StoresToEmit.push_back(std::make_pair(OutVal, Ptr)); 6265 } 6266 6267 // Emit the non-flagged stores from the physregs. 6268 SmallVector<SDValue, 8> OutChains; 6269 for (unsigned i = 0, e = StoresToEmit.size(); i != e; ++i) { 6270 SDValue Val = DAG.getStore(Chain, getCurDebugLoc(), 6271 StoresToEmit[i].first, 6272 getValue(StoresToEmit[i].second), 6273 MachinePointerInfo(StoresToEmit[i].second), 6274 false, false, 0); 6275 OutChains.push_back(Val); 6276 } 6277 6278 if (!OutChains.empty()) 6279 Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, 6280 &OutChains[0], OutChains.size()); 6281 6282 DAG.setRoot(Chain); 6283 } 6284 6285 void SelectionDAGBuilder::visitVAStart(const CallInst &I) { 6286 DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(), 6287 MVT::Other, getRoot(), 6288 getValue(I.getArgOperand(0)), 6289 DAG.getSrcValue(I.getArgOperand(0)))); 6290 } 6291 6292 void SelectionDAGBuilder::visitVAArg(const VAArgInst &I) { 6293 const TargetData &TD = *TLI.getTargetData(); 6294 SDValue V = DAG.getVAArg(TLI.getValueType(I.getType()), getCurDebugLoc(), 6295 getRoot(), getValue(I.getOperand(0)), 6296 DAG.getSrcValue(I.getOperand(0)), 6297 TD.getABITypeAlignment(I.getType())); 6298 setValue(&I, V); 6299 DAG.setRoot(V.getValue(1)); 6300 } 6301 6302 void SelectionDAGBuilder::visitVAEnd(const CallInst &I) { 6303 DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(), 6304 MVT::Other, getRoot(), 6305 getValue(I.getArgOperand(0)), 6306 DAG.getSrcValue(I.getArgOperand(0)))); 6307 } 6308 6309 void SelectionDAGBuilder::visitVACopy(const CallInst &I) { 6310 DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(), 6311 MVT::Other, getRoot(), 6312 getValue(I.getArgOperand(0)), 6313 getValue(I.getArgOperand(1)), 6314 DAG.getSrcValue(I.getArgOperand(0)), 6315 DAG.getSrcValue(I.getArgOperand(1)))); 6316 } 6317 6318 /// TargetLowering::LowerCallTo - This is the default LowerCallTo 6319 /// implementation, which just calls LowerCall. 6320 /// FIXME: When all targets are 6321 /// migrated to using LowerCall, this hook should be integrated into SDISel. 6322 std::pair<SDValue, SDValue> 6323 TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy, 6324 bool RetSExt, bool RetZExt, bool isVarArg, 6325 bool isInreg, unsigned NumFixedArgs, 6326 CallingConv::ID CallConv, bool isTailCall, 6327 bool isReturnValueUsed, 6328 SDValue Callee, 6329 ArgListTy &Args, SelectionDAG &DAG, 6330 DebugLoc dl) const { 6331 // Handle all of the outgoing arguments. 6332 SmallVector<ISD::OutputArg, 32> Outs; 6333 SmallVector<SDValue, 32> OutVals; 6334 for (unsigned i = 0, e = Args.size(); i != e; ++i) { 6335 SmallVector<EVT, 4> ValueVTs; 6336 ComputeValueVTs(*this, Args[i].Ty, ValueVTs); 6337 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6338 Value != NumValues; ++Value) { 6339 EVT VT = ValueVTs[Value]; 6340 Type *ArgTy = VT.getTypeForEVT(RetTy->getContext()); 6341 SDValue Op = SDValue(Args[i].Node.getNode(), 6342 Args[i].Node.getResNo() + Value); 6343 ISD::ArgFlagsTy Flags; 6344 unsigned OriginalAlignment = 6345 getTargetData()->getABITypeAlignment(ArgTy); 6346 6347 if (Args[i].isZExt) 6348 Flags.setZExt(); 6349 if (Args[i].isSExt) 6350 Flags.setSExt(); 6351 if (Args[i].isInReg) 6352 Flags.setInReg(); 6353 if (Args[i].isSRet) 6354 Flags.setSRet(); 6355 if (Args[i].isByVal) { 6356 Flags.setByVal(); 6357 PointerType *Ty = cast<PointerType>(Args[i].Ty); 6358 Type *ElementTy = Ty->getElementType(); 6359 Flags.setByValSize(getTargetData()->getTypeAllocSize(ElementTy)); 6360 // For ByVal, alignment should come from FE. BE will guess if this 6361 // info is not there but there are cases it cannot get right. 6362 unsigned FrameAlign; 6363 if (Args[i].Alignment) 6364 FrameAlign = Args[i].Alignment; 6365 else 6366 FrameAlign = getByValTypeAlignment(ElementTy); 6367 Flags.setByValAlign(FrameAlign); 6368 } 6369 if (Args[i].isNest) 6370 Flags.setNest(); 6371 Flags.setOrigAlign(OriginalAlignment); 6372 6373 EVT PartVT = getRegisterType(RetTy->getContext(), VT); 6374 unsigned NumParts = getNumRegisters(RetTy->getContext(), VT); 6375 SmallVector<SDValue, 4> Parts(NumParts); 6376 ISD::NodeType ExtendKind = ISD::ANY_EXTEND; 6377 6378 if (Args[i].isSExt) 6379 ExtendKind = ISD::SIGN_EXTEND; 6380 else if (Args[i].isZExt) 6381 ExtendKind = ISD::ZERO_EXTEND; 6382 6383 getCopyToParts(DAG, dl, Op, &Parts[0], NumParts, 6384 PartVT, ExtendKind); 6385 6386 for (unsigned j = 0; j != NumParts; ++j) { 6387 // if it isn't first piece, alignment must be 1 6388 ISD::OutputArg MyFlags(Flags, Parts[j].getValueType(), 6389 i < NumFixedArgs); 6390 if (NumParts > 1 && j == 0) 6391 MyFlags.Flags.setSplit(); 6392 else if (j != 0) 6393 MyFlags.Flags.setOrigAlign(1); 6394 6395 Outs.push_back(MyFlags); 6396 OutVals.push_back(Parts[j]); 6397 } 6398 } 6399 } 6400 6401 // Handle the incoming return values from the call. 6402 SmallVector<ISD::InputArg, 32> Ins; 6403 SmallVector<EVT, 4> RetTys; 6404 ComputeValueVTs(*this, RetTy, RetTys); 6405 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6406 EVT VT = RetTys[I]; 6407 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6408 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6409 for (unsigned i = 0; i != NumRegs; ++i) { 6410 ISD::InputArg MyFlags; 6411 MyFlags.VT = RegisterVT.getSimpleVT(); 6412 MyFlags.Used = isReturnValueUsed; 6413 if (RetSExt) 6414 MyFlags.Flags.setSExt(); 6415 if (RetZExt) 6416 MyFlags.Flags.setZExt(); 6417 if (isInreg) 6418 MyFlags.Flags.setInReg(); 6419 Ins.push_back(MyFlags); 6420 } 6421 } 6422 6423 SmallVector<SDValue, 4> InVals; 6424 Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall, 6425 Outs, OutVals, Ins, dl, DAG, InVals); 6426 6427 // Verify that the target's LowerCall behaved as expected. 6428 assert(Chain.getNode() && Chain.getValueType() == MVT::Other && 6429 "LowerCall didn't return a valid chain!"); 6430 assert((!isTailCall || InVals.empty()) && 6431 "LowerCall emitted a return value for a tail call!"); 6432 assert((isTailCall || InVals.size() == Ins.size()) && 6433 "LowerCall didn't emit the correct number of values!"); 6434 6435 // For a tail call, the return value is merely live-out and there aren't 6436 // any nodes in the DAG representing it. Return a special value to 6437 // indicate that a tail call has been emitted and no more Instructions 6438 // should be processed in the current block. 6439 if (isTailCall) { 6440 DAG.setRoot(Chain); 6441 return std::make_pair(SDValue(), SDValue()); 6442 } 6443 6444 DEBUG(for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6445 assert(InVals[i].getNode() && 6446 "LowerCall emitted a null value!"); 6447 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6448 "LowerCall emitted a value with the wrong type!"); 6449 }); 6450 6451 // Collect the legal value parts into potentially illegal values 6452 // that correspond to the original function's return values. 6453 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6454 if (RetSExt) 6455 AssertOp = ISD::AssertSext; 6456 else if (RetZExt) 6457 AssertOp = ISD::AssertZext; 6458 SmallVector<SDValue, 4> ReturnValues; 6459 unsigned CurReg = 0; 6460 for (unsigned I = 0, E = RetTys.size(); I != E; ++I) { 6461 EVT VT = RetTys[I]; 6462 EVT RegisterVT = getRegisterType(RetTy->getContext(), VT); 6463 unsigned NumRegs = getNumRegisters(RetTy->getContext(), VT); 6464 6465 ReturnValues.push_back(getCopyFromParts(DAG, dl, &InVals[CurReg], 6466 NumRegs, RegisterVT, VT, 6467 AssertOp)); 6468 CurReg += NumRegs; 6469 } 6470 6471 // For a function returning void, there is no return value. We can't create 6472 // such a node, so we just return a null return value in that case. In 6473 // that case, nothing will actually look at the value. 6474 if (ReturnValues.empty()) 6475 return std::make_pair(SDValue(), Chain); 6476 6477 SDValue Res = DAG.getNode(ISD::MERGE_VALUES, dl, 6478 DAG.getVTList(&RetTys[0], RetTys.size()), 6479 &ReturnValues[0], ReturnValues.size()); 6480 return std::make_pair(Res, Chain); 6481 } 6482 6483 void TargetLowering::LowerOperationWrapper(SDNode *N, 6484 SmallVectorImpl<SDValue> &Results, 6485 SelectionDAG &DAG) const { 6486 SDValue Res = LowerOperation(SDValue(N, 0), DAG); 6487 if (Res.getNode()) 6488 Results.push_back(Res); 6489 } 6490 6491 SDValue TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { 6492 llvm_unreachable("LowerOperation not implemented for this target!"); 6493 return SDValue(); 6494 } 6495 6496 void 6497 SelectionDAGBuilder::CopyValueToVirtualRegister(const Value *V, unsigned Reg) { 6498 SDValue Op = getNonRegisterValue(V); 6499 assert((Op.getOpcode() != ISD::CopyFromReg || 6500 cast<RegisterSDNode>(Op.getOperand(1))->getReg() != Reg) && 6501 "Copy from a reg to the same reg!"); 6502 assert(!TargetRegisterInfo::isPhysicalRegister(Reg) && "Is a physreg"); 6503 6504 RegsForValue RFV(V->getContext(), TLI, Reg, V->getType()); 6505 SDValue Chain = DAG.getEntryNode(); 6506 RFV.getCopyToRegs(Op, DAG, getCurDebugLoc(), Chain, 0); 6507 PendingExports.push_back(Chain); 6508 } 6509 6510 #include "llvm/CodeGen/SelectionDAGISel.h" 6511 6512 /// isOnlyUsedInEntryBlock - If the specified argument is only used in the 6513 /// entry block, return true. This includes arguments used by switches, since 6514 /// the switch may expand into multiple basic blocks. 6515 static bool isOnlyUsedInEntryBlock(const Argument *A) { 6516 // With FastISel active, we may be splitting blocks, so force creation 6517 // of virtual registers for all non-dead arguments. 6518 if (EnableFastISel) 6519 return A->use_empty(); 6520 6521 const BasicBlock *Entry = A->getParent()->begin(); 6522 for (Value::const_use_iterator UI = A->use_begin(), E = A->use_end(); 6523 UI != E; ++UI) { 6524 const User *U = *UI; 6525 if (cast<Instruction>(U)->getParent() != Entry || isa<SwitchInst>(U)) 6526 return false; // Use not in entry block. 6527 } 6528 return true; 6529 } 6530 6531 void SelectionDAGISel::LowerArguments(const BasicBlock *LLVMBB) { 6532 // If this is the entry block, emit arguments. 6533 const Function &F = *LLVMBB->getParent(); 6534 SelectionDAG &DAG = SDB->DAG; 6535 DebugLoc dl = SDB->getCurDebugLoc(); 6536 const TargetData *TD = TLI.getTargetData(); 6537 SmallVector<ISD::InputArg, 16> Ins; 6538 6539 // Check whether the function can return without sret-demotion. 6540 SmallVector<ISD::OutputArg, 4> Outs; 6541 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(), 6542 Outs, TLI); 6543 6544 if (!FuncInfo->CanLowerReturn) { 6545 // Put in an sret pointer parameter before all the other parameters. 6546 SmallVector<EVT, 1> ValueVTs; 6547 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6548 6549 // NOTE: Assuming that a pointer will never break down to more than one VT 6550 // or one register. 6551 ISD::ArgFlagsTy Flags; 6552 Flags.setSRet(); 6553 EVT RegisterVT = TLI.getRegisterType(*DAG.getContext(), ValueVTs[0]); 6554 ISD::InputArg RetArg(Flags, RegisterVT, true); 6555 Ins.push_back(RetArg); 6556 } 6557 6558 // Set up the incoming argument description vector. 6559 unsigned Idx = 1; 6560 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); 6561 I != E; ++I, ++Idx) { 6562 SmallVector<EVT, 4> ValueVTs; 6563 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6564 bool isArgValueUsed = !I->use_empty(); 6565 for (unsigned Value = 0, NumValues = ValueVTs.size(); 6566 Value != NumValues; ++Value) { 6567 EVT VT = ValueVTs[Value]; 6568 Type *ArgTy = VT.getTypeForEVT(*DAG.getContext()); 6569 ISD::ArgFlagsTy Flags; 6570 unsigned OriginalAlignment = 6571 TD->getABITypeAlignment(ArgTy); 6572 6573 if (F.paramHasAttr(Idx, Attribute::ZExt)) 6574 Flags.setZExt(); 6575 if (F.paramHasAttr(Idx, Attribute::SExt)) 6576 Flags.setSExt(); 6577 if (F.paramHasAttr(Idx, Attribute::InReg)) 6578 Flags.setInReg(); 6579 if (F.paramHasAttr(Idx, Attribute::StructRet)) 6580 Flags.setSRet(); 6581 if (F.paramHasAttr(Idx, Attribute::ByVal)) { 6582 Flags.setByVal(); 6583 PointerType *Ty = cast<PointerType>(I->getType()); 6584 Type *ElementTy = Ty->getElementType(); 6585 Flags.setByValSize(TD->getTypeAllocSize(ElementTy)); 6586 // For ByVal, alignment should be passed from FE. BE will guess if 6587 // this info is not there but there are cases it cannot get right. 6588 unsigned FrameAlign; 6589 if (F.getParamAlignment(Idx)) 6590 FrameAlign = F.getParamAlignment(Idx); 6591 else 6592 FrameAlign = TLI.getByValTypeAlignment(ElementTy); 6593 Flags.setByValAlign(FrameAlign); 6594 } 6595 if (F.paramHasAttr(Idx, Attribute::Nest)) 6596 Flags.setNest(); 6597 Flags.setOrigAlign(OriginalAlignment); 6598 6599 EVT RegisterVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6600 unsigned NumRegs = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6601 for (unsigned i = 0; i != NumRegs; ++i) { 6602 ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed); 6603 if (NumRegs > 1 && i == 0) 6604 MyFlags.Flags.setSplit(); 6605 // if it isn't first piece, alignment must be 1 6606 else if (i > 0) 6607 MyFlags.Flags.setOrigAlign(1); 6608 Ins.push_back(MyFlags); 6609 } 6610 } 6611 } 6612 6613 // Call the target to set up the argument values. 6614 SmallVector<SDValue, 8> InVals; 6615 SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(), F.getCallingConv(), 6616 F.isVarArg(), Ins, 6617 dl, DAG, InVals); 6618 6619 // Verify that the target's LowerFormalArguments behaved as expected. 6620 assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other && 6621 "LowerFormalArguments didn't return a valid chain!"); 6622 assert(InVals.size() == Ins.size() && 6623 "LowerFormalArguments didn't emit the correct number of values!"); 6624 DEBUG({ 6625 for (unsigned i = 0, e = Ins.size(); i != e; ++i) { 6626 assert(InVals[i].getNode() && 6627 "LowerFormalArguments emitted a null value!"); 6628 assert(EVT(Ins[i].VT) == InVals[i].getValueType() && 6629 "LowerFormalArguments emitted a value with the wrong type!"); 6630 } 6631 }); 6632 6633 // Update the DAG with the new chain value resulting from argument lowering. 6634 DAG.setRoot(NewRoot); 6635 6636 // Set up the argument values. 6637 unsigned i = 0; 6638 Idx = 1; 6639 if (!FuncInfo->CanLowerReturn) { 6640 // Create a virtual register for the sret pointer, and put in a copy 6641 // from the sret argument into it. 6642 SmallVector<EVT, 1> ValueVTs; 6643 ComputeValueVTs(TLI, PointerType::getUnqual(F.getReturnType()), ValueVTs); 6644 EVT VT = ValueVTs[0]; 6645 EVT RegVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6646 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6647 SDValue ArgValue = getCopyFromParts(DAG, dl, &InVals[0], 1, 6648 RegVT, VT, AssertOp); 6649 6650 MachineFunction& MF = SDB->DAG.getMachineFunction(); 6651 MachineRegisterInfo& RegInfo = MF.getRegInfo(); 6652 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); 6653 FuncInfo->DemoteRegister = SRetReg; 6654 NewRoot = SDB->DAG.getCopyToReg(NewRoot, SDB->getCurDebugLoc(), 6655 SRetReg, ArgValue); 6656 DAG.setRoot(NewRoot); 6657 6658 // i indexes lowered arguments. Bump it past the hidden sret argument. 6659 // Idx indexes LLVM arguments. Don't touch it. 6660 ++i; 6661 } 6662 6663 for (Function::const_arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E; 6664 ++I, ++Idx) { 6665 SmallVector<SDValue, 4> ArgValues; 6666 SmallVector<EVT, 4> ValueVTs; 6667 ComputeValueVTs(TLI, I->getType(), ValueVTs); 6668 unsigned NumValues = ValueVTs.size(); 6669 6670 // If this argument is unused then remember its value. It is used to generate 6671 // debugging information. 6672 if (I->use_empty() && NumValues) 6673 SDB->setUnusedArgValue(I, InVals[i]); 6674 6675 for (unsigned Val = 0; Val != NumValues; ++Val) { 6676 EVT VT = ValueVTs[Val]; 6677 EVT PartVT = TLI.getRegisterType(*CurDAG->getContext(), VT); 6678 unsigned NumParts = TLI.getNumRegisters(*CurDAG->getContext(), VT); 6679 6680 if (!I->use_empty()) { 6681 ISD::NodeType AssertOp = ISD::DELETED_NODE; 6682 if (F.paramHasAttr(Idx, Attribute::SExt)) 6683 AssertOp = ISD::AssertSext; 6684 else if (F.paramHasAttr(Idx, Attribute::ZExt)) 6685 AssertOp = ISD::AssertZext; 6686 6687 ArgValues.push_back(getCopyFromParts(DAG, dl, &InVals[i], 6688 NumParts, PartVT, VT, 6689 AssertOp)); 6690 } 6691 6692 i += NumParts; 6693 } 6694 6695 // We don't need to do anything else for unused arguments. 6696 if (ArgValues.empty()) 6697 continue; 6698 6699 // Note down frame index. 6700 if (FrameIndexSDNode *FI = 6701 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode())) 6702 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6703 6704 SDValue Res = DAG.getMergeValues(&ArgValues[0], NumValues, 6705 SDB->getCurDebugLoc()); 6706 6707 SDB->setValue(I, Res); 6708 if (!EnableFastISel && Res.getOpcode() == ISD::BUILD_PAIR) { 6709 if (LoadSDNode *LNode = 6710 dyn_cast<LoadSDNode>(Res.getOperand(0).getNode())) 6711 if (FrameIndexSDNode *FI = 6712 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode())) 6713 FuncInfo->setArgumentFrameIndex(I, FI->getIndex()); 6714 } 6715 6716 // If this argument is live outside of the entry block, insert a copy from 6717 // wherever we got it to the vreg that other BB's will reference it as. 6718 if (!EnableFastISel && Res.getOpcode() == ISD::CopyFromReg) { 6719 // If we can, though, try to skip creating an unnecessary vreg. 6720 // FIXME: This isn't very clean... it would be nice to make this more 6721 // general. It's also subtly incompatible with the hacks FastISel 6722 // uses with vregs. 6723 unsigned Reg = cast<RegisterSDNode>(Res.getOperand(1))->getReg(); 6724 if (TargetRegisterInfo::isVirtualRegister(Reg)) { 6725 FuncInfo->ValueMap[I] = Reg; 6726 continue; 6727 } 6728 } 6729 if (!isOnlyUsedInEntryBlock(I)) { 6730 FuncInfo->InitializeRegForValue(I); 6731 SDB->CopyToExportRegsIfNeeded(I); 6732 } 6733 } 6734 6735 assert(i == InVals.size() && "Argument register count mismatch!"); 6736 6737 // Finally, if the target has anything special to do, allow it to do so. 6738 // FIXME: this should insert code into the DAG! 6739 EmitFunctionEntryCode(); 6740 } 6741 6742 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to 6743 /// ensure constants are generated when needed. Remember the virtual registers 6744 /// that need to be added to the Machine PHI nodes as input. We cannot just 6745 /// directly add them, because expansion might result in multiple MBB's for one 6746 /// BB. As such, the start of the BB might correspond to a different MBB than 6747 /// the end. 6748 /// 6749 void 6750 SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(const BasicBlock *LLVMBB) { 6751 const TerminatorInst *TI = LLVMBB->getTerminator(); 6752 6753 SmallPtrSet<MachineBasicBlock *, 4> SuccsHandled; 6754 6755 // Check successor nodes' PHI nodes that expect a constant to be available 6756 // from this block. 6757 for (unsigned succ = 0, e = TI->getNumSuccessors(); succ != e; ++succ) { 6758 const BasicBlock *SuccBB = TI->getSuccessor(succ); 6759 if (!isa<PHINode>(SuccBB->begin())) continue; 6760 MachineBasicBlock *SuccMBB = FuncInfo.MBBMap[SuccBB]; 6761 6762 // If this terminator has multiple identical successors (common for 6763 // switches), only handle each succ once. 6764 if (!SuccsHandled.insert(SuccMBB)) continue; 6765 6766 MachineBasicBlock::iterator MBBI = SuccMBB->begin(); 6767 6768 // At this point we know that there is a 1-1 correspondence between LLVM PHI 6769 // nodes and Machine PHI nodes, but the incoming operands have not been 6770 // emitted yet. 6771 for (BasicBlock::const_iterator I = SuccBB->begin(); 6772 const PHINode *PN = dyn_cast<PHINode>(I); ++I) { 6773 // Ignore dead phi's. 6774 if (PN->use_empty()) continue; 6775 6776 // Skip empty types 6777 if (PN->getType()->isEmptyTy()) 6778 continue; 6779 6780 unsigned Reg; 6781 const Value *PHIOp = PN->getIncomingValueForBlock(LLVMBB); 6782 6783 if (const Constant *C = dyn_cast<Constant>(PHIOp)) { 6784 unsigned &RegOut = ConstantsOut[C]; 6785 if (RegOut == 0) { 6786 RegOut = FuncInfo.CreateRegs(C->getType()); 6787 CopyValueToVirtualRegister(C, RegOut); 6788 } 6789 Reg = RegOut; 6790 } else { 6791 DenseMap<const Value *, unsigned>::iterator I = 6792 FuncInfo.ValueMap.find(PHIOp); 6793 if (I != FuncInfo.ValueMap.end()) 6794 Reg = I->second; 6795 else { 6796 assert(isa<AllocaInst>(PHIOp) && 6797 FuncInfo.StaticAllocaMap.count(cast<AllocaInst>(PHIOp)) && 6798 "Didn't codegen value into a register!??"); 6799 Reg = FuncInfo.CreateRegs(PHIOp->getType()); 6800 CopyValueToVirtualRegister(PHIOp, Reg); 6801 } 6802 } 6803 6804 // Remember that this register needs to added to the machine PHI node as 6805 // the input for this MBB. 6806 SmallVector<EVT, 4> ValueVTs; 6807 ComputeValueVTs(TLI, PN->getType(), ValueVTs); 6808 for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) { 6809 EVT VT = ValueVTs[vti]; 6810 unsigned NumRegisters = TLI.getNumRegisters(*DAG.getContext(), VT); 6811 for (unsigned i = 0, e = NumRegisters; i != e; ++i) 6812 FuncInfo.PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i)); 6813 Reg += NumRegisters; 6814 } 6815 } 6816 } 6817 ConstantsOut.clear(); 6818 } 6819