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      1 //===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
      2 //
      3 //                     The LLVM Compiler Infrastructure
      4 //
      5 // This file is distributed under the University of Illinois Open Source
      6 // License. See LICENSE.TXT for details.
      7 //
      8 //===----------------------------------------------------------------------===//
      9 //
     10 // This file contains the X86 implementation of the TargetInstrInfo class.
     11 //
     12 //===----------------------------------------------------------------------===//
     13 
     14 #include "X86InstrInfo.h"
     15 #include "X86.h"
     16 #include "X86InstrBuilder.h"
     17 #include "X86MachineFunctionInfo.h"
     18 #include "X86Subtarget.h"
     19 #include "X86TargetMachine.h"
     20 #include "llvm/ADT/STLExtras.h"
     21 #include "llvm/CodeGen/LiveVariables.h"
     22 #include "llvm/CodeGen/MachineConstantPool.h"
     23 #include "llvm/CodeGen/MachineDominators.h"
     24 #include "llvm/CodeGen/MachineFrameInfo.h"
     25 #include "llvm/CodeGen/MachineInstrBuilder.h"
     26 #include "llvm/CodeGen/MachineModuleInfo.h"
     27 #include "llvm/CodeGen/MachineRegisterInfo.h"
     28 #include "llvm/CodeGen/StackMaps.h"
     29 #include "llvm/IR/DerivedTypes.h"
     30 #include "llvm/IR/Function.h"
     31 #include "llvm/IR/LLVMContext.h"
     32 #include "llvm/MC/MCAsmInfo.h"
     33 #include "llvm/MC/MCExpr.h"
     34 #include "llvm/MC/MCInst.h"
     35 #include "llvm/Support/CommandLine.h"
     36 #include "llvm/Support/Debug.h"
     37 #include "llvm/Support/ErrorHandling.h"
     38 #include "llvm/Support/raw_ostream.h"
     39 #include "llvm/Target/TargetOptions.h"
     40 #include <limits>
     41 
     42 using namespace llvm;
     43 
     44 #define DEBUG_TYPE "x86-instr-info"
     45 
     46 #define GET_INSTRINFO_CTOR_DTOR
     47 #include "X86GenInstrInfo.inc"
     48 
     49 static cl::opt<bool>
     50 NoFusing("disable-spill-fusing",
     51          cl::desc("Disable fusing of spill code into instructions"));
     52 static cl::opt<bool>
     53 PrintFailedFusing("print-failed-fuse-candidates",
     54                   cl::desc("Print instructions that the allocator wants to"
     55                            " fuse, but the X86 backend currently can't"),
     56                   cl::Hidden);
     57 static cl::opt<bool>
     58 ReMatPICStubLoad("remat-pic-stub-load",
     59                  cl::desc("Re-materialize load from stub in PIC mode"),
     60                  cl::init(false), cl::Hidden);
     61 
     62 enum {
     63   // Select which memory operand is being unfolded.
     64   // (stored in bits 0 - 3)
     65   TB_INDEX_0    = 0,
     66   TB_INDEX_1    = 1,
     67   TB_INDEX_2    = 2,
     68   TB_INDEX_3    = 3,
     69   TB_INDEX_4    = 4,
     70   TB_INDEX_MASK = 0xf,
     71 
     72   // Do not insert the reverse map (MemOp -> RegOp) into the table.
     73   // This may be needed because there is a many -> one mapping.
     74   TB_NO_REVERSE   = 1 << 4,
     75 
     76   // Do not insert the forward map (RegOp -> MemOp) into the table.
     77   // This is needed for Native Client, which prohibits branch
     78   // instructions from using a memory operand.
     79   TB_NO_FORWARD   = 1 << 5,
     80 
     81   TB_FOLDED_LOAD  = 1 << 6,
     82   TB_FOLDED_STORE = 1 << 7,
     83 
     84   // Minimum alignment required for load/store.
     85   // Used for RegOp->MemOp conversion.
     86   // (stored in bits 8 - 15)
     87   TB_ALIGN_SHIFT = 8,
     88   TB_ALIGN_NONE  =    0 << TB_ALIGN_SHIFT,
     89   TB_ALIGN_16    =   16 << TB_ALIGN_SHIFT,
     90   TB_ALIGN_32    =   32 << TB_ALIGN_SHIFT,
     91   TB_ALIGN_64    =   64 << TB_ALIGN_SHIFT,
     92   TB_ALIGN_MASK  = 0xff << TB_ALIGN_SHIFT
     93 };
     94 
     95 struct X86MemoryFoldTableEntry {
     96   uint16_t RegOp;
     97   uint16_t MemOp;
     98   uint16_t Flags;
     99 };
    100 
    101 // Pin the vtable to this file.
    102 void X86InstrInfo::anchor() {}
    103 
    104 X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
    105     : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
    106                                                : X86::ADJCALLSTACKDOWN32),
    107                       (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
    108                                                : X86::ADJCALLSTACKUP32),
    109                       X86::CATCHRET),
    110       Subtarget(STI), RI(STI.getTargetTriple()) {
    111 
    112   static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
    113     { X86::ADC32ri,     X86::ADC32mi,    0 },
    114     { X86::ADC32ri8,    X86::ADC32mi8,   0 },
    115     { X86::ADC32rr,     X86::ADC32mr,    0 },
    116     { X86::ADC64ri32,   X86::ADC64mi32,  0 },
    117     { X86::ADC64ri8,    X86::ADC64mi8,   0 },
    118     { X86::ADC64rr,     X86::ADC64mr,    0 },
    119     { X86::ADD16ri,     X86::ADD16mi,    0 },
    120     { X86::ADD16ri8,    X86::ADD16mi8,   0 },
    121     { X86::ADD16ri_DB,  X86::ADD16mi,    TB_NO_REVERSE },
    122     { X86::ADD16ri8_DB, X86::ADD16mi8,   TB_NO_REVERSE },
    123     { X86::ADD16rr,     X86::ADD16mr,    0 },
    124     { X86::ADD16rr_DB,  X86::ADD16mr,    TB_NO_REVERSE },
    125     { X86::ADD32ri,     X86::ADD32mi,    0 },
    126     { X86::ADD32ri8,    X86::ADD32mi8,   0 },
    127     { X86::ADD32ri_DB,  X86::ADD32mi,    TB_NO_REVERSE },
    128     { X86::ADD32ri8_DB, X86::ADD32mi8,   TB_NO_REVERSE },
    129     { X86::ADD32rr,     X86::ADD32mr,    0 },
    130     { X86::ADD32rr_DB,  X86::ADD32mr,    TB_NO_REVERSE },
    131     { X86::ADD64ri32,   X86::ADD64mi32,  0 },
    132     { X86::ADD64ri8,    X86::ADD64mi8,   0 },
    133     { X86::ADD64ri32_DB,X86::ADD64mi32,  TB_NO_REVERSE },
    134     { X86::ADD64ri8_DB, X86::ADD64mi8,   TB_NO_REVERSE },
    135     { X86::ADD64rr,     X86::ADD64mr,    0 },
    136     { X86::ADD64rr_DB,  X86::ADD64mr,    TB_NO_REVERSE },
    137     { X86::ADD8ri,      X86::ADD8mi,     0 },
    138     { X86::ADD8rr,      X86::ADD8mr,     0 },
    139     { X86::AND16ri,     X86::AND16mi,    0 },
    140     { X86::AND16ri8,    X86::AND16mi8,   0 },
    141     { X86::AND16rr,     X86::AND16mr,    0 },
    142     { X86::AND32ri,     X86::AND32mi,    0 },
    143     { X86::AND32ri8,    X86::AND32mi8,   0 },
    144     { X86::AND32rr,     X86::AND32mr,    0 },
    145     { X86::AND64ri32,   X86::AND64mi32,  0 },
    146     { X86::AND64ri8,    X86::AND64mi8,   0 },
    147     { X86::AND64rr,     X86::AND64mr,    0 },
    148     { X86::AND8ri,      X86::AND8mi,     0 },
    149     { X86::AND8rr,      X86::AND8mr,     0 },
    150     { X86::DEC16r,      X86::DEC16m,     0 },
    151     { X86::DEC32r,      X86::DEC32m,     0 },
    152     { X86::DEC64r,      X86::DEC64m,     0 },
    153     { X86::DEC8r,       X86::DEC8m,      0 },
    154     { X86::INC16r,      X86::INC16m,     0 },
    155     { X86::INC32r,      X86::INC32m,     0 },
    156     { X86::INC64r,      X86::INC64m,     0 },
    157     { X86::INC8r,       X86::INC8m,      0 },
    158     { X86::NEG16r,      X86::NEG16m,     0 },
    159     { X86::NEG32r,      X86::NEG32m,     0 },
    160     { X86::NEG64r,      X86::NEG64m,     0 },
    161     { X86::NEG8r,       X86::NEG8m,      0 },
    162     { X86::NOT16r,      X86::NOT16m,     0 },
    163     { X86::NOT32r,      X86::NOT32m,     0 },
    164     { X86::NOT64r,      X86::NOT64m,     0 },
    165     { X86::NOT8r,       X86::NOT8m,      0 },
    166     { X86::OR16ri,      X86::OR16mi,     0 },
    167     { X86::OR16ri8,     X86::OR16mi8,    0 },
    168     { X86::OR16rr,      X86::OR16mr,     0 },
    169     { X86::OR32ri,      X86::OR32mi,     0 },
    170     { X86::OR32ri8,     X86::OR32mi8,    0 },
    171     { X86::OR32rr,      X86::OR32mr,     0 },
    172     { X86::OR64ri32,    X86::OR64mi32,   0 },
    173     { X86::OR64ri8,     X86::OR64mi8,    0 },
    174     { X86::OR64rr,      X86::OR64mr,     0 },
    175     { X86::OR8ri,       X86::OR8mi,      0 },
    176     { X86::OR8rr,       X86::OR8mr,      0 },
    177     { X86::ROL16r1,     X86::ROL16m1,    0 },
    178     { X86::ROL16rCL,    X86::ROL16mCL,   0 },
    179     { X86::ROL16ri,     X86::ROL16mi,    0 },
    180     { X86::ROL32r1,     X86::ROL32m1,    0 },
    181     { X86::ROL32rCL,    X86::ROL32mCL,   0 },
    182     { X86::ROL32ri,     X86::ROL32mi,    0 },
    183     { X86::ROL64r1,     X86::ROL64m1,    0 },
    184     { X86::ROL64rCL,    X86::ROL64mCL,   0 },
    185     { X86::ROL64ri,     X86::ROL64mi,    0 },
    186     { X86::ROL8r1,      X86::ROL8m1,     0 },
    187     { X86::ROL8rCL,     X86::ROL8mCL,    0 },
    188     { X86::ROL8ri,      X86::ROL8mi,     0 },
    189     { X86::ROR16r1,     X86::ROR16m1,    0 },
    190     { X86::ROR16rCL,    X86::ROR16mCL,   0 },
    191     { X86::ROR16ri,     X86::ROR16mi,    0 },
    192     { X86::ROR32r1,     X86::ROR32m1,    0 },
    193     { X86::ROR32rCL,    X86::ROR32mCL,   0 },
    194     { X86::ROR32ri,     X86::ROR32mi,    0 },
    195     { X86::ROR64r1,     X86::ROR64m1,    0 },
    196     { X86::ROR64rCL,    X86::ROR64mCL,   0 },
    197     { X86::ROR64ri,     X86::ROR64mi,    0 },
    198     { X86::ROR8r1,      X86::ROR8m1,     0 },
    199     { X86::ROR8rCL,     X86::ROR8mCL,    0 },
    200     { X86::ROR8ri,      X86::ROR8mi,     0 },
    201     { X86::SAR16r1,     X86::SAR16m1,    0 },
    202     { X86::SAR16rCL,    X86::SAR16mCL,   0 },
    203     { X86::SAR16ri,     X86::SAR16mi,    0 },
    204     { X86::SAR32r1,     X86::SAR32m1,    0 },
    205     { X86::SAR32rCL,    X86::SAR32mCL,   0 },
    206     { X86::SAR32ri,     X86::SAR32mi,    0 },
    207     { X86::SAR64r1,     X86::SAR64m1,    0 },
    208     { X86::SAR64rCL,    X86::SAR64mCL,   0 },
    209     { X86::SAR64ri,     X86::SAR64mi,    0 },
    210     { X86::SAR8r1,      X86::SAR8m1,     0 },
    211     { X86::SAR8rCL,     X86::SAR8mCL,    0 },
    212     { X86::SAR8ri,      X86::SAR8mi,     0 },
    213     { X86::SBB32ri,     X86::SBB32mi,    0 },
    214     { X86::SBB32ri8,    X86::SBB32mi8,   0 },
    215     { X86::SBB32rr,     X86::SBB32mr,    0 },
    216     { X86::SBB64ri32,   X86::SBB64mi32,  0 },
    217     { X86::SBB64ri8,    X86::SBB64mi8,   0 },
    218     { X86::SBB64rr,     X86::SBB64mr,    0 },
    219     { X86::SHL16rCL,    X86::SHL16mCL,   0 },
    220     { X86::SHL16ri,     X86::SHL16mi,    0 },
    221     { X86::SHL32rCL,    X86::SHL32mCL,   0 },
    222     { X86::SHL32ri,     X86::SHL32mi,    0 },
    223     { X86::SHL64rCL,    X86::SHL64mCL,   0 },
    224     { X86::SHL64ri,     X86::SHL64mi,    0 },
    225     { X86::SHL8rCL,     X86::SHL8mCL,    0 },
    226     { X86::SHL8ri,      X86::SHL8mi,     0 },
    227     { X86::SHLD16rrCL,  X86::SHLD16mrCL, 0 },
    228     { X86::SHLD16rri8,  X86::SHLD16mri8, 0 },
    229     { X86::SHLD32rrCL,  X86::SHLD32mrCL, 0 },
    230     { X86::SHLD32rri8,  X86::SHLD32mri8, 0 },
    231     { X86::SHLD64rrCL,  X86::SHLD64mrCL, 0 },
    232     { X86::SHLD64rri8,  X86::SHLD64mri8, 0 },
    233     { X86::SHR16r1,     X86::SHR16m1,    0 },
    234     { X86::SHR16rCL,    X86::SHR16mCL,   0 },
    235     { X86::SHR16ri,     X86::SHR16mi,    0 },
    236     { X86::SHR32r1,     X86::SHR32m1,    0 },
    237     { X86::SHR32rCL,    X86::SHR32mCL,   0 },
    238     { X86::SHR32ri,     X86::SHR32mi,    0 },
    239     { X86::SHR64r1,     X86::SHR64m1,    0 },
    240     { X86::SHR64rCL,    X86::SHR64mCL,   0 },
    241     { X86::SHR64ri,     X86::SHR64mi,    0 },
    242     { X86::SHR8r1,      X86::SHR8m1,     0 },
    243     { X86::SHR8rCL,     X86::SHR8mCL,    0 },
    244     { X86::SHR8ri,      X86::SHR8mi,     0 },
    245     { X86::SHRD16rrCL,  X86::SHRD16mrCL, 0 },
    246     { X86::SHRD16rri8,  X86::SHRD16mri8, 0 },
    247     { X86::SHRD32rrCL,  X86::SHRD32mrCL, 0 },
    248     { X86::SHRD32rri8,  X86::SHRD32mri8, 0 },
    249     { X86::SHRD64rrCL,  X86::SHRD64mrCL, 0 },
    250     { X86::SHRD64rri8,  X86::SHRD64mri8, 0 },
    251     { X86::SUB16ri,     X86::SUB16mi,    0 },
    252     { X86::SUB16ri8,    X86::SUB16mi8,   0 },
    253     { X86::SUB16rr,     X86::SUB16mr,    0 },
    254     { X86::SUB32ri,     X86::SUB32mi,    0 },
    255     { X86::SUB32ri8,    X86::SUB32mi8,   0 },
    256     { X86::SUB32rr,     X86::SUB32mr,    0 },
    257     { X86::SUB64ri32,   X86::SUB64mi32,  0 },
    258     { X86::SUB64ri8,    X86::SUB64mi8,   0 },
    259     { X86::SUB64rr,     X86::SUB64mr,    0 },
    260     { X86::SUB8ri,      X86::SUB8mi,     0 },
    261     { X86::SUB8rr,      X86::SUB8mr,     0 },
    262     { X86::XOR16ri,     X86::XOR16mi,    0 },
    263     { X86::XOR16ri8,    X86::XOR16mi8,   0 },
    264     { X86::XOR16rr,     X86::XOR16mr,    0 },
    265     { X86::XOR32ri,     X86::XOR32mi,    0 },
    266     { X86::XOR32ri8,    X86::XOR32mi8,   0 },
    267     { X86::XOR32rr,     X86::XOR32mr,    0 },
    268     { X86::XOR64ri32,   X86::XOR64mi32,  0 },
    269     { X86::XOR64ri8,    X86::XOR64mi8,   0 },
    270     { X86::XOR64rr,     X86::XOR64mr,    0 },
    271     { X86::XOR8ri,      X86::XOR8mi,     0 },
    272     { X86::XOR8rr,      X86::XOR8mr,     0 }
    273   };
    274 
    275   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
    276     AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
    277                   Entry.RegOp, Entry.MemOp,
    278                   // Index 0, folded load and store, no alignment requirement.
    279                   Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
    280   }
    281 
    282   static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
    283     { X86::BT16ri8,     X86::BT16mi8,       TB_FOLDED_LOAD },
    284     { X86::BT32ri8,     X86::BT32mi8,       TB_FOLDED_LOAD },
    285     { X86::BT64ri8,     X86::BT64mi8,       TB_FOLDED_LOAD },
    286     { X86::CALL32r,     X86::CALL32m,       TB_FOLDED_LOAD },
    287     { X86::CALL64r,     X86::CALL64m,       TB_FOLDED_LOAD },
    288     { X86::CMP16ri,     X86::CMP16mi,       TB_FOLDED_LOAD },
    289     { X86::CMP16ri8,    X86::CMP16mi8,      TB_FOLDED_LOAD },
    290     { X86::CMP16rr,     X86::CMP16mr,       TB_FOLDED_LOAD },
    291     { X86::CMP32ri,     X86::CMP32mi,       TB_FOLDED_LOAD },
    292     { X86::CMP32ri8,    X86::CMP32mi8,      TB_FOLDED_LOAD },
    293     { X86::CMP32rr,     X86::CMP32mr,       TB_FOLDED_LOAD },
    294     { X86::CMP64ri32,   X86::CMP64mi32,     TB_FOLDED_LOAD },
    295     { X86::CMP64ri8,    X86::CMP64mi8,      TB_FOLDED_LOAD },
    296     { X86::CMP64rr,     X86::CMP64mr,       TB_FOLDED_LOAD },
    297     { X86::CMP8ri,      X86::CMP8mi,        TB_FOLDED_LOAD },
    298     { X86::CMP8rr,      X86::CMP8mr,        TB_FOLDED_LOAD },
    299     { X86::DIV16r,      X86::DIV16m,        TB_FOLDED_LOAD },
    300     { X86::DIV32r,      X86::DIV32m,        TB_FOLDED_LOAD },
    301     { X86::DIV64r,      X86::DIV64m,        TB_FOLDED_LOAD },
    302     { X86::DIV8r,       X86::DIV8m,         TB_FOLDED_LOAD },
    303     { X86::EXTRACTPSrr, X86::EXTRACTPSmr,   TB_FOLDED_STORE },
    304     { X86::IDIV16r,     X86::IDIV16m,       TB_FOLDED_LOAD },
    305     { X86::IDIV32r,     X86::IDIV32m,       TB_FOLDED_LOAD },
    306     { X86::IDIV64r,     X86::IDIV64m,       TB_FOLDED_LOAD },
    307     { X86::IDIV8r,      X86::IDIV8m,        TB_FOLDED_LOAD },
    308     { X86::IMUL16r,     X86::IMUL16m,       TB_FOLDED_LOAD },
    309     { X86::IMUL32r,     X86::IMUL32m,       TB_FOLDED_LOAD },
    310     { X86::IMUL64r,     X86::IMUL64m,       TB_FOLDED_LOAD },
    311     { X86::IMUL8r,      X86::IMUL8m,        TB_FOLDED_LOAD },
    312     { X86::JMP32r,      X86::JMP32m,        TB_FOLDED_LOAD },
    313     { X86::JMP64r,      X86::JMP64m,        TB_FOLDED_LOAD },
    314     { X86::MOV16ri,     X86::MOV16mi,       TB_FOLDED_STORE },
    315     { X86::MOV16rr,     X86::MOV16mr,       TB_FOLDED_STORE },
    316     { X86::MOV32ri,     X86::MOV32mi,       TB_FOLDED_STORE },
    317     { X86::MOV32rr,     X86::MOV32mr,       TB_FOLDED_STORE },
    318     { X86::MOV64ri32,   X86::MOV64mi32,     TB_FOLDED_STORE },
    319     { X86::MOV64rr,     X86::MOV64mr,       TB_FOLDED_STORE },
    320     { X86::MOV8ri,      X86::MOV8mi,        TB_FOLDED_STORE },
    321     { X86::MOV8rr,      X86::MOV8mr,        TB_FOLDED_STORE },
    322     { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
    323     { X86::MOVAPDrr,    X86::MOVAPDmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
    324     { X86::MOVAPSrr,    X86::MOVAPSmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
    325     { X86::MOVDQArr,    X86::MOVDQAmr,      TB_FOLDED_STORE | TB_ALIGN_16 },
    326     { X86::MOVPDI2DIrr, X86::MOVPDI2DImr,   TB_FOLDED_STORE },
    327     { X86::MOVPQIto64rr,X86::MOVPQI2QImr,   TB_FOLDED_STORE },
    328     { X86::MOVSDto64rr, X86::MOVSDto64mr,   TB_FOLDED_STORE },
    329     { X86::MOVSS2DIrr,  X86::MOVSS2DImr,    TB_FOLDED_STORE },
    330     { X86::MOVUPDrr,    X86::MOVUPDmr,      TB_FOLDED_STORE },
    331     { X86::MOVUPSrr,    X86::MOVUPSmr,      TB_FOLDED_STORE },
    332     { X86::MUL16r,      X86::MUL16m,        TB_FOLDED_LOAD },
    333     { X86::MUL32r,      X86::MUL32m,        TB_FOLDED_LOAD },
    334     { X86::MUL64r,      X86::MUL64m,        TB_FOLDED_LOAD },
    335     { X86::MUL8r,       X86::MUL8m,         TB_FOLDED_LOAD },
    336     { X86::PEXTRDrr,    X86::PEXTRDmr,      TB_FOLDED_STORE },
    337     { X86::PEXTRQrr,    X86::PEXTRQmr,      TB_FOLDED_STORE },
    338     { X86::PUSH16r,     X86::PUSH16rmm,     TB_FOLDED_LOAD },
    339     { X86::PUSH32r,     X86::PUSH32rmm,     TB_FOLDED_LOAD },
    340     { X86::PUSH64r,     X86::PUSH64rmm,     TB_FOLDED_LOAD },
    341     { X86::SETAEr,      X86::SETAEm,        TB_FOLDED_STORE },
    342     { X86::SETAr,       X86::SETAm,         TB_FOLDED_STORE },
    343     { X86::SETBEr,      X86::SETBEm,        TB_FOLDED_STORE },
    344     { X86::SETBr,       X86::SETBm,         TB_FOLDED_STORE },
    345     { X86::SETEr,       X86::SETEm,         TB_FOLDED_STORE },
    346     { X86::SETGEr,      X86::SETGEm,        TB_FOLDED_STORE },
    347     { X86::SETGr,       X86::SETGm,         TB_FOLDED_STORE },
    348     { X86::SETLEr,      X86::SETLEm,        TB_FOLDED_STORE },
    349     { X86::SETLr,       X86::SETLm,         TB_FOLDED_STORE },
    350     { X86::SETNEr,      X86::SETNEm,        TB_FOLDED_STORE },
    351     { X86::SETNOr,      X86::SETNOm,        TB_FOLDED_STORE },
    352     { X86::SETNPr,      X86::SETNPm,        TB_FOLDED_STORE },
    353     { X86::SETNSr,      X86::SETNSm,        TB_FOLDED_STORE },
    354     { X86::SETOr,       X86::SETOm,         TB_FOLDED_STORE },
    355     { X86::SETPr,       X86::SETPm,         TB_FOLDED_STORE },
    356     { X86::SETSr,       X86::SETSm,         TB_FOLDED_STORE },
    357     { X86::TAILJMPr,    X86::TAILJMPm,      TB_FOLDED_LOAD },
    358     { X86::TAILJMPr64,  X86::TAILJMPm64,    TB_FOLDED_LOAD },
    359     { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
    360     { X86::TEST16ri,    X86::TEST16mi,      TB_FOLDED_LOAD },
    361     { X86::TEST32ri,    X86::TEST32mi,      TB_FOLDED_LOAD },
    362     { X86::TEST64ri32,  X86::TEST64mi32,    TB_FOLDED_LOAD },
    363     { X86::TEST8ri,     X86::TEST8mi,       TB_FOLDED_LOAD },
    364 
    365     // AVX 128-bit versions of foldable instructions
    366     { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr,  TB_FOLDED_STORE  },
    367     { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
    368     { X86::VMOVAPDrr,   X86::VMOVAPDmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
    369     { X86::VMOVAPSrr,   X86::VMOVAPSmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
    370     { X86::VMOVDQArr,   X86::VMOVDQAmr,     TB_FOLDED_STORE | TB_ALIGN_16 },
    371     { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr,  TB_FOLDED_STORE },
    372     { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
    373     { X86::VMOVSDto64rr,X86::VMOVSDto64mr,  TB_FOLDED_STORE },
    374     { X86::VMOVSS2DIrr, X86::VMOVSS2DImr,   TB_FOLDED_STORE },
    375     { X86::VMOVUPDrr,   X86::VMOVUPDmr,     TB_FOLDED_STORE },
    376     { X86::VMOVUPSrr,   X86::VMOVUPSmr,     TB_FOLDED_STORE },
    377     { X86::VPEXTRDrr,   X86::VPEXTRDmr,     TB_FOLDED_STORE },
    378     { X86::VPEXTRQrr,   X86::VPEXTRQmr,     TB_FOLDED_STORE },
    379 
    380     // AVX 256-bit foldable instructions
    381     { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
    382     { X86::VMOVAPDYrr,  X86::VMOVAPDYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
    383     { X86::VMOVAPSYrr,  X86::VMOVAPSYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
    384     { X86::VMOVDQAYrr,  X86::VMOVDQAYmr,    TB_FOLDED_STORE | TB_ALIGN_32 },
    385     { X86::VMOVUPDYrr,  X86::VMOVUPDYmr,    TB_FOLDED_STORE },
    386     { X86::VMOVUPSYrr,  X86::VMOVUPSYmr,    TB_FOLDED_STORE },
    387 
    388     // AVX-512 foldable instructions
    389     { X86::VMOVPDI2DIZrr,   X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
    390     { X86::VMOVAPDZrr,      X86::VMOVAPDZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
    391     { X86::VMOVAPSZrr,      X86::VMOVAPSZmr,    TB_FOLDED_STORE | TB_ALIGN_64 },
    392     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
    393     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zmr,  TB_FOLDED_STORE | TB_ALIGN_64 },
    394     { X86::VMOVUPDZrr,      X86::VMOVUPDZmr,    TB_FOLDED_STORE },
    395     { X86::VMOVUPSZrr,      X86::VMOVUPSZmr,    TB_FOLDED_STORE },
    396     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zmr,   TB_FOLDED_STORE },
    397     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zmr,  TB_FOLDED_STORE },
    398     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zmr,  TB_FOLDED_STORE },
    399     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zmr,  TB_FOLDED_STORE },
    400 
    401     // AVX-512 foldable instructions (256-bit versions)
    402     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
    403     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256mr,    TB_FOLDED_STORE | TB_ALIGN_32 },
    404     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
    405     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256mr,  TB_FOLDED_STORE | TB_ALIGN_32 },
    406     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256mr,    TB_FOLDED_STORE },
    407     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256mr,    TB_FOLDED_STORE },
    408     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256mr,   TB_FOLDED_STORE },
    409     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256mr,  TB_FOLDED_STORE },
    410     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256mr,  TB_FOLDED_STORE },
    411     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256mr,  TB_FOLDED_STORE },
    412 
    413     // AVX-512 foldable instructions (128-bit versions)
    414     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
    415     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128mr,    TB_FOLDED_STORE | TB_ALIGN_16 },
    416     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
    417     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128mr,  TB_FOLDED_STORE | TB_ALIGN_16 },
    418     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128mr,    TB_FOLDED_STORE },
    419     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128mr,    TB_FOLDED_STORE },
    420     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128mr,   TB_FOLDED_STORE },
    421     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128mr,  TB_FOLDED_STORE },
    422     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128mr,  TB_FOLDED_STORE },
    423     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128mr,  TB_FOLDED_STORE },
    424 
    425     // F16C foldable instructions
    426     { X86::VCVTPS2PHrr,        X86::VCVTPS2PHmr,      TB_FOLDED_STORE },
    427     { X86::VCVTPS2PHYrr,       X86::VCVTPS2PHYmr,     TB_FOLDED_STORE }
    428   };
    429 
    430   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
    431     AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
    432                   Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
    433   }
    434 
    435   static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
    436     { X86::BSF16rr,         X86::BSF16rm,             0 },
    437     { X86::BSF32rr,         X86::BSF32rm,             0 },
    438     { X86::BSF64rr,         X86::BSF64rm,             0 },
    439     { X86::BSR16rr,         X86::BSR16rm,             0 },
    440     { X86::BSR32rr,         X86::BSR32rm,             0 },
    441     { X86::BSR64rr,         X86::BSR64rm,             0 },
    442     { X86::CMP16rr,         X86::CMP16rm,             0 },
    443     { X86::CMP32rr,         X86::CMP32rm,             0 },
    444     { X86::CMP64rr,         X86::CMP64rm,             0 },
    445     { X86::CMP8rr,          X86::CMP8rm,              0 },
    446     { X86::CVTSD2SSrr,      X86::CVTSD2SSrm,          0 },
    447     { X86::CVTSI2SD64rr,    X86::CVTSI2SD64rm,        0 },
    448     { X86::CVTSI2SDrr,      X86::CVTSI2SDrm,          0 },
    449     { X86::CVTSI2SS64rr,    X86::CVTSI2SS64rm,        0 },
    450     { X86::CVTSI2SSrr,      X86::CVTSI2SSrm,          0 },
    451     { X86::CVTSS2SDrr,      X86::CVTSS2SDrm,          0 },
    452     { X86::CVTTSD2SI64rr,   X86::CVTTSD2SI64rm,       0 },
    453     { X86::CVTTSD2SIrr,     X86::CVTTSD2SIrm,         0 },
    454     { X86::CVTTSS2SI64rr,   X86::CVTTSS2SI64rm,       0 },
    455     { X86::CVTTSS2SIrr,     X86::CVTTSS2SIrm,         0 },
    456     { X86::IMUL16rri,       X86::IMUL16rmi,           0 },
    457     { X86::IMUL16rri8,      X86::IMUL16rmi8,          0 },
    458     { X86::IMUL32rri,       X86::IMUL32rmi,           0 },
    459     { X86::IMUL32rri8,      X86::IMUL32rmi8,          0 },
    460     { X86::IMUL64rri32,     X86::IMUL64rmi32,         0 },
    461     { X86::IMUL64rri8,      X86::IMUL64rmi8,          0 },
    462     { X86::Int_COMISDrr,    X86::Int_COMISDrm,        0 },
    463     { X86::Int_COMISSrr,    X86::Int_COMISSrm,        0 },
    464     { X86::CVTSD2SI64rr,    X86::CVTSD2SI64rm,        0 },
    465     { X86::CVTSD2SIrr,      X86::CVTSD2SIrm,          0 },
    466     { X86::CVTSS2SI64rr,    X86::CVTSS2SI64rm,        0 },
    467     { X86::CVTSS2SIrr,      X86::CVTSS2SIrm,          0 },
    468     { X86::CVTDQ2PDrr,      X86::CVTDQ2PDrm,          TB_ALIGN_16 },
    469     { X86::CVTDQ2PSrr,      X86::CVTDQ2PSrm,          TB_ALIGN_16 },
    470     { X86::CVTPD2DQrr,      X86::CVTPD2DQrm,          TB_ALIGN_16 },
    471     { X86::CVTPD2PSrr,      X86::CVTPD2PSrm,          TB_ALIGN_16 },
    472     { X86::CVTPS2DQrr,      X86::CVTPS2DQrm,          TB_ALIGN_16 },
    473     { X86::CVTPS2PDrr,      X86::CVTPS2PDrm,          TB_ALIGN_16 },
    474     { X86::CVTTPD2DQrr,     X86::CVTTPD2DQrm,         TB_ALIGN_16 },
    475     { X86::CVTTPS2DQrr,     X86::CVTTPS2DQrm,         TB_ALIGN_16 },
    476     { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm,  0 },
    477     { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm,     0 },
    478     { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm,  0 },
    479     { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm,     0 },
    480     { X86::Int_UCOMISDrr,   X86::Int_UCOMISDrm,       0 },
    481     { X86::Int_UCOMISSrr,   X86::Int_UCOMISSrm,       0 },
    482     { X86::MOV16rr,         X86::MOV16rm,             0 },
    483     { X86::MOV32rr,         X86::MOV32rm,             0 },
    484     { X86::MOV64rr,         X86::MOV64rm,             0 },
    485     { X86::MOV64toPQIrr,    X86::MOVQI2PQIrm,         0 },
    486     { X86::MOV64toSDrr,     X86::MOV64toSDrm,         0 },
    487     { X86::MOV8rr,          X86::MOV8rm,              0 },
    488     { X86::MOVAPDrr,        X86::MOVAPDrm,            TB_ALIGN_16 },
    489     { X86::MOVAPSrr,        X86::MOVAPSrm,            TB_ALIGN_16 },
    490     { X86::MOVDDUPrr,       X86::MOVDDUPrm,           0 },
    491     { X86::MOVDI2PDIrr,     X86::MOVDI2PDIrm,         0 },
    492     { X86::MOVDI2SSrr,      X86::MOVDI2SSrm,          0 },
    493     { X86::MOVDQArr,        X86::MOVDQArm,            TB_ALIGN_16 },
    494     { X86::MOVSHDUPrr,      X86::MOVSHDUPrm,          TB_ALIGN_16 },
    495     { X86::MOVSLDUPrr,      X86::MOVSLDUPrm,          TB_ALIGN_16 },
    496     { X86::MOVSX16rr8,      X86::MOVSX16rm8,          0 },
    497     { X86::MOVSX32rr16,     X86::MOVSX32rm16,         0 },
    498     { X86::MOVSX32rr8,      X86::MOVSX32rm8,          0 },
    499     { X86::MOVSX64rr16,     X86::MOVSX64rm16,         0 },
    500     { X86::MOVSX64rr32,     X86::MOVSX64rm32,         0 },
    501     { X86::MOVSX64rr8,      X86::MOVSX64rm8,          0 },
    502     { X86::MOVUPDrr,        X86::MOVUPDrm,            TB_ALIGN_16 },
    503     { X86::MOVUPSrr,        X86::MOVUPSrm,            0 },
    504     { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm,     TB_ALIGN_16 },
    505     { X86::MOVZX16rr8,      X86::MOVZX16rm8,          0 },
    506     { X86::MOVZX32rr16,     X86::MOVZX32rm16,         0 },
    507     { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8,   0 },
    508     { X86::MOVZX32rr8,      X86::MOVZX32rm8,          0 },
    509     { X86::PABSBrr128,      X86::PABSBrm128,          TB_ALIGN_16 },
    510     { X86::PABSDrr128,      X86::PABSDrm128,          TB_ALIGN_16 },
    511     { X86::PABSWrr128,      X86::PABSWrm128,          TB_ALIGN_16 },
    512     { X86::PCMPESTRIrr,     X86::PCMPESTRIrm,         TB_ALIGN_16 },
    513     { X86::PCMPESTRM128rr,  X86::PCMPESTRM128rm,      TB_ALIGN_16 },
    514     { X86::PCMPISTRIrr,     X86::PCMPISTRIrm,         TB_ALIGN_16 },
    515     { X86::PCMPISTRM128rr,  X86::PCMPISTRM128rm,      TB_ALIGN_16 },
    516     { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128,     TB_ALIGN_16 },
    517     { X86::PMOVSXBDrr,      X86::PMOVSXBDrm,          TB_ALIGN_16 },
    518     { X86::PMOVSXBQrr,      X86::PMOVSXBQrm,          TB_ALIGN_16 },
    519     { X86::PMOVSXBWrr,      X86::PMOVSXBWrm,          TB_ALIGN_16 },
    520     { X86::PMOVSXDQrr,      X86::PMOVSXDQrm,          TB_ALIGN_16 },
    521     { X86::PMOVSXWDrr,      X86::PMOVSXWDrm,          TB_ALIGN_16 },
    522     { X86::PMOVSXWQrr,      X86::PMOVSXWQrm,          TB_ALIGN_16 },
    523     { X86::PMOVZXBDrr,      X86::PMOVZXBDrm,          TB_ALIGN_16 },
    524     { X86::PMOVZXBQrr,      X86::PMOVZXBQrm,          TB_ALIGN_16 },
    525     { X86::PMOVZXBWrr,      X86::PMOVZXBWrm,          TB_ALIGN_16 },
    526     { X86::PMOVZXDQrr,      X86::PMOVZXDQrm,          TB_ALIGN_16 },
    527     { X86::PMOVZXWDrr,      X86::PMOVZXWDrm,          TB_ALIGN_16 },
    528     { X86::PMOVZXWQrr,      X86::PMOVZXWQrm,          TB_ALIGN_16 },
    529     { X86::PSHUFDri,        X86::PSHUFDmi,            TB_ALIGN_16 },
    530     { X86::PSHUFHWri,       X86::PSHUFHWmi,           TB_ALIGN_16 },
    531     { X86::PSHUFLWri,       X86::PSHUFLWmi,           TB_ALIGN_16 },
    532     { X86::PTESTrr,         X86::PTESTrm,             TB_ALIGN_16 },
    533     { X86::RCPPSr,          X86::RCPPSm,              TB_ALIGN_16 },
    534     { X86::RCPSSr,          X86::RCPSSm,              0 },
    535     { X86::RCPSSr_Int,      X86::RCPSSm_Int,          0 },
    536     { X86::ROUNDPDr,        X86::ROUNDPDm,            TB_ALIGN_16 },
    537     { X86::ROUNDPSr,        X86::ROUNDPSm,            TB_ALIGN_16 },
    538     { X86::RSQRTPSr,        X86::RSQRTPSm,            TB_ALIGN_16 },
    539     { X86::RSQRTSSr,        X86::RSQRTSSm,            0 },
    540     { X86::RSQRTSSr_Int,    X86::RSQRTSSm_Int,        0 },
    541     { X86::SQRTPDr,         X86::SQRTPDm,             TB_ALIGN_16 },
    542     { X86::SQRTPSr,         X86::SQRTPSm,             TB_ALIGN_16 },
    543     { X86::SQRTSDr,         X86::SQRTSDm,             0 },
    544     { X86::SQRTSDr_Int,     X86::SQRTSDm_Int,         0 },
    545     { X86::SQRTSSr,         X86::SQRTSSm,             0 },
    546     { X86::SQRTSSr_Int,     X86::SQRTSSm_Int,         0 },
    547     { X86::TEST16rr,        X86::TEST16rm,            0 },
    548     { X86::TEST32rr,        X86::TEST32rm,            0 },
    549     { X86::TEST64rr,        X86::TEST64rm,            0 },
    550     { X86::TEST8rr,         X86::TEST8rm,             0 },
    551     // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
    552     { X86::UCOMISDrr,       X86::UCOMISDrm,           0 },
    553     { X86::UCOMISSrr,       X86::UCOMISSrm,           0 },
    554 
    555     // MMX version of foldable instructions
    556     { X86::MMX_CVTPD2PIirr,   X86::MMX_CVTPD2PIirm,   0 },
    557     { X86::MMX_CVTPI2PDirr,   X86::MMX_CVTPI2PDirm,   0 },
    558     { X86::MMX_CVTPS2PIirr,   X86::MMX_CVTPS2PIirm,   0 },
    559     { X86::MMX_CVTTPD2PIirr,  X86::MMX_CVTTPD2PIirm,  0 },
    560     { X86::MMX_CVTTPS2PIirr,  X86::MMX_CVTTPS2PIirm,  0 },
    561     { X86::MMX_MOVD64to64rr,  X86::MMX_MOVQ64rm,      0 },
    562     { X86::MMX_PABSBrr64,     X86::MMX_PABSBrm64,     0 },
    563     { X86::MMX_PABSDrr64,     X86::MMX_PABSDrm64,     0 },
    564     { X86::MMX_PABSWrr64,     X86::MMX_PABSWrm64,     0 },
    565     { X86::MMX_PSHUFWri,      X86::MMX_PSHUFWmi,      0 },
    566 
    567     // 3DNow! version of foldable instructions
    568     { X86::PF2IDrr,         X86::PF2IDrm,             0 },
    569     { X86::PF2IWrr,         X86::PF2IWrm,             0 },
    570     { X86::PFRCPrr,         X86::PFRCPrm,             0 },
    571     { X86::PFRSQRTrr,       X86::PFRSQRTrm,           0 },
    572     { X86::PI2FDrr,         X86::PI2FDrm,             0 },
    573     { X86::PI2FWrr,         X86::PI2FWrm,             0 },
    574     { X86::PSWAPDrr,        X86::PSWAPDrm,            0 },
    575 
    576     // AVX 128-bit versions of foldable instructions
    577     { X86::Int_VCOMISDrr,   X86::Int_VCOMISDrm,       0 },
    578     { X86::Int_VCOMISSrr,   X86::Int_VCOMISSrm,       0 },
    579     { X86::Int_VUCOMISDrr,  X86::Int_VUCOMISDrm,      0 },
    580     { X86::Int_VUCOMISSrr,  X86::Int_VUCOMISSrm,      0 },
    581     { X86::VCVTTSD2SI64rr,  X86::VCVTTSD2SI64rm,      0 },
    582     { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
    583     { X86::VCVTTSD2SIrr,    X86::VCVTTSD2SIrm,        0 },
    584     { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm,    0 },
    585     { X86::VCVTTSS2SI64rr,  X86::VCVTTSS2SI64rm,      0 },
    586     { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
    587     { X86::VCVTTSS2SIrr,    X86::VCVTTSS2SIrm,        0 },
    588     { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm,    0 },
    589     { X86::VCVTSD2SI64rr,   X86::VCVTSD2SI64rm,       0 },
    590     { X86::VCVTSD2SIrr,     X86::VCVTSD2SIrm,         0 },
    591     { X86::VCVTSS2SI64rr,   X86::VCVTSS2SI64rm,       0 },
    592     { X86::VCVTSS2SIrr,     X86::VCVTSS2SIrm,         0 },
    593     { X86::VCVTDQ2PDrr,     X86::VCVTDQ2PDrm,         0 },
    594     { X86::VCVTDQ2PSrr,     X86::VCVTDQ2PSrm,         0 },
    595     { X86::VCVTPD2DQrr,     X86::VCVTPD2DQXrm,        0 },
    596     { X86::VCVTPD2PSrr,     X86::VCVTPD2PSXrm,        0 },
    597     { X86::VCVTPS2DQrr,     X86::VCVTPS2DQrm,         0 },
    598     { X86::VCVTPS2PDrr,     X86::VCVTPS2PDrm,         0 },
    599     { X86::VCVTTPD2DQrr,    X86::VCVTTPD2DQXrm,       0 },
    600     { X86::VCVTTPS2DQrr,    X86::VCVTTPS2DQrm,        0 },
    601     { X86::VMOV64toPQIrr,   X86::VMOVQI2PQIrm,        0 },
    602     { X86::VMOV64toSDrr,    X86::VMOV64toSDrm,        0 },
    603     { X86::VMOVAPDrr,       X86::VMOVAPDrm,           TB_ALIGN_16 },
    604     { X86::VMOVAPSrr,       X86::VMOVAPSrm,           TB_ALIGN_16 },
    605     { X86::VMOVDDUPrr,      X86::VMOVDDUPrm,          0 },
    606     { X86::VMOVDI2PDIrr,    X86::VMOVDI2PDIrm,        0 },
    607     { X86::VMOVDI2SSrr,     X86::VMOVDI2SSrm,         0 },
    608     { X86::VMOVDQArr,       X86::VMOVDQArm,           TB_ALIGN_16 },
    609     { X86::VMOVSLDUPrr,     X86::VMOVSLDUPrm,         0 },
    610     { X86::VMOVSHDUPrr,     X86::VMOVSHDUPrm,         0 },
    611     { X86::VMOVUPDrr,       X86::VMOVUPDrm,           0 },
    612     { X86::VMOVUPSrr,       X86::VMOVUPSrm,           0 },
    613     { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm,    TB_ALIGN_16 },
    614     { X86::VPABSBrr128,     X86::VPABSBrm128,         0 },
    615     { X86::VPABSDrr128,     X86::VPABSDrm128,         0 },
    616     { X86::VPABSWrr128,     X86::VPABSWrm128,         0 },
    617     { X86::VPCMPESTRIrr,    X86::VPCMPESTRIrm,        0 },
    618     { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm,     0 },
    619     { X86::VPCMPISTRIrr,    X86::VPCMPISTRIrm,        0 },
    620     { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm,     0 },
    621     { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128,   0 },
    622     { X86::VPERMILPDri,     X86::VPERMILPDmi,         0 },
    623     { X86::VPERMILPSri,     X86::VPERMILPSmi,         0 },
    624     { X86::VPMOVSXBDrr,     X86::VPMOVSXBDrm,         0 },
    625     { X86::VPMOVSXBQrr,     X86::VPMOVSXBQrm,         0 },
    626     { X86::VPMOVSXBWrr,     X86::VPMOVSXBWrm,         0 },
    627     { X86::VPMOVSXDQrr,     X86::VPMOVSXDQrm,         0 },
    628     { X86::VPMOVSXWDrr,     X86::VPMOVSXWDrm,         0 },
    629     { X86::VPMOVSXWQrr,     X86::VPMOVSXWQrm,         0 },
    630     { X86::VPMOVZXBDrr,     X86::VPMOVZXBDrm,         0 },
    631     { X86::VPMOVZXBQrr,     X86::VPMOVZXBQrm,         0 },
    632     { X86::VPMOVZXBWrr,     X86::VPMOVZXBWrm,         0 },
    633     { X86::VPMOVZXDQrr,     X86::VPMOVZXDQrm,         0 },
    634     { X86::VPMOVZXWDrr,     X86::VPMOVZXWDrm,         0 },
    635     { X86::VPMOVZXWQrr,     X86::VPMOVZXWQrm,         0 },
    636     { X86::VPSHUFDri,       X86::VPSHUFDmi,           0 },
    637     { X86::VPSHUFHWri,      X86::VPSHUFHWmi,          0 },
    638     { X86::VPSHUFLWri,      X86::VPSHUFLWmi,          0 },
    639     { X86::VPTESTrr,        X86::VPTESTrm,            0 },
    640     { X86::VRCPPSr,         X86::VRCPPSm,             0 },
    641     { X86::VROUNDPDr,       X86::VROUNDPDm,           0 },
    642     { X86::VROUNDPSr,       X86::VROUNDPSm,           0 },
    643     { X86::VRSQRTPSr,       X86::VRSQRTPSm,           0 },
    644     { X86::VSQRTPDr,        X86::VSQRTPDm,            0 },
    645     { X86::VSQRTPSr,        X86::VSQRTPSm,            0 },
    646     { X86::VTESTPDrr,       X86::VTESTPDrm,           0 },
    647     { X86::VTESTPSrr,       X86::VTESTPSrm,           0 },
    648     { X86::VUCOMISDrr,      X86::VUCOMISDrm,          0 },
    649     { X86::VUCOMISSrr,      X86::VUCOMISSrm,          0 },
    650 
    651     // AVX 256-bit foldable instructions
    652     { X86::VCVTDQ2PDYrr,    X86::VCVTDQ2PDYrm,        0 },
    653     { X86::VCVTDQ2PSYrr,    X86::VCVTDQ2PSYrm,        0 },
    654     { X86::VCVTPD2DQYrr,    X86::VCVTPD2DQYrm,        0 },
    655     { X86::VCVTPD2PSYrr,    X86::VCVTPD2PSYrm,        0 },
    656     { X86::VCVTPS2DQYrr,    X86::VCVTPS2DQYrm,        0 },
    657     { X86::VCVTPS2PDYrr,    X86::VCVTPS2PDYrm,        0 },
    658     { X86::VCVTTPD2DQYrr,   X86::VCVTTPD2DQYrm,       0 },
    659     { X86::VCVTTPS2DQYrr,   X86::VCVTTPS2DQYrm,       0 },
    660     { X86::VMOVAPDYrr,      X86::VMOVAPDYrm,          TB_ALIGN_32 },
    661     { X86::VMOVAPSYrr,      X86::VMOVAPSYrm,          TB_ALIGN_32 },
    662     { X86::VMOVDDUPYrr,     X86::VMOVDDUPYrm,         0 },
    663     { X86::VMOVDQAYrr,      X86::VMOVDQAYrm,          TB_ALIGN_32 },
    664     { X86::VMOVSLDUPYrr,    X86::VMOVSLDUPYrm,        0 },
    665     { X86::VMOVSHDUPYrr,    X86::VMOVSHDUPYrm,        0 },
    666     { X86::VMOVUPDYrr,      X86::VMOVUPDYrm,          0 },
    667     { X86::VMOVUPSYrr,      X86::VMOVUPSYrm,          0 },
    668     { X86::VPERMILPDYri,    X86::VPERMILPDYmi,        0 },
    669     { X86::VPERMILPSYri,    X86::VPERMILPSYmi,        0 },
    670     { X86::VPTESTYrr,       X86::VPTESTYrm,           0 },
    671     { X86::VRCPPSYr,        X86::VRCPPSYm,            0 },
    672     { X86::VROUNDYPDr,      X86::VROUNDYPDm,          0 },
    673     { X86::VROUNDYPSr,      X86::VROUNDYPSm,          0 },
    674     { X86::VRSQRTPSYr,      X86::VRSQRTPSYm,          0 },
    675     { X86::VSQRTPDYr,       X86::VSQRTPDYm,           0 },
    676     { X86::VSQRTPSYr,       X86::VSQRTPSYm,           0 },
    677     { X86::VTESTPDYrr,      X86::VTESTPDYrm,          0 },
    678     { X86::VTESTPSYrr,      X86::VTESTPSYrm,          0 },
    679 
    680     // AVX2 foldable instructions
    681 
    682     // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
    683     // VBROADCASTS{SD}rm memory instructions were available from AVX1.
    684     // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
    685     // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
    686     // so they don't need an equivalent limitation.
    687     { X86::VBROADCASTSSrr,  X86::VBROADCASTSSrm,      TB_NO_REVERSE },
    688     { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm,     TB_NO_REVERSE },
    689     { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm,     TB_NO_REVERSE },
    690     { X86::VPABSBrr256,     X86::VPABSBrm256,         0 },
    691     { X86::VPABSDrr256,     X86::VPABSDrm256,         0 },
    692     { X86::VPABSWrr256,     X86::VPABSWrm256,         0 },
    693     { X86::VPBROADCASTBrr,  X86::VPBROADCASTBrm,      0 },
    694     { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm,     0 },
    695     { X86::VPBROADCASTDrr,  X86::VPBROADCASTDrm,      0 },
    696     { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm,     0 },
    697     { X86::VPBROADCASTQrr,  X86::VPBROADCASTQrm,      0 },
    698     { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm,     0 },
    699     { X86::VPBROADCASTWrr,  X86::VPBROADCASTWrm,      0 },
    700     { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm,     0 },
    701     { X86::VPERMPDYri,      X86::VPERMPDYmi,          0 },
    702     { X86::VPERMQYri,       X86::VPERMQYmi,           0 },
    703     { X86::VPMOVSXBDYrr,    X86::VPMOVSXBDYrm,        0 },
    704     { X86::VPMOVSXBQYrr,    X86::VPMOVSXBQYrm,        0 },
    705     { X86::VPMOVSXBWYrr,    X86::VPMOVSXBWYrm,        0 },
    706     { X86::VPMOVSXDQYrr,    X86::VPMOVSXDQYrm,        0 },
    707     { X86::VPMOVSXWDYrr,    X86::VPMOVSXWDYrm,        0 },
    708     { X86::VPMOVSXWQYrr,    X86::VPMOVSXWQYrm,        0 },
    709     { X86::VPMOVZXBDYrr,    X86::VPMOVZXBDYrm,        0 },
    710     { X86::VPMOVZXBQYrr,    X86::VPMOVZXBQYrm,        0 },
    711     { X86::VPMOVZXBWYrr,    X86::VPMOVZXBWYrm,        0 },
    712     { X86::VPMOVZXDQYrr,    X86::VPMOVZXDQYrm,        0 },
    713     { X86::VPMOVZXWDYrr,    X86::VPMOVZXWDYrm,        0 },
    714     { X86::VPMOVZXWQYrr,    X86::VPMOVZXWQYrm,        0 },
    715     { X86::VPSHUFDYri,      X86::VPSHUFDYmi,          0 },
    716     { X86::VPSHUFHWYri,     X86::VPSHUFHWYmi,         0 },
    717     { X86::VPSHUFLWYri,     X86::VPSHUFLWYmi,         0 },
    718 
    719     // XOP foldable instructions
    720     { X86::VFRCZPDrr,          X86::VFRCZPDrm,        0 },
    721     { X86::VFRCZPDrrY,         X86::VFRCZPDrmY,       0 },
    722     { X86::VFRCZPSrr,          X86::VFRCZPSrm,        0 },
    723     { X86::VFRCZPSrrY,         X86::VFRCZPSrmY,       0 },
    724     { X86::VFRCZSDrr,          X86::VFRCZSDrm,        0 },
    725     { X86::VFRCZSSrr,          X86::VFRCZSSrm,        0 },
    726     { X86::VPHADDBDrr,         X86::VPHADDBDrm,       0 },
    727     { X86::VPHADDBQrr,         X86::VPHADDBQrm,       0 },
    728     { X86::VPHADDBWrr,         X86::VPHADDBWrm,       0 },
    729     { X86::VPHADDDQrr,         X86::VPHADDDQrm,       0 },
    730     { X86::VPHADDWDrr,         X86::VPHADDWDrm,       0 },
    731     { X86::VPHADDWQrr,         X86::VPHADDWQrm,       0 },
    732     { X86::VPHADDUBDrr,        X86::VPHADDUBDrm,      0 },
    733     { X86::VPHADDUBQrr,        X86::VPHADDUBQrm,      0 },
    734     { X86::VPHADDUBWrr,        X86::VPHADDUBWrm,      0 },
    735     { X86::VPHADDUDQrr,        X86::VPHADDUDQrm,      0 },
    736     { X86::VPHADDUWDrr,        X86::VPHADDUWDrm,      0 },
    737     { X86::VPHADDUWQrr,        X86::VPHADDUWQrm,      0 },
    738     { X86::VPHSUBBWrr,         X86::VPHSUBBWrm,       0 },
    739     { X86::VPHSUBDQrr,         X86::VPHSUBDQrm,       0 },
    740     { X86::VPHSUBWDrr,         X86::VPHSUBWDrm,       0 },
    741     { X86::VPROTBri,           X86::VPROTBmi,         0 },
    742     { X86::VPROTBrr,           X86::VPROTBmr,         0 },
    743     { X86::VPROTDri,           X86::VPROTDmi,         0 },
    744     { X86::VPROTDrr,           X86::VPROTDmr,         0 },
    745     { X86::VPROTQri,           X86::VPROTQmi,         0 },
    746     { X86::VPROTQrr,           X86::VPROTQmr,         0 },
    747     { X86::VPROTWri,           X86::VPROTWmi,         0 },
    748     { X86::VPROTWrr,           X86::VPROTWmr,         0 },
    749     { X86::VPSHABrr,           X86::VPSHABmr,         0 },
    750     { X86::VPSHADrr,           X86::VPSHADmr,         0 },
    751     { X86::VPSHAQrr,           X86::VPSHAQmr,         0 },
    752     { X86::VPSHAWrr,           X86::VPSHAWmr,         0 },
    753     { X86::VPSHLBrr,           X86::VPSHLBmr,         0 },
    754     { X86::VPSHLDrr,           X86::VPSHLDmr,         0 },
    755     { X86::VPSHLQrr,           X86::VPSHLQmr,         0 },
    756     { X86::VPSHLWrr,           X86::VPSHLWmr,         0 },
    757 
    758     // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
    759     { X86::BEXTR32rr,       X86::BEXTR32rm,           0 },
    760     { X86::BEXTR64rr,       X86::BEXTR64rm,           0 },
    761     { X86::BEXTRI32ri,      X86::BEXTRI32mi,          0 },
    762     { X86::BEXTRI64ri,      X86::BEXTRI64mi,          0 },
    763     { X86::BLCFILL32rr,     X86::BLCFILL32rm,         0 },
    764     { X86::BLCFILL64rr,     X86::BLCFILL64rm,         0 },
    765     { X86::BLCI32rr,        X86::BLCI32rm,            0 },
    766     { X86::BLCI64rr,        X86::BLCI64rm,            0 },
    767     { X86::BLCIC32rr,       X86::BLCIC32rm,           0 },
    768     { X86::BLCIC64rr,       X86::BLCIC64rm,           0 },
    769     { X86::BLCMSK32rr,      X86::BLCMSK32rm,          0 },
    770     { X86::BLCMSK64rr,      X86::BLCMSK64rm,          0 },
    771     { X86::BLCS32rr,        X86::BLCS32rm,            0 },
    772     { X86::BLCS64rr,        X86::BLCS64rm,            0 },
    773     { X86::BLSFILL32rr,     X86::BLSFILL32rm,         0 },
    774     { X86::BLSFILL64rr,     X86::BLSFILL64rm,         0 },
    775     { X86::BLSI32rr,        X86::BLSI32rm,            0 },
    776     { X86::BLSI64rr,        X86::BLSI64rm,            0 },
    777     { X86::BLSIC32rr,       X86::BLSIC32rm,           0 },
    778     { X86::BLSIC64rr,       X86::BLSIC64rm,           0 },
    779     { X86::BLSMSK32rr,      X86::BLSMSK32rm,          0 },
    780     { X86::BLSMSK64rr,      X86::BLSMSK64rm,          0 },
    781     { X86::BLSR32rr,        X86::BLSR32rm,            0 },
    782     { X86::BLSR64rr,        X86::BLSR64rm,            0 },
    783     { X86::BZHI32rr,        X86::BZHI32rm,            0 },
    784     { X86::BZHI64rr,        X86::BZHI64rm,            0 },
    785     { X86::LZCNT16rr,       X86::LZCNT16rm,           0 },
    786     { X86::LZCNT32rr,       X86::LZCNT32rm,           0 },
    787     { X86::LZCNT64rr,       X86::LZCNT64rm,           0 },
    788     { X86::POPCNT16rr,      X86::POPCNT16rm,          0 },
    789     { X86::POPCNT32rr,      X86::POPCNT32rm,          0 },
    790     { X86::POPCNT64rr,      X86::POPCNT64rm,          0 },
    791     { X86::RORX32ri,        X86::RORX32mi,            0 },
    792     { X86::RORX64ri,        X86::RORX64mi,            0 },
    793     { X86::SARX32rr,        X86::SARX32rm,            0 },
    794     { X86::SARX64rr,        X86::SARX64rm,            0 },
    795     { X86::SHRX32rr,        X86::SHRX32rm,            0 },
    796     { X86::SHRX64rr,        X86::SHRX64rm,            0 },
    797     { X86::SHLX32rr,        X86::SHLX32rm,            0 },
    798     { X86::SHLX64rr,        X86::SHLX64rm,            0 },
    799     { X86::T1MSKC32rr,      X86::T1MSKC32rm,          0 },
    800     { X86::T1MSKC64rr,      X86::T1MSKC64rm,          0 },
    801     { X86::TZCNT16rr,       X86::TZCNT16rm,           0 },
    802     { X86::TZCNT32rr,       X86::TZCNT32rm,           0 },
    803     { X86::TZCNT64rr,       X86::TZCNT64rm,           0 },
    804     { X86::TZMSK32rr,       X86::TZMSK32rm,           0 },
    805     { X86::TZMSK64rr,       X86::TZMSK64rm,           0 },
    806 
    807     // AVX-512 foldable instructions
    808     { X86::VMOV64toPQIZrr,  X86::VMOVQI2PQIZrm,       0 },
    809     { X86::VMOVDI2SSZrr,    X86::VMOVDI2SSZrm,        0 },
    810     { X86::VMOVAPDZrr,      X86::VMOVAPDZrm,          TB_ALIGN_64 },
    811     { X86::VMOVAPSZrr,      X86::VMOVAPSZrm,          TB_ALIGN_64 },
    812     { X86::VMOVDQA32Zrr,    X86::VMOVDQA32Zrm,        TB_ALIGN_64 },
    813     { X86::VMOVDQA64Zrr,    X86::VMOVDQA64Zrm,        TB_ALIGN_64 },
    814     { X86::VMOVDQU8Zrr,     X86::VMOVDQU8Zrm,         0 },
    815     { X86::VMOVDQU16Zrr,    X86::VMOVDQU16Zrm,        0 },
    816     { X86::VMOVDQU32Zrr,    X86::VMOVDQU32Zrm,        0 },
    817     { X86::VMOVDQU64Zrr,    X86::VMOVDQU64Zrm,        0 },
    818     { X86::VMOVUPDZrr,      X86::VMOVUPDZrm,          0 },
    819     { X86::VMOVUPSZrr,      X86::VMOVUPSZrm,          0 },
    820     { X86::VPABSDZrr,       X86::VPABSDZrm,           0 },
    821     { X86::VPABSQZrr,       X86::VPABSQZrm,           0 },
    822     { X86::VBROADCASTSSZr,  X86::VBROADCASTSSZm,      TB_NO_REVERSE },
    823     { X86::VBROADCASTSDZr,  X86::VBROADCASTSDZm,      TB_NO_REVERSE },
    824 
    825     // AVX-512 foldable instructions (256-bit versions)
    826     { X86::VMOVAPDZ256rr,      X86::VMOVAPDZ256rm,          TB_ALIGN_32 },
    827     { X86::VMOVAPSZ256rr,      X86::VMOVAPSZ256rm,          TB_ALIGN_32 },
    828     { X86::VMOVDQA32Z256rr,    X86::VMOVDQA32Z256rm,        TB_ALIGN_32 },
    829     { X86::VMOVDQA64Z256rr,    X86::VMOVDQA64Z256rm,        TB_ALIGN_32 },
    830     { X86::VMOVDQU8Z256rr,     X86::VMOVDQU8Z256rm,         0 },
    831     { X86::VMOVDQU16Z256rr,    X86::VMOVDQU16Z256rm,        0 },
    832     { X86::VMOVDQU32Z256rr,    X86::VMOVDQU32Z256rm,        0 },
    833     { X86::VMOVDQU64Z256rr,    X86::VMOVDQU64Z256rm,        0 },
    834     { X86::VMOVUPDZ256rr,      X86::VMOVUPDZ256rm,          0 },
    835     { X86::VMOVUPSZ256rr,      X86::VMOVUPSZ256rm,          0 },
    836     { X86::VBROADCASTSSZ256r,  X86::VBROADCASTSSZ256m,      TB_NO_REVERSE },
    837     { X86::VBROADCASTSDZ256r,  X86::VBROADCASTSDZ256m,      TB_NO_REVERSE },
    838 
    839     // AVX-512 foldable instructions (256-bit versions)
    840     { X86::VMOVAPDZ128rr,      X86::VMOVAPDZ128rm,          TB_ALIGN_16 },
    841     { X86::VMOVAPSZ128rr,      X86::VMOVAPSZ128rm,          TB_ALIGN_16 },
    842     { X86::VMOVDQA32Z128rr,    X86::VMOVDQA32Z128rm,        TB_ALIGN_16 },
    843     { X86::VMOVDQA64Z128rr,    X86::VMOVDQA64Z128rm,        TB_ALIGN_16 },
    844     { X86::VMOVDQU8Z128rr,     X86::VMOVDQU8Z128rm,         0 },
    845     { X86::VMOVDQU16Z128rr,    X86::VMOVDQU16Z128rm,        0 },
    846     { X86::VMOVDQU32Z128rr,    X86::VMOVDQU32Z128rm,        0 },
    847     { X86::VMOVDQU64Z128rr,    X86::VMOVDQU64Z128rm,        0 },
    848     { X86::VMOVUPDZ128rr,      X86::VMOVUPDZ128rm,          0 },
    849     { X86::VMOVUPSZ128rr,      X86::VMOVUPSZ128rm,          0 },
    850     { X86::VBROADCASTSSZ128r,  X86::VBROADCASTSSZ128m,      TB_NO_REVERSE },
    851 
    852     // F16C foldable instructions
    853     { X86::VCVTPH2PSrr,        X86::VCVTPH2PSrm,            0 },
    854     { X86::VCVTPH2PSYrr,       X86::VCVTPH2PSYrm,           0 },
    855 
    856     // AES foldable instructions
    857     { X86::AESIMCrr,              X86::AESIMCrm,              TB_ALIGN_16 },
    858     { X86::AESKEYGENASSIST128rr,  X86::AESKEYGENASSIST128rm,  TB_ALIGN_16 },
    859     { X86::VAESIMCrr,             X86::VAESIMCrm,             0 },
    860     { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
    861   };
    862 
    863   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
    864     AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
    865                   Entry.RegOp, Entry.MemOp,
    866                   // Index 1, folded load
    867                   Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
    868   }
    869 
    870   static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
    871     { X86::ADC32rr,         X86::ADC32rm,       0 },
    872     { X86::ADC64rr,         X86::ADC64rm,       0 },
    873     { X86::ADD16rr,         X86::ADD16rm,       0 },
    874     { X86::ADD16rr_DB,      X86::ADD16rm,       TB_NO_REVERSE },
    875     { X86::ADD32rr,         X86::ADD32rm,       0 },
    876     { X86::ADD32rr_DB,      X86::ADD32rm,       TB_NO_REVERSE },
    877     { X86::ADD64rr,         X86::ADD64rm,       0 },
    878     { X86::ADD64rr_DB,      X86::ADD64rm,       TB_NO_REVERSE },
    879     { X86::ADD8rr,          X86::ADD8rm,        0 },
    880     { X86::ADDPDrr,         X86::ADDPDrm,       TB_ALIGN_16 },
    881     { X86::ADDPSrr,         X86::ADDPSrm,       TB_ALIGN_16 },
    882     { X86::ADDSDrr,         X86::ADDSDrm,       0 },
    883     { X86::ADDSDrr_Int,     X86::ADDSDrm_Int,   0 },
    884     { X86::ADDSSrr,         X86::ADDSSrm,       0 },
    885     { X86::ADDSSrr_Int,     X86::ADDSSrm_Int,   0 },
    886     { X86::ADDSUBPDrr,      X86::ADDSUBPDrm,    TB_ALIGN_16 },
    887     { X86::ADDSUBPSrr,      X86::ADDSUBPSrm,    TB_ALIGN_16 },
    888     { X86::AND16rr,         X86::AND16rm,       0 },
    889     { X86::AND32rr,         X86::AND32rm,       0 },
    890     { X86::AND64rr,         X86::AND64rm,       0 },
    891     { X86::AND8rr,          X86::AND8rm,        0 },
    892     { X86::ANDNPDrr,        X86::ANDNPDrm,      TB_ALIGN_16 },
    893     { X86::ANDNPSrr,        X86::ANDNPSrm,      TB_ALIGN_16 },
    894     { X86::ANDPDrr,         X86::ANDPDrm,       TB_ALIGN_16 },
    895     { X86::ANDPSrr,         X86::ANDPSrm,       TB_ALIGN_16 },
    896     { X86::BLENDPDrri,      X86::BLENDPDrmi,    TB_ALIGN_16 },
    897     { X86::BLENDPSrri,      X86::BLENDPSrmi,    TB_ALIGN_16 },
    898     { X86::BLENDVPDrr0,     X86::BLENDVPDrm0,   TB_ALIGN_16 },
    899     { X86::BLENDVPSrr0,     X86::BLENDVPSrm0,   TB_ALIGN_16 },
    900     { X86::CMOVA16rr,       X86::CMOVA16rm,     0 },
    901     { X86::CMOVA32rr,       X86::CMOVA32rm,     0 },
    902     { X86::CMOVA64rr,       X86::CMOVA64rm,     0 },
    903     { X86::CMOVAE16rr,      X86::CMOVAE16rm,    0 },
    904     { X86::CMOVAE32rr,      X86::CMOVAE32rm,    0 },
    905     { X86::CMOVAE64rr,      X86::CMOVAE64rm,    0 },
    906     { X86::CMOVB16rr,       X86::CMOVB16rm,     0 },
    907     { X86::CMOVB32rr,       X86::CMOVB32rm,     0 },
    908     { X86::CMOVB64rr,       X86::CMOVB64rm,     0 },
    909     { X86::CMOVBE16rr,      X86::CMOVBE16rm,    0 },
    910     { X86::CMOVBE32rr,      X86::CMOVBE32rm,    0 },
    911     { X86::CMOVBE64rr,      X86::CMOVBE64rm,    0 },
    912     { X86::CMOVE16rr,       X86::CMOVE16rm,     0 },
    913     { X86::CMOVE32rr,       X86::CMOVE32rm,     0 },
    914     { X86::CMOVE64rr,       X86::CMOVE64rm,     0 },
    915     { X86::CMOVG16rr,       X86::CMOVG16rm,     0 },
    916     { X86::CMOVG32rr,       X86::CMOVG32rm,     0 },
    917     { X86::CMOVG64rr,       X86::CMOVG64rm,     0 },
    918     { X86::CMOVGE16rr,      X86::CMOVGE16rm,    0 },
    919     { X86::CMOVGE32rr,      X86::CMOVGE32rm,    0 },
    920     { X86::CMOVGE64rr,      X86::CMOVGE64rm,    0 },
    921     { X86::CMOVL16rr,       X86::CMOVL16rm,     0 },
    922     { X86::CMOVL32rr,       X86::CMOVL32rm,     0 },
    923     { X86::CMOVL64rr,       X86::CMOVL64rm,     0 },
    924     { X86::CMOVLE16rr,      X86::CMOVLE16rm,    0 },
    925     { X86::CMOVLE32rr,      X86::CMOVLE32rm,    0 },
    926     { X86::CMOVLE64rr,      X86::CMOVLE64rm,    0 },
    927     { X86::CMOVNE16rr,      X86::CMOVNE16rm,    0 },
    928     { X86::CMOVNE32rr,      X86::CMOVNE32rm,    0 },
    929     { X86::CMOVNE64rr,      X86::CMOVNE64rm,    0 },
    930     { X86::CMOVNO16rr,      X86::CMOVNO16rm,    0 },
    931     { X86::CMOVNO32rr,      X86::CMOVNO32rm,    0 },
    932     { X86::CMOVNO64rr,      X86::CMOVNO64rm,    0 },
    933     { X86::CMOVNP16rr,      X86::CMOVNP16rm,    0 },
    934     { X86::CMOVNP32rr,      X86::CMOVNP32rm,    0 },
    935     { X86::CMOVNP64rr,      X86::CMOVNP64rm,    0 },
    936     { X86::CMOVNS16rr,      X86::CMOVNS16rm,    0 },
    937     { X86::CMOVNS32rr,      X86::CMOVNS32rm,    0 },
    938     { X86::CMOVNS64rr,      X86::CMOVNS64rm,    0 },
    939     { X86::CMOVO16rr,       X86::CMOVO16rm,     0 },
    940     { X86::CMOVO32rr,       X86::CMOVO32rm,     0 },
    941     { X86::CMOVO64rr,       X86::CMOVO64rm,     0 },
    942     { X86::CMOVP16rr,       X86::CMOVP16rm,     0 },
    943     { X86::CMOVP32rr,       X86::CMOVP32rm,     0 },
    944     { X86::CMOVP64rr,       X86::CMOVP64rm,     0 },
    945     { X86::CMOVS16rr,       X86::CMOVS16rm,     0 },
    946     { X86::CMOVS32rr,       X86::CMOVS32rm,     0 },
    947     { X86::CMOVS64rr,       X86::CMOVS64rm,     0 },
    948     { X86::CMPPDrri,        X86::CMPPDrmi,      TB_ALIGN_16 },
    949     { X86::CMPPSrri,        X86::CMPPSrmi,      TB_ALIGN_16 },
    950     { X86::CMPSDrr,         X86::CMPSDrm,       0 },
    951     { X86::CMPSSrr,         X86::CMPSSrm,       0 },
    952     { X86::CRC32r32r32,     X86::CRC32r32m32,   0 },
    953     { X86::CRC32r64r64,     X86::CRC32r64m64,   0 },
    954     { X86::DIVPDrr,         X86::DIVPDrm,       TB_ALIGN_16 },
    955     { X86::DIVPSrr,         X86::DIVPSrm,       TB_ALIGN_16 },
    956     { X86::DIVSDrr,         X86::DIVSDrm,       0 },
    957     { X86::DIVSDrr_Int,     X86::DIVSDrm_Int,   0 },
    958     { X86::DIVSSrr,         X86::DIVSSrm,       0 },
    959     { X86::DIVSSrr_Int,     X86::DIVSSrm_Int,   0 },
    960     { X86::DPPDrri,         X86::DPPDrmi,       TB_ALIGN_16 },
    961     { X86::DPPSrri,         X86::DPPSrmi,       TB_ALIGN_16 },
    962 
    963     // Do not fold Fs* scalar logical op loads because there are no scalar
    964     // load variants for these instructions. When folded, the load is required
    965     // to be 128-bits, so the load size would not match.
    966 
    967     { X86::FvANDNPDrr,      X86::FvANDNPDrm,    TB_ALIGN_16 },
    968     { X86::FvANDNPSrr,      X86::FvANDNPSrm,    TB_ALIGN_16 },
    969     { X86::FvANDPDrr,       X86::FvANDPDrm,     TB_ALIGN_16 },
    970     { X86::FvANDPSrr,       X86::FvANDPSrm,     TB_ALIGN_16 },
    971     { X86::FvORPDrr,        X86::FvORPDrm,      TB_ALIGN_16 },
    972     { X86::FvORPSrr,        X86::FvORPSrm,      TB_ALIGN_16 },
    973     { X86::FvXORPDrr,       X86::FvXORPDrm,     TB_ALIGN_16 },
    974     { X86::FvXORPSrr,       X86::FvXORPSrm,     TB_ALIGN_16 },
    975     { X86::HADDPDrr,        X86::HADDPDrm,      TB_ALIGN_16 },
    976     { X86::HADDPSrr,        X86::HADDPSrm,      TB_ALIGN_16 },
    977     { X86::HSUBPDrr,        X86::HSUBPDrm,      TB_ALIGN_16 },
    978     { X86::HSUBPSrr,        X86::HSUBPSrm,      TB_ALIGN_16 },
    979     { X86::IMUL16rr,        X86::IMUL16rm,      0 },
    980     { X86::IMUL32rr,        X86::IMUL32rm,      0 },
    981     { X86::IMUL64rr,        X86::IMUL64rm,      0 },
    982     { X86::Int_CMPSDrr,     X86::Int_CMPSDrm,   0 },
    983     { X86::Int_CMPSSrr,     X86::Int_CMPSSrm,   0 },
    984     { X86::Int_CVTSD2SSrr,  X86::Int_CVTSD2SSrm,      0 },
    985     { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm,    0 },
    986     { X86::Int_CVTSI2SDrr,  X86::Int_CVTSI2SDrm,      0 },
    987     { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm,    0 },
    988     { X86::Int_CVTSI2SSrr,  X86::Int_CVTSI2SSrm,      0 },
    989     { X86::Int_CVTSS2SDrr,  X86::Int_CVTSS2SDrm,      0 },
    990     { X86::MAXPDrr,         X86::MAXPDrm,       TB_ALIGN_16 },
    991     { X86::MAXPSrr,         X86::MAXPSrm,       TB_ALIGN_16 },
    992     { X86::MAXSDrr,         X86::MAXSDrm,       0 },
    993     { X86::MAXSDrr_Int,     X86::MAXSDrm_Int,   0 },
    994     { X86::MAXSSrr,         X86::MAXSSrm,       0 },
    995     { X86::MAXSSrr_Int,     X86::MAXSSrm_Int,   0 },
    996     { X86::MINPDrr,         X86::MINPDrm,       TB_ALIGN_16 },
    997     { X86::MINPSrr,         X86::MINPSrm,       TB_ALIGN_16 },
    998     { X86::MINSDrr,         X86::MINSDrm,       0 },
    999     { X86::MINSDrr_Int,     X86::MINSDrm_Int,   0 },
   1000     { X86::MINSSrr,         X86::MINSSrm,       0 },
   1001     { X86::MINSSrr_Int,     X86::MINSSrm_Int,   0 },
   1002     { X86::MPSADBWrri,      X86::MPSADBWrmi,    TB_ALIGN_16 },
   1003     { X86::MULPDrr,         X86::MULPDrm,       TB_ALIGN_16 },
   1004     { X86::MULPSrr,         X86::MULPSrm,       TB_ALIGN_16 },
   1005     { X86::MULSDrr,         X86::MULSDrm,       0 },
   1006     { X86::MULSDrr_Int,     X86::MULSDrm_Int,   0 },
   1007     { X86::MULSSrr,         X86::MULSSrm,       0 },
   1008     { X86::MULSSrr_Int,     X86::MULSSrm_Int,   0 },
   1009     { X86::OR16rr,          X86::OR16rm,        0 },
   1010     { X86::OR32rr,          X86::OR32rm,        0 },
   1011     { X86::OR64rr,          X86::OR64rm,        0 },
   1012     { X86::OR8rr,           X86::OR8rm,         0 },
   1013     { X86::ORPDrr,          X86::ORPDrm,        TB_ALIGN_16 },
   1014     { X86::ORPSrr,          X86::ORPSrm,        TB_ALIGN_16 },
   1015     { X86::PACKSSDWrr,      X86::PACKSSDWrm,    TB_ALIGN_16 },
   1016     { X86::PACKSSWBrr,      X86::PACKSSWBrm,    TB_ALIGN_16 },
   1017     { X86::PACKUSDWrr,      X86::PACKUSDWrm,    TB_ALIGN_16 },
   1018     { X86::PACKUSWBrr,      X86::PACKUSWBrm,    TB_ALIGN_16 },
   1019     { X86::PADDBrr,         X86::PADDBrm,       TB_ALIGN_16 },
   1020     { X86::PADDDrr,         X86::PADDDrm,       TB_ALIGN_16 },
   1021     { X86::PADDQrr,         X86::PADDQrm,       TB_ALIGN_16 },
   1022     { X86::PADDSBrr,        X86::PADDSBrm,      TB_ALIGN_16 },
   1023     { X86::PADDSWrr,        X86::PADDSWrm,      TB_ALIGN_16 },
   1024     { X86::PADDUSBrr,       X86::PADDUSBrm,     TB_ALIGN_16 },
   1025     { X86::PADDUSWrr,       X86::PADDUSWrm,     TB_ALIGN_16 },
   1026     { X86::PADDWrr,         X86::PADDWrm,       TB_ALIGN_16 },
   1027     { X86::PALIGNR128rr,    X86::PALIGNR128rm,  TB_ALIGN_16 },
   1028     { X86::PANDNrr,         X86::PANDNrm,       TB_ALIGN_16 },
   1029     { X86::PANDrr,          X86::PANDrm,        TB_ALIGN_16 },
   1030     { X86::PAVGBrr,         X86::PAVGBrm,       TB_ALIGN_16 },
   1031     { X86::PAVGWrr,         X86::PAVGWrm,       TB_ALIGN_16 },
   1032     { X86::PBLENDVBrr0,     X86::PBLENDVBrm0,   TB_ALIGN_16 },
   1033     { X86::PBLENDWrri,      X86::PBLENDWrmi,    TB_ALIGN_16 },
   1034     { X86::PCLMULQDQrr,     X86::PCLMULQDQrm,   TB_ALIGN_16 },
   1035     { X86::PCMPEQBrr,       X86::PCMPEQBrm,     TB_ALIGN_16 },
   1036     { X86::PCMPEQDrr,       X86::PCMPEQDrm,     TB_ALIGN_16 },
   1037     { X86::PCMPEQQrr,       X86::PCMPEQQrm,     TB_ALIGN_16 },
   1038     { X86::PCMPEQWrr,       X86::PCMPEQWrm,     TB_ALIGN_16 },
   1039     { X86::PCMPGTBrr,       X86::PCMPGTBrm,     TB_ALIGN_16 },
   1040     { X86::PCMPGTDrr,       X86::PCMPGTDrm,     TB_ALIGN_16 },
   1041     { X86::PCMPGTQrr,       X86::PCMPGTQrm,     TB_ALIGN_16 },
   1042     { X86::PCMPGTWrr,       X86::PCMPGTWrm,     TB_ALIGN_16 },
   1043     { X86::PHADDDrr,        X86::PHADDDrm,      TB_ALIGN_16 },
   1044     { X86::PHADDWrr,        X86::PHADDWrm,      TB_ALIGN_16 },
   1045     { X86::PHADDSWrr128,    X86::PHADDSWrm128,  TB_ALIGN_16 },
   1046     { X86::PHSUBDrr,        X86::PHSUBDrm,      TB_ALIGN_16 },
   1047     { X86::PHSUBSWrr128,    X86::PHSUBSWrm128,  TB_ALIGN_16 },
   1048     { X86::PHSUBWrr,        X86::PHSUBWrm,      TB_ALIGN_16 },
   1049     { X86::PINSRBrr,        X86::PINSRBrm,      0 },
   1050     { X86::PINSRDrr,        X86::PINSRDrm,      0 },
   1051     { X86::PINSRQrr,        X86::PINSRQrm,      0 },
   1052     { X86::PINSRWrri,       X86::PINSRWrmi,     0 },
   1053     { X86::PMADDUBSWrr128,  X86::PMADDUBSWrm128, TB_ALIGN_16 },
   1054     { X86::PMADDWDrr,       X86::PMADDWDrm,     TB_ALIGN_16 },
   1055     { X86::PMAXSWrr,        X86::PMAXSWrm,      TB_ALIGN_16 },
   1056     { X86::PMAXUBrr,        X86::PMAXUBrm,      TB_ALIGN_16 },
   1057     { X86::PMINSWrr,        X86::PMINSWrm,      TB_ALIGN_16 },
   1058     { X86::PMINUBrr,        X86::PMINUBrm,      TB_ALIGN_16 },
   1059     { X86::PMINSBrr,        X86::PMINSBrm,      TB_ALIGN_16 },
   1060     { X86::PMINSDrr,        X86::PMINSDrm,      TB_ALIGN_16 },
   1061     { X86::PMINUDrr,        X86::PMINUDrm,      TB_ALIGN_16 },
   1062     { X86::PMINUWrr,        X86::PMINUWrm,      TB_ALIGN_16 },
   1063     { X86::PMAXSBrr,        X86::PMAXSBrm,      TB_ALIGN_16 },
   1064     { X86::PMAXSDrr,        X86::PMAXSDrm,      TB_ALIGN_16 },
   1065     { X86::PMAXUDrr,        X86::PMAXUDrm,      TB_ALIGN_16 },
   1066     { X86::PMAXUWrr,        X86::PMAXUWrm,      TB_ALIGN_16 },
   1067     { X86::PMULDQrr,        X86::PMULDQrm,      TB_ALIGN_16 },
   1068     { X86::PMULHRSWrr128,   X86::PMULHRSWrm128, TB_ALIGN_16 },
   1069     { X86::PMULHUWrr,       X86::PMULHUWrm,     TB_ALIGN_16 },
   1070     { X86::PMULHWrr,        X86::PMULHWrm,      TB_ALIGN_16 },
   1071     { X86::PMULLDrr,        X86::PMULLDrm,      TB_ALIGN_16 },
   1072     { X86::PMULLWrr,        X86::PMULLWrm,      TB_ALIGN_16 },
   1073     { X86::PMULUDQrr,       X86::PMULUDQrm,     TB_ALIGN_16 },
   1074     { X86::PORrr,           X86::PORrm,         TB_ALIGN_16 },
   1075     { X86::PSADBWrr,        X86::PSADBWrm,      TB_ALIGN_16 },
   1076     { X86::PSHUFBrr,        X86::PSHUFBrm,      TB_ALIGN_16 },
   1077     { X86::PSIGNBrr,        X86::PSIGNBrm,      TB_ALIGN_16 },
   1078     { X86::PSIGNWrr,        X86::PSIGNWrm,      TB_ALIGN_16 },
   1079     { X86::PSIGNDrr,        X86::PSIGNDrm,      TB_ALIGN_16 },
   1080     { X86::PSLLDrr,         X86::PSLLDrm,       TB_ALIGN_16 },
   1081     { X86::PSLLQrr,         X86::PSLLQrm,       TB_ALIGN_16 },
   1082     { X86::PSLLWrr,         X86::PSLLWrm,       TB_ALIGN_16 },
   1083     { X86::PSRADrr,         X86::PSRADrm,       TB_ALIGN_16 },
   1084     { X86::PSRAWrr,         X86::PSRAWrm,       TB_ALIGN_16 },
   1085     { X86::PSRLDrr,         X86::PSRLDrm,       TB_ALIGN_16 },
   1086     { X86::PSRLQrr,         X86::PSRLQrm,       TB_ALIGN_16 },
   1087     { X86::PSRLWrr,         X86::PSRLWrm,       TB_ALIGN_16 },
   1088     { X86::PSUBBrr,         X86::PSUBBrm,       TB_ALIGN_16 },
   1089     { X86::PSUBDrr,         X86::PSUBDrm,       TB_ALIGN_16 },
   1090     { X86::PSUBQrr,         X86::PSUBQrm,       TB_ALIGN_16 },
   1091     { X86::PSUBSBrr,        X86::PSUBSBrm,      TB_ALIGN_16 },
   1092     { X86::PSUBSWrr,        X86::PSUBSWrm,      TB_ALIGN_16 },
   1093     { X86::PSUBUSBrr,       X86::PSUBUSBrm,     TB_ALIGN_16 },
   1094     { X86::PSUBUSWrr,       X86::PSUBUSWrm,     TB_ALIGN_16 },
   1095     { X86::PSUBWrr,         X86::PSUBWrm,       TB_ALIGN_16 },
   1096     { X86::PUNPCKHBWrr,     X86::PUNPCKHBWrm,   TB_ALIGN_16 },
   1097     { X86::PUNPCKHDQrr,     X86::PUNPCKHDQrm,   TB_ALIGN_16 },
   1098     { X86::PUNPCKHQDQrr,    X86::PUNPCKHQDQrm,  TB_ALIGN_16 },
   1099     { X86::PUNPCKHWDrr,     X86::PUNPCKHWDrm,   TB_ALIGN_16 },
   1100     { X86::PUNPCKLBWrr,     X86::PUNPCKLBWrm,   TB_ALIGN_16 },
   1101     { X86::PUNPCKLDQrr,     X86::PUNPCKLDQrm,   TB_ALIGN_16 },
   1102     { X86::PUNPCKLQDQrr,    X86::PUNPCKLQDQrm,  TB_ALIGN_16 },
   1103     { X86::PUNPCKLWDrr,     X86::PUNPCKLWDrm,   TB_ALIGN_16 },
   1104     { X86::PXORrr,          X86::PXORrm,        TB_ALIGN_16 },
   1105     { X86::ROUNDSDr,        X86::ROUNDSDm,      0 },
   1106     { X86::ROUNDSSr,        X86::ROUNDSSm,      0 },
   1107     { X86::SBB32rr,         X86::SBB32rm,       0 },
   1108     { X86::SBB64rr,         X86::SBB64rm,       0 },
   1109     { X86::SHUFPDrri,       X86::SHUFPDrmi,     TB_ALIGN_16 },
   1110     { X86::SHUFPSrri,       X86::SHUFPSrmi,     TB_ALIGN_16 },
   1111     { X86::SUB16rr,         X86::SUB16rm,       0 },
   1112     { X86::SUB32rr,         X86::SUB32rm,       0 },
   1113     { X86::SUB64rr,         X86::SUB64rm,       0 },
   1114     { X86::SUB8rr,          X86::SUB8rm,        0 },
   1115     { X86::SUBPDrr,         X86::SUBPDrm,       TB_ALIGN_16 },
   1116     { X86::SUBPSrr,         X86::SUBPSrm,       TB_ALIGN_16 },
   1117     { X86::SUBSDrr,         X86::SUBSDrm,       0 },
   1118     { X86::SUBSDrr_Int,     X86::SUBSDrm_Int,   0 },
   1119     { X86::SUBSSrr,         X86::SUBSSrm,       0 },
   1120     { X86::SUBSSrr_Int,     X86::SUBSSrm_Int,   0 },
   1121     // FIXME: TEST*rr -> swapped operand of TEST*mr.
   1122     { X86::UNPCKHPDrr,      X86::UNPCKHPDrm,    TB_ALIGN_16 },
   1123     { X86::UNPCKHPSrr,      X86::UNPCKHPSrm,    TB_ALIGN_16 },
   1124     { X86::UNPCKLPDrr,      X86::UNPCKLPDrm,    TB_ALIGN_16 },
   1125     { X86::UNPCKLPSrr,      X86::UNPCKLPSrm,    TB_ALIGN_16 },
   1126     { X86::XOR16rr,         X86::XOR16rm,       0 },
   1127     { X86::XOR32rr,         X86::XOR32rm,       0 },
   1128     { X86::XOR64rr,         X86::XOR64rm,       0 },
   1129     { X86::XOR8rr,          X86::XOR8rm,        0 },
   1130     { X86::XORPDrr,         X86::XORPDrm,       TB_ALIGN_16 },
   1131     { X86::XORPSrr,         X86::XORPSrm,       TB_ALIGN_16 },
   1132 
   1133     // MMX version of foldable instructions
   1134     { X86::MMX_CVTPI2PSirr,   X86::MMX_CVTPI2PSirm,   0 },
   1135     { X86::MMX_PACKSSDWirr,   X86::MMX_PACKSSDWirm,   0 },
   1136     { X86::MMX_PACKSSWBirr,   X86::MMX_PACKSSWBirm,   0 },
   1137     { X86::MMX_PACKUSWBirr,   X86::MMX_PACKUSWBirm,   0 },
   1138     { X86::MMX_PADDBirr,      X86::MMX_PADDBirm,      0 },
   1139     { X86::MMX_PADDDirr,      X86::MMX_PADDDirm,      0 },
   1140     { X86::MMX_PADDQirr,      X86::MMX_PADDQirm,      0 },
   1141     { X86::MMX_PADDSBirr,     X86::MMX_PADDSBirm,     0 },
   1142     { X86::MMX_PADDSWirr,     X86::MMX_PADDSWirm,     0 },
   1143     { X86::MMX_PADDUSBirr,    X86::MMX_PADDUSBirm,    0 },
   1144     { X86::MMX_PADDUSWirr,    X86::MMX_PADDUSWirm,    0 },
   1145     { X86::MMX_PADDWirr,      X86::MMX_PADDWirm,      0 },
   1146     { X86::MMX_PALIGNR64irr,  X86::MMX_PALIGNR64irm,  0 },
   1147     { X86::MMX_PANDNirr,      X86::MMX_PANDNirm,      0 },
   1148     { X86::MMX_PANDirr,       X86::MMX_PANDirm,       0 },
   1149     { X86::MMX_PAVGBirr,      X86::MMX_PAVGBirm,      0 },
   1150     { X86::MMX_PAVGWirr,      X86::MMX_PAVGWirm,      0 },
   1151     { X86::MMX_PCMPEQBirr,    X86::MMX_PCMPEQBirm,    0 },
   1152     { X86::MMX_PCMPEQDirr,    X86::MMX_PCMPEQDirm,    0 },
   1153     { X86::MMX_PCMPEQWirr,    X86::MMX_PCMPEQWirm,    0 },
   1154     { X86::MMX_PCMPGTBirr,    X86::MMX_PCMPGTBirm,    0 },
   1155     { X86::MMX_PCMPGTDirr,    X86::MMX_PCMPGTDirm,    0 },
   1156     { X86::MMX_PCMPGTWirr,    X86::MMX_PCMPGTWirm,    0 },
   1157     { X86::MMX_PHADDSWrr64,   X86::MMX_PHADDSWrm64,   0 },
   1158     { X86::MMX_PHADDWrr64,    X86::MMX_PHADDWrm64,    0 },
   1159     { X86::MMX_PHADDrr64,     X86::MMX_PHADDrm64,     0 },
   1160     { X86::MMX_PHSUBDrr64,    X86::MMX_PHSUBDrm64,    0 },
   1161     { X86::MMX_PHSUBSWrr64,   X86::MMX_PHSUBSWrm64,   0 },
   1162     { X86::MMX_PHSUBWrr64,    X86::MMX_PHSUBWrm64,    0 },
   1163     { X86::MMX_PINSRWirri,    X86::MMX_PINSRWirmi,    0 },
   1164     { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
   1165     { X86::MMX_PMADDWDirr,    X86::MMX_PMADDWDirm,    0 },
   1166     { X86::MMX_PMAXSWirr,     X86::MMX_PMAXSWirm,     0 },
   1167     { X86::MMX_PMAXUBirr,     X86::MMX_PMAXUBirm,     0 },
   1168     { X86::MMX_PMINSWirr,     X86::MMX_PMINSWirm,     0 },
   1169     { X86::MMX_PMINUBirr,     X86::MMX_PMINUBirm,     0 },
   1170     { X86::MMX_PMULHRSWrr64,  X86::MMX_PMULHRSWrm64,  0 },
   1171     { X86::MMX_PMULHUWirr,    X86::MMX_PMULHUWirm,    0 },
   1172     { X86::MMX_PMULHWirr,     X86::MMX_PMULHWirm,     0 },
   1173     { X86::MMX_PMULLWirr,     X86::MMX_PMULLWirm,     0 },
   1174     { X86::MMX_PMULUDQirr,    X86::MMX_PMULUDQirm,    0 },
   1175     { X86::MMX_PORirr,        X86::MMX_PORirm,        0 },
   1176     { X86::MMX_PSADBWirr,     X86::MMX_PSADBWirm,     0 },
   1177     { X86::MMX_PSHUFBrr64,    X86::MMX_PSHUFBrm64,    0 },
   1178     { X86::MMX_PSIGNBrr64,    X86::MMX_PSIGNBrm64,    0 },
   1179     { X86::MMX_PSIGNDrr64,    X86::MMX_PSIGNDrm64,    0 },
   1180     { X86::MMX_PSIGNWrr64,    X86::MMX_PSIGNWrm64,    0 },
   1181     { X86::MMX_PSLLDrr,       X86::MMX_PSLLDrm,       0 },
   1182     { X86::MMX_PSLLQrr,       X86::MMX_PSLLQrm,       0 },
   1183     { X86::MMX_PSLLWrr,       X86::MMX_PSLLWrm,       0 },
   1184     { X86::MMX_PSRADrr,       X86::MMX_PSRADrm,       0 },
   1185     { X86::MMX_PSRAWrr,       X86::MMX_PSRAWrm,       0 },
   1186     { X86::MMX_PSRLDrr,       X86::MMX_PSRLDrm,       0 },
   1187     { X86::MMX_PSRLQrr,       X86::MMX_PSRLQrm,       0 },
   1188     { X86::MMX_PSRLWrr,       X86::MMX_PSRLWrm,       0 },
   1189     { X86::MMX_PSUBBirr,      X86::MMX_PSUBBirm,      0 },
   1190     { X86::MMX_PSUBDirr,      X86::MMX_PSUBDirm,      0 },
   1191     { X86::MMX_PSUBQirr,      X86::MMX_PSUBQirm,      0 },
   1192     { X86::MMX_PSUBSBirr,     X86::MMX_PSUBSBirm,     0 },
   1193     { X86::MMX_PSUBSWirr,     X86::MMX_PSUBSWirm,     0 },
   1194     { X86::MMX_PSUBUSBirr,    X86::MMX_PSUBUSBirm,    0 },
   1195     { X86::MMX_PSUBUSWirr,    X86::MMX_PSUBUSWirm,    0 },
   1196     { X86::MMX_PSUBWirr,      X86::MMX_PSUBWirm,      0 },
   1197     { X86::MMX_PUNPCKHBWirr,  X86::MMX_PUNPCKHBWirm,  0 },
   1198     { X86::MMX_PUNPCKHDQirr,  X86::MMX_PUNPCKHDQirm,  0 },
   1199     { X86::MMX_PUNPCKHWDirr,  X86::MMX_PUNPCKHWDirm,  0 },
   1200     { X86::MMX_PUNPCKLBWirr,  X86::MMX_PUNPCKLBWirm,  0 },
   1201     { X86::MMX_PUNPCKLDQirr,  X86::MMX_PUNPCKLDQirm,  0 },
   1202     { X86::MMX_PUNPCKLWDirr,  X86::MMX_PUNPCKLWDirm,  0 },
   1203     { X86::MMX_PXORirr,       X86::MMX_PXORirm,       0 },
   1204 
   1205     // 3DNow! version of foldable instructions
   1206     { X86::PAVGUSBrr,         X86::PAVGUSBrm,         0 },
   1207     { X86::PFACCrr,           X86::PFACCrm,           0 },
   1208     { X86::PFADDrr,           X86::PFADDrm,           0 },
   1209     { X86::PFCMPEQrr,         X86::PFCMPEQrm,         0 },
   1210     { X86::PFCMPGErr,         X86::PFCMPGErm,         0 },
   1211     { X86::PFCMPGTrr,         X86::PFCMPGTrm,         0 },
   1212     { X86::PFMAXrr,           X86::PFMAXrm,           0 },
   1213     { X86::PFMINrr,           X86::PFMINrm,           0 },
   1214     { X86::PFMULrr,           X86::PFMULrm,           0 },
   1215     { X86::PFNACCrr,          X86::PFNACCrm,          0 },
   1216     { X86::PFPNACCrr,         X86::PFPNACCrm,         0 },
   1217     { X86::PFRCPIT1rr,        X86::PFRCPIT1rm,        0 },
   1218     { X86::PFRCPIT2rr,        X86::PFRCPIT2rm,        0 },
   1219     { X86::PFRSQIT1rr,        X86::PFRSQIT1rm,        0 },
   1220     { X86::PFSUBrr,           X86::PFSUBrm,           0 },
   1221     { X86::PFSUBRrr,          X86::PFSUBRrm,          0 },
   1222     { X86::PMULHRWrr,         X86::PMULHRWrm,         0 },
   1223 
   1224     // AVX 128-bit versions of foldable instructions
   1225     { X86::VCVTSD2SSrr,       X86::VCVTSD2SSrm,        0 },
   1226     { X86::Int_VCVTSD2SSrr,   X86::Int_VCVTSD2SSrm,    0 },
   1227     { X86::VCVTSI2SD64rr,     X86::VCVTSI2SD64rm,      0 },
   1228     { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm,  0 },
   1229     { X86::VCVTSI2SDrr,       X86::VCVTSI2SDrm,        0 },
   1230     { X86::Int_VCVTSI2SDrr,   X86::Int_VCVTSI2SDrm,    0 },
   1231     { X86::VCVTSI2SS64rr,     X86::VCVTSI2SS64rm,      0 },
   1232     { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm,  0 },
   1233     { X86::VCVTSI2SSrr,       X86::VCVTSI2SSrm,        0 },
   1234     { X86::Int_VCVTSI2SSrr,   X86::Int_VCVTSI2SSrm,    0 },
   1235     { X86::VCVTSS2SDrr,       X86::VCVTSS2SDrm,        0 },
   1236     { X86::Int_VCVTSS2SDrr,   X86::Int_VCVTSS2SDrm,    0 },
   1237     { X86::VRCPSSr,           X86::VRCPSSm,            0 },
   1238     { X86::VRCPSSr_Int,       X86::VRCPSSm_Int,        0 },
   1239     { X86::VRSQRTSSr,         X86::VRSQRTSSm,          0 },
   1240     { X86::VRSQRTSSr_Int,     X86::VRSQRTSSm_Int,      0 },
   1241     { X86::VSQRTSDr,          X86::VSQRTSDm,           0 },
   1242     { X86::VSQRTSDr_Int,      X86::VSQRTSDm_Int,       0 },
   1243     { X86::VSQRTSSr,          X86::VSQRTSSm,           0 },
   1244     { X86::VSQRTSSr_Int,      X86::VSQRTSSm_Int,       0 },
   1245     { X86::VADDPDrr,          X86::VADDPDrm,           0 },
   1246     { X86::VADDPSrr,          X86::VADDPSrm,           0 },
   1247     { X86::VADDSDrr,          X86::VADDSDrm,           0 },
   1248     { X86::VADDSDrr_Int,      X86::VADDSDrm_Int,       0 },
   1249     { X86::VADDSSrr,          X86::VADDSSrm,           0 },
   1250     { X86::VADDSSrr_Int,      X86::VADDSSrm_Int,       0 },
   1251     { X86::VADDSUBPDrr,       X86::VADDSUBPDrm,        0 },
   1252     { X86::VADDSUBPSrr,       X86::VADDSUBPSrm,        0 },
   1253     { X86::VANDNPDrr,         X86::VANDNPDrm,          0 },
   1254     { X86::VANDNPSrr,         X86::VANDNPSrm,          0 },
   1255     { X86::VANDPDrr,          X86::VANDPDrm,           0 },
   1256     { X86::VANDPSrr,          X86::VANDPSrm,           0 },
   1257     { X86::VBLENDPDrri,       X86::VBLENDPDrmi,        0 },
   1258     { X86::VBLENDPSrri,       X86::VBLENDPSrmi,        0 },
   1259     { X86::VBLENDVPDrr,       X86::VBLENDVPDrm,        0 },
   1260     { X86::VBLENDVPSrr,       X86::VBLENDVPSrm,        0 },
   1261     { X86::VCMPPDrri,         X86::VCMPPDrmi,          0 },
   1262     { X86::VCMPPSrri,         X86::VCMPPSrmi,          0 },
   1263     { X86::VCMPSDrr,          X86::VCMPSDrm,           0 },
   1264     { X86::VCMPSSrr,          X86::VCMPSSrm,           0 },
   1265     { X86::VDIVPDrr,          X86::VDIVPDrm,           0 },
   1266     { X86::VDIVPSrr,          X86::VDIVPSrm,           0 },
   1267     { X86::VDIVSDrr,          X86::VDIVSDrm,           0 },
   1268     { X86::VDIVSDrr_Int,      X86::VDIVSDrm_Int,       0 },
   1269     { X86::VDIVSSrr,          X86::VDIVSSrm,           0 },
   1270     { X86::VDIVSSrr_Int,      X86::VDIVSSrm_Int,       0 },
   1271     { X86::VDPPDrri,          X86::VDPPDrmi,           0 },
   1272     { X86::VDPPSrri,          X86::VDPPSrmi,           0 },
   1273     // Do not fold VFs* loads because there are no scalar load variants for
   1274     // these instructions. When folded, the load is required to be 128-bits, so
   1275     // the load size would not match.
   1276     { X86::VFvANDNPDrr,       X86::VFvANDNPDrm,        0 },
   1277     { X86::VFvANDNPSrr,       X86::VFvANDNPSrm,        0 },
   1278     { X86::VFvANDPDrr,        X86::VFvANDPDrm,         0 },
   1279     { X86::VFvANDPSrr,        X86::VFvANDPSrm,         0 },
   1280     { X86::VFvORPDrr,         X86::VFvORPDrm,          0 },
   1281     { X86::VFvORPSrr,         X86::VFvORPSrm,          0 },
   1282     { X86::VFvXORPDrr,        X86::VFvXORPDrm,         0 },
   1283     { X86::VFvXORPSrr,        X86::VFvXORPSrm,         0 },
   1284     { X86::VHADDPDrr,         X86::VHADDPDrm,          0 },
   1285     { X86::VHADDPSrr,         X86::VHADDPSrm,          0 },
   1286     { X86::VHSUBPDrr,         X86::VHSUBPDrm,          0 },
   1287     { X86::VHSUBPSrr,         X86::VHSUBPSrm,          0 },
   1288     { X86::Int_VCMPSDrr,      X86::Int_VCMPSDrm,       0 },
   1289     { X86::Int_VCMPSSrr,      X86::Int_VCMPSSrm,       0 },
   1290     { X86::VMAXPDrr,          X86::VMAXPDrm,           0 },
   1291     { X86::VMAXPSrr,          X86::VMAXPSrm,           0 },
   1292     { X86::VMAXSDrr,          X86::VMAXSDrm,           0 },
   1293     { X86::VMAXSDrr_Int,      X86::VMAXSDrm_Int,       0 },
   1294     { X86::VMAXSSrr,          X86::VMAXSSrm,           0 },
   1295     { X86::VMAXSSrr_Int,      X86::VMAXSSrm_Int,       0 },
   1296     { X86::VMINPDrr,          X86::VMINPDrm,           0 },
   1297     { X86::VMINPSrr,          X86::VMINPSrm,           0 },
   1298     { X86::VMINSDrr,          X86::VMINSDrm,           0 },
   1299     { X86::VMINSDrr_Int,      X86::VMINSDrm_Int,       0 },
   1300     { X86::VMINSSrr,          X86::VMINSSrm,           0 },
   1301     { X86::VMINSSrr_Int,      X86::VMINSSrm_Int,       0 },
   1302     { X86::VMPSADBWrri,       X86::VMPSADBWrmi,        0 },
   1303     { X86::VMULPDrr,          X86::VMULPDrm,           0 },
   1304     { X86::VMULPSrr,          X86::VMULPSrm,           0 },
   1305     { X86::VMULSDrr,          X86::VMULSDrm,           0 },
   1306     { X86::VMULSDrr_Int,      X86::VMULSDrm_Int,       0 },
   1307     { X86::VMULSSrr,          X86::VMULSSrm,           0 },
   1308     { X86::VMULSSrr_Int,      X86::VMULSSrm_Int,       0 },
   1309     { X86::VORPDrr,           X86::VORPDrm,            0 },
   1310     { X86::VORPSrr,           X86::VORPSrm,            0 },
   1311     { X86::VPACKSSDWrr,       X86::VPACKSSDWrm,        0 },
   1312     { X86::VPACKSSWBrr,       X86::VPACKSSWBrm,        0 },
   1313     { X86::VPACKUSDWrr,       X86::VPACKUSDWrm,        0 },
   1314     { X86::VPACKUSWBrr,       X86::VPACKUSWBrm,        0 },
   1315     { X86::VPADDBrr,          X86::VPADDBrm,           0 },
   1316     { X86::VPADDDrr,          X86::VPADDDrm,           0 },
   1317     { X86::VPADDQrr,          X86::VPADDQrm,           0 },
   1318     { X86::VPADDSBrr,         X86::VPADDSBrm,          0 },
   1319     { X86::VPADDSWrr,         X86::VPADDSWrm,          0 },
   1320     { X86::VPADDUSBrr,        X86::VPADDUSBrm,         0 },
   1321     { X86::VPADDUSWrr,        X86::VPADDUSWrm,         0 },
   1322     { X86::VPADDWrr,          X86::VPADDWrm,           0 },
   1323     { X86::VPALIGNR128rr,     X86::VPALIGNR128rm,      0 },
   1324     { X86::VPANDNrr,          X86::VPANDNrm,           0 },
   1325     { X86::VPANDrr,           X86::VPANDrm,            0 },
   1326     { X86::VPAVGBrr,          X86::VPAVGBrm,           0 },
   1327     { X86::VPAVGWrr,          X86::VPAVGWrm,           0 },
   1328     { X86::VPBLENDVBrr,       X86::VPBLENDVBrm,        0 },
   1329     { X86::VPBLENDWrri,       X86::VPBLENDWrmi,        0 },
   1330     { X86::VPCLMULQDQrr,      X86::VPCLMULQDQrm,       0 },
   1331     { X86::VPCMPEQBrr,        X86::VPCMPEQBrm,         0 },
   1332     { X86::VPCMPEQDrr,        X86::VPCMPEQDrm,         0 },
   1333     { X86::VPCMPEQQrr,        X86::VPCMPEQQrm,         0 },
   1334     { X86::VPCMPEQWrr,        X86::VPCMPEQWrm,         0 },
   1335     { X86::VPCMPGTBrr,        X86::VPCMPGTBrm,         0 },
   1336     { X86::VPCMPGTDrr,        X86::VPCMPGTDrm,         0 },
   1337     { X86::VPCMPGTQrr,        X86::VPCMPGTQrm,         0 },
   1338     { X86::VPCMPGTWrr,        X86::VPCMPGTWrm,         0 },
   1339     { X86::VPHADDDrr,         X86::VPHADDDrm,          0 },
   1340     { X86::VPHADDSWrr128,     X86::VPHADDSWrm128,      0 },
   1341     { X86::VPHADDWrr,         X86::VPHADDWrm,          0 },
   1342     { X86::VPHSUBDrr,         X86::VPHSUBDrm,          0 },
   1343     { X86::VPHSUBSWrr128,     X86::VPHSUBSWrm128,      0 },
   1344     { X86::VPHSUBWrr,         X86::VPHSUBWrm,          0 },
   1345     { X86::VPERMILPDrr,       X86::VPERMILPDrm,        0 },
   1346     { X86::VPERMILPSrr,       X86::VPERMILPSrm,        0 },
   1347     { X86::VPINSRBrr,         X86::VPINSRBrm,          0 },
   1348     { X86::VPINSRDrr,         X86::VPINSRDrm,          0 },
   1349     { X86::VPINSRQrr,         X86::VPINSRQrm,          0 },
   1350     { X86::VPINSRWrri,        X86::VPINSRWrmi,         0 },
   1351     { X86::VPMADDUBSWrr128,   X86::VPMADDUBSWrm128,    0 },
   1352     { X86::VPMADDWDrr,        X86::VPMADDWDrm,         0 },
   1353     { X86::VPMAXSWrr,         X86::VPMAXSWrm,          0 },
   1354     { X86::VPMAXUBrr,         X86::VPMAXUBrm,          0 },
   1355     { X86::VPMINSWrr,         X86::VPMINSWrm,          0 },
   1356     { X86::VPMINUBrr,         X86::VPMINUBrm,          0 },
   1357     { X86::VPMINSBrr,         X86::VPMINSBrm,          0 },
   1358     { X86::VPMINSDrr,         X86::VPMINSDrm,          0 },
   1359     { X86::VPMINUDrr,         X86::VPMINUDrm,          0 },
   1360     { X86::VPMINUWrr,         X86::VPMINUWrm,          0 },
   1361     { X86::VPMAXSBrr,         X86::VPMAXSBrm,          0 },
   1362     { X86::VPMAXSDrr,         X86::VPMAXSDrm,          0 },
   1363     { X86::VPMAXUDrr,         X86::VPMAXUDrm,          0 },
   1364     { X86::VPMAXUWrr,         X86::VPMAXUWrm,          0 },
   1365     { X86::VPMULDQrr,         X86::VPMULDQrm,          0 },
   1366     { X86::VPMULHRSWrr128,    X86::VPMULHRSWrm128,     0 },
   1367     { X86::VPMULHUWrr,        X86::VPMULHUWrm,         0 },
   1368     { X86::VPMULHWrr,         X86::VPMULHWrm,          0 },
   1369     { X86::VPMULLDrr,         X86::VPMULLDrm,          0 },
   1370     { X86::VPMULLWrr,         X86::VPMULLWrm,          0 },
   1371     { X86::VPMULUDQrr,        X86::VPMULUDQrm,         0 },
   1372     { X86::VPORrr,            X86::VPORrm,             0 },
   1373     { X86::VPSADBWrr,         X86::VPSADBWrm,          0 },
   1374     { X86::VPSHUFBrr,         X86::VPSHUFBrm,          0 },
   1375     { X86::VPSIGNBrr,         X86::VPSIGNBrm,          0 },
   1376     { X86::VPSIGNWrr,         X86::VPSIGNWrm,          0 },
   1377     { X86::VPSIGNDrr,         X86::VPSIGNDrm,          0 },
   1378     { X86::VPSLLDrr,          X86::VPSLLDrm,           0 },
   1379     { X86::VPSLLQrr,          X86::VPSLLQrm,           0 },
   1380     { X86::VPSLLWrr,          X86::VPSLLWrm,           0 },
   1381     { X86::VPSRADrr,          X86::VPSRADrm,           0 },
   1382     { X86::VPSRAWrr,          X86::VPSRAWrm,           0 },
   1383     { X86::VPSRLDrr,          X86::VPSRLDrm,           0 },
   1384     { X86::VPSRLQrr,          X86::VPSRLQrm,           0 },
   1385     { X86::VPSRLWrr,          X86::VPSRLWrm,           0 },
   1386     { X86::VPSUBBrr,          X86::VPSUBBrm,           0 },
   1387     { X86::VPSUBDrr,          X86::VPSUBDrm,           0 },
   1388     { X86::VPSUBQrr,          X86::VPSUBQrm,           0 },
   1389     { X86::VPSUBSBrr,         X86::VPSUBSBrm,          0 },
   1390     { X86::VPSUBSWrr,         X86::VPSUBSWrm,          0 },
   1391     { X86::VPSUBUSBrr,        X86::VPSUBUSBrm,         0 },
   1392     { X86::VPSUBUSWrr,        X86::VPSUBUSWrm,         0 },
   1393     { X86::VPSUBWrr,          X86::VPSUBWrm,           0 },
   1394     { X86::VPUNPCKHBWrr,      X86::VPUNPCKHBWrm,       0 },
   1395     { X86::VPUNPCKHDQrr,      X86::VPUNPCKHDQrm,       0 },
   1396     { X86::VPUNPCKHQDQrr,     X86::VPUNPCKHQDQrm,      0 },
   1397     { X86::VPUNPCKHWDrr,      X86::VPUNPCKHWDrm,       0 },
   1398     { X86::VPUNPCKLBWrr,      X86::VPUNPCKLBWrm,       0 },
   1399     { X86::VPUNPCKLDQrr,      X86::VPUNPCKLDQrm,       0 },
   1400     { X86::VPUNPCKLQDQrr,     X86::VPUNPCKLQDQrm,      0 },
   1401     { X86::VPUNPCKLWDrr,      X86::VPUNPCKLWDrm,       0 },
   1402     { X86::VPXORrr,           X86::VPXORrm,            0 },
   1403     { X86::VROUNDSDr,         X86::VROUNDSDm,          0 },
   1404     { X86::VROUNDSSr,         X86::VROUNDSSm,          0 },
   1405     { X86::VSHUFPDrri,        X86::VSHUFPDrmi,         0 },
   1406     { X86::VSHUFPSrri,        X86::VSHUFPSrmi,         0 },
   1407     { X86::VSUBPDrr,          X86::VSUBPDrm,           0 },
   1408     { X86::VSUBPSrr,          X86::VSUBPSrm,           0 },
   1409     { X86::VSUBSDrr,          X86::VSUBSDrm,           0 },
   1410     { X86::VSUBSDrr_Int,      X86::VSUBSDrm_Int,       0 },
   1411     { X86::VSUBSSrr,          X86::VSUBSSrm,           0 },
   1412     { X86::VSUBSSrr_Int,      X86::VSUBSSrm_Int,       0 },
   1413     { X86::VUNPCKHPDrr,       X86::VUNPCKHPDrm,        0 },
   1414     { X86::VUNPCKHPSrr,       X86::VUNPCKHPSrm,        0 },
   1415     { X86::VUNPCKLPDrr,       X86::VUNPCKLPDrm,        0 },
   1416     { X86::VUNPCKLPSrr,       X86::VUNPCKLPSrm,        0 },
   1417     { X86::VXORPDrr,          X86::VXORPDrm,           0 },
   1418     { X86::VXORPSrr,          X86::VXORPSrm,           0 },
   1419 
   1420     // AVX 256-bit foldable instructions
   1421     { X86::VADDPDYrr,         X86::VADDPDYrm,          0 },
   1422     { X86::VADDPSYrr,         X86::VADDPSYrm,          0 },
   1423     { X86::VADDSUBPDYrr,      X86::VADDSUBPDYrm,       0 },
   1424     { X86::VADDSUBPSYrr,      X86::VADDSUBPSYrm,       0 },
   1425     { X86::VANDNPDYrr,        X86::VANDNPDYrm,         0 },
   1426     { X86::VANDNPSYrr,        X86::VANDNPSYrm,         0 },
   1427     { X86::VANDPDYrr,         X86::VANDPDYrm,          0 },
   1428     { X86::VANDPSYrr,         X86::VANDPSYrm,          0 },
   1429     { X86::VBLENDPDYrri,      X86::VBLENDPDYrmi,       0 },
   1430     { X86::VBLENDPSYrri,      X86::VBLENDPSYrmi,       0 },
   1431     { X86::VBLENDVPDYrr,      X86::VBLENDVPDYrm,       0 },
   1432     { X86::VBLENDVPSYrr,      X86::VBLENDVPSYrm,       0 },
   1433     { X86::VCMPPDYrri,        X86::VCMPPDYrmi,         0 },
   1434     { X86::VCMPPSYrri,        X86::VCMPPSYrmi,         0 },
   1435     { X86::VDIVPDYrr,         X86::VDIVPDYrm,          0 },
   1436     { X86::VDIVPSYrr,         X86::VDIVPSYrm,          0 },
   1437     { X86::VDPPSYrri,         X86::VDPPSYrmi,          0 },
   1438     { X86::VHADDPDYrr,        X86::VHADDPDYrm,         0 },
   1439     { X86::VHADDPSYrr,        X86::VHADDPSYrm,         0 },
   1440     { X86::VHSUBPDYrr,        X86::VHSUBPDYrm,         0 },
   1441     { X86::VHSUBPSYrr,        X86::VHSUBPSYrm,         0 },
   1442     { X86::VINSERTF128rr,     X86::VINSERTF128rm,      0 },
   1443     { X86::VMAXPDYrr,         X86::VMAXPDYrm,          0 },
   1444     { X86::VMAXPSYrr,         X86::VMAXPSYrm,          0 },
   1445     { X86::VMINPDYrr,         X86::VMINPDYrm,          0 },
   1446     { X86::VMINPSYrr,         X86::VMINPSYrm,          0 },
   1447     { X86::VMULPDYrr,         X86::VMULPDYrm,          0 },
   1448     { X86::VMULPSYrr,         X86::VMULPSYrm,          0 },
   1449     { X86::VORPDYrr,          X86::VORPDYrm,           0 },
   1450     { X86::VORPSYrr,          X86::VORPSYrm,           0 },
   1451     { X86::VPERM2F128rr,      X86::VPERM2F128rm,       0 },
   1452     { X86::VPERMILPDYrr,      X86::VPERMILPDYrm,       0 },
   1453     { X86::VPERMILPSYrr,      X86::VPERMILPSYrm,       0 },
   1454     { X86::VSHUFPDYrri,       X86::VSHUFPDYrmi,        0 },
   1455     { X86::VSHUFPSYrri,       X86::VSHUFPSYrmi,        0 },
   1456     { X86::VSUBPDYrr,         X86::VSUBPDYrm,          0 },
   1457     { X86::VSUBPSYrr,         X86::VSUBPSYrm,          0 },
   1458     { X86::VUNPCKHPDYrr,      X86::VUNPCKHPDYrm,       0 },
   1459     { X86::VUNPCKHPSYrr,      X86::VUNPCKHPSYrm,       0 },
   1460     { X86::VUNPCKLPDYrr,      X86::VUNPCKLPDYrm,       0 },
   1461     { X86::VUNPCKLPSYrr,      X86::VUNPCKLPSYrm,       0 },
   1462     { X86::VXORPDYrr,         X86::VXORPDYrm,          0 },
   1463     { X86::VXORPSYrr,         X86::VXORPSYrm,          0 },
   1464 
   1465     // AVX2 foldable instructions
   1466     { X86::VINSERTI128rr,     X86::VINSERTI128rm,      0 },
   1467     { X86::VPACKSSDWYrr,      X86::VPACKSSDWYrm,       0 },
   1468     { X86::VPACKSSWBYrr,      X86::VPACKSSWBYrm,       0 },
   1469     { X86::VPACKUSDWYrr,      X86::VPACKUSDWYrm,       0 },
   1470     { X86::VPACKUSWBYrr,      X86::VPACKUSWBYrm,       0 },
   1471     { X86::VPADDBYrr,         X86::VPADDBYrm,          0 },
   1472     { X86::VPADDDYrr,         X86::VPADDDYrm,          0 },
   1473     { X86::VPADDQYrr,         X86::VPADDQYrm,          0 },
   1474     { X86::VPADDSBYrr,        X86::VPADDSBYrm,         0 },
   1475     { X86::VPADDSWYrr,        X86::VPADDSWYrm,         0 },
   1476     { X86::VPADDUSBYrr,       X86::VPADDUSBYrm,        0 },
   1477     { X86::VPADDUSWYrr,       X86::VPADDUSWYrm,        0 },
   1478     { X86::VPADDWYrr,         X86::VPADDWYrm,          0 },
   1479     { X86::VPALIGNR256rr,     X86::VPALIGNR256rm,      0 },
   1480     { X86::VPANDNYrr,         X86::VPANDNYrm,          0 },
   1481     { X86::VPANDYrr,          X86::VPANDYrm,           0 },
   1482     { X86::VPAVGBYrr,         X86::VPAVGBYrm,          0 },
   1483     { X86::VPAVGWYrr,         X86::VPAVGWYrm,          0 },
   1484     { X86::VPBLENDDrri,       X86::VPBLENDDrmi,        0 },
   1485     { X86::VPBLENDDYrri,      X86::VPBLENDDYrmi,       0 },
   1486     { X86::VPBLENDVBYrr,      X86::VPBLENDVBYrm,       0 },
   1487     { X86::VPBLENDWYrri,      X86::VPBLENDWYrmi,       0 },
   1488     { X86::VPCMPEQBYrr,       X86::VPCMPEQBYrm,        0 },
   1489     { X86::VPCMPEQDYrr,       X86::VPCMPEQDYrm,        0 },
   1490     { X86::VPCMPEQQYrr,       X86::VPCMPEQQYrm,        0 },
   1491     { X86::VPCMPEQWYrr,       X86::VPCMPEQWYrm,        0 },
   1492     { X86::VPCMPGTBYrr,       X86::VPCMPGTBYrm,        0 },
   1493     { X86::VPCMPGTDYrr,       X86::VPCMPGTDYrm,        0 },
   1494     { X86::VPCMPGTQYrr,       X86::VPCMPGTQYrm,        0 },
   1495     { X86::VPCMPGTWYrr,       X86::VPCMPGTWYrm,        0 },
   1496     { X86::VPERM2I128rr,      X86::VPERM2I128rm,       0 },
   1497     { X86::VPERMDYrr,         X86::VPERMDYrm,          0 },
   1498     { X86::VPERMPSYrr,        X86::VPERMPSYrm,         0 },
   1499     { X86::VPHADDDYrr,        X86::VPHADDDYrm,         0 },
   1500     { X86::VPHADDSWrr256,     X86::VPHADDSWrm256,      0 },
   1501     { X86::VPHADDWYrr,        X86::VPHADDWYrm,         0 },
   1502     { X86::VPHSUBDYrr,        X86::VPHSUBDYrm,         0 },
   1503     { X86::VPHSUBSWrr256,     X86::VPHSUBSWrm256,      0 },
   1504     { X86::VPHSUBWYrr,        X86::VPHSUBWYrm,         0 },
   1505     { X86::VPMADDUBSWrr256,   X86::VPMADDUBSWrm256,    0 },
   1506     { X86::VPMADDWDYrr,       X86::VPMADDWDYrm,        0 },
   1507     { X86::VPMAXSWYrr,        X86::VPMAXSWYrm,         0 },
   1508     { X86::VPMAXUBYrr,        X86::VPMAXUBYrm,         0 },
   1509     { X86::VPMINSWYrr,        X86::VPMINSWYrm,         0 },
   1510     { X86::VPMINUBYrr,        X86::VPMINUBYrm,         0 },
   1511     { X86::VPMINSBYrr,        X86::VPMINSBYrm,         0 },
   1512     { X86::VPMINSDYrr,        X86::VPMINSDYrm,         0 },
   1513     { X86::VPMINUDYrr,        X86::VPMINUDYrm,         0 },
   1514     { X86::VPMINUWYrr,        X86::VPMINUWYrm,         0 },
   1515     { X86::VPMAXSBYrr,        X86::VPMAXSBYrm,         0 },
   1516     { X86::VPMAXSDYrr,        X86::VPMAXSDYrm,         0 },
   1517     { X86::VPMAXUDYrr,        X86::VPMAXUDYrm,         0 },
   1518     { X86::VPMAXUWYrr,        X86::VPMAXUWYrm,         0 },
   1519     { X86::VMPSADBWYrri,      X86::VMPSADBWYrmi,       0 },
   1520     { X86::VPMULDQYrr,        X86::VPMULDQYrm,         0 },
   1521     { X86::VPMULHRSWrr256,    X86::VPMULHRSWrm256,     0 },
   1522     { X86::VPMULHUWYrr,       X86::VPMULHUWYrm,        0 },
   1523     { X86::VPMULHWYrr,        X86::VPMULHWYrm,         0 },
   1524     { X86::VPMULLDYrr,        X86::VPMULLDYrm,         0 },
   1525     { X86::VPMULLWYrr,        X86::VPMULLWYrm,         0 },
   1526     { X86::VPMULUDQYrr,       X86::VPMULUDQYrm,        0 },
   1527     { X86::VPORYrr,           X86::VPORYrm,            0 },
   1528     { X86::VPSADBWYrr,        X86::VPSADBWYrm,         0 },
   1529     { X86::VPSHUFBYrr,        X86::VPSHUFBYrm,         0 },
   1530     { X86::VPSIGNBYrr,        X86::VPSIGNBYrm,         0 },
   1531     { X86::VPSIGNWYrr,        X86::VPSIGNWYrm,         0 },
   1532     { X86::VPSIGNDYrr,        X86::VPSIGNDYrm,         0 },
   1533     { X86::VPSLLDYrr,         X86::VPSLLDYrm,          0 },
   1534     { X86::VPSLLQYrr,         X86::VPSLLQYrm,          0 },
   1535     { X86::VPSLLWYrr,         X86::VPSLLWYrm,          0 },
   1536     { X86::VPSLLVDrr,         X86::VPSLLVDrm,          0 },
   1537     { X86::VPSLLVDYrr,        X86::VPSLLVDYrm,         0 },
   1538     { X86::VPSLLVQrr,         X86::VPSLLVQrm,          0 },
   1539     { X86::VPSLLVQYrr,        X86::VPSLLVQYrm,         0 },
   1540     { X86::VPSRADYrr,         X86::VPSRADYrm,          0 },
   1541     { X86::VPSRAWYrr,         X86::VPSRAWYrm,          0 },
   1542     { X86::VPSRAVDrr,         X86::VPSRAVDrm,          0 },
   1543     { X86::VPSRAVDYrr,        X86::VPSRAVDYrm,         0 },
   1544     { X86::VPSRLDYrr,         X86::VPSRLDYrm,          0 },
   1545     { X86::VPSRLQYrr,         X86::VPSRLQYrm,          0 },
   1546     { X86::VPSRLWYrr,         X86::VPSRLWYrm,          0 },
   1547     { X86::VPSRLVDrr,         X86::VPSRLVDrm,          0 },
   1548     { X86::VPSRLVDYrr,        X86::VPSRLVDYrm,         0 },
   1549     { X86::VPSRLVQrr,         X86::VPSRLVQrm,          0 },
   1550     { X86::VPSRLVQYrr,        X86::VPSRLVQYrm,         0 },
   1551     { X86::VPSUBBYrr,         X86::VPSUBBYrm,          0 },
   1552     { X86::VPSUBDYrr,         X86::VPSUBDYrm,          0 },
   1553     { X86::VPSUBQYrr,         X86::VPSUBQYrm,          0 },
   1554     { X86::VPSUBSBYrr,        X86::VPSUBSBYrm,         0 },
   1555     { X86::VPSUBSWYrr,        X86::VPSUBSWYrm,         0 },
   1556     { X86::VPSUBUSBYrr,       X86::VPSUBUSBYrm,        0 },
   1557     { X86::VPSUBUSWYrr,       X86::VPSUBUSWYrm,        0 },
   1558     { X86::VPSUBWYrr,         X86::VPSUBWYrm,          0 },
   1559     { X86::VPUNPCKHBWYrr,     X86::VPUNPCKHBWYrm,      0 },
   1560     { X86::VPUNPCKHDQYrr,     X86::VPUNPCKHDQYrm,      0 },
   1561     { X86::VPUNPCKHQDQYrr,    X86::VPUNPCKHQDQYrm,     0 },
   1562     { X86::VPUNPCKHWDYrr,     X86::VPUNPCKHWDYrm,      0 },
   1563     { X86::VPUNPCKLBWYrr,     X86::VPUNPCKLBWYrm,      0 },
   1564     { X86::VPUNPCKLDQYrr,     X86::VPUNPCKLDQYrm,      0 },
   1565     { X86::VPUNPCKLQDQYrr,    X86::VPUNPCKLQDQYrm,     0 },
   1566     { X86::VPUNPCKLWDYrr,     X86::VPUNPCKLWDYrm,      0 },
   1567     { X86::VPXORYrr,          X86::VPXORYrm,           0 },
   1568 
   1569     // FMA4 foldable patterns
   1570     { X86::VFMADDSS4rr,       X86::VFMADDSS4mr,        TB_ALIGN_NONE },
   1571     { X86::VFMADDSD4rr,       X86::VFMADDSD4mr,        TB_ALIGN_NONE },
   1572     { X86::VFMADDPS4rr,       X86::VFMADDPS4mr,        TB_ALIGN_NONE },
   1573     { X86::VFMADDPD4rr,       X86::VFMADDPD4mr,        TB_ALIGN_NONE },
   1574     { X86::VFMADDPS4rrY,      X86::VFMADDPS4mrY,       TB_ALIGN_NONE },
   1575     { X86::VFMADDPD4rrY,      X86::VFMADDPD4mrY,       TB_ALIGN_NONE },
   1576     { X86::VFNMADDSS4rr,      X86::VFNMADDSS4mr,       TB_ALIGN_NONE },
   1577     { X86::VFNMADDSD4rr,      X86::VFNMADDSD4mr,       TB_ALIGN_NONE },
   1578     { X86::VFNMADDPS4rr,      X86::VFNMADDPS4mr,       TB_ALIGN_NONE },
   1579     { X86::VFNMADDPD4rr,      X86::VFNMADDPD4mr,       TB_ALIGN_NONE },
   1580     { X86::VFNMADDPS4rrY,     X86::VFNMADDPS4mrY,      TB_ALIGN_NONE },
   1581     { X86::VFNMADDPD4rrY,     X86::VFNMADDPD4mrY,      TB_ALIGN_NONE },
   1582     { X86::VFMSUBSS4rr,       X86::VFMSUBSS4mr,        TB_ALIGN_NONE },
   1583     { X86::VFMSUBSD4rr,       X86::VFMSUBSD4mr,        TB_ALIGN_NONE },
   1584     { X86::VFMSUBPS4rr,       X86::VFMSUBPS4mr,        TB_ALIGN_NONE },
   1585     { X86::VFMSUBPD4rr,       X86::VFMSUBPD4mr,        TB_ALIGN_NONE },
   1586     { X86::VFMSUBPS4rrY,      X86::VFMSUBPS4mrY,       TB_ALIGN_NONE },
   1587     { X86::VFMSUBPD4rrY,      X86::VFMSUBPD4mrY,       TB_ALIGN_NONE },
   1588     { X86::VFNMSUBSS4rr,      X86::VFNMSUBSS4mr,       TB_ALIGN_NONE },
   1589     { X86::VFNMSUBSD4rr,      X86::VFNMSUBSD4mr,       TB_ALIGN_NONE },
   1590     { X86::VFNMSUBPS4rr,      X86::VFNMSUBPS4mr,       TB_ALIGN_NONE },
   1591     { X86::VFNMSUBPD4rr,      X86::VFNMSUBPD4mr,       TB_ALIGN_NONE },
   1592     { X86::VFNMSUBPS4rrY,     X86::VFNMSUBPS4mrY,      TB_ALIGN_NONE },
   1593     { X86::VFNMSUBPD4rrY,     X86::VFNMSUBPD4mrY,      TB_ALIGN_NONE },
   1594     { X86::VFMADDSUBPS4rr,    X86::VFMADDSUBPS4mr,     TB_ALIGN_NONE },
   1595     { X86::VFMADDSUBPD4rr,    X86::VFMADDSUBPD4mr,     TB_ALIGN_NONE },
   1596     { X86::VFMADDSUBPS4rrY,   X86::VFMADDSUBPS4mrY,    TB_ALIGN_NONE },
   1597     { X86::VFMADDSUBPD4rrY,   X86::VFMADDSUBPD4mrY,    TB_ALIGN_NONE },
   1598     { X86::VFMSUBADDPS4rr,    X86::VFMSUBADDPS4mr,     TB_ALIGN_NONE },
   1599     { X86::VFMSUBADDPD4rr,    X86::VFMSUBADDPD4mr,     TB_ALIGN_NONE },
   1600     { X86::VFMSUBADDPS4rrY,   X86::VFMSUBADDPS4mrY,    TB_ALIGN_NONE },
   1601     { X86::VFMSUBADDPD4rrY,   X86::VFMSUBADDPD4mrY,    TB_ALIGN_NONE },
   1602 
   1603     // XOP foldable instructions
   1604     { X86::VPCMOVrr,          X86::VPCMOVmr,            0 },
   1605     { X86::VPCMOVrrY,         X86::VPCMOVmrY,           0 },
   1606     { X86::VPCOMBri,          X86::VPCOMBmi,            0 },
   1607     { X86::VPCOMDri,          X86::VPCOMDmi,            0 },
   1608     { X86::VPCOMQri,          X86::VPCOMQmi,            0 },
   1609     { X86::VPCOMWri,          X86::VPCOMWmi,            0 },
   1610     { X86::VPCOMUBri,         X86::VPCOMUBmi,           0 },
   1611     { X86::VPCOMUDri,         X86::VPCOMUDmi,           0 },
   1612     { X86::VPCOMUQri,         X86::VPCOMUQmi,           0 },
   1613     { X86::VPCOMUWri,         X86::VPCOMUWmi,           0 },
   1614     { X86::VPERMIL2PDrr,      X86::VPERMIL2PDmr,        0 },
   1615     { X86::VPERMIL2PDrrY,     X86::VPERMIL2PDmrY,       0 },
   1616     { X86::VPERMIL2PSrr,      X86::VPERMIL2PSmr,        0 },
   1617     { X86::VPERMIL2PSrrY,     X86::VPERMIL2PSmrY,       0 },
   1618     { X86::VPMACSDDrr,        X86::VPMACSDDrm,          0 },
   1619     { X86::VPMACSDQHrr,       X86::VPMACSDQHrm,         0 },
   1620     { X86::VPMACSDQLrr,       X86::VPMACSDQLrm,         0 },
   1621     { X86::VPMACSSDDrr,       X86::VPMACSSDDrm,         0 },
   1622     { X86::VPMACSSDQHrr,      X86::VPMACSSDQHrm,        0 },
   1623     { X86::VPMACSSDQLrr,      X86::VPMACSSDQLrm,        0 },
   1624     { X86::VPMACSSWDrr,       X86::VPMACSSWDrm,         0 },
   1625     { X86::VPMACSSWWrr,       X86::VPMACSSWWrm,         0 },
   1626     { X86::VPMACSWDrr,        X86::VPMACSWDrm,          0 },
   1627     { X86::VPMACSWWrr,        X86::VPMACSWWrm,          0 },
   1628     { X86::VPMADCSSWDrr,      X86::VPMADCSSWDrm,        0 },
   1629     { X86::VPMADCSWDrr,       X86::VPMADCSWDrm,         0 },
   1630     { X86::VPPERMrr,          X86::VPPERMmr,            0 },
   1631     { X86::VPROTBrr,          X86::VPROTBrm,            0 },
   1632     { X86::VPROTDrr,          X86::VPROTDrm,            0 },
   1633     { X86::VPROTQrr,          X86::VPROTQrm,            0 },
   1634     { X86::VPROTWrr,          X86::VPROTWrm,            0 },
   1635     { X86::VPSHABrr,          X86::VPSHABrm,            0 },
   1636     { X86::VPSHADrr,          X86::VPSHADrm,            0 },
   1637     { X86::VPSHAQrr,          X86::VPSHAQrm,            0 },
   1638     { X86::VPSHAWrr,          X86::VPSHAWrm,            0 },
   1639     { X86::VPSHLBrr,          X86::VPSHLBrm,            0 },
   1640     { X86::VPSHLDrr,          X86::VPSHLDrm,            0 },
   1641     { X86::VPSHLQrr,          X86::VPSHLQrm,            0 },
   1642     { X86::VPSHLWrr,          X86::VPSHLWrm,            0 },
   1643 
   1644     // BMI/BMI2 foldable instructions
   1645     { X86::ANDN32rr,          X86::ANDN32rm,            0 },
   1646     { X86::ANDN64rr,          X86::ANDN64rm,            0 },
   1647     { X86::MULX32rr,          X86::MULX32rm,            0 },
   1648     { X86::MULX64rr,          X86::MULX64rm,            0 },
   1649     { X86::PDEP32rr,          X86::PDEP32rm,            0 },
   1650     { X86::PDEP64rr,          X86::PDEP64rm,            0 },
   1651     { X86::PEXT32rr,          X86::PEXT32rm,            0 },
   1652     { X86::PEXT64rr,          X86::PEXT64rm,            0 },
   1653 
   1654     // ADX foldable instructions
   1655     { X86::ADCX32rr,          X86::ADCX32rm,            0 },
   1656     { X86::ADCX64rr,          X86::ADCX64rm,            0 },
   1657     { X86::ADOX32rr,          X86::ADOX32rm,            0 },
   1658     { X86::ADOX64rr,          X86::ADOX64rm,            0 },
   1659 
   1660     // AVX-512 foldable instructions
   1661     { X86::VADDPSZrr,         X86::VADDPSZrm,           0 },
   1662     { X86::VADDPDZrr,         X86::VADDPDZrm,           0 },
   1663     { X86::VSUBPSZrr,         X86::VSUBPSZrm,           0 },
   1664     { X86::VSUBPDZrr,         X86::VSUBPDZrm,           0 },
   1665     { X86::VMULPSZrr,         X86::VMULPSZrm,           0 },
   1666     { X86::VMULPDZrr,         X86::VMULPDZrm,           0 },
   1667     { X86::VDIVPSZrr,         X86::VDIVPSZrm,           0 },
   1668     { X86::VDIVPDZrr,         X86::VDIVPDZrm,           0 },
   1669     { X86::VMINPSZrr,         X86::VMINPSZrm,           0 },
   1670     { X86::VMINPDZrr,         X86::VMINPDZrm,           0 },
   1671     { X86::VMAXPSZrr,         X86::VMAXPSZrm,           0 },
   1672     { X86::VMAXPDZrr,         X86::VMAXPDZrm,           0 },
   1673     { X86::VPADDDZrr,         X86::VPADDDZrm,           0 },
   1674     { X86::VPADDQZrr,         X86::VPADDQZrm,           0 },
   1675     { X86::VPERMPDZri,        X86::VPERMPDZmi,          0 },
   1676     { X86::VPERMPSZrr,        X86::VPERMPSZrm,          0 },
   1677     { X86::VPMAXSDZrr,        X86::VPMAXSDZrm,          0 },
   1678     { X86::VPMAXSQZrr,        X86::VPMAXSQZrm,          0 },
   1679     { X86::VPMAXUDZrr,        X86::VPMAXUDZrm,          0 },
   1680     { X86::VPMAXUQZrr,        X86::VPMAXUQZrm,          0 },
   1681     { X86::VPMINSDZrr,        X86::VPMINSDZrm,          0 },
   1682     { X86::VPMINSQZrr,        X86::VPMINSQZrm,          0 },
   1683     { X86::VPMINUDZrr,        X86::VPMINUDZrm,          0 },
   1684     { X86::VPMINUQZrr,        X86::VPMINUQZrm,          0 },
   1685     { X86::VPMULDQZrr,        X86::VPMULDQZrm,          0 },
   1686     { X86::VPSLLVDZrr,        X86::VPSLLVDZrm,          0 },
   1687     { X86::VPSLLVQZrr,        X86::VPSLLVQZrm,          0 },
   1688     { X86::VPSRAVDZrr,        X86::VPSRAVDZrm,          0 },
   1689     { X86::VPSRLVDZrr,        X86::VPSRLVDZrm,          0 },
   1690     { X86::VPSRLVQZrr,        X86::VPSRLVQZrm,          0 },
   1691     { X86::VPSUBDZrr,         X86::VPSUBDZrm,           0 },
   1692     { X86::VPSUBQZrr,         X86::VPSUBQZrm,           0 },
   1693     { X86::VSHUFPDZrri,       X86::VSHUFPDZrmi,         0 },
   1694     { X86::VSHUFPSZrri,       X86::VSHUFPSZrmi,         0 },
   1695     { X86::VALIGNQZrri,       X86::VALIGNQZrmi,         0 },
   1696     { X86::VALIGNDZrri,       X86::VALIGNDZrmi,         0 },
   1697     { X86::VPMULUDQZrr,       X86::VPMULUDQZrm,         0 },
   1698     { X86::VBROADCASTSSZrkz,  X86::VBROADCASTSSZmkz,    TB_NO_REVERSE },
   1699     { X86::VBROADCASTSDZrkz,  X86::VBROADCASTSDZmkz,    TB_NO_REVERSE },
   1700 
   1701     // AVX-512{F,VL} foldable instructions
   1702     { X86::VBROADCASTSSZ256rkz,  X86::VBROADCASTSSZ256mkz,      TB_NO_REVERSE },
   1703     { X86::VBROADCASTSDZ256rkz,  X86::VBROADCASTSDZ256mkz,      TB_NO_REVERSE },
   1704     { X86::VBROADCASTSSZ128rkz,  X86::VBROADCASTSSZ128mkz,      TB_NO_REVERSE },
   1705 
   1706     // AVX-512{F,VL} foldable instructions
   1707     { X86::VADDPDZ128rr,      X86::VADDPDZ128rm,        0 },
   1708     { X86::VADDPDZ256rr,      X86::VADDPDZ256rm,        0 },
   1709     { X86::VADDPSZ128rr,      X86::VADDPSZ128rm,        0 },
   1710     { X86::VADDPSZ256rr,      X86::VADDPSZ256rm,        0 },
   1711 
   1712     // AES foldable instructions
   1713     { X86::AESDECLASTrr,      X86::AESDECLASTrm,        TB_ALIGN_16 },
   1714     { X86::AESDECrr,          X86::AESDECrm,            TB_ALIGN_16 },
   1715     { X86::AESENCLASTrr,      X86::AESENCLASTrm,        TB_ALIGN_16 },
   1716     { X86::AESENCrr,          X86::AESENCrm,            TB_ALIGN_16 },
   1717     { X86::VAESDECLASTrr,     X86::VAESDECLASTrm,       0 },
   1718     { X86::VAESDECrr,         X86::VAESDECrm,           0 },
   1719     { X86::VAESENCLASTrr,     X86::VAESENCLASTrm,       0 },
   1720     { X86::VAESENCrr,         X86::VAESENCrm,           0 },
   1721 
   1722     // SHA foldable instructions
   1723     { X86::SHA1MSG1rr,        X86::SHA1MSG1rm,          TB_ALIGN_16 },
   1724     { X86::SHA1MSG2rr,        X86::SHA1MSG2rm,          TB_ALIGN_16 },
   1725     { X86::SHA1NEXTErr,       X86::SHA1NEXTErm,         TB_ALIGN_16 },
   1726     { X86::SHA1RNDS4rri,      X86::SHA1RNDS4rmi,        TB_ALIGN_16 },
   1727     { X86::SHA256MSG1rr,      X86::SHA256MSG1rm,        TB_ALIGN_16 },
   1728     { X86::SHA256MSG2rr,      X86::SHA256MSG2rm,        TB_ALIGN_16 },
   1729     { X86::SHA256RNDS2rr,     X86::SHA256RNDS2rm,       TB_ALIGN_16 }
   1730   };
   1731 
   1732   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
   1733     AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
   1734                   Entry.RegOp, Entry.MemOp,
   1735                   // Index 2, folded load
   1736                   Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
   1737   }
   1738 
   1739   static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
   1740     // FMA foldable instructions
   1741     { X86::VFMADDSSr231r,         X86::VFMADDSSr231m,         TB_ALIGN_NONE },
   1742     { X86::VFMADDSSr231r_Int,     X86::VFMADDSSr231m_Int,     TB_ALIGN_NONE },
   1743     { X86::VFMADDSDr231r,         X86::VFMADDSDr231m,         TB_ALIGN_NONE },
   1744     { X86::VFMADDSDr231r_Int,     X86::VFMADDSDr231m_Int,     TB_ALIGN_NONE },
   1745     { X86::VFMADDSSr132r,         X86::VFMADDSSr132m,         TB_ALIGN_NONE },
   1746     { X86::VFMADDSSr132r_Int,     X86::VFMADDSSr132m_Int,     TB_ALIGN_NONE },
   1747     { X86::VFMADDSDr132r,         X86::VFMADDSDr132m,         TB_ALIGN_NONE },
   1748     { X86::VFMADDSDr132r_Int,     X86::VFMADDSDr132m_Int,     TB_ALIGN_NONE },
   1749     { X86::VFMADDSSr213r,         X86::VFMADDSSr213m,         TB_ALIGN_NONE },
   1750     { X86::VFMADDSSr213r_Int,     X86::VFMADDSSr213m_Int,     TB_ALIGN_NONE },
   1751     { X86::VFMADDSDr213r,         X86::VFMADDSDr213m,         TB_ALIGN_NONE },
   1752     { X86::VFMADDSDr213r_Int,     X86::VFMADDSDr213m_Int,     TB_ALIGN_NONE },
   1753 
   1754     { X86::VFMADDPSr231r,         X86::VFMADDPSr231m,         TB_ALIGN_NONE },
   1755     { X86::VFMADDPDr231r,         X86::VFMADDPDr231m,         TB_ALIGN_NONE },
   1756     { X86::VFMADDPSr132r,         X86::VFMADDPSr132m,         TB_ALIGN_NONE },
   1757     { X86::VFMADDPDr132r,         X86::VFMADDPDr132m,         TB_ALIGN_NONE },
   1758     { X86::VFMADDPSr213r,         X86::VFMADDPSr213m,         TB_ALIGN_NONE },
   1759     { X86::VFMADDPDr213r,         X86::VFMADDPDr213m,         TB_ALIGN_NONE },
   1760     { X86::VFMADDPSr231rY,        X86::VFMADDPSr231mY,        TB_ALIGN_NONE },
   1761     { X86::VFMADDPDr231rY,        X86::VFMADDPDr231mY,        TB_ALIGN_NONE },
   1762     { X86::VFMADDPSr132rY,        X86::VFMADDPSr132mY,        TB_ALIGN_NONE },
   1763     { X86::VFMADDPDr132rY,        X86::VFMADDPDr132mY,        TB_ALIGN_NONE },
   1764     { X86::VFMADDPSr213rY,        X86::VFMADDPSr213mY,        TB_ALIGN_NONE },
   1765     { X86::VFMADDPDr213rY,        X86::VFMADDPDr213mY,        TB_ALIGN_NONE },
   1766 
   1767     { X86::VFNMADDSSr231r,        X86::VFNMADDSSr231m,        TB_ALIGN_NONE },
   1768     { X86::VFNMADDSSr231r_Int,    X86::VFNMADDSSr231m_Int,    TB_ALIGN_NONE },
   1769     { X86::VFNMADDSDr231r,        X86::VFNMADDSDr231m,        TB_ALIGN_NONE },
   1770     { X86::VFNMADDSDr231r_Int,    X86::VFNMADDSDr231m_Int,    TB_ALIGN_NONE },
   1771     { X86::VFNMADDSSr132r,        X86::VFNMADDSSr132m,        TB_ALIGN_NONE },
   1772     { X86::VFNMADDSSr132r_Int,    X86::VFNMADDSSr132m_Int,    TB_ALIGN_NONE },
   1773     { X86::VFNMADDSDr132r,        X86::VFNMADDSDr132m,        TB_ALIGN_NONE },
   1774     { X86::VFNMADDSDr132r_Int,    X86::VFNMADDSDr132m_Int,    TB_ALIGN_NONE },
   1775     { X86::VFNMADDSSr213r,        X86::VFNMADDSSr213m,        TB_ALIGN_NONE },
   1776     { X86::VFNMADDSSr213r_Int,    X86::VFNMADDSSr213m_Int,    TB_ALIGN_NONE },
   1777     { X86::VFNMADDSDr213r,        X86::VFNMADDSDr213m,        TB_ALIGN_NONE },
   1778     { X86::VFNMADDSDr213r_Int,    X86::VFNMADDSDr213m_Int,    TB_ALIGN_NONE },
   1779 
   1780     { X86::VFNMADDPSr231r,        X86::VFNMADDPSr231m,        TB_ALIGN_NONE },
   1781     { X86::VFNMADDPDr231r,        X86::VFNMADDPDr231m,        TB_ALIGN_NONE },
   1782     { X86::VFNMADDPSr132r,        X86::VFNMADDPSr132m,        TB_ALIGN_NONE },
   1783     { X86::VFNMADDPDr132r,        X86::VFNMADDPDr132m,        TB_ALIGN_NONE },
   1784     { X86::VFNMADDPSr213r,        X86::VFNMADDPSr213m,        TB_ALIGN_NONE },
   1785     { X86::VFNMADDPDr213r,        X86::VFNMADDPDr213m,        TB_ALIGN_NONE },
   1786     { X86::VFNMADDPSr231rY,       X86::VFNMADDPSr231mY,       TB_ALIGN_NONE },
   1787     { X86::VFNMADDPDr231rY,       X86::VFNMADDPDr231mY,       TB_ALIGN_NONE },
   1788     { X86::VFNMADDPSr132rY,       X86::VFNMADDPSr132mY,       TB_ALIGN_NONE },
   1789     { X86::VFNMADDPDr132rY,       X86::VFNMADDPDr132mY,       TB_ALIGN_NONE },
   1790     { X86::VFNMADDPSr213rY,       X86::VFNMADDPSr213mY,       TB_ALIGN_NONE },
   1791     { X86::VFNMADDPDr213rY,       X86::VFNMADDPDr213mY,       TB_ALIGN_NONE },
   1792 
   1793     { X86::VFMSUBSSr231r,         X86::VFMSUBSSr231m,         TB_ALIGN_NONE },
   1794     { X86::VFMSUBSSr231r_Int,     X86::VFMSUBSSr231m_Int,     TB_ALIGN_NONE },
   1795     { X86::VFMSUBSDr231r,         X86::VFMSUBSDr231m,         TB_ALIGN_NONE },
   1796     { X86::VFMSUBSDr231r_Int,     X86::VFMSUBSDr231m_Int,     TB_ALIGN_NONE },
   1797     { X86::VFMSUBSSr132r,         X86::VFMSUBSSr132m,         TB_ALIGN_NONE },
   1798     { X86::VFMSUBSSr132r_Int,     X86::VFMSUBSSr132m_Int,     TB_ALIGN_NONE },
   1799     { X86::VFMSUBSDr132r,         X86::VFMSUBSDr132m,         TB_ALIGN_NONE },
   1800     { X86::VFMSUBSDr132r_Int,     X86::VFMSUBSDr132m_Int,     TB_ALIGN_NONE },
   1801     { X86::VFMSUBSSr213r,         X86::VFMSUBSSr213m,         TB_ALIGN_NONE },
   1802     { X86::VFMSUBSSr213r_Int,     X86::VFMSUBSSr213m_Int,     TB_ALIGN_NONE },
   1803     { X86::VFMSUBSDr213r,         X86::VFMSUBSDr213m,         TB_ALIGN_NONE },
   1804     { X86::VFMSUBSDr213r_Int,     X86::VFMSUBSDr213m_Int,     TB_ALIGN_NONE },
   1805 
   1806     { X86::VFMSUBPSr231r,         X86::VFMSUBPSr231m,         TB_ALIGN_NONE },
   1807     { X86::VFMSUBPDr231r,         X86::VFMSUBPDr231m,         TB_ALIGN_NONE },
   1808     { X86::VFMSUBPSr132r,         X86::VFMSUBPSr132m,         TB_ALIGN_NONE },
   1809     { X86::VFMSUBPDr132r,         X86::VFMSUBPDr132m,         TB_ALIGN_NONE },
   1810     { X86::VFMSUBPSr213r,         X86::VFMSUBPSr213m,         TB_ALIGN_NONE },
   1811     { X86::VFMSUBPDr213r,         X86::VFMSUBPDr213m,         TB_ALIGN_NONE },
   1812     { X86::VFMSUBPSr231rY,        X86::VFMSUBPSr231mY,        TB_ALIGN_NONE },
   1813     { X86::VFMSUBPDr231rY,        X86::VFMSUBPDr231mY,        TB_ALIGN_NONE },
   1814     { X86::VFMSUBPSr132rY,        X86::VFMSUBPSr132mY,        TB_ALIGN_NONE },
   1815     { X86::VFMSUBPDr132rY,        X86::VFMSUBPDr132mY,        TB_ALIGN_NONE },
   1816     { X86::VFMSUBPSr213rY,        X86::VFMSUBPSr213mY,        TB_ALIGN_NONE },
   1817     { X86::VFMSUBPDr213rY,        X86::VFMSUBPDr213mY,        TB_ALIGN_NONE },
   1818 
   1819     { X86::VFNMSUBSSr231r,        X86::VFNMSUBSSr231m,        TB_ALIGN_NONE },
   1820     { X86::VFNMSUBSSr231r_Int,    X86::VFNMSUBSSr231m_Int,    TB_ALIGN_NONE },
   1821     { X86::VFNMSUBSDr231r,        X86::VFNMSUBSDr231m,        TB_ALIGN_NONE },
   1822     { X86::VFNMSUBSDr231r_Int,    X86::VFNMSUBSDr231m_Int,    TB_ALIGN_NONE },
   1823     { X86::VFNMSUBSSr132r,        X86::VFNMSUBSSr132m,        TB_ALIGN_NONE },
   1824     { X86::VFNMSUBSSr132r_Int,    X86::VFNMSUBSSr132m_Int,    TB_ALIGN_NONE },
   1825     { X86::VFNMSUBSDr132r,        X86::VFNMSUBSDr132m,        TB_ALIGN_NONE },
   1826     { X86::VFNMSUBSDr132r_Int,    X86::VFNMSUBSDr132m_Int,    TB_ALIGN_NONE },
   1827     { X86::VFNMSUBSSr213r,        X86::VFNMSUBSSr213m,        TB_ALIGN_NONE },
   1828     { X86::VFNMSUBSSr213r_Int,    X86::VFNMSUBSSr213m_Int,    TB_ALIGN_NONE },
   1829     { X86::VFNMSUBSDr213r,        X86::VFNMSUBSDr213m,        TB_ALIGN_NONE },
   1830     { X86::VFNMSUBSDr213r_Int,    X86::VFNMSUBSDr213m_Int,    TB_ALIGN_NONE },
   1831 
   1832     { X86::VFNMSUBPSr231r,        X86::VFNMSUBPSr231m,        TB_ALIGN_NONE },
   1833     { X86::VFNMSUBPDr231r,        X86::VFNMSUBPDr231m,        TB_ALIGN_NONE },
   1834     { X86::VFNMSUBPSr132r,        X86::VFNMSUBPSr132m,        TB_ALIGN_NONE },
   1835     { X86::VFNMSUBPDr132r,        X86::VFNMSUBPDr132m,        TB_ALIGN_NONE },
   1836     { X86::VFNMSUBPSr213r,        X86::VFNMSUBPSr213m,        TB_ALIGN_NONE },
   1837     { X86::VFNMSUBPDr213r,        X86::VFNMSUBPDr213m,        TB_ALIGN_NONE },
   1838     { X86::VFNMSUBPSr231rY,       X86::VFNMSUBPSr231mY,       TB_ALIGN_NONE },
   1839     { X86::VFNMSUBPDr231rY,       X86::VFNMSUBPDr231mY,       TB_ALIGN_NONE },
   1840     { X86::VFNMSUBPSr132rY,       X86::VFNMSUBPSr132mY,       TB_ALIGN_NONE },
   1841     { X86::VFNMSUBPDr132rY,       X86::VFNMSUBPDr132mY,       TB_ALIGN_NONE },
   1842     { X86::VFNMSUBPSr213rY,       X86::VFNMSUBPSr213mY,       TB_ALIGN_NONE },
   1843     { X86::VFNMSUBPDr213rY,       X86::VFNMSUBPDr213mY,       TB_ALIGN_NONE },
   1844 
   1845     { X86::VFMADDSUBPSr231r,      X86::VFMADDSUBPSr231m,      TB_ALIGN_NONE },
   1846     { X86::VFMADDSUBPDr231r,      X86::VFMADDSUBPDr231m,      TB_ALIGN_NONE },
   1847     { X86::VFMADDSUBPSr132r,      X86::VFMADDSUBPSr132m,      TB_ALIGN_NONE },
   1848     { X86::VFMADDSUBPDr132r,      X86::VFMADDSUBPDr132m,      TB_ALIGN_NONE },
   1849     { X86::VFMADDSUBPSr213r,      X86::VFMADDSUBPSr213m,      TB_ALIGN_NONE },
   1850     { X86::VFMADDSUBPDr213r,      X86::VFMADDSUBPDr213m,      TB_ALIGN_NONE },
   1851     { X86::VFMADDSUBPSr231rY,     X86::VFMADDSUBPSr231mY,     TB_ALIGN_NONE },
   1852     { X86::VFMADDSUBPDr231rY,     X86::VFMADDSUBPDr231mY,     TB_ALIGN_NONE },
   1853     { X86::VFMADDSUBPSr132rY,     X86::VFMADDSUBPSr132mY,     TB_ALIGN_NONE },
   1854     { X86::VFMADDSUBPDr132rY,     X86::VFMADDSUBPDr132mY,     TB_ALIGN_NONE },
   1855     { X86::VFMADDSUBPSr213rY,     X86::VFMADDSUBPSr213mY,     TB_ALIGN_NONE },
   1856     { X86::VFMADDSUBPDr213rY,     X86::VFMADDSUBPDr213mY,     TB_ALIGN_NONE },
   1857 
   1858     { X86::VFMSUBADDPSr231r,      X86::VFMSUBADDPSr231m,      TB_ALIGN_NONE },
   1859     { X86::VFMSUBADDPDr231r,      X86::VFMSUBADDPDr231m,      TB_ALIGN_NONE },
   1860     { X86::VFMSUBADDPSr132r,      X86::VFMSUBADDPSr132m,      TB_ALIGN_NONE },
   1861     { X86::VFMSUBADDPDr132r,      X86::VFMSUBADDPDr132m,      TB_ALIGN_NONE },
   1862     { X86::VFMSUBADDPSr213r,      X86::VFMSUBADDPSr213m,      TB_ALIGN_NONE },
   1863     { X86::VFMSUBADDPDr213r,      X86::VFMSUBADDPDr213m,      TB_ALIGN_NONE },
   1864     { X86::VFMSUBADDPSr231rY,     X86::VFMSUBADDPSr231mY,     TB_ALIGN_NONE },
   1865     { X86::VFMSUBADDPDr231rY,     X86::VFMSUBADDPDr231mY,     TB_ALIGN_NONE },
   1866     { X86::VFMSUBADDPSr132rY,     X86::VFMSUBADDPSr132mY,     TB_ALIGN_NONE },
   1867     { X86::VFMSUBADDPDr132rY,     X86::VFMSUBADDPDr132mY,     TB_ALIGN_NONE },
   1868     { X86::VFMSUBADDPSr213rY,     X86::VFMSUBADDPSr213mY,     TB_ALIGN_NONE },
   1869     { X86::VFMSUBADDPDr213rY,     X86::VFMSUBADDPDr213mY,     TB_ALIGN_NONE },
   1870 
   1871     // FMA4 foldable patterns
   1872     { X86::VFMADDSS4rr,           X86::VFMADDSS4rm,           TB_ALIGN_NONE },
   1873     { X86::VFMADDSD4rr,           X86::VFMADDSD4rm,           TB_ALIGN_NONE },
   1874     { X86::VFMADDPS4rr,           X86::VFMADDPS4rm,           TB_ALIGN_NONE },
   1875     { X86::VFMADDPD4rr,           X86::VFMADDPD4rm,           TB_ALIGN_NONE },
   1876     { X86::VFMADDPS4rrY,          X86::VFMADDPS4rmY,          TB_ALIGN_NONE },
   1877     { X86::VFMADDPD4rrY,          X86::VFMADDPD4rmY,          TB_ALIGN_NONE },
   1878     { X86::VFNMADDSS4rr,          X86::VFNMADDSS4rm,          TB_ALIGN_NONE },
   1879     { X86::VFNMADDSD4rr,          X86::VFNMADDSD4rm,          TB_ALIGN_NONE },
   1880     { X86::VFNMADDPS4rr,          X86::VFNMADDPS4rm,          TB_ALIGN_NONE },
   1881     { X86::VFNMADDPD4rr,          X86::VFNMADDPD4rm,          TB_ALIGN_NONE },
   1882     { X86::VFNMADDPS4rrY,         X86::VFNMADDPS4rmY,         TB_ALIGN_NONE },
   1883     { X86::VFNMADDPD4rrY,         X86::VFNMADDPD4rmY,         TB_ALIGN_NONE },
   1884     { X86::VFMSUBSS4rr,           X86::VFMSUBSS4rm,           TB_ALIGN_NONE },
   1885     { X86::VFMSUBSD4rr,           X86::VFMSUBSD4rm,           TB_ALIGN_NONE },
   1886     { X86::VFMSUBPS4rr,           X86::VFMSUBPS4rm,           TB_ALIGN_NONE },
   1887     { X86::VFMSUBPD4rr,           X86::VFMSUBPD4rm,           TB_ALIGN_NONE },
   1888     { X86::VFMSUBPS4rrY,          X86::VFMSUBPS4rmY,          TB_ALIGN_NONE },
   1889     { X86::VFMSUBPD4rrY,          X86::VFMSUBPD4rmY,          TB_ALIGN_NONE },
   1890     { X86::VFNMSUBSS4rr,          X86::VFNMSUBSS4rm,          TB_ALIGN_NONE },
   1891     { X86::VFNMSUBSD4rr,          X86::VFNMSUBSD4rm,          TB_ALIGN_NONE },
   1892     { X86::VFNMSUBPS4rr,          X86::VFNMSUBPS4rm,          TB_ALIGN_NONE },
   1893     { X86::VFNMSUBPD4rr,          X86::VFNMSUBPD4rm,          TB_ALIGN_NONE },
   1894     { X86::VFNMSUBPS4rrY,         X86::VFNMSUBPS4rmY,         TB_ALIGN_NONE },
   1895     { X86::VFNMSUBPD4rrY,         X86::VFNMSUBPD4rmY,         TB_ALIGN_NONE },
   1896     { X86::VFMADDSUBPS4rr,        X86::VFMADDSUBPS4rm,        TB_ALIGN_NONE },
   1897     { X86::VFMADDSUBPD4rr,        X86::VFMADDSUBPD4rm,        TB_ALIGN_NONE },
   1898     { X86::VFMADDSUBPS4rrY,       X86::VFMADDSUBPS4rmY,       TB_ALIGN_NONE },
   1899     { X86::VFMADDSUBPD4rrY,       X86::VFMADDSUBPD4rmY,       TB_ALIGN_NONE },
   1900     { X86::VFMSUBADDPS4rr,        X86::VFMSUBADDPS4rm,        TB_ALIGN_NONE },
   1901     { X86::VFMSUBADDPD4rr,        X86::VFMSUBADDPD4rm,        TB_ALIGN_NONE },
   1902     { X86::VFMSUBADDPS4rrY,       X86::VFMSUBADDPS4rmY,       TB_ALIGN_NONE },
   1903     { X86::VFMSUBADDPD4rrY,       X86::VFMSUBADDPD4rmY,       TB_ALIGN_NONE },
   1904 
   1905     // XOP foldable instructions
   1906     { X86::VPCMOVrr,              X86::VPCMOVrm,              0 },
   1907     { X86::VPCMOVrrY,             X86::VPCMOVrmY,             0 },
   1908     { X86::VPERMIL2PDrr,          X86::VPERMIL2PDrm,          0 },
   1909     { X86::VPERMIL2PDrrY,         X86::VPERMIL2PDrmY,         0 },
   1910     { X86::VPERMIL2PSrr,          X86::VPERMIL2PSrm,          0 },
   1911     { X86::VPERMIL2PSrrY,         X86::VPERMIL2PSrmY,         0 },
   1912     { X86::VPPERMrr,              X86::VPPERMrm,              0 },
   1913 
   1914     // AVX-512 VPERMI instructions with 3 source operands.
   1915     { X86::VPERMI2Drr,            X86::VPERMI2Drm,            0 },
   1916     { X86::VPERMI2Qrr,            X86::VPERMI2Qrm,            0 },
   1917     { X86::VPERMI2PSrr,           X86::VPERMI2PSrm,           0 },
   1918     { X86::VPERMI2PDrr,           X86::VPERMI2PDrm,           0 },
   1919     { X86::VBLENDMPDZrr,          X86::VBLENDMPDZrm,          0 },
   1920     { X86::VBLENDMPSZrr,          X86::VBLENDMPSZrm,          0 },
   1921     { X86::VPBLENDMDZrr,          X86::VPBLENDMDZrm,          0 },
   1922     { X86::VPBLENDMQZrr,          X86::VPBLENDMQZrm,          0 },
   1923     { X86::VBROADCASTSSZrk,       X86::VBROADCASTSSZmk,       TB_NO_REVERSE },
   1924     { X86::VBROADCASTSDZrk,       X86::VBROADCASTSDZmk,       TB_NO_REVERSE },
   1925     { X86::VBROADCASTSSZ256rk,    X86::VBROADCASTSSZ256mk,    TB_NO_REVERSE },
   1926     { X86::VBROADCASTSDZ256rk,    X86::VBROADCASTSDZ256mk,    TB_NO_REVERSE },
   1927     { X86::VBROADCASTSSZ128rk,    X86::VBROADCASTSSZ128mk,    TB_NO_REVERSE },
   1928      // AVX-512 arithmetic instructions
   1929     { X86::VADDPSZrrkz,           X86::VADDPSZrmkz,           0 },
   1930     { X86::VADDPDZrrkz,           X86::VADDPDZrmkz,           0 },
   1931     { X86::VSUBPSZrrkz,           X86::VSUBPSZrmkz,           0 },
   1932     { X86::VSUBPDZrrkz,           X86::VSUBPDZrmkz,           0 },
   1933     { X86::VMULPSZrrkz,           X86::VMULPSZrmkz,           0 },
   1934     { X86::VMULPDZrrkz,           X86::VMULPDZrmkz,           0 },
   1935     { X86::VDIVPSZrrkz,           X86::VDIVPSZrmkz,           0 },
   1936     { X86::VDIVPDZrrkz,           X86::VDIVPDZrmkz,           0 },
   1937     { X86::VMINPSZrrkz,           X86::VMINPSZrmkz,           0 },
   1938     { X86::VMINPDZrrkz,           X86::VMINPDZrmkz,           0 },
   1939     { X86::VMAXPSZrrkz,           X86::VMAXPSZrmkz,           0 },
   1940     { X86::VMAXPDZrrkz,           X86::VMAXPDZrmkz,           0 },
   1941     // AVX-512{F,VL} arithmetic instructions 256-bit
   1942     { X86::VADDPSZ256rrkz,        X86::VADDPSZ256rmkz,        0 },
   1943     { X86::VADDPDZ256rrkz,        X86::VADDPDZ256rmkz,        0 },
   1944     { X86::VSUBPSZ256rrkz,        X86::VSUBPSZ256rmkz,        0 },
   1945     { X86::VSUBPDZ256rrkz,        X86::VSUBPDZ256rmkz,        0 },
   1946     { X86::VMULPSZ256rrkz,        X86::VMULPSZ256rmkz,        0 },
   1947     { X86::VMULPDZ256rrkz,        X86::VMULPDZ256rmkz,        0 },
   1948     { X86::VDIVPSZ256rrkz,        X86::VDIVPSZ256rmkz,        0 },
   1949     { X86::VDIVPDZ256rrkz,        X86::VDIVPDZ256rmkz,        0 },
   1950     { X86::VMINPSZ256rrkz,        X86::VMINPSZ256rmkz,        0 },
   1951     { X86::VMINPDZ256rrkz,        X86::VMINPDZ256rmkz,        0 },
   1952     { X86::VMAXPSZ256rrkz,        X86::VMAXPSZ256rmkz,        0 },
   1953     { X86::VMAXPDZ256rrkz,        X86::VMAXPDZ256rmkz,        0 },
   1954     // AVX-512{F,VL} arithmetic instructions 128-bit
   1955     { X86::VADDPSZ128rrkz,        X86::VADDPSZ128rmkz,        0 },
   1956     { X86::VADDPDZ128rrkz,        X86::VADDPDZ128rmkz,        0 },
   1957     { X86::VSUBPSZ128rrkz,        X86::VSUBPSZ128rmkz,        0 },
   1958     { X86::VSUBPDZ128rrkz,        X86::VSUBPDZ128rmkz,        0 },
   1959     { X86::VMULPSZ128rrkz,        X86::VMULPSZ128rmkz,        0 },
   1960     { X86::VMULPDZ128rrkz,        X86::VMULPDZ128rmkz,        0 },
   1961     { X86::VDIVPSZ128rrkz,        X86::VDIVPSZ128rmkz,        0 },
   1962     { X86::VDIVPDZ128rrkz,        X86::VDIVPDZ128rmkz,        0 },
   1963     { X86::VMINPSZ128rrkz,        X86::VMINPSZ128rmkz,        0 },
   1964     { X86::VMINPDZ128rrkz,        X86::VMINPDZ128rmkz,        0 },
   1965     { X86::VMAXPSZ128rrkz,        X86::VMAXPSZ128rmkz,        0 },
   1966     { X86::VMAXPDZ128rrkz,        X86::VMAXPDZ128rmkz,        0 }
   1967   };
   1968 
   1969   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
   1970     AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
   1971                   Entry.RegOp, Entry.MemOp,
   1972                   // Index 3, folded load
   1973                   Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
   1974   }
   1975 
   1976   static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
   1977      // AVX-512 foldable instructions
   1978     { X86::VADDPSZrrk,         X86::VADDPSZrmk,           0 },
   1979     { X86::VADDPDZrrk,         X86::VADDPDZrmk,           0 },
   1980     { X86::VSUBPSZrrk,         X86::VSUBPSZrmk,           0 },
   1981     { X86::VSUBPDZrrk,         X86::VSUBPDZrmk,           0 },
   1982     { X86::VMULPSZrrk,         X86::VMULPSZrmk,           0 },
   1983     { X86::VMULPDZrrk,         X86::VMULPDZrmk,           0 },
   1984     { X86::VDIVPSZrrk,         X86::VDIVPSZrmk,           0 },
   1985     { X86::VDIVPDZrrk,         X86::VDIVPDZrmk,           0 },
   1986     { X86::VMINPSZrrk,         X86::VMINPSZrmk,           0 },
   1987     { X86::VMINPDZrrk,         X86::VMINPDZrmk,           0 },
   1988     { X86::VMAXPSZrrk,         X86::VMAXPSZrmk,           0 },
   1989     { X86::VMAXPDZrrk,         X86::VMAXPDZrmk,           0 },
   1990     // AVX-512{F,VL} foldable instructions 256-bit
   1991     { X86::VADDPSZ256rrk,      X86::VADDPSZ256rmk,        0 },
   1992     { X86::VADDPDZ256rrk,      X86::VADDPDZ256rmk,        0 },
   1993     { X86::VSUBPSZ256rrk,      X86::VSUBPSZ256rmk,        0 },
   1994     { X86::VSUBPDZ256rrk,      X86::VSUBPDZ256rmk,        0 },
   1995     { X86::VMULPSZ256rrk,      X86::VMULPSZ256rmk,        0 },
   1996     { X86::VMULPDZ256rrk,      X86::VMULPDZ256rmk,        0 },
   1997     { X86::VDIVPSZ256rrk,      X86::VDIVPSZ256rmk,        0 },
   1998     { X86::VDIVPDZ256rrk,      X86::VDIVPDZ256rmk,        0 },
   1999     { X86::VMINPSZ256rrk,      X86::VMINPSZ256rmk,        0 },
   2000     { X86::VMINPDZ256rrk,      X86::VMINPDZ256rmk,        0 },
   2001     { X86::VMAXPSZ256rrk,      X86::VMAXPSZ256rmk,        0 },
   2002     { X86::VMAXPDZ256rrk,      X86::VMAXPDZ256rmk,        0 },
   2003     // AVX-512{F,VL} foldable instructions 128-bit
   2004     { X86::VADDPSZ128rrk,      X86::VADDPSZ128rmk,        0 },
   2005     { X86::VADDPDZ128rrk,      X86::VADDPDZ128rmk,        0 },
   2006     { X86::VSUBPSZ128rrk,      X86::VSUBPSZ128rmk,        0 },
   2007     { X86::VSUBPDZ128rrk,      X86::VSUBPDZ128rmk,        0 },
   2008     { X86::VMULPSZ128rrk,      X86::VMULPSZ128rmk,        0 },
   2009     { X86::VMULPDZ128rrk,      X86::VMULPDZ128rmk,        0 },
   2010     { X86::VDIVPSZ128rrk,      X86::VDIVPSZ128rmk,        0 },
   2011     { X86::VDIVPDZ128rrk,      X86::VDIVPDZ128rmk,        0 },
   2012     { X86::VMINPSZ128rrk,      X86::VMINPSZ128rmk,        0 },
   2013     { X86::VMINPDZ128rrk,      X86::VMINPDZ128rmk,        0 },
   2014     { X86::VMAXPSZ128rrk,      X86::VMAXPSZ128rmk,        0 },
   2015     { X86::VMAXPDZ128rrk,      X86::VMAXPDZ128rmk,        0 }
   2016   };
   2017 
   2018   for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
   2019     AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
   2020                   Entry.RegOp, Entry.MemOp,
   2021                   // Index 4, folded load
   2022                   Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
   2023   }
   2024 }
   2025 
   2026 void
   2027 X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
   2028                             MemOp2RegOpTableType &M2RTable,
   2029                             unsigned RegOp, unsigned MemOp, unsigned Flags) {
   2030     if ((Flags & TB_NO_FORWARD) == 0) {
   2031       assert(!R2MTable.count(RegOp) && "Duplicate entry!");
   2032       R2MTable[RegOp] = std::make_pair(MemOp, Flags);
   2033     }
   2034     if ((Flags & TB_NO_REVERSE) == 0) {
   2035       assert(!M2RTable.count(MemOp) &&
   2036            "Duplicated entries in unfolding maps?");
   2037       M2RTable[MemOp] = std::make_pair(RegOp, Flags);
   2038     }
   2039 }
   2040 
   2041 bool
   2042 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
   2043                                     unsigned &SrcReg, unsigned &DstReg,
   2044                                     unsigned &SubIdx) const {
   2045   switch (MI.getOpcode()) {
   2046   default: break;
   2047   case X86::MOVSX16rr8:
   2048   case X86::MOVZX16rr8:
   2049   case X86::MOVSX32rr8:
   2050   case X86::MOVZX32rr8:
   2051   case X86::MOVSX64rr8:
   2052     if (!Subtarget.is64Bit())
   2053       // It's not always legal to reference the low 8-bit of the larger
   2054       // register in 32-bit mode.
   2055       return false;
   2056   case X86::MOVSX32rr16:
   2057   case X86::MOVZX32rr16:
   2058   case X86::MOVSX64rr16:
   2059   case X86::MOVSX64rr32: {
   2060     if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
   2061       // Be conservative.
   2062       return false;
   2063     SrcReg = MI.getOperand(1).getReg();
   2064     DstReg = MI.getOperand(0).getReg();
   2065     switch (MI.getOpcode()) {
   2066     default: llvm_unreachable("Unreachable!");
   2067     case X86::MOVSX16rr8:
   2068     case X86::MOVZX16rr8:
   2069     case X86::MOVSX32rr8:
   2070     case X86::MOVZX32rr8:
   2071     case X86::MOVSX64rr8:
   2072       SubIdx = X86::sub_8bit;
   2073       break;
   2074     case X86::MOVSX32rr16:
   2075     case X86::MOVZX32rr16:
   2076     case X86::MOVSX64rr16:
   2077       SubIdx = X86::sub_16bit;
   2078       break;
   2079     case X86::MOVSX64rr32:
   2080       SubIdx = X86::sub_32bit;
   2081       break;
   2082     }
   2083     return true;
   2084   }
   2085   }
   2086   return false;
   2087 }
   2088 
   2089 int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
   2090   const MachineFunction *MF = MI->getParent()->getParent();
   2091   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
   2092 
   2093   if (MI->getOpcode() == getCallFrameSetupOpcode() ||
   2094       MI->getOpcode() == getCallFrameDestroyOpcode()) {
   2095     unsigned StackAlign = TFI->getStackAlignment();
   2096     int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
   2097                  StackAlign;
   2098 
   2099     SPAdj -= MI->getOperand(1).getImm();
   2100 
   2101     if (MI->getOpcode() == getCallFrameSetupOpcode())
   2102       return SPAdj;
   2103     else
   2104       return -SPAdj;
   2105   }
   2106 
   2107   // To know whether a call adjusts the stack, we need information
   2108   // that is bound to the following ADJCALLSTACKUP pseudo.
   2109   // Look for the next ADJCALLSTACKUP that follows the call.
   2110   if (MI->isCall()) {
   2111     const MachineBasicBlock* MBB = MI->getParent();
   2112     auto I = ++MachineBasicBlock::const_iterator(MI);
   2113     for (auto E = MBB->end(); I != E; ++I) {
   2114       if (I->getOpcode() == getCallFrameDestroyOpcode() ||
   2115           I->isCall())
   2116         break;
   2117     }
   2118 
   2119     // If we could not find a frame destroy opcode, then it has already
   2120     // been simplified, so we don't care.
   2121     if (I->getOpcode() != getCallFrameDestroyOpcode())
   2122       return 0;
   2123 
   2124     return -(I->getOperand(1).getImm());
   2125   }
   2126 
   2127   // Currently handle only PUSHes we can reasonably expect to see
   2128   // in call sequences
   2129   switch (MI->getOpcode()) {
   2130   default:
   2131     return 0;
   2132   case X86::PUSH32i8:
   2133   case X86::PUSH32r:
   2134   case X86::PUSH32rmm:
   2135   case X86::PUSH32rmr:
   2136   case X86::PUSHi32:
   2137     return 4;
   2138   }
   2139 }
   2140 
   2141 /// Return true and the FrameIndex if the specified
   2142 /// operand and follow operands form a reference to the stack frame.
   2143 bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
   2144                                   int &FrameIndex) const {
   2145   if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
   2146       MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
   2147       MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
   2148       MI->getOperand(Op+X86::AddrDisp).isImm() &&
   2149       MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
   2150       MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
   2151       MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
   2152     FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
   2153     return true;
   2154   }
   2155   return false;
   2156 }
   2157 
   2158 static bool isFrameLoadOpcode(int Opcode) {
   2159   switch (Opcode) {
   2160   default:
   2161     return false;
   2162   case X86::MOV8rm:
   2163   case X86::MOV16rm:
   2164   case X86::MOV32rm:
   2165   case X86::MOV64rm:
   2166   case X86::LD_Fp64m:
   2167   case X86::MOVSSrm:
   2168   case X86::MOVSDrm:
   2169   case X86::MOVAPSrm:
   2170   case X86::MOVAPDrm:
   2171   case X86::MOVDQArm:
   2172   case X86::VMOVSSrm:
   2173   case X86::VMOVSDrm:
   2174   case X86::VMOVAPSrm:
   2175   case X86::VMOVAPDrm:
   2176   case X86::VMOVDQArm:
   2177   case X86::VMOVUPSYrm:
   2178   case X86::VMOVAPSYrm:
   2179   case X86::VMOVUPDYrm:
   2180   case X86::VMOVAPDYrm:
   2181   case X86::VMOVDQUYrm:
   2182   case X86::VMOVDQAYrm:
   2183   case X86::MMX_MOVD64rm:
   2184   case X86::MMX_MOVQ64rm:
   2185   case X86::VMOVAPSZrm:
   2186   case X86::VMOVUPSZrm:
   2187     return true;
   2188   }
   2189 }
   2190 
   2191 static bool isFrameStoreOpcode(int Opcode) {
   2192   switch (Opcode) {
   2193   default: break;
   2194   case X86::MOV8mr:
   2195   case X86::MOV16mr:
   2196   case X86::MOV32mr:
   2197   case X86::MOV64mr:
   2198   case X86::ST_FpP64m:
   2199   case X86::MOVSSmr:
   2200   case X86::MOVSDmr:
   2201   case X86::MOVAPSmr:
   2202   case X86::MOVAPDmr:
   2203   case X86::MOVDQAmr:
   2204   case X86::VMOVSSmr:
   2205   case X86::VMOVSDmr:
   2206   case X86::VMOVAPSmr:
   2207   case X86::VMOVAPDmr:
   2208   case X86::VMOVDQAmr:
   2209   case X86::VMOVUPSYmr:
   2210   case X86::VMOVAPSYmr:
   2211   case X86::VMOVUPDYmr:
   2212   case X86::VMOVAPDYmr:
   2213   case X86::VMOVDQUYmr:
   2214   case X86::VMOVDQAYmr:
   2215   case X86::VMOVUPSZmr:
   2216   case X86::VMOVAPSZmr:
   2217   case X86::MMX_MOVD64mr:
   2218   case X86::MMX_MOVQ64mr:
   2219   case X86::MMX_MOVNTQmr:
   2220     return true;
   2221   }
   2222   return false;
   2223 }
   2224 
   2225 unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
   2226                                            int &FrameIndex) const {
   2227   if (isFrameLoadOpcode(MI->getOpcode()))
   2228     if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
   2229       return MI->getOperand(0).getReg();
   2230   return 0;
   2231 }
   2232 
   2233 unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
   2234                                                  int &FrameIndex) const {
   2235   if (isFrameLoadOpcode(MI->getOpcode())) {
   2236     unsigned Reg;
   2237     if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
   2238       return Reg;
   2239     // Check for post-frame index elimination operations
   2240     const MachineMemOperand *Dummy;
   2241     return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
   2242   }
   2243   return 0;
   2244 }
   2245 
   2246 unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
   2247                                           int &FrameIndex) const {
   2248   if (isFrameStoreOpcode(MI->getOpcode()))
   2249     if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
   2250         isFrameOperand(MI, 0, FrameIndex))
   2251       return MI->getOperand(X86::AddrNumOperands).getReg();
   2252   return 0;
   2253 }
   2254 
   2255 unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
   2256                                                 int &FrameIndex) const {
   2257   if (isFrameStoreOpcode(MI->getOpcode())) {
   2258     unsigned Reg;
   2259     if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
   2260       return Reg;
   2261     // Check for post-frame index elimination operations
   2262     const MachineMemOperand *Dummy;
   2263     return hasStoreToStackSlot(MI, Dummy, FrameIndex);
   2264   }
   2265   return 0;
   2266 }
   2267 
   2268 /// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
   2269 static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
   2270   // Don't waste compile time scanning use-def chains of physregs.
   2271   if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
   2272     return false;
   2273   bool isPICBase = false;
   2274   for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
   2275          E = MRI.def_instr_end(); I != E; ++I) {
   2276     MachineInstr *DefMI = &*I;
   2277     if (DefMI->getOpcode() != X86::MOVPC32r)
   2278       return false;
   2279     assert(!isPICBase && "More than one PIC base?");
   2280     isPICBase = true;
   2281   }
   2282   return isPICBase;
   2283 }
   2284 
   2285 bool
   2286 X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
   2287                                                 AliasAnalysis *AA) const {
   2288   switch (MI->getOpcode()) {
   2289   default: break;
   2290   case X86::MOV8rm:
   2291   case X86::MOV16rm:
   2292   case X86::MOV32rm:
   2293   case X86::MOV64rm:
   2294   case X86::LD_Fp64m:
   2295   case X86::MOVSSrm:
   2296   case X86::MOVSDrm:
   2297   case X86::MOVAPSrm:
   2298   case X86::MOVUPSrm:
   2299   case X86::MOVAPDrm:
   2300   case X86::MOVDQArm:
   2301   case X86::MOVDQUrm:
   2302   case X86::VMOVSSrm:
   2303   case X86::VMOVSDrm:
   2304   case X86::VMOVAPSrm:
   2305   case X86::VMOVUPSrm:
   2306   case X86::VMOVAPDrm:
   2307   case X86::VMOVDQArm:
   2308   case X86::VMOVDQUrm:
   2309   case X86::VMOVAPSYrm:
   2310   case X86::VMOVUPSYrm:
   2311   case X86::VMOVAPDYrm:
   2312   case X86::VMOVDQAYrm:
   2313   case X86::VMOVDQUYrm:
   2314   case X86::MMX_MOVD64rm:
   2315   case X86::MMX_MOVQ64rm:
   2316   case X86::FsVMOVAPSrm:
   2317   case X86::FsVMOVAPDrm:
   2318   case X86::FsMOVAPSrm:
   2319   case X86::FsMOVAPDrm:
   2320   // AVX-512
   2321   case X86::VMOVAPDZ128rm:
   2322   case X86::VMOVAPDZ256rm:
   2323   case X86::VMOVAPDZrm:
   2324   case X86::VMOVAPSZ128rm:
   2325   case X86::VMOVAPSZ256rm:
   2326   case X86::VMOVAPSZrm:
   2327   case X86::VMOVDQA32Z128rm:
   2328   case X86::VMOVDQA32Z256rm:
   2329   case X86::VMOVDQA32Zrm:
   2330   case X86::VMOVDQA64Z128rm:
   2331   case X86::VMOVDQA64Z256rm:
   2332   case X86::VMOVDQA64Zrm:
   2333   case X86::VMOVDQU16Z128rm:
   2334   case X86::VMOVDQU16Z256rm:
   2335   case X86::VMOVDQU16Zrm:
   2336   case X86::VMOVDQU32Z128rm:
   2337   case X86::VMOVDQU32Z256rm:
   2338   case X86::VMOVDQU32Zrm:
   2339   case X86::VMOVDQU64Z128rm:
   2340   case X86::VMOVDQU64Z256rm:
   2341   case X86::VMOVDQU64Zrm:
   2342   case X86::VMOVDQU8Z128rm:
   2343   case X86::VMOVDQU8Z256rm:
   2344   case X86::VMOVDQU8Zrm:
   2345   case X86::VMOVUPSZ128rm:
   2346   case X86::VMOVUPSZ256rm:
   2347   case X86::VMOVUPSZrm: {
   2348     // Loads from constant pools are trivially rematerializable.
   2349     if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
   2350         MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
   2351         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
   2352         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
   2353         MI->isInvariantLoad(AA)) {
   2354       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
   2355       if (BaseReg == 0 || BaseReg == X86::RIP)
   2356         return true;
   2357       // Allow re-materialization of PIC load.
   2358       if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
   2359         return false;
   2360       const MachineFunction &MF = *MI->getParent()->getParent();
   2361       const MachineRegisterInfo &MRI = MF.getRegInfo();
   2362       return regIsPICBase(BaseReg, MRI);
   2363     }
   2364     return false;
   2365   }
   2366 
   2367   case X86::LEA32r:
   2368   case X86::LEA64r: {
   2369     if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
   2370         MI->getOperand(1+X86::AddrIndexReg).isReg() &&
   2371         MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
   2372         !MI->getOperand(1+X86::AddrDisp).isReg()) {
   2373       // lea fi#, lea GV, etc. are all rematerializable.
   2374       if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
   2375         return true;
   2376       unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
   2377       if (BaseReg == 0)
   2378         return true;
   2379       // Allow re-materialization of lea PICBase + x.
   2380       const MachineFunction &MF = *MI->getParent()->getParent();
   2381       const MachineRegisterInfo &MRI = MF.getRegInfo();
   2382       return regIsPICBase(BaseReg, MRI);
   2383     }
   2384     return false;
   2385   }
   2386   }
   2387 
   2388   // All other instructions marked M_REMATERIALIZABLE are always trivially
   2389   // rematerializable.
   2390   return true;
   2391 }
   2392 
   2393 bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
   2394                                          MachineBasicBlock::iterator I) const {
   2395   MachineBasicBlock::iterator E = MBB.end();
   2396 
   2397   // For compile time consideration, if we are not able to determine the
   2398   // safety after visiting 4 instructions in each direction, we will assume
   2399   // it's not safe.
   2400   MachineBasicBlock::iterator Iter = I;
   2401   for (unsigned i = 0; Iter != E && i < 4; ++i) {
   2402     bool SeenDef = false;
   2403     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
   2404       MachineOperand &MO = Iter->getOperand(j);
   2405       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
   2406         SeenDef = true;
   2407       if (!MO.isReg())
   2408         continue;
   2409       if (MO.getReg() == X86::EFLAGS) {
   2410         if (MO.isUse())
   2411           return false;
   2412         SeenDef = true;
   2413       }
   2414     }
   2415 
   2416     if (SeenDef)
   2417       // This instruction defines EFLAGS, no need to look any further.
   2418       return true;
   2419     ++Iter;
   2420     // Skip over DBG_VALUE.
   2421     while (Iter != E && Iter->isDebugValue())
   2422       ++Iter;
   2423   }
   2424 
   2425   // It is safe to clobber EFLAGS at the end of a block of no successor has it
   2426   // live in.
   2427   if (Iter == E) {
   2428     for (MachineBasicBlock *S : MBB.successors())
   2429       if (S->isLiveIn(X86::EFLAGS))
   2430         return false;
   2431     return true;
   2432   }
   2433 
   2434   MachineBasicBlock::iterator B = MBB.begin();
   2435   Iter = I;
   2436   for (unsigned i = 0; i < 4; ++i) {
   2437     // If we make it to the beginning of the block, it's safe to clobber
   2438     // EFLAGS iff EFLAGS is not live-in.
   2439     if (Iter == B)
   2440       return !MBB.isLiveIn(X86::EFLAGS);
   2441 
   2442     --Iter;
   2443     // Skip over DBG_VALUE.
   2444     while (Iter != B && Iter->isDebugValue())
   2445       --Iter;
   2446 
   2447     bool SawKill = false;
   2448     for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
   2449       MachineOperand &MO = Iter->getOperand(j);
   2450       // A register mask may clobber EFLAGS, but we should still look for a
   2451       // live EFLAGS def.
   2452       if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
   2453         SawKill = true;
   2454       if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
   2455         if (MO.isDef()) return MO.isDead();
   2456         if (MO.isKill()) SawKill = true;
   2457       }
   2458     }
   2459 
   2460     if (SawKill)
   2461       // This instruction kills EFLAGS and doesn't redefine it, so
   2462       // there's no need to look further.
   2463       return true;
   2464   }
   2465 
   2466   // Conservative answer.
   2467   return false;
   2468 }
   2469 
   2470 void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
   2471                                  MachineBasicBlock::iterator I,
   2472                                  unsigned DestReg, unsigned SubIdx,
   2473                                  const MachineInstr *Orig,
   2474                                  const TargetRegisterInfo &TRI) const {
   2475   bool ClobbersEFLAGS = false;
   2476   for (const MachineOperand &MO : Orig->operands()) {
   2477     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
   2478       ClobbersEFLAGS = true;
   2479       break;
   2480     }
   2481   }
   2482 
   2483   if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
   2484     // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
   2485     // effects.
   2486     int Value;
   2487     switch (Orig->getOpcode()) {
   2488     case X86::MOV32r0:  Value = 0; break;
   2489     case X86::MOV32r1:  Value = 1; break;
   2490     case X86::MOV32r_1: Value = -1; break;
   2491     default:
   2492       llvm_unreachable("Unexpected instruction!");
   2493     }
   2494 
   2495     DebugLoc DL = Orig->getDebugLoc();
   2496     BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
   2497       .addImm(Value);
   2498   } else {
   2499     MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
   2500     MBB.insert(I, MI);
   2501   }
   2502 
   2503   MachineInstr *NewMI = std::prev(I);
   2504   NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
   2505 }
   2506 
   2507 /// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
   2508 bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
   2509   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
   2510     MachineOperand &MO = MI->getOperand(i);
   2511     if (MO.isReg() && MO.isDef() &&
   2512         MO.getReg() == X86::EFLAGS && !MO.isDead()) {
   2513       return true;
   2514     }
   2515   }
   2516   return false;
   2517 }
   2518 
   2519 /// Check whether the shift count for a machine operand is non-zero.
   2520 inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
   2521                                               unsigned ShiftAmtOperandIdx) {
   2522   // The shift count is six bits with the REX.W prefix and five bits without.
   2523   unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
   2524   unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
   2525   return Imm & ShiftCountMask;
   2526 }
   2527 
   2528 /// Check whether the given shift count is appropriate
   2529 /// can be represented by a LEA instruction.
   2530 inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
   2531   // Left shift instructions can be transformed into load-effective-address
   2532   // instructions if we can encode them appropriately.
   2533   // A LEA instruction utilizes a SIB byte to encode its scale factor.
   2534   // The SIB.scale field is two bits wide which means that we can encode any
   2535   // shift amount less than 4.
   2536   return ShAmt < 4 && ShAmt > 0;
   2537 }
   2538 
   2539 bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
   2540                                   unsigned Opc, bool AllowSP,
   2541                                   unsigned &NewSrc, bool &isKill, bool &isUndef,
   2542                                   MachineOperand &ImplicitOp) const {
   2543   MachineFunction &MF = *MI->getParent()->getParent();
   2544   const TargetRegisterClass *RC;
   2545   if (AllowSP) {
   2546     RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
   2547   } else {
   2548     RC = Opc != X86::LEA32r ?
   2549       &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
   2550   }
   2551   unsigned SrcReg = Src.getReg();
   2552 
   2553   // For both LEA64 and LEA32 the register already has essentially the right
   2554   // type (32-bit or 64-bit) we may just need to forbid SP.
   2555   if (Opc != X86::LEA64_32r) {
   2556     NewSrc = SrcReg;
   2557     isKill = Src.isKill();
   2558     isUndef = Src.isUndef();
   2559 
   2560     if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
   2561         !MF.getRegInfo().constrainRegClass(NewSrc, RC))
   2562       return false;
   2563 
   2564     return true;
   2565   }
   2566 
   2567   // This is for an LEA64_32r and incoming registers are 32-bit. One way or
   2568   // another we need to add 64-bit registers to the final MI.
   2569   if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
   2570     ImplicitOp = Src;
   2571     ImplicitOp.setImplicit();
   2572 
   2573     NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
   2574     MachineBasicBlock::LivenessQueryResult LQR =
   2575       MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
   2576 
   2577     switch (LQR) {
   2578     case MachineBasicBlock::LQR_Unknown:
   2579       // We can't give sane liveness flags to the instruction, abandon LEA
   2580       // formation.
   2581       return false;
   2582     case MachineBasicBlock::LQR_Live:
   2583       isKill = MI->killsRegister(SrcReg);
   2584       isUndef = false;
   2585       break;
   2586     default:
   2587       // The physreg itself is dead, so we have to use it as an <undef>.
   2588       isKill = false;
   2589       isUndef = true;
   2590       break;
   2591     }
   2592   } else {
   2593     // Virtual register of the wrong class, we have to create a temporary 64-bit
   2594     // vreg to feed into the LEA.
   2595     NewSrc = MF.getRegInfo().createVirtualRegister(RC);
   2596     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
   2597             get(TargetOpcode::COPY))
   2598       .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
   2599         .addOperand(Src);
   2600 
   2601     // Which is obviously going to be dead after we're done with it.
   2602     isKill = true;
   2603     isUndef = false;
   2604   }
   2605 
   2606   // We've set all the parameters without issue.
   2607   return true;
   2608 }
   2609 
   2610 /// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
   2611 /// LEA to form 3-address code by promoting to a 32-bit superregister and then
   2612 /// truncating back down to a 16-bit subregister.
   2613 MachineInstr *
   2614 X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
   2615                                            MachineFunction::iterator &MFI,
   2616                                            MachineBasicBlock::iterator &MBBI,
   2617                                            LiveVariables *LV) const {
   2618   MachineInstr *MI = MBBI;
   2619   unsigned Dest = MI->getOperand(0).getReg();
   2620   unsigned Src = MI->getOperand(1).getReg();
   2621   bool isDead = MI->getOperand(0).isDead();
   2622   bool isKill = MI->getOperand(1).isKill();
   2623 
   2624   MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
   2625   unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
   2626   unsigned Opc, leaInReg;
   2627   if (Subtarget.is64Bit()) {
   2628     Opc = X86::LEA64_32r;
   2629     leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
   2630   } else {
   2631     Opc = X86::LEA32r;
   2632     leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
   2633   }
   2634 
   2635   // Build and insert into an implicit UNDEF value. This is OK because
   2636   // well be shifting and then extracting the lower 16-bits.
   2637   // This has the potential to cause partial register stall. e.g.
   2638   //   movw    (%rbp,%rcx,2), %dx
   2639   //   leal    -65(%rdx), %esi
   2640   // But testing has shown this *does* help performance in 64-bit mode (at
   2641   // least on modern x86 machines).
   2642   BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
   2643   MachineInstr *InsMI =
   2644     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
   2645     .addReg(leaInReg, RegState::Define, X86::sub_16bit)
   2646     .addReg(Src, getKillRegState(isKill));
   2647 
   2648   MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
   2649                                     get(Opc), leaOutReg);
   2650   switch (MIOpc) {
   2651   default: llvm_unreachable("Unreachable!");
   2652   case X86::SHL16ri: {
   2653     unsigned ShAmt = MI->getOperand(2).getImm();
   2654     MIB.addReg(0).addImm(1 << ShAmt)
   2655        .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
   2656     break;
   2657   }
   2658   case X86::INC16r:
   2659     addRegOffset(MIB, leaInReg, true, 1);
   2660     break;
   2661   case X86::DEC16r:
   2662     addRegOffset(MIB, leaInReg, true, -1);
   2663     break;
   2664   case X86::ADD16ri:
   2665   case X86::ADD16ri8:
   2666   case X86::ADD16ri_DB:
   2667   case X86::ADD16ri8_DB:
   2668     addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
   2669     break;
   2670   case X86::ADD16rr:
   2671   case X86::ADD16rr_DB: {
   2672     unsigned Src2 = MI->getOperand(2).getReg();
   2673     bool isKill2 = MI->getOperand(2).isKill();
   2674     unsigned leaInReg2 = 0;
   2675     MachineInstr *InsMI2 = nullptr;
   2676     if (Src == Src2) {
   2677       // ADD16rr %reg1028<kill>, %reg1028
   2678       // just a single insert_subreg.
   2679       addRegReg(MIB, leaInReg, true, leaInReg, false);
   2680     } else {
   2681       if (Subtarget.is64Bit())
   2682         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
   2683       else
   2684         leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
   2685       // Build and insert into an implicit UNDEF value. This is OK because
   2686       // well be shifting and then extracting the lower 16-bits.
   2687       BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
   2688       InsMI2 =
   2689         BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
   2690         .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
   2691         .addReg(Src2, getKillRegState(isKill2));
   2692       addRegReg(MIB, leaInReg, true, leaInReg2, true);
   2693     }
   2694     if (LV && isKill2 && InsMI2)
   2695       LV->replaceKillInstruction(Src2, MI, InsMI2);
   2696     break;
   2697   }
   2698   }
   2699 
   2700   MachineInstr *NewMI = MIB;
   2701   MachineInstr *ExtMI =
   2702     BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
   2703     .addReg(Dest, RegState::Define | getDeadRegState(isDead))
   2704     .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
   2705 
   2706   if (LV) {
   2707     // Update live variables
   2708     LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
   2709     LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
   2710     if (isKill)
   2711       LV->replaceKillInstruction(Src, MI, InsMI);
   2712     if (isDead)
   2713       LV->replaceKillInstruction(Dest, MI, ExtMI);
   2714   }
   2715 
   2716   return ExtMI;
   2717 }
   2718 
   2719 /// This method must be implemented by targets that
   2720 /// set the M_CONVERTIBLE_TO_3_ADDR flag.  When this flag is set, the target
   2721 /// may be able to convert a two-address instruction into a true
   2722 /// three-address instruction on demand.  This allows the X86 target (for
   2723 /// example) to convert ADD and SHL instructions into LEA instructions if they
   2724 /// would require register copies due to two-addressness.
   2725 ///
   2726 /// This method returns a null pointer if the transformation cannot be
   2727 /// performed, otherwise it returns the new instruction.
   2728 ///
   2729 MachineInstr *
   2730 X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
   2731                                     MachineBasicBlock::iterator &MBBI,
   2732                                     LiveVariables *LV) const {
   2733   MachineInstr *MI = MBBI;
   2734 
   2735   // The following opcodes also sets the condition code register(s). Only
   2736   // convert them to equivalent lea if the condition code register def's
   2737   // are dead!
   2738   if (hasLiveCondCodeDef(MI))
   2739     return nullptr;
   2740 
   2741   MachineFunction &MF = *MI->getParent()->getParent();
   2742   // All instructions input are two-addr instructions.  Get the known operands.
   2743   const MachineOperand &Dest = MI->getOperand(0);
   2744   const MachineOperand &Src = MI->getOperand(1);
   2745 
   2746   MachineInstr *NewMI = nullptr;
   2747   // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's.  When
   2748   // we have better subtarget support, enable the 16-bit LEA generation here.
   2749   // 16-bit LEA is also slow on Core2.
   2750   bool DisableLEA16 = true;
   2751   bool is64Bit = Subtarget.is64Bit();
   2752 
   2753   unsigned MIOpc = MI->getOpcode();
   2754   switch (MIOpc) {
   2755   default: return nullptr;
   2756   case X86::SHL64ri: {
   2757     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
   2758     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
   2759     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
   2760 
   2761     // LEA can't handle RSP.
   2762     if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
   2763         !MF.getRegInfo().constrainRegClass(Src.getReg(),
   2764                                            &X86::GR64_NOSPRegClass))
   2765       return nullptr;
   2766 
   2767     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
   2768       .addOperand(Dest)
   2769       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
   2770     break;
   2771   }
   2772   case X86::SHL32ri: {
   2773     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
   2774     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
   2775     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
   2776 
   2777     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
   2778 
   2779     // LEA can't handle ESP.
   2780     bool isKill, isUndef;
   2781     unsigned SrcReg;
   2782     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
   2783     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
   2784                         SrcReg, isKill, isUndef, ImplicitOp))
   2785       return nullptr;
   2786 
   2787     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
   2788       .addOperand(Dest)
   2789       .addReg(0).addImm(1 << ShAmt)
   2790       .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
   2791       .addImm(0).addReg(0);
   2792     if (ImplicitOp.getReg() != 0)
   2793       MIB.addOperand(ImplicitOp);
   2794     NewMI = MIB;
   2795 
   2796     break;
   2797   }
   2798   case X86::SHL16ri: {
   2799     assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
   2800     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
   2801     if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
   2802 
   2803     if (DisableLEA16)
   2804       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
   2805     NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
   2806       .addOperand(Dest)
   2807       .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
   2808     break;
   2809   }
   2810   case X86::INC64r:
   2811   case X86::INC32r: {
   2812     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
   2813     unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
   2814       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
   2815     bool isKill, isUndef;
   2816     unsigned SrcReg;
   2817     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
   2818     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
   2819                         SrcReg, isKill, isUndef, ImplicitOp))
   2820       return nullptr;
   2821 
   2822     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
   2823         .addOperand(Dest)
   2824         .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
   2825     if (ImplicitOp.getReg() != 0)
   2826       MIB.addOperand(ImplicitOp);
   2827 
   2828     NewMI = addOffset(MIB, 1);
   2829     break;
   2830   }
   2831   case X86::INC16r:
   2832     if (DisableLEA16)
   2833       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
   2834                      : nullptr;
   2835     assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
   2836     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
   2837                       .addOperand(Dest).addOperand(Src), 1);
   2838     break;
   2839   case X86::DEC64r:
   2840   case X86::DEC32r: {
   2841     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
   2842     unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
   2843       : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
   2844 
   2845     bool isKill, isUndef;
   2846     unsigned SrcReg;
   2847     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
   2848     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
   2849                         SrcReg, isKill, isUndef, ImplicitOp))
   2850       return nullptr;
   2851 
   2852     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
   2853         .addOperand(Dest)
   2854         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
   2855     if (ImplicitOp.getReg() != 0)
   2856       MIB.addOperand(ImplicitOp);
   2857 
   2858     NewMI = addOffset(MIB, -1);
   2859 
   2860     break;
   2861   }
   2862   case X86::DEC16r:
   2863     if (DisableLEA16)
   2864       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
   2865                      : nullptr;
   2866     assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
   2867     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
   2868                       .addOperand(Dest).addOperand(Src), -1);
   2869     break;
   2870   case X86::ADD64rr:
   2871   case X86::ADD64rr_DB:
   2872   case X86::ADD32rr:
   2873   case X86::ADD32rr_DB: {
   2874     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
   2875     unsigned Opc;
   2876     if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
   2877       Opc = X86::LEA64r;
   2878     else
   2879       Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
   2880 
   2881     bool isKill, isUndef;
   2882     unsigned SrcReg;
   2883     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
   2884     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
   2885                         SrcReg, isKill, isUndef, ImplicitOp))
   2886       return nullptr;
   2887 
   2888     const MachineOperand &Src2 = MI->getOperand(2);
   2889     bool isKill2, isUndef2;
   2890     unsigned SrcReg2;
   2891     MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
   2892     if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
   2893                         SrcReg2, isKill2, isUndef2, ImplicitOp2))
   2894       return nullptr;
   2895 
   2896     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
   2897       .addOperand(Dest);
   2898     if (ImplicitOp.getReg() != 0)
   2899       MIB.addOperand(ImplicitOp);
   2900     if (ImplicitOp2.getReg() != 0)
   2901       MIB.addOperand(ImplicitOp2);
   2902 
   2903     NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
   2904 
   2905     // Preserve undefness of the operands.
   2906     NewMI->getOperand(1).setIsUndef(isUndef);
   2907     NewMI->getOperand(3).setIsUndef(isUndef2);
   2908 
   2909     if (LV && Src2.isKill())
   2910       LV->replaceKillInstruction(SrcReg2, MI, NewMI);
   2911     break;
   2912   }
   2913   case X86::ADD16rr:
   2914   case X86::ADD16rr_DB: {
   2915     if (DisableLEA16)
   2916       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
   2917                      : nullptr;
   2918     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
   2919     unsigned Src2 = MI->getOperand(2).getReg();
   2920     bool isKill2 = MI->getOperand(2).isKill();
   2921     NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
   2922                       .addOperand(Dest),
   2923                       Src.getReg(), Src.isKill(), Src2, isKill2);
   2924 
   2925     // Preserve undefness of the operands.
   2926     bool isUndef = MI->getOperand(1).isUndef();
   2927     bool isUndef2 = MI->getOperand(2).isUndef();
   2928     NewMI->getOperand(1).setIsUndef(isUndef);
   2929     NewMI->getOperand(3).setIsUndef(isUndef2);
   2930 
   2931     if (LV && isKill2)
   2932       LV->replaceKillInstruction(Src2, MI, NewMI);
   2933     break;
   2934   }
   2935   case X86::ADD64ri32:
   2936   case X86::ADD64ri8:
   2937   case X86::ADD64ri32_DB:
   2938   case X86::ADD64ri8_DB:
   2939     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
   2940     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
   2941                       .addOperand(Dest).addOperand(Src),
   2942                       MI->getOperand(2).getImm());
   2943     break;
   2944   case X86::ADD32ri:
   2945   case X86::ADD32ri8:
   2946   case X86::ADD32ri_DB:
   2947   case X86::ADD32ri8_DB: {
   2948     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
   2949     unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
   2950 
   2951     bool isKill, isUndef;
   2952     unsigned SrcReg;
   2953     MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
   2954     if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
   2955                         SrcReg, isKill, isUndef, ImplicitOp))
   2956       return nullptr;
   2957 
   2958     MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
   2959         .addOperand(Dest)
   2960         .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
   2961     if (ImplicitOp.getReg() != 0)
   2962       MIB.addOperand(ImplicitOp);
   2963 
   2964     NewMI = addOffset(MIB, MI->getOperand(2).getImm());
   2965     break;
   2966   }
   2967   case X86::ADD16ri:
   2968   case X86::ADD16ri8:
   2969   case X86::ADD16ri_DB:
   2970   case X86::ADD16ri8_DB:
   2971     if (DisableLEA16)
   2972       return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
   2973                      : nullptr;
   2974     assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
   2975     NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
   2976                       .addOperand(Dest).addOperand(Src),
   2977                       MI->getOperand(2).getImm());
   2978     break;
   2979   }
   2980 
   2981   if (!NewMI) return nullptr;
   2982 
   2983   if (LV) {  // Update live variables
   2984     if (Src.isKill())
   2985       LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
   2986     if (Dest.isDead())
   2987       LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
   2988   }
   2989 
   2990   MFI->insert(MBBI, NewMI);          // Insert the new inst
   2991   return NewMI;
   2992 }
   2993 
   2994 /// Returns true if the given instruction opcode is FMA3.
   2995 /// Otherwise, returns false.
   2996 /// The second parameter is optional and is used as the second return from
   2997 /// the function. It is set to true if the given instruction has FMA3 opcode
   2998 /// that is used for lowering of scalar FMA intrinsics, and it is set to false
   2999 /// otherwise.
   3000 static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
   3001   if (IsIntrinsic)
   3002     *IsIntrinsic = false;
   3003 
   3004   switch (Opcode) {
   3005     case X86::VFMADDSDr132r:      case X86::VFMADDSDr132m:
   3006     case X86::VFMADDSSr132r:      case X86::VFMADDSSr132m:
   3007     case X86::VFMSUBSDr132r:      case X86::VFMSUBSDr132m:
   3008     case X86::VFMSUBSSr132r:      case X86::VFMSUBSSr132m:
   3009     case X86::VFNMADDSDr132r:     case X86::VFNMADDSDr132m:
   3010     case X86::VFNMADDSSr132r:     case X86::VFNMADDSSr132m:
   3011     case X86::VFNMSUBSDr132r:     case X86::VFNMSUBSDr132m:
   3012     case X86::VFNMSUBSSr132r:     case X86::VFNMSUBSSr132m:
   3013 
   3014     case X86::VFMADDSDr213r:      case X86::VFMADDSDr213m:
   3015     case X86::VFMADDSSr213r:      case X86::VFMADDSSr213m:
   3016     case X86::VFMSUBSDr213r:      case X86::VFMSUBSDr213m:
   3017     case X86::VFMSUBSSr213r:      case X86::VFMSUBSSr213m:
   3018     case X86::VFNMADDSDr213r:     case X86::VFNMADDSDr213m:
   3019     case X86::VFNMADDSSr213r:     case X86::VFNMADDSSr213m:
   3020     case X86::VFNMSUBSDr213r:     case X86::VFNMSUBSDr213m:
   3021     case X86::VFNMSUBSSr213r:     case X86::VFNMSUBSSr213m:
   3022 
   3023     case X86::VFMADDSDr231r:      case X86::VFMADDSDr231m:
   3024     case X86::VFMADDSSr231r:      case X86::VFMADDSSr231m:
   3025     case X86::VFMSUBSDr231r:      case X86::VFMSUBSDr231m:
   3026     case X86::VFMSUBSSr231r:      case X86::VFMSUBSSr231m:
   3027     case X86::VFNMADDSDr231r:     case X86::VFNMADDSDr231m:
   3028     case X86::VFNMADDSSr231r:     case X86::VFNMADDSSr231m:
   3029     case X86::VFNMSUBSDr231r:     case X86::VFNMSUBSDr231m:
   3030     case X86::VFNMSUBSSr231r:     case X86::VFNMSUBSSr231m:
   3031 
   3032     case X86::VFMADDSUBPDr132r:   case X86::VFMADDSUBPDr132m:
   3033     case X86::VFMADDSUBPSr132r:   case X86::VFMADDSUBPSr132m:
   3034     case X86::VFMSUBADDPDr132r:   case X86::VFMSUBADDPDr132m:
   3035     case X86::VFMSUBADDPSr132r:   case X86::VFMSUBADDPSr132m:
   3036     case X86::VFMADDSUBPDr132rY:  case X86::VFMADDSUBPDr132mY:
   3037     case X86::VFMADDSUBPSr132rY:  case X86::VFMADDSUBPSr132mY:
   3038     case X86::VFMSUBADDPDr132rY:  case X86::VFMSUBADDPDr132mY:
   3039     case X86::VFMSUBADDPSr132rY:  case X86::VFMSUBADDPSr132mY:
   3040 
   3041     case X86::VFMADDPDr132r:      case X86::VFMADDPDr132m:
   3042     case X86::VFMADDPSr132r:      case X86::VFMADDPSr132m:
   3043     case X86::VFMSUBPDr132r:      case X86::VFMSUBPDr132m:
   3044     case X86::VFMSUBPSr132r:      case X86::VFMSUBPSr132m:
   3045     case X86::VFNMADDPDr132r:     case X86::VFNMADDPDr132m:
   3046     case X86::VFNMADDPSr132r:     case X86::VFNMADDPSr132m:
   3047     case X86::VFNMSUBPDr132r:     case X86::VFNMSUBPDr132m:
   3048     case X86::VFNMSUBPSr132r:     case X86::VFNMSUBPSr132m:
   3049     case X86::VFMADDPDr132rY:     case X86::VFMADDPDr132mY:
   3050     case X86::VFMADDPSr132rY:     case X86::VFMADDPSr132mY:
   3051     case X86::VFMSUBPDr132rY:     case X86::VFMSUBPDr132mY:
   3052     case X86::VFMSUBPSr132rY:     case X86::VFMSUBPSr132mY:
   3053     case X86::VFNMADDPDr132rY:    case X86::VFNMADDPDr132mY:
   3054     case X86::VFNMADDPSr132rY:    case X86::VFNMADDPSr132mY:
   3055     case X86::VFNMSUBPDr132rY:    case X86::VFNMSUBPDr132mY:
   3056     case X86::VFNMSUBPSr132rY:    case X86::VFNMSUBPSr132mY:
   3057 
   3058     case X86::VFMADDSUBPDr213r:   case X86::VFMADDSUBPDr213m:
   3059     case X86::VFMADDSUBPSr213r:   case X86::VFMADDSUBPSr213m:
   3060     case X86::VFMSUBADDPDr213r:   case X86::VFMSUBADDPDr213m:
   3061     case X86::VFMSUBADDPSr213r:   case X86::VFMSUBADDPSr213m:
   3062     case X86::VFMADDSUBPDr213rY:  case X86::VFMADDSUBPDr213mY:
   3063     case X86::VFMADDSUBPSr213rY:  case X86::VFMADDSUBPSr213mY:
   3064     case X86::VFMSUBADDPDr213rY:  case X86::VFMSUBADDPDr213mY:
   3065     case X86::VFMSUBADDPSr213rY:  case X86::VFMSUBADDPSr213mY:
   3066 
   3067     case X86::VFMADDPDr213r:      case X86::VFMADDPDr213m:
   3068     case X86::VFMADDPSr213r:      case X86::VFMADDPSr213m:
   3069     case X86::VFMSUBPDr213r:      case X86::VFMSUBPDr213m:
   3070     case X86::VFMSUBPSr213r:      case X86::VFMSUBPSr213m:
   3071     case X86::VFNMADDPDr213r:     case X86::VFNMADDPDr213m:
   3072     case X86::VFNMADDPSr213r:     case X86::VFNMADDPSr213m:
   3073     case X86::VFNMSUBPDr213r:     case X86::VFNMSUBPDr213m:
   3074     case X86::VFNMSUBPSr213r:     case X86::VFNMSUBPSr213m:
   3075     case X86::VFMADDPDr213rY:     case X86::VFMADDPDr213mY:
   3076     case X86::VFMADDPSr213rY:     case X86::VFMADDPSr213mY:
   3077     case X86::VFMSUBPDr213rY:     case X86::VFMSUBPDr213mY:
   3078     case X86::VFMSUBPSr213rY:     case X86::VFMSUBPSr213mY:
   3079     case X86::VFNMADDPDr213rY:    case X86::VFNMADDPDr213mY:
   3080     case X86::VFNMADDPSr213rY:    case X86::VFNMADDPSr213mY:
   3081     case X86::VFNMSUBPDr213rY:    case X86::VFNMSUBPDr213mY:
   3082     case X86::VFNMSUBPSr213rY:    case X86::VFNMSUBPSr213mY:
   3083 
   3084     case X86::VFMADDSUBPDr231r:   case X86::VFMADDSUBPDr231m:
   3085     case X86::VFMADDSUBPSr231r:   case X86::VFMADDSUBPSr231m:
   3086     case X86::VFMSUBADDPDr231r:   case X86::VFMSUBADDPDr231m:
   3087     case X86::VFMSUBADDPSr231r:   case X86::VFMSUBADDPSr231m:
   3088     case X86::VFMADDSUBPDr231rY:  case X86::VFMADDSUBPDr231mY:
   3089     case X86::VFMADDSUBPSr231rY:  case X86::VFMADDSUBPSr231mY:
   3090     case X86::VFMSUBADDPDr231rY:  case X86::VFMSUBADDPDr231mY:
   3091     case X86::VFMSUBADDPSr231rY:  case X86::VFMSUBADDPSr231mY:
   3092 
   3093     case X86::VFMADDPDr231r:      case X86::VFMADDPDr231m:
   3094     case X86::VFMADDPSr231r:      case X86::VFMADDPSr231m:
   3095     case X86::VFMSUBPDr231r:      case X86::VFMSUBPDr231m:
   3096     case X86::VFMSUBPSr231r:      case X86::VFMSUBPSr231m:
   3097     case X86::VFNMADDPDr231r:     case X86::VFNMADDPDr231m:
   3098     case X86::VFNMADDPSr231r:     case X86::VFNMADDPSr231m:
   3099     case X86::VFNMSUBPDr231r:     case X86::VFNMSUBPDr231m:
   3100     case X86::VFNMSUBPSr231r:     case X86::VFNMSUBPSr231m:
   3101     case X86::VFMADDPDr231rY:     case X86::VFMADDPDr231mY:
   3102     case X86::VFMADDPSr231rY:     case X86::VFMADDPSr231mY:
   3103     case X86::VFMSUBPDr231rY:     case X86::VFMSUBPDr231mY:
   3104     case X86::VFMSUBPSr231rY:     case X86::VFMSUBPSr231mY:
   3105     case X86::VFNMADDPDr231rY:    case X86::VFNMADDPDr231mY:
   3106     case X86::VFNMADDPSr231rY:    case X86::VFNMADDPSr231mY:
   3107     case X86::VFNMSUBPDr231rY:    case X86::VFNMSUBPDr231mY:
   3108     case X86::VFNMSUBPSr231rY:    case X86::VFNMSUBPSr231mY:
   3109       return true;
   3110 
   3111     case X86::VFMADDSDr132r_Int:  case X86::VFMADDSDr132m_Int:
   3112     case X86::VFMADDSSr132r_Int:  case X86::VFMADDSSr132m_Int:
   3113     case X86::VFMSUBSDr132r_Int:  case X86::VFMSUBSDr132m_Int:
   3114     case X86::VFMSUBSSr132r_Int:  case X86::VFMSUBSSr132m_Int:
   3115     case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
   3116     case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
   3117     case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
   3118     case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
   3119 
   3120     case X86::VFMADDSDr213r_Int:  case X86::VFMADDSDr213m_Int:
   3121     case X86::VFMADDSSr213r_Int:  case X86::VFMADDSSr213m_Int:
   3122     case X86::VFMSUBSDr213r_Int:  case X86::VFMSUBSDr213m_Int:
   3123     case X86::VFMSUBSSr213r_Int:  case X86::VFMSUBSSr213m_Int:
   3124     case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
   3125     case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
   3126     case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
   3127     case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
   3128 
   3129     case X86::VFMADDSDr231r_Int:  case X86::VFMADDSDr231m_Int:
   3130     case X86::VFMADDSSr231r_Int:  case X86::VFMADDSSr231m_Int:
   3131     case X86::VFMSUBSDr231r_Int:  case X86::VFMSUBSDr231m_Int:
   3132     case X86::VFMSUBSSr231r_Int:  case X86::VFMSUBSSr231m_Int:
   3133     case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
   3134     case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
   3135     case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
   3136     case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
   3137       if (IsIntrinsic)
   3138         *IsIntrinsic = true;
   3139       return true;
   3140     default:
   3141       return false;
   3142   }
   3143   llvm_unreachable("Opcode not handled by the switch");
   3144 }
   3145 
   3146 MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
   3147                                                    bool NewMI,
   3148                                                    unsigned OpIdx1,
   3149                                                    unsigned OpIdx2) const {
   3150   switch (MI->getOpcode()) {
   3151   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
   3152   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
   3153   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
   3154   case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
   3155   case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
   3156   case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
   3157     unsigned Opc;
   3158     unsigned Size;
   3159     switch (MI->getOpcode()) {
   3160     default: llvm_unreachable("Unreachable!");
   3161     case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
   3162     case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
   3163     case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
   3164     case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
   3165     case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
   3166     case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
   3167     }
   3168     unsigned Amt = MI->getOperand(3).getImm();
   3169     if (NewMI) {
   3170       MachineFunction &MF = *MI->getParent()->getParent();
   3171       MI = MF.CloneMachineInstr(MI);
   3172       NewMI = false;
   3173     }
   3174     MI->setDesc(get(Opc));
   3175     MI->getOperand(3).setImm(Size-Amt);
   3176     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3177   }
   3178   case X86::BLENDPDrri:
   3179   case X86::BLENDPSrri:
   3180   case X86::PBLENDWrri:
   3181   case X86::VBLENDPDrri:
   3182   case X86::VBLENDPSrri:
   3183   case X86::VBLENDPDYrri:
   3184   case X86::VBLENDPSYrri:
   3185   case X86::VPBLENDDrri:
   3186   case X86::VPBLENDWrri:
   3187   case X86::VPBLENDDYrri:
   3188   case X86::VPBLENDWYrri:{
   3189     unsigned Mask;
   3190     switch (MI->getOpcode()) {
   3191     default: llvm_unreachable("Unreachable!");
   3192     case X86::BLENDPDrri:    Mask = 0x03; break;
   3193     case X86::BLENDPSrri:    Mask = 0x0F; break;
   3194     case X86::PBLENDWrri:    Mask = 0xFF; break;
   3195     case X86::VBLENDPDrri:   Mask = 0x03; break;
   3196     case X86::VBLENDPSrri:   Mask = 0x0F; break;
   3197     case X86::VBLENDPDYrri:  Mask = 0x0F; break;
   3198     case X86::VBLENDPSYrri:  Mask = 0xFF; break;
   3199     case X86::VPBLENDDrri:   Mask = 0x0F; break;
   3200     case X86::VPBLENDWrri:   Mask = 0xFF; break;
   3201     case X86::VPBLENDDYrri:  Mask = 0xFF; break;
   3202     case X86::VPBLENDWYrri:  Mask = 0xFF; break;
   3203     }
   3204     // Only the least significant bits of Imm are used.
   3205     unsigned Imm = MI->getOperand(3).getImm() & Mask;
   3206     if (NewMI) {
   3207       MachineFunction &MF = *MI->getParent()->getParent();
   3208       MI = MF.CloneMachineInstr(MI);
   3209       NewMI = false;
   3210     }
   3211     MI->getOperand(3).setImm(Mask ^ Imm);
   3212     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3213   }
   3214   case X86::PCLMULQDQrr:
   3215   case X86::VPCLMULQDQrr:{
   3216     // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
   3217     // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
   3218     unsigned Imm = MI->getOperand(3).getImm();
   3219     unsigned Src1Hi = Imm & 0x01;
   3220     unsigned Src2Hi = Imm & 0x10;
   3221     if (NewMI) {
   3222       MachineFunction &MF = *MI->getParent()->getParent();
   3223       MI = MF.CloneMachineInstr(MI);
   3224       NewMI = false;
   3225     }
   3226     MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
   3227     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3228   }
   3229   case X86::CMPPDrri:
   3230   case X86::CMPPSrri:
   3231   case X86::VCMPPDrri:
   3232   case X86::VCMPPSrri:
   3233   case X86::VCMPPDYrri:
   3234   case X86::VCMPPSYrri: {
   3235     // Float comparison can be safely commuted for
   3236     // Ordered/Unordered/Equal/NotEqual tests
   3237     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
   3238     switch (Imm) {
   3239     case 0x00: // EQUAL
   3240     case 0x03: // UNORDERED
   3241     case 0x04: // NOT EQUAL
   3242     case 0x07: // ORDERED
   3243       if (NewMI) {
   3244         MachineFunction &MF = *MI->getParent()->getParent();
   3245         MI = MF.CloneMachineInstr(MI);
   3246         NewMI = false;
   3247       }
   3248       return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3249     default:
   3250       return nullptr;
   3251     }
   3252   }
   3253   case X86::VPCOMBri: case X86::VPCOMUBri:
   3254   case X86::VPCOMDri: case X86::VPCOMUDri:
   3255   case X86::VPCOMQri: case X86::VPCOMUQri:
   3256   case X86::VPCOMWri: case X86::VPCOMUWri: {
   3257     // Flip comparison mode immediate (if necessary).
   3258     unsigned Imm = MI->getOperand(3).getImm() & 0x7;
   3259     switch (Imm) {
   3260     case 0x00: Imm = 0x02; break; // LT -> GT
   3261     case 0x01: Imm = 0x03; break; // LE -> GE
   3262     case 0x02: Imm = 0x00; break; // GT -> LT
   3263     case 0x03: Imm = 0x01; break; // GE -> LE
   3264     case 0x04: // EQ
   3265     case 0x05: // NE
   3266     case 0x06: // FALSE
   3267     case 0x07: // TRUE
   3268     default:
   3269       break;
   3270     }
   3271     if (NewMI) {
   3272       MachineFunction &MF = *MI->getParent()->getParent();
   3273       MI = MF.CloneMachineInstr(MI);
   3274       NewMI = false;
   3275     }
   3276     MI->getOperand(3).setImm(Imm);
   3277     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3278   }
   3279   case X86::CMOVB16rr:  case X86::CMOVB32rr:  case X86::CMOVB64rr:
   3280   case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
   3281   case X86::CMOVE16rr:  case X86::CMOVE32rr:  case X86::CMOVE64rr:
   3282   case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
   3283   case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
   3284   case X86::CMOVA16rr:  case X86::CMOVA32rr:  case X86::CMOVA64rr:
   3285   case X86::CMOVL16rr:  case X86::CMOVL32rr:  case X86::CMOVL64rr:
   3286   case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
   3287   case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
   3288   case X86::CMOVG16rr:  case X86::CMOVG32rr:  case X86::CMOVG64rr:
   3289   case X86::CMOVS16rr:  case X86::CMOVS32rr:  case X86::CMOVS64rr:
   3290   case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
   3291   case X86::CMOVP16rr:  case X86::CMOVP32rr:  case X86::CMOVP64rr:
   3292   case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
   3293   case X86::CMOVO16rr:  case X86::CMOVO32rr:  case X86::CMOVO64rr:
   3294   case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
   3295     unsigned Opc;
   3296     switch (MI->getOpcode()) {
   3297     default: llvm_unreachable("Unreachable!");
   3298     case X86::CMOVB16rr:  Opc = X86::CMOVAE16rr; break;
   3299     case X86::CMOVB32rr:  Opc = X86::CMOVAE32rr; break;
   3300     case X86::CMOVB64rr:  Opc = X86::CMOVAE64rr; break;
   3301     case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
   3302     case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
   3303     case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
   3304     case X86::CMOVE16rr:  Opc = X86::CMOVNE16rr; break;
   3305     case X86::CMOVE32rr:  Opc = X86::CMOVNE32rr; break;
   3306     case X86::CMOVE64rr:  Opc = X86::CMOVNE64rr; break;
   3307     case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
   3308     case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
   3309     case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
   3310     case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
   3311     case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
   3312     case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
   3313     case X86::CMOVA16rr:  Opc = X86::CMOVBE16rr; break;
   3314     case X86::CMOVA32rr:  Opc = X86::CMOVBE32rr; break;
   3315     case X86::CMOVA64rr:  Opc = X86::CMOVBE64rr; break;
   3316     case X86::CMOVL16rr:  Opc = X86::CMOVGE16rr; break;
   3317     case X86::CMOVL32rr:  Opc = X86::CMOVGE32rr; break;
   3318     case X86::CMOVL64rr:  Opc = X86::CMOVGE64rr; break;
   3319     case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
   3320     case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
   3321     case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
   3322     case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
   3323     case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
   3324     case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
   3325     case X86::CMOVG16rr:  Opc = X86::CMOVLE16rr; break;
   3326     case X86::CMOVG32rr:  Opc = X86::CMOVLE32rr; break;
   3327     case X86::CMOVG64rr:  Opc = X86::CMOVLE64rr; break;
   3328     case X86::CMOVS16rr:  Opc = X86::CMOVNS16rr; break;
   3329     case X86::CMOVS32rr:  Opc = X86::CMOVNS32rr; break;
   3330     case X86::CMOVS64rr:  Opc = X86::CMOVNS64rr; break;
   3331     case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
   3332     case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
   3333     case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
   3334     case X86::CMOVP16rr:  Opc = X86::CMOVNP16rr; break;
   3335     case X86::CMOVP32rr:  Opc = X86::CMOVNP32rr; break;
   3336     case X86::CMOVP64rr:  Opc = X86::CMOVNP64rr; break;
   3337     case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
   3338     case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
   3339     case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
   3340     case X86::CMOVO16rr:  Opc = X86::CMOVNO16rr; break;
   3341     case X86::CMOVO32rr:  Opc = X86::CMOVNO32rr; break;
   3342     case X86::CMOVO64rr:  Opc = X86::CMOVNO64rr; break;
   3343     case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
   3344     case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
   3345     case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
   3346     }
   3347     if (NewMI) {
   3348       MachineFunction &MF = *MI->getParent()->getParent();
   3349       MI = MF.CloneMachineInstr(MI);
   3350       NewMI = false;
   3351     }
   3352     MI->setDesc(get(Opc));
   3353     // Fallthrough intended.
   3354   }
   3355   default:
   3356     if (isFMA3(MI->getOpcode())) {
   3357       unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
   3358       if (Opc == 0)
   3359         return nullptr;
   3360       if (NewMI) {
   3361         MachineFunction &MF = *MI->getParent()->getParent();
   3362         MI = MF.CloneMachineInstr(MI);
   3363         NewMI = false;
   3364       }
   3365       MI->setDesc(get(Opc));
   3366     }
   3367     return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
   3368   }
   3369 }
   3370 
   3371 bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
   3372                                              unsigned &SrcOpIdx1,
   3373                                              unsigned &SrcOpIdx2) const {
   3374 
   3375   unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
   3376 
   3377   // Only the first RegOpsNum operands are commutable.
   3378   // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
   3379   // that the operand is not specified/fixed.
   3380   if (SrcOpIdx1 != CommuteAnyOperandIndex &&
   3381       (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
   3382     return false;
   3383   if (SrcOpIdx2 != CommuteAnyOperandIndex &&
   3384       (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
   3385     return false;
   3386 
   3387   // Look for two different register operands assumed to be commutable
   3388   // regardless of the FMA opcode. The FMA opcode is adjusted later.
   3389   if (SrcOpIdx1 == CommuteAnyOperandIndex ||
   3390       SrcOpIdx2 == CommuteAnyOperandIndex) {
   3391     unsigned CommutableOpIdx1 = SrcOpIdx1;
   3392     unsigned CommutableOpIdx2 = SrcOpIdx2;
   3393 
   3394     // At least one of operands to be commuted is not specified and
   3395     // this method is free to choose appropriate commutable operands.
   3396     if (SrcOpIdx1 == SrcOpIdx2)
   3397       // Both of operands are not fixed. By default set one of commutable
   3398       // operands to the last register operand of the instruction.
   3399       CommutableOpIdx2 = RegOpsNum;
   3400     else if (SrcOpIdx2 == CommuteAnyOperandIndex)
   3401       // Only one of operands is not fixed.
   3402       CommutableOpIdx2 = SrcOpIdx1;
   3403 
   3404     // CommutableOpIdx2 is well defined now. Let's choose another commutable
   3405     // operand and assign its index to CommutableOpIdx1.
   3406     unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
   3407     for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
   3408       // The commuted operands must have different registers.
   3409       // Otherwise, the commute transformation does not change anything and
   3410       // is useless then.
   3411       if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
   3412         break;
   3413     }
   3414 
   3415     // No appropriate commutable operands were found.
   3416     if (CommutableOpIdx1 == 0)
   3417       return false;
   3418 
   3419     // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
   3420     // to return those values.
   3421     if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
   3422                               CommutableOpIdx1, CommutableOpIdx2))
   3423       return false;
   3424   }
   3425 
   3426   // Check if we can adjust the opcode to preserve the semantics when
   3427   // commute the register operands.
   3428   return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
   3429 }
   3430 
   3431 unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
   3432                                                       unsigned SrcOpIdx1,
   3433                                                       unsigned SrcOpIdx2) const {
   3434   unsigned Opc = MI->getOpcode();
   3435 
   3436   // Define the array that holds FMA opcodes in groups
   3437   // of 3 opcodes(132, 213, 231) in each group.
   3438   static const unsigned RegularOpcodeGroups[][3] = {
   3439     { X86::VFMADDSSr132r,   X86::VFMADDSSr213r,   X86::VFMADDSSr231r  },
   3440     { X86::VFMADDSDr132r,   X86::VFMADDSDr213r,   X86::VFMADDSDr231r  },
   3441     { X86::VFMADDPSr132r,   X86::VFMADDPSr213r,   X86::VFMADDPSr231r  },
   3442     { X86::VFMADDPDr132r,   X86::VFMADDPDr213r,   X86::VFMADDPDr231r  },
   3443     { X86::VFMADDPSr132rY,  X86::VFMADDPSr213rY,  X86::VFMADDPSr231rY },
   3444     { X86::VFMADDPDr132rY,  X86::VFMADDPDr213rY,  X86::VFMADDPDr231rY },
   3445     { X86::VFMADDSSr132m,   X86::VFMADDSSr213m,   X86::VFMADDSSr231m  },
   3446     { X86::VFMADDSDr132m,   X86::VFMADDSDr213m,   X86::VFMADDSDr231m  },
   3447     { X86::VFMADDPSr132m,   X86::VFMADDPSr213m,   X86::VFMADDPSr231m  },
   3448     { X86::VFMADDPDr132m,   X86::VFMADDPDr213m,   X86::VFMADDPDr231m  },
   3449     { X86::VFMADDPSr132mY,  X86::VFMADDPSr213mY,  X86::VFMADDPSr231mY },
   3450     { X86::VFMADDPDr132mY,  X86::VFMADDPDr213mY,  X86::VFMADDPDr231mY },
   3451 
   3452     { X86::VFMSUBSSr132r,   X86::VFMSUBSSr213r,   X86::VFMSUBSSr231r  },
   3453     { X86::VFMSUBSDr132r,   X86::VFMSUBSDr213r,   X86::VFMSUBSDr231r  },
   3454     { X86::VFMSUBPSr132r,   X86::VFMSUBPSr213r,   X86::VFMSUBPSr231r  },
   3455     { X86::VFMSUBPDr132r,   X86::VFMSUBPDr213r,   X86::VFMSUBPDr231r  },
   3456     { X86::VFMSUBPSr132rY,  X86::VFMSUBPSr213rY,  X86::VFMSUBPSr231rY },
   3457     { X86::VFMSUBPDr132rY,  X86::VFMSUBPDr213rY,  X86::VFMSUBPDr231rY },
   3458     { X86::VFMSUBSSr132m,   X86::VFMSUBSSr213m,   X86::VFMSUBSSr231m  },
   3459     { X86::VFMSUBSDr132m,   X86::VFMSUBSDr213m,   X86::VFMSUBSDr231m  },
   3460     { X86::VFMSUBPSr132m,   X86::VFMSUBPSr213m,   X86::VFMSUBPSr231m  },
   3461     { X86::VFMSUBPDr132m,   X86::VFMSUBPDr213m,   X86::VFMSUBPDr231m  },
   3462     { X86::VFMSUBPSr132mY,  X86::VFMSUBPSr213mY,  X86::VFMSUBPSr231mY },
   3463     { X86::VFMSUBPDr132mY,  X86::VFMSUBPDr213mY,  X86::VFMSUBPDr231mY },
   3464 
   3465     { X86::VFNMADDSSr132r,  X86::VFNMADDSSr213r,  X86::VFNMADDSSr231r  },
   3466     { X86::VFNMADDSDr132r,  X86::VFNMADDSDr213r,  X86::VFNMADDSDr231r  },
   3467     { X86::VFNMADDPSr132r,  X86::VFNMADDPSr213r,  X86::VFNMADDPSr231r  },
   3468     { X86::VFNMADDPDr132r,  X86::VFNMADDPDr213r,  X86::VFNMADDPDr231r  },
   3469     { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
   3470     { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
   3471     { X86::VFNMADDSSr132m,  X86::VFNMADDSSr213m,  X86::VFNMADDSSr231m  },
   3472     { X86::VFNMADDSDr132m,  X86::VFNMADDSDr213m,  X86::VFNMADDSDr231m  },
   3473     { X86::VFNMADDPSr132m,  X86::VFNMADDPSr213m,  X86::VFNMADDPSr231m  },
   3474     { X86::VFNMADDPDr132m,  X86::VFNMADDPDr213m,  X86::VFNMADDPDr231m  },
   3475     { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
   3476     { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
   3477 
   3478     { X86::VFNMSUBSSr132r,  X86::VFNMSUBSSr213r,  X86::VFNMSUBSSr231r  },
   3479     { X86::VFNMSUBSDr132r,  X86::VFNMSUBSDr213r,  X86::VFNMSUBSDr231r  },
   3480     { X86::VFNMSUBPSr132r,  X86::VFNMSUBPSr213r,  X86::VFNMSUBPSr231r  },
   3481     { X86::VFNMSUBPDr132r,  X86::VFNMSUBPDr213r,  X86::VFNMSUBPDr231r  },
   3482     { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
   3483     { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
   3484     { X86::VFNMSUBSSr132m,  X86::VFNMSUBSSr213m,  X86::VFNMSUBSSr231m  },
   3485     { X86::VFNMSUBSDr132m,  X86::VFNMSUBSDr213m,  X86::VFNMSUBSDr231m  },
   3486     { X86::VFNMSUBPSr132m,  X86::VFNMSUBPSr213m,  X86::VFNMSUBPSr231m  },
   3487     { X86::VFNMSUBPDr132m,  X86::VFNMSUBPDr213m,  X86::VFNMSUBPDr231m  },
   3488     { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
   3489     { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
   3490 
   3491     { X86::VFMADDSUBPSr132r,  X86::VFMADDSUBPSr213r,  X86::VFMADDSUBPSr231r  },
   3492     { X86::VFMADDSUBPDr132r,  X86::VFMADDSUBPDr213r,  X86::VFMADDSUBPDr231r  },
   3493     { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
   3494     { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
   3495     { X86::VFMADDSUBPSr132m,  X86::VFMADDSUBPSr213m,  X86::VFMADDSUBPSr231m  },
   3496     { X86::VFMADDSUBPDr132m,  X86::VFMADDSUBPDr213m,  X86::VFMADDSUBPDr231m  },
   3497     { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
   3498     { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
   3499 
   3500     { X86::VFMSUBADDPSr132r,  X86::VFMSUBADDPSr213r,  X86::VFMSUBADDPSr231r  },
   3501     { X86::VFMSUBADDPDr132r,  X86::VFMSUBADDPDr213r,  X86::VFMSUBADDPDr231r  },
   3502     { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
   3503     { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
   3504     { X86::VFMSUBADDPSr132m,  X86::VFMSUBADDPSr213m,  X86::VFMSUBADDPSr231m  },
   3505     { X86::VFMSUBADDPDr132m,  X86::VFMSUBADDPDr213m,  X86::VFMSUBADDPDr231m  },
   3506     { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
   3507     { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
   3508   };
   3509 
   3510   // Define the array that holds FMA*_Int opcodes in groups
   3511   // of 3 opcodes(132, 213, 231) in each group.
   3512   static const unsigned IntrinOpcodeGroups[][3] = {
   3513     { X86::VFMADDSSr132r_Int,  X86::VFMADDSSr213r_Int,  X86::VFMADDSSr231r_Int },
   3514     { X86::VFMADDSDr132r_Int,  X86::VFMADDSDr213r_Int,  X86::VFMADDSDr231r_Int },
   3515     { X86::VFMADDSSr132m_Int,  X86::VFMADDSSr213m_Int,  X86::VFMADDSSr231m_Int },
   3516     { X86::VFMADDSDr132m_Int,  X86::VFMADDSDr213m_Int,  X86::VFMADDSDr231m_Int },
   3517 
   3518     { X86::VFMSUBSSr132r_Int,  X86::VFMSUBSSr213r_Int,  X86::VFMSUBSSr231r_Int },
   3519     { X86::VFMSUBSDr132r_Int,  X86::VFMSUBSDr213r_Int,  X86::VFMSUBSDr231r_Int },
   3520     { X86::VFMSUBSSr132m_Int,  X86::VFMSUBSSr213m_Int,  X86::VFMSUBSSr231m_Int },
   3521     { X86::VFMSUBSDr132m_Int,  X86::VFMSUBSDr213m_Int,  X86::VFMSUBSDr231m_Int },
   3522 
   3523     { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
   3524     { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
   3525     { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
   3526     { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
   3527 
   3528     { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
   3529     { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
   3530     { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
   3531     { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
   3532   };
   3533 
   3534   const unsigned Form132Index = 0;
   3535   const unsigned Form213Index = 1;
   3536   const unsigned Form231Index = 2;
   3537   const unsigned FormsNum = 3;
   3538 
   3539   bool IsIntrinOpcode;
   3540   isFMA3(Opc, &IsIntrinOpcode);
   3541 
   3542   size_t GroupsNum;
   3543   const unsigned (*OpcodeGroups)[3];
   3544   if (IsIntrinOpcode) {
   3545     GroupsNum = array_lengthof(IntrinOpcodeGroups);
   3546     OpcodeGroups = IntrinOpcodeGroups;
   3547   } else {
   3548     GroupsNum = array_lengthof(RegularOpcodeGroups);
   3549     OpcodeGroups = RegularOpcodeGroups;
   3550   }
   3551 
   3552   const unsigned *FoundOpcodesGroup = nullptr;
   3553   size_t FormIndex;
   3554 
   3555   // Look for the input opcode in the corresponding opcodes table.
   3556   for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
   3557          ++GroupIndex) {
   3558     for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
   3559       if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
   3560         FoundOpcodesGroup = OpcodeGroups[GroupIndex];
   3561         break;
   3562       }
   3563     }
   3564   }
   3565 
   3566   // The input opcode does not match with any of the opcodes from the tables.
   3567   // The unsupported FMA opcode must be added to one of the two opcode groups
   3568   // defined above.
   3569   assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
   3570 
   3571   // Put the lowest index to SrcOpIdx1 to simplify the checks below.
   3572   if (SrcOpIdx1 > SrcOpIdx2)
   3573     std::swap(SrcOpIdx1, SrcOpIdx2);
   3574 
   3575   // TODO: Commuting the 1st operand of FMA*_Int requires some additional
   3576   // analysis. The commute optimization is legal only if all users of FMA*_Int
   3577   // use only the lowest element of the FMA*_Int instruction. Such analysis are
   3578   // not implemented yet. So, just return 0 in that case.
   3579   // When such analysis are available this place will be the right place for
   3580   // calling it.
   3581   if (IsIntrinOpcode && SrcOpIdx1 == 1)
   3582     return 0;
   3583 
   3584   unsigned Case;
   3585   if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
   3586     Case = 0;
   3587   else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
   3588     Case = 1;
   3589   else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
   3590     Case = 2;
   3591   else
   3592     return 0;
   3593 
   3594   // Define the FMA forms mapping array that helps to map input FMA form
   3595   // to output FMA form to preserve the operation semantics after
   3596   // commuting the operands.
   3597   static const unsigned FormMapping[][3] = {
   3598     // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
   3599     // FMA132 A, C, b; ==> FMA231 C, A, b;
   3600     // FMA213 B, A, c; ==> FMA213 A, B, c;
   3601     // FMA231 C, A, b; ==> FMA132 A, C, b;
   3602     { Form231Index, Form213Index, Form132Index },
   3603     // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
   3604     // FMA132 A, c, B; ==> FMA132 B, c, A;
   3605     // FMA213 B, a, C; ==> FMA231 C, a, B;
   3606     // FMA231 C, a, B; ==> FMA213 B, a, C;
   3607     { Form132Index, Form231Index, Form213Index },
   3608     // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
   3609     // FMA132 a, C, B; ==> FMA213 a, B, C;
   3610     // FMA213 b, A, C; ==> FMA132 b, C, A;
   3611     // FMA231 c, A, B; ==> FMA231 c, B, A;
   3612     { Form213Index, Form132Index, Form231Index }
   3613   };
   3614 
   3615   // Everything is ready, just adjust the FMA opcode and return it.
   3616   FormIndex = FormMapping[Case][FormIndex];
   3617   return FoundOpcodesGroup[FormIndex];
   3618 }
   3619 
   3620 bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
   3621                                          unsigned &SrcOpIdx1,
   3622                                          unsigned &SrcOpIdx2) const {
   3623   switch (MI->getOpcode()) {
   3624     case X86::CMPPDrri:
   3625     case X86::CMPPSrri:
   3626     case X86::VCMPPDrri:
   3627     case X86::VCMPPSrri:
   3628     case X86::VCMPPDYrri:
   3629     case X86::VCMPPSYrri: {
   3630       // Float comparison can be safely commuted for
   3631       // Ordered/Unordered/Equal/NotEqual tests
   3632       unsigned Imm = MI->getOperand(3).getImm() & 0x7;
   3633       switch (Imm) {
   3634         case 0x00: // EQUAL
   3635         case 0x03: // UNORDERED
   3636         case 0x04: // NOT EQUAL
   3637         case 0x07: // ORDERED
   3638           // The indices of the commutable operands are 1 and 2.
   3639           // Assign them to the returned operand indices here.
   3640           return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
   3641       }
   3642       return false;
   3643     }
   3644     default:
   3645       if (isFMA3(MI->getOpcode()))
   3646         return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
   3647       return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
   3648   }
   3649   return false;
   3650 }
   3651 
   3652 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
   3653   switch (BrOpc) {
   3654   default: return X86::COND_INVALID;
   3655   case X86::JE_1:  return X86::COND_E;
   3656   case X86::JNE_1: return X86::COND_NE;
   3657   case X86::JL_1:  return X86::COND_L;
   3658   case X86::JLE_1: return X86::COND_LE;
   3659   case X86::JG_1:  return X86::COND_G;
   3660   case X86::JGE_1: return X86::COND_GE;
   3661   case X86::JB_1:  return X86::COND_B;
   3662   case X86::JBE_1: return X86::COND_BE;
   3663   case X86::JA_1:  return X86::COND_A;
   3664   case X86::JAE_1: return X86::COND_AE;
   3665   case X86::JS_1:  return X86::COND_S;
   3666   case X86::JNS_1: return X86::COND_NS;
   3667   case X86::JP_1:  return X86::COND_P;
   3668   case X86::JNP_1: return X86::COND_NP;
   3669   case X86::JO_1:  return X86::COND_O;
   3670   case X86::JNO_1: return X86::COND_NO;
   3671   }
   3672 }
   3673 
   3674 /// Return condition code of a SET opcode.
   3675 static X86::CondCode getCondFromSETOpc(unsigned Opc) {
   3676   switch (Opc) {
   3677   default: return X86::COND_INVALID;
   3678   case X86::SETAr:  case X86::SETAm:  return X86::COND_A;
   3679   case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
   3680   case X86::SETBr:  case X86::SETBm:  return X86::COND_B;
   3681   case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
   3682   case X86::SETEr:  case X86::SETEm:  return X86::COND_E;
   3683   case X86::SETGr:  case X86::SETGm:  return X86::COND_G;
   3684   case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
   3685   case X86::SETLr:  case X86::SETLm:  return X86::COND_L;
   3686   case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
   3687   case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
   3688   case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
   3689   case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
   3690   case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
   3691   case X86::SETOr:  case X86::SETOm:  return X86::COND_O;
   3692   case X86::SETPr:  case X86::SETPm:  return X86::COND_P;
   3693   case X86::SETSr:  case X86::SETSm:  return X86::COND_S;
   3694   }
   3695 }
   3696 
   3697 /// Return condition code of a CMov opcode.
   3698 X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
   3699   switch (Opc) {
   3700   default: return X86::COND_INVALID;
   3701   case X86::CMOVA16rm:  case X86::CMOVA16rr:  case X86::CMOVA32rm:
   3702   case X86::CMOVA32rr:  case X86::CMOVA64rm:  case X86::CMOVA64rr:
   3703     return X86::COND_A;
   3704   case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
   3705   case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
   3706     return X86::COND_AE;
   3707   case X86::CMOVB16rm:  case X86::CMOVB16rr:  case X86::CMOVB32rm:
   3708   case X86::CMOVB32rr:  case X86::CMOVB64rm:  case X86::CMOVB64rr:
   3709     return X86::COND_B;
   3710   case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
   3711   case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
   3712     return X86::COND_BE;
   3713   case X86::CMOVE16rm:  case X86::CMOVE16rr:  case X86::CMOVE32rm:
   3714   case X86::CMOVE32rr:  case X86::CMOVE64rm:  case X86::CMOVE64rr:
   3715     return X86::COND_E;
   3716   case X86::CMOVG16rm:  case X86::CMOVG16rr:  case X86::CMOVG32rm:
   3717   case X86::CMOVG32rr:  case X86::CMOVG64rm:  case X86::CMOVG64rr:
   3718     return X86::COND_G;
   3719   case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
   3720   case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
   3721     return X86::COND_GE;
   3722   case X86::CMOVL16rm:  case X86::CMOVL16rr:  case X86::CMOVL32rm:
   3723   case X86::CMOVL32rr:  case X86::CMOVL64rm:  case X86::CMOVL64rr:
   3724     return X86::COND_L;
   3725   case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
   3726   case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
   3727     return X86::COND_LE;
   3728   case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
   3729   case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
   3730     return X86::COND_NE;
   3731   case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
   3732   case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
   3733     return X86::COND_NO;
   3734   case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
   3735   case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
   3736     return X86::COND_NP;
   3737   case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
   3738   case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
   3739     return X86::COND_NS;
   3740   case X86::CMOVO16rm:  case X86::CMOVO16rr:  case X86::CMOVO32rm:
   3741   case X86::CMOVO32rr:  case X86::CMOVO64rm:  case X86::CMOVO64rr:
   3742     return X86::COND_O;
   3743   case X86::CMOVP16rm:  case X86::CMOVP16rr:  case X86::CMOVP32rm:
   3744   case X86::CMOVP32rr:  case X86::CMOVP64rm:  case X86::CMOVP64rr:
   3745     return X86::COND_P;
   3746   case X86::CMOVS16rm:  case X86::CMOVS16rr:  case X86::CMOVS32rm:
   3747   case X86::CMOVS32rr:  case X86::CMOVS64rm:  case X86::CMOVS64rr:
   3748     return X86::COND_S;
   3749   }
   3750 }
   3751 
   3752 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
   3753   switch (CC) {
   3754   default: llvm_unreachable("Illegal condition code!");
   3755   case X86::COND_E:  return X86::JE_1;
   3756   case X86::COND_NE: return X86::JNE_1;
   3757   case X86::COND_L:  return X86::JL_1;
   3758   case X86::COND_LE: return X86::JLE_1;
   3759   case X86::COND_G:  return X86::JG_1;
   3760   case X86::COND_GE: return X86::JGE_1;
   3761   case X86::COND_B:  return X86::JB_1;
   3762   case X86::COND_BE: return X86::JBE_1;
   3763   case X86::COND_A:  return X86::JA_1;
   3764   case X86::COND_AE: return X86::JAE_1;
   3765   case X86::COND_S:  return X86::JS_1;
   3766   case X86::COND_NS: return X86::JNS_1;
   3767   case X86::COND_P:  return X86::JP_1;
   3768   case X86::COND_NP: return X86::JNP_1;
   3769   case X86::COND_O:  return X86::JO_1;
   3770   case X86::COND_NO: return X86::JNO_1;
   3771   }
   3772 }
   3773 
   3774 /// Return the inverse of the specified condition,
   3775 /// e.g. turning COND_E to COND_NE.
   3776 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
   3777   switch (CC) {
   3778   default: llvm_unreachable("Illegal condition code!");
   3779   case X86::COND_E:  return X86::COND_NE;
   3780   case X86::COND_NE: return X86::COND_E;
   3781   case X86::COND_L:  return X86::COND_GE;
   3782   case X86::COND_LE: return X86::COND_G;
   3783   case X86::COND_G:  return X86::COND_LE;
   3784   case X86::COND_GE: return X86::COND_L;
   3785   case X86::COND_B:  return X86::COND_AE;
   3786   case X86::COND_BE: return X86::COND_A;
   3787   case X86::COND_A:  return X86::COND_BE;
   3788   case X86::COND_AE: return X86::COND_B;
   3789   case X86::COND_S:  return X86::COND_NS;
   3790   case X86::COND_NS: return X86::COND_S;
   3791   case X86::COND_P:  return X86::COND_NP;
   3792   case X86::COND_NP: return X86::COND_P;
   3793   case X86::COND_O:  return X86::COND_NO;
   3794   case X86::COND_NO: return X86::COND_O;
   3795   }
   3796 }
   3797 
   3798 /// Assuming the flags are set by MI(a,b), return the condition code if we
   3799 /// modify the instructions such that flags are set by MI(b,a).
   3800 static X86::CondCode getSwappedCondition(X86::CondCode CC) {
   3801   switch (CC) {
   3802   default: return X86::COND_INVALID;
   3803   case X86::COND_E:  return X86::COND_E;
   3804   case X86::COND_NE: return X86::COND_NE;
   3805   case X86::COND_L:  return X86::COND_G;
   3806   case X86::COND_LE: return X86::COND_GE;
   3807   case X86::COND_G:  return X86::COND_L;
   3808   case X86::COND_GE: return X86::COND_LE;
   3809   case X86::COND_B:  return X86::COND_A;
   3810   case X86::COND_BE: return X86::COND_AE;
   3811   case X86::COND_A:  return X86::COND_B;
   3812   case X86::COND_AE: return X86::COND_BE;
   3813   }
   3814 }
   3815 
   3816 /// Return a set opcode for the given condition and
   3817 /// whether it has memory operand.
   3818 unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
   3819   static const uint16_t Opc[16][2] = {
   3820     { X86::SETAr,  X86::SETAm  },
   3821     { X86::SETAEr, X86::SETAEm },
   3822     { X86::SETBr,  X86::SETBm  },
   3823     { X86::SETBEr, X86::SETBEm },
   3824     { X86::SETEr,  X86::SETEm  },
   3825     { X86::SETGr,  X86::SETGm  },
   3826     { X86::SETGEr, X86::SETGEm },
   3827     { X86::SETLr,  X86::SETLm  },
   3828     { X86::SETLEr, X86::SETLEm },
   3829     { X86::SETNEr, X86::SETNEm },
   3830     { X86::SETNOr, X86::SETNOm },
   3831     { X86::SETNPr, X86::SETNPm },
   3832     { X86::SETNSr, X86::SETNSm },
   3833     { X86::SETOr,  X86::SETOm  },
   3834     { X86::SETPr,  X86::SETPm  },
   3835     { X86::SETSr,  X86::SETSm  }
   3836   };
   3837 
   3838   assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
   3839   return Opc[CC][HasMemoryOperand ? 1 : 0];
   3840 }
   3841 
   3842 /// Return a cmov opcode for the given condition,
   3843 /// register size in bytes, and operand type.
   3844 unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
   3845                               bool HasMemoryOperand) {
   3846   static const uint16_t Opc[32][3] = {
   3847     { X86::CMOVA16rr,  X86::CMOVA32rr,  X86::CMOVA64rr  },
   3848     { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
   3849     { X86::CMOVB16rr,  X86::CMOVB32rr,  X86::CMOVB64rr  },
   3850     { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
   3851     { X86::CMOVE16rr,  X86::CMOVE32rr,  X86::CMOVE64rr  },
   3852     { X86::CMOVG16rr,  X86::CMOVG32rr,  X86::CMOVG64rr  },
   3853     { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
   3854     { X86::CMOVL16rr,  X86::CMOVL32rr,  X86::CMOVL64rr  },
   3855     { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
   3856     { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
   3857     { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
   3858     { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
   3859     { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
   3860     { X86::CMOVO16rr,  X86::CMOVO32rr,  X86::CMOVO64rr  },
   3861     { X86::CMOVP16rr,  X86::CMOVP32rr,  X86::CMOVP64rr  },
   3862     { X86::CMOVS16rr,  X86::CMOVS32rr,  X86::CMOVS64rr  },
   3863     { X86::CMOVA16rm,  X86::CMOVA32rm,  X86::CMOVA64rm  },
   3864     { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
   3865     { X86::CMOVB16rm,  X86::CMOVB32rm,  X86::CMOVB64rm  },
   3866     { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
   3867     { X86::CMOVE16rm,  X86::CMOVE32rm,  X86::CMOVE64rm  },
   3868     { X86::CMOVG16rm,  X86::CMOVG32rm,  X86::CMOVG64rm  },
   3869     { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
   3870     { X86::CMOVL16rm,  X86::CMOVL32rm,  X86::CMOVL64rm  },
   3871     { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
   3872     { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
   3873     { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
   3874     { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
   3875     { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
   3876     { X86::CMOVO16rm,  X86::CMOVO32rm,  X86::CMOVO64rm  },
   3877     { X86::CMOVP16rm,  X86::CMOVP32rm,  X86::CMOVP64rm  },
   3878     { X86::CMOVS16rm,  X86::CMOVS32rm,  X86::CMOVS64rm  }
   3879   };
   3880 
   3881   assert(CC < 16 && "Can only handle standard cond codes");
   3882   unsigned Idx = HasMemoryOperand ? 16+CC : CC;
   3883   switch(RegBytes) {
   3884   default: llvm_unreachable("Illegal register size!");
   3885   case 2: return Opc[Idx][0];
   3886   case 4: return Opc[Idx][1];
   3887   case 8: return Opc[Idx][2];
   3888   }
   3889 }
   3890 
   3891 bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
   3892   if (!MI->isTerminator()) return false;
   3893 
   3894   // Conditional branch is a special case.
   3895   if (MI->isBranch() && !MI->isBarrier())
   3896     return true;
   3897   if (!MI->isPredicable())
   3898     return true;
   3899   return !isPredicated(MI);
   3900 }
   3901 
   3902 bool X86InstrInfo::AnalyzeBranchImpl(
   3903     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
   3904     SmallVectorImpl<MachineOperand> &Cond,
   3905     SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
   3906 
   3907   // Start from the bottom of the block and work up, examining the
   3908   // terminator instructions.
   3909   MachineBasicBlock::iterator I = MBB.end();
   3910   MachineBasicBlock::iterator UnCondBrIter = MBB.end();
   3911   while (I != MBB.begin()) {
   3912     --I;
   3913     if (I->isDebugValue())
   3914       continue;
   3915 
   3916     // Working from the bottom, when we see a non-terminator instruction, we're
   3917     // done.
   3918     if (!isUnpredicatedTerminator(I))
   3919       break;
   3920 
   3921     // A terminator that isn't a branch can't easily be handled by this
   3922     // analysis.
   3923     if (!I->isBranch())
   3924       return true;
   3925 
   3926     // Handle unconditional branches.
   3927     if (I->getOpcode() == X86::JMP_1) {
   3928       UnCondBrIter = I;
   3929 
   3930       if (!AllowModify) {
   3931         TBB = I->getOperand(0).getMBB();
   3932         continue;
   3933       }
   3934 
   3935       // If the block has any instructions after a JMP, delete them.
   3936       while (std::next(I) != MBB.end())
   3937         std::next(I)->eraseFromParent();
   3938 
   3939       Cond.clear();
   3940       FBB = nullptr;
   3941 
   3942       // Delete the JMP if it's equivalent to a fall-through.
   3943       if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
   3944         TBB = nullptr;
   3945         I->eraseFromParent();
   3946         I = MBB.end();
   3947         UnCondBrIter = MBB.end();
   3948         continue;
   3949       }
   3950 
   3951       // TBB is used to indicate the unconditional destination.
   3952       TBB = I->getOperand(0).getMBB();
   3953       continue;
   3954     }
   3955 
   3956     // Handle conditional branches.
   3957     X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
   3958     if (BranchCode == X86::COND_INVALID)
   3959       return true;  // Can't handle indirect branch.
   3960 
   3961     // Working from the bottom, handle the first conditional branch.
   3962     if (Cond.empty()) {
   3963       MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
   3964       if (AllowModify && UnCondBrIter != MBB.end() &&
   3965           MBB.isLayoutSuccessor(TargetBB)) {
   3966         // If we can modify the code and it ends in something like:
   3967         //
   3968         //     jCC L1
   3969         //     jmp L2
   3970         //   L1:
   3971         //     ...
   3972         //   L2:
   3973         //
   3974         // Then we can change this to:
   3975         //
   3976         //     jnCC L2
   3977         //   L1:
   3978         //     ...
   3979         //   L2:
   3980         //
   3981         // Which is a bit more efficient.
   3982         // We conditionally jump to the fall-through block.
   3983         BranchCode = GetOppositeBranchCondition(BranchCode);
   3984         unsigned JNCC = GetCondBranchFromCond(BranchCode);
   3985         MachineBasicBlock::iterator OldInst = I;
   3986 
   3987         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
   3988           .addMBB(UnCondBrIter->getOperand(0).getMBB());
   3989         BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
   3990           .addMBB(TargetBB);
   3991 
   3992         OldInst->eraseFromParent();
   3993         UnCondBrIter->eraseFromParent();
   3994 
   3995         // Restart the analysis.
   3996         UnCondBrIter = MBB.end();
   3997         I = MBB.end();
   3998         continue;
   3999       }
   4000 
   4001       FBB = TBB;
   4002       TBB = I->getOperand(0).getMBB();
   4003       Cond.push_back(MachineOperand::CreateImm(BranchCode));
   4004       CondBranches.push_back(I);
   4005       continue;
   4006     }
   4007 
   4008     // Handle subsequent conditional branches. Only handle the case where all
   4009     // conditional branches branch to the same destination and their condition
   4010     // opcodes fit one of the special multi-branch idioms.
   4011     assert(Cond.size() == 1);
   4012     assert(TBB);
   4013 
   4014     // Only handle the case where all conditional branches branch to the same
   4015     // destination.
   4016     if (TBB != I->getOperand(0).getMBB())
   4017       return true;
   4018 
   4019     // If the conditions are the same, we can leave them alone.
   4020     X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
   4021     if (OldBranchCode == BranchCode)
   4022       continue;
   4023 
   4024     // If they differ, see if they fit one of the known patterns. Theoretically,
   4025     // we could handle more patterns here, but we shouldn't expect to see them
   4026     // if instruction selection has done a reasonable job.
   4027     if ((OldBranchCode == X86::COND_NP &&
   4028          BranchCode == X86::COND_E) ||
   4029         (OldBranchCode == X86::COND_E &&
   4030          BranchCode == X86::COND_NP))
   4031       BranchCode = X86::COND_NP_OR_E;
   4032     else if ((OldBranchCode == X86::COND_P &&
   4033               BranchCode == X86::COND_NE) ||
   4034              (OldBranchCode == X86::COND_NE &&
   4035               BranchCode == X86::COND_P))
   4036       BranchCode = X86::COND_NE_OR_P;
   4037     else
   4038       return true;
   4039 
   4040     // Update the MachineOperand.
   4041     Cond[0].setImm(BranchCode);
   4042     CondBranches.push_back(I);
   4043   }
   4044 
   4045   return false;
   4046 }
   4047 
   4048 bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
   4049                                  MachineBasicBlock *&TBB,
   4050                                  MachineBasicBlock *&FBB,
   4051                                  SmallVectorImpl<MachineOperand> &Cond,
   4052                                  bool AllowModify) const {
   4053   SmallVector<MachineInstr *, 4> CondBranches;
   4054   return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
   4055 }
   4056 
   4057 bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
   4058                                           MachineBranchPredicate &MBP,
   4059                                           bool AllowModify) const {
   4060   using namespace std::placeholders;
   4061 
   4062   SmallVector<MachineOperand, 4> Cond;
   4063   SmallVector<MachineInstr *, 4> CondBranches;
   4064   if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
   4065                         AllowModify))
   4066     return true;
   4067 
   4068   if (Cond.size() != 1)
   4069     return true;
   4070 
   4071   assert(MBP.TrueDest && "expected!");
   4072 
   4073   if (!MBP.FalseDest)
   4074     MBP.FalseDest = MBB.getNextNode();
   4075 
   4076   const TargetRegisterInfo *TRI = &getRegisterInfo();
   4077 
   4078   MachineInstr *ConditionDef = nullptr;
   4079   bool SingleUseCondition = true;
   4080 
   4081   for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
   4082     if (I->modifiesRegister(X86::EFLAGS, TRI)) {
   4083       ConditionDef = &*I;
   4084       break;
   4085     }
   4086 
   4087     if (I->readsRegister(X86::EFLAGS, TRI))
   4088       SingleUseCondition = false;
   4089   }
   4090 
   4091   if (!ConditionDef)
   4092     return true;
   4093 
   4094   if (SingleUseCondition) {
   4095     for (auto *Succ : MBB.successors())
   4096       if (Succ->isLiveIn(X86::EFLAGS))
   4097         SingleUseCondition = false;
   4098   }
   4099 
   4100   MBP.ConditionDef = ConditionDef;
   4101   MBP.SingleUseCondition = SingleUseCondition;
   4102 
   4103   // Currently we only recognize the simple pattern:
   4104   //
   4105   //   test %reg, %reg
   4106   //   je %label
   4107   //
   4108   const unsigned TestOpcode =
   4109       Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
   4110 
   4111   if (ConditionDef->getOpcode() == TestOpcode &&
   4112       ConditionDef->getNumOperands() == 3 &&
   4113       ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
   4114       (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
   4115     MBP.LHS = ConditionDef->getOperand(0);
   4116     MBP.RHS = MachineOperand::CreateImm(0);
   4117     MBP.Predicate = Cond[0].getImm() == X86::COND_NE
   4118                         ? MachineBranchPredicate::PRED_NE
   4119                         : MachineBranchPredicate::PRED_EQ;
   4120     return false;
   4121   }
   4122 
   4123   return true;
   4124 }
   4125 
   4126 unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
   4127   MachineBasicBlock::iterator I = MBB.end();
   4128   unsigned Count = 0;
   4129 
   4130   while (I != MBB.begin()) {
   4131     --I;
   4132     if (I->isDebugValue())
   4133       continue;
   4134     if (I->getOpcode() != X86::JMP_1 &&
   4135         getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
   4136       break;
   4137     // Remove the branch.
   4138     I->eraseFromParent();
   4139     I = MBB.end();
   4140     ++Count;
   4141   }
   4142 
   4143   return Count;
   4144 }
   4145 
   4146 unsigned
   4147 X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   4148                            MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
   4149                            DebugLoc DL) const {
   4150   // Shouldn't be a fall through.
   4151   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
   4152   assert((Cond.size() == 1 || Cond.size() == 0) &&
   4153          "X86 branch conditions have one component!");
   4154 
   4155   if (Cond.empty()) {
   4156     // Unconditional branch?
   4157     assert(!FBB && "Unconditional branch with multiple successors!");
   4158     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
   4159     return 1;
   4160   }
   4161 
   4162   // Conditional branch.
   4163   unsigned Count = 0;
   4164   X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
   4165   switch (CC) {
   4166   case X86::COND_NP_OR_E:
   4167     // Synthesize NP_OR_E with two branches.
   4168     BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
   4169     ++Count;
   4170     BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
   4171     ++Count;
   4172     break;
   4173   case X86::COND_NE_OR_P:
   4174     // Synthesize NE_OR_P with two branches.
   4175     BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
   4176     ++Count;
   4177     BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
   4178     ++Count;
   4179     break;
   4180   default: {
   4181     unsigned Opc = GetCondBranchFromCond(CC);
   4182     BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
   4183     ++Count;
   4184   }
   4185   }
   4186   if (FBB) {
   4187     // Two-way Conditional branch. Insert the second branch.
   4188     BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
   4189     ++Count;
   4190   }
   4191   return Count;
   4192 }
   4193 
   4194 bool X86InstrInfo::
   4195 canInsertSelect(const MachineBasicBlock &MBB,
   4196                 ArrayRef<MachineOperand> Cond,
   4197                 unsigned TrueReg, unsigned FalseReg,
   4198                 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
   4199   // Not all subtargets have cmov instructions.
   4200   if (!Subtarget.hasCMov())
   4201     return false;
   4202   if (Cond.size() != 1)
   4203     return false;
   4204   // We cannot do the composite conditions, at least not in SSA form.
   4205   if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
   4206     return false;
   4207 
   4208   // Check register classes.
   4209   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   4210   const TargetRegisterClass *RC =
   4211     RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
   4212   if (!RC)
   4213     return false;
   4214 
   4215   // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
   4216   if (X86::GR16RegClass.hasSubClassEq(RC) ||
   4217       X86::GR32RegClass.hasSubClassEq(RC) ||
   4218       X86::GR64RegClass.hasSubClassEq(RC)) {
   4219     // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
   4220     // Bridge. Probably Ivy Bridge as well.
   4221     CondCycles = 2;
   4222     TrueCycles = 2;
   4223     FalseCycles = 2;
   4224     return true;
   4225   }
   4226 
   4227   // Can't do vectors.
   4228   return false;
   4229 }
   4230 
   4231 void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
   4232                                 MachineBasicBlock::iterator I, DebugLoc DL,
   4233                                 unsigned DstReg, ArrayRef<MachineOperand> Cond,
   4234                                 unsigned TrueReg, unsigned FalseReg) const {
   4235    MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
   4236    assert(Cond.size() == 1 && "Invalid Cond array");
   4237    unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
   4238                                   MRI.getRegClass(DstReg)->getSize(),
   4239                                   false/*HasMemoryOperand*/);
   4240    BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
   4241 }
   4242 
   4243 /// Test if the given register is a physical h register.
   4244 static bool isHReg(unsigned Reg) {
   4245   return X86::GR8_ABCD_HRegClass.contains(Reg);
   4246 }
   4247 
   4248 // Try and copy between VR128/VR64 and GR64 registers.
   4249 static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
   4250                                         const X86Subtarget &Subtarget) {
   4251 
   4252   // SrcReg(VR128) -> DestReg(GR64)
   4253   // SrcReg(VR64)  -> DestReg(GR64)
   4254   // SrcReg(GR64)  -> DestReg(VR128)
   4255   // SrcReg(GR64)  -> DestReg(VR64)
   4256 
   4257   bool HasAVX = Subtarget.hasAVX();
   4258   bool HasAVX512 = Subtarget.hasAVX512();
   4259   if (X86::GR64RegClass.contains(DestReg)) {
   4260     if (X86::VR128XRegClass.contains(SrcReg))
   4261       // Copy from a VR128 register to a GR64 register.
   4262       return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
   4263                                                X86::MOVPQIto64rr);
   4264     if (X86::VR64RegClass.contains(SrcReg))
   4265       // Copy from a VR64 register to a GR64 register.
   4266       return X86::MMX_MOVD64from64rr;
   4267   } else if (X86::GR64RegClass.contains(SrcReg)) {
   4268     // Copy from a GR64 register to a VR128 register.
   4269     if (X86::VR128XRegClass.contains(DestReg))
   4270       return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
   4271                                                X86::MOV64toPQIrr);
   4272     // Copy from a GR64 register to a VR64 register.
   4273     if (X86::VR64RegClass.contains(DestReg))
   4274       return X86::MMX_MOVD64to64rr;
   4275   }
   4276 
   4277   // SrcReg(FR32) -> DestReg(GR32)
   4278   // SrcReg(GR32) -> DestReg(FR32)
   4279 
   4280   if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
   4281     // Copy from a FR32 register to a GR32 register.
   4282     return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
   4283 
   4284   if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
   4285     // Copy from a GR32 register to a FR32 register.
   4286     return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
   4287   return 0;
   4288 }
   4289 
   4290 static bool MaskRegClassContains(unsigned Reg) {
   4291   return X86::VK8RegClass.contains(Reg) ||
   4292          X86::VK16RegClass.contains(Reg) ||
   4293          X86::VK32RegClass.contains(Reg) ||
   4294          X86::VK64RegClass.contains(Reg) ||
   4295          X86::VK1RegClass.contains(Reg);
   4296 }
   4297 
   4298 static bool GRRegClassContains(unsigned Reg) {
   4299   return X86::GR64RegClass.contains(Reg) ||
   4300          X86::GR32RegClass.contains(Reg) ||
   4301          X86::GR16RegClass.contains(Reg) ||
   4302          X86::GR8RegClass.contains(Reg);
   4303 }
   4304 static
   4305 unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
   4306   if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
   4307     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
   4308     return X86::KMOVBrk;
   4309   }
   4310   if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
   4311     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
   4312     return X86::KMOVBkr;
   4313   }
   4314   return 0;
   4315 }
   4316 
   4317 static
   4318 unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
   4319   if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
   4320     return X86::KMOVQkk;
   4321   if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
   4322     return X86::KMOVDrk;
   4323   if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
   4324     return X86::KMOVQrk;
   4325   if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
   4326     return X86::KMOVDkr;
   4327   if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
   4328     return X86::KMOVQkr;
   4329   return 0;
   4330 }
   4331 
   4332 static
   4333 unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
   4334                                   const X86Subtarget &Subtarget)
   4335 {
   4336   if (Subtarget.hasDQI())
   4337     if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
   4338       return Opc;
   4339   if (Subtarget.hasBWI())
   4340     if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
   4341       return Opc;
   4342   if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
   4343       X86::VR256XRegClass.contains(DestReg, SrcReg) ||
   4344       X86::VR512RegClass.contains(DestReg, SrcReg)) {
   4345      DestReg = get512BitSuperRegister(DestReg);
   4346      SrcReg = get512BitSuperRegister(SrcReg);
   4347      return X86::VMOVAPSZrr;
   4348   }
   4349   if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
   4350     return X86::KMOVWkk;
   4351   if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
   4352     SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
   4353     return X86::KMOVWkr;
   4354   }
   4355   if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
   4356     DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
   4357     return X86::KMOVWrk;
   4358   }
   4359   return 0;
   4360 }
   4361 
   4362 void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   4363                                MachineBasicBlock::iterator MI, DebugLoc DL,
   4364                                unsigned DestReg, unsigned SrcReg,
   4365                                bool KillSrc) const {
   4366   // First deal with the normal symmetric copies.
   4367   bool HasAVX = Subtarget.hasAVX();
   4368   bool HasAVX512 = Subtarget.hasAVX512();
   4369   unsigned Opc = 0;
   4370   if (X86::GR64RegClass.contains(DestReg, SrcReg))
   4371     Opc = X86::MOV64rr;
   4372   else if (X86::GR32RegClass.contains(DestReg, SrcReg))
   4373     Opc = X86::MOV32rr;
   4374   else if (X86::GR16RegClass.contains(DestReg, SrcReg))
   4375     Opc = X86::MOV16rr;
   4376   else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
   4377     // Copying to or from a physical H register on x86-64 requires a NOREX
   4378     // move.  Otherwise use a normal move.
   4379     if ((isHReg(DestReg) || isHReg(SrcReg)) &&
   4380         Subtarget.is64Bit()) {
   4381       Opc = X86::MOV8rr_NOREX;
   4382       // Both operands must be encodable without an REX prefix.
   4383       assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
   4384              "8-bit H register can not be copied outside GR8_NOREX");
   4385     } else
   4386       Opc = X86::MOV8rr;
   4387   }
   4388   else if (X86::VR64RegClass.contains(DestReg, SrcReg))
   4389     Opc = X86::MMX_MOVQ64rr;
   4390   else if (HasAVX512)
   4391     Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
   4392   else if (X86::VR128RegClass.contains(DestReg, SrcReg))
   4393     Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
   4394   else if (X86::VR256RegClass.contains(DestReg, SrcReg))
   4395     Opc = X86::VMOVAPSYrr;
   4396   if (!Opc)
   4397     Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
   4398 
   4399   if (Opc) {
   4400     BuildMI(MBB, MI, DL, get(Opc), DestReg)
   4401       .addReg(SrcReg, getKillRegState(KillSrc));
   4402     return;
   4403   }
   4404 
   4405   bool FromEFLAGS = SrcReg == X86::EFLAGS;
   4406   bool ToEFLAGS = DestReg == X86::EFLAGS;
   4407   int Reg = FromEFLAGS ? DestReg : SrcReg;
   4408   bool is32 = X86::GR32RegClass.contains(Reg);
   4409   bool is64 = X86::GR64RegClass.contains(Reg);
   4410 
   4411   if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
   4412     int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
   4413     int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
   4414     int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
   4415     int Pop = is64 ? X86::POP64r : X86::POP32r;
   4416     int PopF = is64 ? X86::POPF64 : X86::POPF32;
   4417     int AX = is64 ? X86::RAX : X86::EAX;
   4418 
   4419     if (!Subtarget.hasLAHFSAHF()) {
   4420       assert(Subtarget.is64Bit() &&
   4421              "Not having LAHF/SAHF only happens on 64-bit.");
   4422       // Moving EFLAGS to / from another register requires a push and a pop.
   4423       // Notice that we have to adjust the stack if we don't want to clobber the
   4424       // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
   4425       if (FromEFLAGS) {
   4426         BuildMI(MBB, MI, DL, get(PushF));
   4427         BuildMI(MBB, MI, DL, get(Pop), DestReg);
   4428       }
   4429       if (ToEFLAGS) {
   4430         BuildMI(MBB, MI, DL, get(Push))
   4431             .addReg(SrcReg, getKillRegState(KillSrc));
   4432         BuildMI(MBB, MI, DL, get(PopF));
   4433       }
   4434       return;
   4435     }
   4436 
   4437     // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
   4438     // inefficient. Instead:
   4439     //   - Save the overflow flag OF into AL using SETO, and restore it using a
   4440     //     signed 8-bit addition of AL and INT8_MAX.
   4441     //   - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
   4442     //     using LAHF/SAHF.
   4443     //   - When RAX/EAX is live and isn't the destination register, make sure it
   4444     //     isn't clobbered by PUSH/POP'ing it before and after saving/restoring
   4445     //     the flags.
   4446     // This approach is ~2.25x faster than using PUSHF/POPF.
   4447     //
   4448     // This is still somewhat inefficient because we don't know which flags are
   4449     // actually live inside EFLAGS. Were we able to do a single SETcc instead of
   4450     // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
   4451     //
   4452     // PUSHF/POPF is also potentially incorrect because it affects other flags
   4453     // such as TF/IF/DF, which LLVM doesn't model.
   4454     //
   4455     // Notice that we have to adjust the stack if we don't want to clobber the
   4456     // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
   4457 
   4458 
   4459     bool AXDead = (Reg == AX) ||
   4460                   (MachineBasicBlock::LQR_Dead ==
   4461                    MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
   4462     if (!AXDead) {
   4463       // FIXME: If computeRegisterLiveness() reported LQR_Unknown then AX may
   4464       // actually be dead. This is not a problem for correctness as we are just
   4465       // (unnecessarily) saving+restoring a dead register. However the
   4466       // MachineVerifier expects operands that read from dead registers
   4467       // to be marked with the "undef" flag.
   4468       BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
   4469     }
   4470     if (FromEFLAGS) {
   4471       BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
   4472       BuildMI(MBB, MI, DL, get(X86::LAHF));
   4473       BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
   4474     }
   4475     if (ToEFLAGS) {
   4476       BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
   4477       BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
   4478           .addReg(X86::AL)
   4479           .addImm(INT8_MAX);
   4480       BuildMI(MBB, MI, DL, get(X86::SAHF));
   4481     }
   4482     if (!AXDead)
   4483       BuildMI(MBB, MI, DL, get(Pop), AX);
   4484     return;
   4485   }
   4486 
   4487   DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
   4488                << " to " << RI.getName(DestReg) << '\n');
   4489   llvm_unreachable("Cannot emit physreg copy instruction");
   4490 }
   4491 
   4492 static unsigned getLoadStoreRegOpcode(unsigned Reg,
   4493                                       const TargetRegisterClass *RC,
   4494                                       bool isStackAligned,
   4495                                       const X86Subtarget &STI,
   4496                                       bool load) {
   4497   if (STI.hasAVX512()) {
   4498     if (X86::VK8RegClass.hasSubClassEq(RC)  ||
   4499       X86::VK16RegClass.hasSubClassEq(RC))
   4500       return load ? X86::KMOVWkm : X86::KMOVWmk;
   4501     if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
   4502       return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
   4503     if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
   4504       return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
   4505     if (X86::VR512RegClass.hasSubClassEq(RC))
   4506       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
   4507   }
   4508 
   4509   bool HasAVX = STI.hasAVX();
   4510   switch (RC->getSize()) {
   4511   default:
   4512     llvm_unreachable("Unknown spill size");
   4513   case 1:
   4514     assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
   4515     if (STI.is64Bit())
   4516       // Copying to or from a physical H register on x86-64 requires a NOREX
   4517       // move.  Otherwise use a normal move.
   4518       if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
   4519         return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
   4520     return load ? X86::MOV8rm : X86::MOV8mr;
   4521   case 2:
   4522     assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
   4523     return load ? X86::MOV16rm : X86::MOV16mr;
   4524   case 4:
   4525     if (X86::GR32RegClass.hasSubClassEq(RC))
   4526       return load ? X86::MOV32rm : X86::MOV32mr;
   4527     if (X86::FR32RegClass.hasSubClassEq(RC))
   4528       return load ?
   4529         (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
   4530         (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
   4531     if (X86::RFP32RegClass.hasSubClassEq(RC))
   4532       return load ? X86::LD_Fp32m : X86::ST_Fp32m;
   4533     llvm_unreachable("Unknown 4-byte regclass");
   4534   case 8:
   4535     if (X86::GR64RegClass.hasSubClassEq(RC))
   4536       return load ? X86::MOV64rm : X86::MOV64mr;
   4537     if (X86::FR64RegClass.hasSubClassEq(RC))
   4538       return load ?
   4539         (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
   4540         (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
   4541     if (X86::VR64RegClass.hasSubClassEq(RC))
   4542       return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
   4543     if (X86::RFP64RegClass.hasSubClassEq(RC))
   4544       return load ? X86::LD_Fp64m : X86::ST_Fp64m;
   4545     llvm_unreachable("Unknown 8-byte regclass");
   4546   case 10:
   4547     assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
   4548     return load ? X86::LD_Fp80m : X86::ST_FpP80m;
   4549   case 16: {
   4550     assert((X86::VR128RegClass.hasSubClassEq(RC) ||
   4551             X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
   4552     // If stack is realigned we can use aligned stores.
   4553     if (isStackAligned)
   4554       return load ?
   4555         (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
   4556         (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
   4557     else
   4558       return load ?
   4559         (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
   4560         (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
   4561   }
   4562   case 32:
   4563     assert((X86::VR256RegClass.hasSubClassEq(RC) ||
   4564             X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
   4565     // If stack is realigned we can use aligned stores.
   4566     if (isStackAligned)
   4567       return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
   4568     else
   4569       return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
   4570   case 64:
   4571     assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
   4572     if (isStackAligned)
   4573       return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
   4574     else
   4575       return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
   4576   }
   4577 }
   4578 
   4579 bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
   4580                                          unsigned &Offset,
   4581                                          const TargetRegisterInfo *TRI) const {
   4582   const MCInstrDesc &Desc = MemOp->getDesc();
   4583   int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
   4584   if (MemRefBegin < 0)
   4585     return false;
   4586 
   4587   MemRefBegin += X86II::getOperandBias(Desc);
   4588 
   4589   BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
   4590   if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
   4591     return false;
   4592 
   4593   if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
   4594       X86::NoRegister)
   4595     return false;
   4596 
   4597   const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
   4598 
   4599   // Displacement can be symbolic
   4600   if (!DispMO.isImm())
   4601     return false;
   4602 
   4603   Offset = DispMO.getImm();
   4604 
   4605   return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
   4606           X86::NoRegister);
   4607 }
   4608 
   4609 static unsigned getStoreRegOpcode(unsigned SrcReg,
   4610                                   const TargetRegisterClass *RC,
   4611                                   bool isStackAligned,
   4612                                   const X86Subtarget &STI) {
   4613   return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
   4614 }
   4615 
   4616 
   4617 static unsigned getLoadRegOpcode(unsigned DestReg,
   4618                                  const TargetRegisterClass *RC,
   4619                                  bool isStackAligned,
   4620                                  const X86Subtarget &STI) {
   4621   return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
   4622 }
   4623 
   4624 void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
   4625                                        MachineBasicBlock::iterator MI,
   4626                                        unsigned SrcReg, bool isKill, int FrameIdx,
   4627                                        const TargetRegisterClass *RC,
   4628                                        const TargetRegisterInfo *TRI) const {
   4629   const MachineFunction &MF = *MBB.getParent();
   4630   assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
   4631          "Stack slot too small for store");
   4632   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
   4633   bool isAligned =
   4634       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
   4635       RI.canRealignStack(MF);
   4636   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
   4637   DebugLoc DL = MBB.findDebugLoc(MI);
   4638   addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
   4639     .addReg(SrcReg, getKillRegState(isKill));
   4640 }
   4641 
   4642 void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
   4643                                   bool isKill,
   4644                                   SmallVectorImpl<MachineOperand> &Addr,
   4645                                   const TargetRegisterClass *RC,
   4646                                   MachineInstr::mmo_iterator MMOBegin,
   4647                                   MachineInstr::mmo_iterator MMOEnd,
   4648                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
   4649   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
   4650   bool isAligned = MMOBegin != MMOEnd &&
   4651                    (*MMOBegin)->getAlignment() >= Alignment;
   4652   unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
   4653   DebugLoc DL;
   4654   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
   4655   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
   4656     MIB.addOperand(Addr[i]);
   4657   MIB.addReg(SrcReg, getKillRegState(isKill));
   4658   (*MIB).setMemRefs(MMOBegin, MMOEnd);
   4659   NewMIs.push_back(MIB);
   4660 }
   4661 
   4662 
   4663 void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
   4664                                         MachineBasicBlock::iterator MI,
   4665                                         unsigned DestReg, int FrameIdx,
   4666                                         const TargetRegisterClass *RC,
   4667                                         const TargetRegisterInfo *TRI) const {
   4668   const MachineFunction &MF = *MBB.getParent();
   4669   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
   4670   bool isAligned =
   4671       (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
   4672       RI.canRealignStack(MF);
   4673   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
   4674   DebugLoc DL = MBB.findDebugLoc(MI);
   4675   addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
   4676 }
   4677 
   4678 void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
   4679                                  SmallVectorImpl<MachineOperand> &Addr,
   4680                                  const TargetRegisterClass *RC,
   4681                                  MachineInstr::mmo_iterator MMOBegin,
   4682                                  MachineInstr::mmo_iterator MMOEnd,
   4683                                  SmallVectorImpl<MachineInstr*> &NewMIs) const {
   4684   unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
   4685   bool isAligned = MMOBegin != MMOEnd &&
   4686                    (*MMOBegin)->getAlignment() >= Alignment;
   4687   unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
   4688   DebugLoc DL;
   4689   MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
   4690   for (unsigned i = 0, e = Addr.size(); i != e; ++i)
   4691     MIB.addOperand(Addr[i]);
   4692   (*MIB).setMemRefs(MMOBegin, MMOEnd);
   4693   NewMIs.push_back(MIB);
   4694 }
   4695 
   4696 bool X86InstrInfo::
   4697 analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
   4698                int &CmpMask, int &CmpValue) const {
   4699   switch (MI->getOpcode()) {
   4700   default: break;
   4701   case X86::CMP64ri32:
   4702   case X86::CMP64ri8:
   4703   case X86::CMP32ri:
   4704   case X86::CMP32ri8:
   4705   case X86::CMP16ri:
   4706   case X86::CMP16ri8:
   4707   case X86::CMP8ri:
   4708     SrcReg = MI->getOperand(0).getReg();
   4709     SrcReg2 = 0;
   4710     CmpMask = ~0;
   4711     CmpValue = MI->getOperand(1).getImm();
   4712     return true;
   4713   // A SUB can be used to perform comparison.
   4714   case X86::SUB64rm:
   4715   case X86::SUB32rm:
   4716   case X86::SUB16rm:
   4717   case X86::SUB8rm:
   4718     SrcReg = MI->getOperand(1).getReg();
   4719     SrcReg2 = 0;
   4720     CmpMask = ~0;
   4721     CmpValue = 0;
   4722     return true;
   4723   case X86::SUB64rr:
   4724   case X86::SUB32rr:
   4725   case X86::SUB16rr:
   4726   case X86::SUB8rr:
   4727     SrcReg = MI->getOperand(1).getReg();
   4728     SrcReg2 = MI->getOperand(2).getReg();
   4729     CmpMask = ~0;
   4730     CmpValue = 0;
   4731     return true;
   4732   case X86::SUB64ri32:
   4733   case X86::SUB64ri8:
   4734   case X86::SUB32ri:
   4735   case X86::SUB32ri8:
   4736   case X86::SUB16ri:
   4737   case X86::SUB16ri8:
   4738   case X86::SUB8ri:
   4739     SrcReg = MI->getOperand(1).getReg();
   4740     SrcReg2 = 0;
   4741     CmpMask = ~0;
   4742     CmpValue = MI->getOperand(2).getImm();
   4743     return true;
   4744   case X86::CMP64rr:
   4745   case X86::CMP32rr:
   4746   case X86::CMP16rr:
   4747   case X86::CMP8rr:
   4748     SrcReg = MI->getOperand(0).getReg();
   4749     SrcReg2 = MI->getOperand(1).getReg();
   4750     CmpMask = ~0;
   4751     CmpValue = 0;
   4752     return true;
   4753   case X86::TEST8rr:
   4754   case X86::TEST16rr:
   4755   case X86::TEST32rr:
   4756   case X86::TEST64rr:
   4757     SrcReg = MI->getOperand(0).getReg();
   4758     if (MI->getOperand(1).getReg() != SrcReg) return false;
   4759     // Compare against zero.
   4760     SrcReg2 = 0;
   4761     CmpMask = ~0;
   4762     CmpValue = 0;
   4763     return true;
   4764   }
   4765   return false;
   4766 }
   4767 
   4768 /// Check whether the first instruction, whose only
   4769 /// purpose is to update flags, can be made redundant.
   4770 /// CMPrr can be made redundant by SUBrr if the operands are the same.
   4771 /// This function can be extended later on.
   4772 /// SrcReg, SrcRegs: register operands for FlagI.
   4773 /// ImmValue: immediate for FlagI if it takes an immediate.
   4774 inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
   4775                                         unsigned SrcReg2, int ImmValue,
   4776                                         MachineInstr *OI) {
   4777   if (((FlagI->getOpcode() == X86::CMP64rr &&
   4778         OI->getOpcode() == X86::SUB64rr) ||
   4779        (FlagI->getOpcode() == X86::CMP32rr &&
   4780         OI->getOpcode() == X86::SUB32rr)||
   4781        (FlagI->getOpcode() == X86::CMP16rr &&
   4782         OI->getOpcode() == X86::SUB16rr)||
   4783        (FlagI->getOpcode() == X86::CMP8rr &&
   4784         OI->getOpcode() == X86::SUB8rr)) &&
   4785       ((OI->getOperand(1).getReg() == SrcReg &&
   4786         OI->getOperand(2).getReg() == SrcReg2) ||
   4787        (OI->getOperand(1).getReg() == SrcReg2 &&
   4788         OI->getOperand(2).getReg() == SrcReg)))
   4789     return true;
   4790 
   4791   if (((FlagI->getOpcode() == X86::CMP64ri32 &&
   4792         OI->getOpcode() == X86::SUB64ri32) ||
   4793        (FlagI->getOpcode() == X86::CMP64ri8 &&
   4794         OI->getOpcode() == X86::SUB64ri8) ||
   4795        (FlagI->getOpcode() == X86::CMP32ri &&
   4796         OI->getOpcode() == X86::SUB32ri) ||
   4797        (FlagI->getOpcode() == X86::CMP32ri8 &&
   4798         OI->getOpcode() == X86::SUB32ri8) ||
   4799        (FlagI->getOpcode() == X86::CMP16ri &&
   4800         OI->getOpcode() == X86::SUB16ri) ||
   4801        (FlagI->getOpcode() == X86::CMP16ri8 &&
   4802         OI->getOpcode() == X86::SUB16ri8) ||
   4803        (FlagI->getOpcode() == X86::CMP8ri &&
   4804         OI->getOpcode() == X86::SUB8ri)) &&
   4805       OI->getOperand(1).getReg() == SrcReg &&
   4806       OI->getOperand(2).getImm() == ImmValue)
   4807     return true;
   4808   return false;
   4809 }
   4810 
   4811 /// Check whether the definition can be converted
   4812 /// to remove a comparison against zero.
   4813 inline static bool isDefConvertible(MachineInstr *MI) {
   4814   switch (MI->getOpcode()) {
   4815   default: return false;
   4816 
   4817   // The shift instructions only modify ZF if their shift count is non-zero.
   4818   // N.B.: The processor truncates the shift count depending on the encoding.
   4819   case X86::SAR8ri:    case X86::SAR16ri:  case X86::SAR32ri:case X86::SAR64ri:
   4820   case X86::SHR8ri:    case X86::SHR16ri:  case X86::SHR32ri:case X86::SHR64ri:
   4821      return getTruncatedShiftCount(MI, 2) != 0;
   4822 
   4823   // Some left shift instructions can be turned into LEA instructions but only
   4824   // if their flags aren't used. Avoid transforming such instructions.
   4825   case X86::SHL8ri:    case X86::SHL16ri:  case X86::SHL32ri:case X86::SHL64ri:{
   4826     unsigned ShAmt = getTruncatedShiftCount(MI, 2);
   4827     if (isTruncatedShiftCountForLEA(ShAmt)) return false;
   4828     return ShAmt != 0;
   4829   }
   4830 
   4831   case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
   4832   case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
   4833      return getTruncatedShiftCount(MI, 3) != 0;
   4834 
   4835   case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
   4836   case X86::SUB32ri8:  case X86::SUB16ri:  case X86::SUB16ri8:
   4837   case X86::SUB8ri:    case X86::SUB64rr:  case X86::SUB32rr:
   4838   case X86::SUB16rr:   case X86::SUB8rr:   case X86::SUB64rm:
   4839   case X86::SUB32rm:   case X86::SUB16rm:  case X86::SUB8rm:
   4840   case X86::DEC64r:    case X86::DEC32r:   case X86::DEC16r: case X86::DEC8r:
   4841   case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
   4842   case X86::ADD32ri8:  case X86::ADD16ri:  case X86::ADD16ri8:
   4843   case X86::ADD8ri:    case X86::ADD64rr:  case X86::ADD32rr:
   4844   case X86::ADD16rr:   case X86::ADD8rr:   case X86::ADD64rm:
   4845   case X86::ADD32rm:   case X86::ADD16rm:  case X86::ADD8rm:
   4846   case X86::INC64r:    case X86::INC32r:   case X86::INC16r: case X86::INC8r:
   4847   case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
   4848   case X86::AND32ri8:  case X86::AND16ri:  case X86::AND16ri8:
   4849   case X86::AND8ri:    case X86::AND64rr:  case X86::AND32rr:
   4850   case X86::AND16rr:   case X86::AND8rr:   case X86::AND64rm:
   4851   case X86::AND32rm:   case X86::AND16rm:  case X86::AND8rm:
   4852   case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
   4853   case X86::XOR32ri8:  case X86::XOR16ri:  case X86::XOR16ri8:
   4854   case X86::XOR8ri:    case X86::XOR64rr:  case X86::XOR32rr:
   4855   case X86::XOR16rr:   case X86::XOR8rr:   case X86::XOR64rm:
   4856   case X86::XOR32rm:   case X86::XOR16rm:  case X86::XOR8rm:
   4857   case X86::OR64ri32:  case X86::OR64ri8:  case X86::OR32ri:
   4858   case X86::OR32ri8:   case X86::OR16ri:   case X86::OR16ri8:
   4859   case X86::OR8ri:     case X86::OR64rr:   case X86::OR32rr:
   4860   case X86::OR16rr:    case X86::OR8rr:    case X86::OR64rm:
   4861   case X86::OR32rm:    case X86::OR16rm:   case X86::OR8rm:
   4862   case X86::NEG8r:     case X86::NEG16r:   case X86::NEG32r: case X86::NEG64r:
   4863   case X86::SAR8r1:    case X86::SAR16r1:  case X86::SAR32r1:case X86::SAR64r1:
   4864   case X86::SHR8r1:    case X86::SHR16r1:  case X86::SHR32r1:case X86::SHR64r1:
   4865   case X86::SHL8r1:    case X86::SHL16r1:  case X86::SHL32r1:case X86::SHL64r1:
   4866   case X86::ADC32ri:   case X86::ADC32ri8:
   4867   case X86::ADC32rr:   case X86::ADC64ri32:
   4868   case X86::ADC64ri8:  case X86::ADC64rr:
   4869   case X86::SBB32ri:   case X86::SBB32ri8:
   4870   case X86::SBB32rr:   case X86::SBB64ri32:
   4871   case X86::SBB64ri8:  case X86::SBB64rr:
   4872   case X86::ANDN32rr:  case X86::ANDN32rm:
   4873   case X86::ANDN64rr:  case X86::ANDN64rm:
   4874   case X86::BEXTR32rr: case X86::BEXTR64rr:
   4875   case X86::BEXTR32rm: case X86::BEXTR64rm:
   4876   case X86::BLSI32rr:  case X86::BLSI32rm:
   4877   case X86::BLSI64rr:  case X86::BLSI64rm:
   4878   case X86::BLSMSK32rr:case X86::BLSMSK32rm:
   4879   case X86::BLSMSK64rr:case X86::BLSMSK64rm:
   4880   case X86::BLSR32rr:  case X86::BLSR32rm:
   4881   case X86::BLSR64rr:  case X86::BLSR64rm:
   4882   case X86::BZHI32rr:  case X86::BZHI32rm:
   4883   case X86::BZHI64rr:  case X86::BZHI64rm:
   4884   case X86::LZCNT16rr: case X86::LZCNT16rm:
   4885   case X86::LZCNT32rr: case X86::LZCNT32rm:
   4886   case X86::LZCNT64rr: case X86::LZCNT64rm:
   4887   case X86::POPCNT16rr:case X86::POPCNT16rm:
   4888   case X86::POPCNT32rr:case X86::POPCNT32rm:
   4889   case X86::POPCNT64rr:case X86::POPCNT64rm:
   4890   case X86::TZCNT16rr: case X86::TZCNT16rm:
   4891   case X86::TZCNT32rr: case X86::TZCNT32rm:
   4892   case X86::TZCNT64rr: case X86::TZCNT64rm:
   4893     return true;
   4894   }
   4895 }
   4896 
   4897 /// Check whether the use can be converted to remove a comparison against zero.
   4898 static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
   4899   switch (MI->getOpcode()) {
   4900   default: return X86::COND_INVALID;
   4901   case X86::LZCNT16rr: case X86::LZCNT16rm:
   4902   case X86::LZCNT32rr: case X86::LZCNT32rm:
   4903   case X86::LZCNT64rr: case X86::LZCNT64rm:
   4904     return X86::COND_B;
   4905   case X86::POPCNT16rr:case X86::POPCNT16rm:
   4906   case X86::POPCNT32rr:case X86::POPCNT32rm:
   4907   case X86::POPCNT64rr:case X86::POPCNT64rm:
   4908     return X86::COND_E;
   4909   case X86::TZCNT16rr: case X86::TZCNT16rm:
   4910   case X86::TZCNT32rr: case X86::TZCNT32rm:
   4911   case X86::TZCNT64rr: case X86::TZCNT64rm:
   4912     return X86::COND_B;
   4913   }
   4914 }
   4915 
   4916 /// Check if there exists an earlier instruction that
   4917 /// operates on the same source operands and sets flags in the same way as
   4918 /// Compare; remove Compare if possible.
   4919 bool X86InstrInfo::
   4920 optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
   4921                      int CmpMask, int CmpValue,
   4922                      const MachineRegisterInfo *MRI) const {
   4923   // Check whether we can replace SUB with CMP.
   4924   unsigned NewOpcode = 0;
   4925   switch (CmpInstr->getOpcode()) {
   4926   default: break;
   4927   case X86::SUB64ri32:
   4928   case X86::SUB64ri8:
   4929   case X86::SUB32ri:
   4930   case X86::SUB32ri8:
   4931   case X86::SUB16ri:
   4932   case X86::SUB16ri8:
   4933   case X86::SUB8ri:
   4934   case X86::SUB64rm:
   4935   case X86::SUB32rm:
   4936   case X86::SUB16rm:
   4937   case X86::SUB8rm:
   4938   case X86::SUB64rr:
   4939   case X86::SUB32rr:
   4940   case X86::SUB16rr:
   4941   case X86::SUB8rr: {
   4942     if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
   4943       return false;
   4944     // There is no use of the destination register, we can replace SUB with CMP.
   4945     switch (CmpInstr->getOpcode()) {
   4946     default: llvm_unreachable("Unreachable!");
   4947     case X86::SUB64rm:   NewOpcode = X86::CMP64rm;   break;
   4948     case X86::SUB32rm:   NewOpcode = X86::CMP32rm;   break;
   4949     case X86::SUB16rm:   NewOpcode = X86::CMP16rm;   break;
   4950     case X86::SUB8rm:    NewOpcode = X86::CMP8rm;    break;
   4951     case X86::SUB64rr:   NewOpcode = X86::CMP64rr;   break;
   4952     case X86::SUB32rr:   NewOpcode = X86::CMP32rr;   break;
   4953     case X86::SUB16rr:   NewOpcode = X86::CMP16rr;   break;
   4954     case X86::SUB8rr:    NewOpcode = X86::CMP8rr;    break;
   4955     case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
   4956     case X86::SUB64ri8:  NewOpcode = X86::CMP64ri8;  break;
   4957     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
   4958     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
   4959     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
   4960     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
   4961     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
   4962     }
   4963     CmpInstr->setDesc(get(NewOpcode));
   4964     CmpInstr->RemoveOperand(0);
   4965     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
   4966     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
   4967         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
   4968       return false;
   4969   }
   4970   }
   4971 
   4972   // Get the unique definition of SrcReg.
   4973   MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
   4974   if (!MI) return false;
   4975 
   4976   // CmpInstr is the first instruction of the BB.
   4977   MachineBasicBlock::iterator I = CmpInstr, Def = MI;
   4978 
   4979   // If we are comparing against zero, check whether we can use MI to update
   4980   // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
   4981   bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
   4982   if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
   4983     return false;
   4984 
   4985   // If we have a use of the source register between the def and our compare
   4986   // instruction we can eliminate the compare iff the use sets EFLAGS in the
   4987   // right way.
   4988   bool ShouldUpdateCC = false;
   4989   X86::CondCode NewCC = X86::COND_INVALID;
   4990   if (IsCmpZero && !isDefConvertible(MI)) {
   4991     // Scan forward from the use until we hit the use we're looking for or the
   4992     // compare instruction.
   4993     for (MachineBasicBlock::iterator J = MI;; ++J) {
   4994       // Do we have a convertible instruction?
   4995       NewCC = isUseDefConvertible(J);
   4996       if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
   4997           J->getOperand(1).getReg() == SrcReg) {
   4998         assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
   4999         ShouldUpdateCC = true; // Update CC later on.
   5000         // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
   5001         // with the new def.
   5002         MI = Def = J;
   5003         break;
   5004       }
   5005 
   5006       if (J == I)
   5007         return false;
   5008     }
   5009   }
   5010 
   5011   // We are searching for an earlier instruction that can make CmpInstr
   5012   // redundant and that instruction will be saved in Sub.
   5013   MachineInstr *Sub = nullptr;
   5014   const TargetRegisterInfo *TRI = &getRegisterInfo();
   5015 
   5016   // We iterate backward, starting from the instruction before CmpInstr and
   5017   // stop when reaching the definition of a source register or done with the BB.
   5018   // RI points to the instruction before CmpInstr.
   5019   // If the definition is in this basic block, RE points to the definition;
   5020   // otherwise, RE is the rend of the basic block.
   5021   MachineBasicBlock::reverse_iterator
   5022       RI = MachineBasicBlock::reverse_iterator(I),
   5023       RE = CmpInstr->getParent() == MI->getParent() ?
   5024            MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
   5025            CmpInstr->getParent()->rend();
   5026   MachineInstr *Movr0Inst = nullptr;
   5027   for (; RI != RE; ++RI) {
   5028     MachineInstr *Instr = &*RI;
   5029     // Check whether CmpInstr can be made redundant by the current instruction.
   5030     if (!IsCmpZero &&
   5031         isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
   5032       Sub = Instr;
   5033       break;
   5034     }
   5035 
   5036     if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
   5037         Instr->readsRegister(X86::EFLAGS, TRI)) {
   5038       // This instruction modifies or uses EFLAGS.
   5039 
   5040       // MOV32r0 etc. are implemented with xor which clobbers condition code.
   5041       // They are safe to move up, if the definition to EFLAGS is dead and
   5042       // earlier instructions do not read or write EFLAGS.
   5043       if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
   5044           Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
   5045         Movr0Inst = Instr;
   5046         continue;
   5047       }
   5048 
   5049       // We can't remove CmpInstr.
   5050       return false;
   5051     }
   5052   }
   5053 
   5054   // Return false if no candidates exist.
   5055   if (!IsCmpZero && !Sub)
   5056     return false;
   5057 
   5058   bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
   5059                     Sub->getOperand(2).getReg() == SrcReg);
   5060 
   5061   // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
   5062   // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
   5063   // If we are done with the basic block, we need to check whether EFLAGS is
   5064   // live-out.
   5065   bool IsSafe = false;
   5066   SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
   5067   MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
   5068   for (++I; I != E; ++I) {
   5069     const MachineInstr &Instr = *I;
   5070     bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
   5071     bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
   5072     // We should check the usage if this instruction uses and updates EFLAGS.
   5073     if (!UseEFLAGS && ModifyEFLAGS) {
   5074       // It is safe to remove CmpInstr if EFLAGS is updated again.
   5075       IsSafe = true;
   5076       break;
   5077     }
   5078     if (!UseEFLAGS && !ModifyEFLAGS)
   5079       continue;
   5080 
   5081     // EFLAGS is used by this instruction.
   5082     X86::CondCode OldCC = X86::COND_INVALID;
   5083     bool OpcIsSET = false;
   5084     if (IsCmpZero || IsSwapped) {
   5085       // We decode the condition code from opcode.
   5086       if (Instr.isBranch())
   5087         OldCC = getCondFromBranchOpc(Instr.getOpcode());
   5088       else {
   5089         OldCC = getCondFromSETOpc(Instr.getOpcode());
   5090         if (OldCC != X86::COND_INVALID)
   5091           OpcIsSET = true;
   5092         else
   5093           OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
   5094       }
   5095       if (OldCC == X86::COND_INVALID) return false;
   5096     }
   5097     if (IsCmpZero) {
   5098       switch (OldCC) {
   5099       default: break;
   5100       case X86::COND_A: case X86::COND_AE:
   5101       case X86::COND_B: case X86::COND_BE:
   5102       case X86::COND_G: case X86::COND_GE:
   5103       case X86::COND_L: case X86::COND_LE:
   5104       case X86::COND_O: case X86::COND_NO:
   5105         // CF and OF are used, we can't perform this optimization.
   5106         return false;
   5107       }
   5108 
   5109       // If we're updating the condition code check if we have to reverse the
   5110       // condition.
   5111       if (ShouldUpdateCC)
   5112         switch (OldCC) {
   5113         default:
   5114           return false;
   5115         case X86::COND_E:
   5116           break;
   5117         case X86::COND_NE:
   5118           NewCC = GetOppositeBranchCondition(NewCC);
   5119           break;
   5120         }
   5121     } else if (IsSwapped) {
   5122       // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
   5123       // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
   5124       // We swap the condition code and synthesize the new opcode.
   5125       NewCC = getSwappedCondition(OldCC);
   5126       if (NewCC == X86::COND_INVALID) return false;
   5127     }
   5128 
   5129     if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
   5130       // Synthesize the new opcode.
   5131       bool HasMemoryOperand = Instr.hasOneMemOperand();
   5132       unsigned NewOpc;
   5133       if (Instr.isBranch())
   5134         NewOpc = GetCondBranchFromCond(NewCC);
   5135       else if(OpcIsSET)
   5136         NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
   5137       else {
   5138         unsigned DstReg = Instr.getOperand(0).getReg();
   5139         NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
   5140                                  HasMemoryOperand);
   5141       }
   5142 
   5143       // Push the MachineInstr to OpsToUpdate.
   5144       // If it is safe to remove CmpInstr, the condition code of these
   5145       // instructions will be modified.
   5146       OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
   5147     }
   5148     if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
   5149       // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
   5150       IsSafe = true;
   5151       break;
   5152     }
   5153   }
   5154 
   5155   // If EFLAGS is not killed nor re-defined, we should check whether it is
   5156   // live-out. If it is live-out, do not optimize.
   5157   if ((IsCmpZero || IsSwapped) && !IsSafe) {
   5158     MachineBasicBlock *MBB = CmpInstr->getParent();
   5159     for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
   5160              SE = MBB->succ_end(); SI != SE; ++SI)
   5161       if ((*SI)->isLiveIn(X86::EFLAGS))
   5162         return false;
   5163   }
   5164 
   5165   // The instruction to be updated is either Sub or MI.
   5166   Sub = IsCmpZero ? MI : Sub;
   5167   // Move Movr0Inst to the appropriate place before Sub.
   5168   if (Movr0Inst) {
   5169     // Look backwards until we find a def that doesn't use the current EFLAGS.
   5170     Def = Sub;
   5171     MachineBasicBlock::reverse_iterator
   5172       InsertI = MachineBasicBlock::reverse_iterator(++Def),
   5173                 InsertE = Sub->getParent()->rend();
   5174     for (; InsertI != InsertE; ++InsertI) {
   5175       MachineInstr *Instr = &*InsertI;
   5176       if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
   5177           Instr->modifiesRegister(X86::EFLAGS, TRI)) {
   5178         Sub->getParent()->remove(Movr0Inst);
   5179         Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
   5180                                    Movr0Inst);
   5181         break;
   5182       }
   5183     }
   5184     if (InsertI == InsertE)
   5185       return false;
   5186   }
   5187 
   5188   // Make sure Sub instruction defines EFLAGS and mark the def live.
   5189   unsigned i = 0, e = Sub->getNumOperands();
   5190   for (; i != e; ++i) {
   5191     MachineOperand &MO = Sub->getOperand(i);
   5192     if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
   5193       MO.setIsDead(false);
   5194       break;
   5195     }
   5196   }
   5197   assert(i != e && "Unable to locate a def EFLAGS operand");
   5198 
   5199   CmpInstr->eraseFromParent();
   5200 
   5201   // Modify the condition code of instructions in OpsToUpdate.
   5202   for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
   5203     OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
   5204   return true;
   5205 }
   5206 
   5207 /// Try to remove the load by folding it to a register
   5208 /// operand at the use. We fold the load instructions if load defines a virtual
   5209 /// register, the virtual register is used once in the same BB, and the
   5210 /// instructions in-between do not load or store, and have no side effects.
   5211 MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
   5212                                               const MachineRegisterInfo *MRI,
   5213                                               unsigned &FoldAsLoadDefReg,
   5214                                               MachineInstr *&DefMI) const {
   5215   if (FoldAsLoadDefReg == 0)
   5216     return nullptr;
   5217   // To be conservative, if there exists another load, clear the load candidate.
   5218   if (MI->mayLoad()) {
   5219     FoldAsLoadDefReg = 0;
   5220     return nullptr;
   5221   }
   5222 
   5223   // Check whether we can move DefMI here.
   5224   DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
   5225   assert(DefMI);
   5226   bool SawStore = false;
   5227   if (!DefMI->isSafeToMove(nullptr, SawStore))
   5228     return nullptr;
   5229 
   5230   // Collect information about virtual register operands of MI.
   5231   unsigned SrcOperandId = 0;
   5232   bool FoundSrcOperand = false;
   5233   for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
   5234     MachineOperand &MO = MI->getOperand(i);
   5235     if (!MO.isReg())
   5236       continue;
   5237     unsigned Reg = MO.getReg();
   5238     if (Reg != FoldAsLoadDefReg)
   5239       continue;
   5240     // Do not fold if we have a subreg use or a def or multiple uses.
   5241     if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
   5242       return nullptr;
   5243 
   5244     SrcOperandId = i;
   5245     FoundSrcOperand = true;
   5246   }
   5247   if (!FoundSrcOperand)
   5248     return nullptr;
   5249 
   5250   // Check whether we can fold the def into SrcOperandId.
   5251   MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
   5252   if (FoldMI) {
   5253     FoldAsLoadDefReg = 0;
   5254     return FoldMI;
   5255   }
   5256 
   5257   return nullptr;
   5258 }
   5259 
   5260 /// Expand a single-def pseudo instruction to a two-addr
   5261 /// instruction with two undef reads of the register being defined.
   5262 /// This is used for mapping:
   5263 ///   %xmm4 = V_SET0
   5264 /// to:
   5265 ///   %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
   5266 ///
   5267 static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
   5268                              const MCInstrDesc &Desc) {
   5269   assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
   5270   unsigned Reg = MIB->getOperand(0).getReg();
   5271   MIB->setDesc(Desc);
   5272 
   5273   // MachineInstr::addOperand() will insert explicit operands before any
   5274   // implicit operands.
   5275   MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
   5276   // But we don't trust that.
   5277   assert(MIB->getOperand(1).getReg() == Reg &&
   5278          MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
   5279   return true;
   5280 }
   5281 
   5282 static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
   5283                           bool MinusOne) {
   5284   MachineBasicBlock &MBB = *MIB->getParent();
   5285   DebugLoc DL = MIB->getDebugLoc();
   5286   unsigned Reg = MIB->getOperand(0).getReg();
   5287 
   5288   // Insert the XOR.
   5289   BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
   5290       .addReg(Reg, RegState::Undef)
   5291       .addReg(Reg, RegState::Undef);
   5292 
   5293   // Turn the pseudo into an INC or DEC.
   5294   MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
   5295   MIB.addReg(Reg);
   5296 
   5297   return true;
   5298 }
   5299 
   5300 bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
   5301   MachineBasicBlock &MBB = *MIB->getParent();
   5302   DebugLoc DL = MIB->getDebugLoc();
   5303   int64_t Imm = MIB->getOperand(1).getImm();
   5304   assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
   5305   MachineBasicBlock::iterator I = MIB.getInstr();
   5306 
   5307   int StackAdjustment;
   5308 
   5309   if (Subtarget.is64Bit()) {
   5310     assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
   5311            MIB->getOpcode() == X86::MOV32ImmSExti8);
   5312     // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
   5313     // widen the register if necessary.
   5314     StackAdjustment = 8;
   5315     BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
   5316     MIB->setDesc(get(X86::POP64r));
   5317     MIB->getOperand(0)
   5318         .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), MVT::i64));
   5319   } else {
   5320     assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
   5321     StackAdjustment = 4;
   5322     BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
   5323     MIB->setDesc(get(X86::POP32r));
   5324   }
   5325 
   5326   // Build CFI if necessary.
   5327   MachineFunction &MF = *MBB.getParent();
   5328   const X86FrameLowering *TFL = Subtarget.getFrameLowering();
   5329   bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
   5330   bool NeedsDwarfCFI =
   5331       !IsWin64Prologue &&
   5332       (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
   5333   bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
   5334   if (EmitCFI) {
   5335     TFL->BuildCFI(MBB, I, DL,
   5336         MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
   5337     TFL->BuildCFI(MBB, std::next(I), DL,
   5338         MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
   5339   }
   5340 
   5341   return true;
   5342 }
   5343 
   5344 // LoadStackGuard has so far only been implemented for 64-bit MachO. Different
   5345 // code sequence is needed for other targets.
   5346 static void expandLoadStackGuard(MachineInstrBuilder &MIB,
   5347                                  const TargetInstrInfo &TII) {
   5348   MachineBasicBlock &MBB = *MIB->getParent();
   5349   DebugLoc DL = MIB->getDebugLoc();
   5350   unsigned Reg = MIB->getOperand(0).getReg();
   5351   const GlobalValue *GV =
   5352       cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
   5353   unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
   5354   MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
   5355       MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
   5356   MachineBasicBlock::iterator I = MIB.getInstr();
   5357 
   5358   BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
   5359       .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
   5360       .addMemOperand(MMO);
   5361   MIB->setDebugLoc(DL);
   5362   MIB->setDesc(TII.get(X86::MOV64rm));
   5363   MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
   5364 }
   5365 
   5366 bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
   5367   bool HasAVX = Subtarget.hasAVX();
   5368   MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
   5369   switch (MI->getOpcode()) {
   5370   case X86::MOV32r0:
   5371     return Expand2AddrUndef(MIB, get(X86::XOR32rr));
   5372   case X86::MOV32r1:
   5373     return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
   5374   case X86::MOV32r_1:
   5375     return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
   5376   case X86::MOV32ImmSExti8:
   5377   case X86::MOV64ImmSExti8:
   5378     return ExpandMOVImmSExti8(MIB);
   5379   case X86::SETB_C8r:
   5380     return Expand2AddrUndef(MIB, get(X86::SBB8rr));
   5381   case X86::SETB_C16r:
   5382     return Expand2AddrUndef(MIB, get(X86::SBB16rr));
   5383   case X86::SETB_C32r:
   5384     return Expand2AddrUndef(MIB, get(X86::SBB32rr));
   5385   case X86::SETB_C64r:
   5386     return Expand2AddrUndef(MIB, get(X86::SBB64rr));
   5387   case X86::V_SET0:
   5388   case X86::FsFLD0SS:
   5389   case X86::FsFLD0SD:
   5390     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
   5391   case X86::AVX_SET0:
   5392     assert(HasAVX && "AVX not supported");
   5393     return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
   5394   case X86::AVX512_512_SET0:
   5395     return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
   5396   case X86::V_SETALLONES:
   5397     return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
   5398   case X86::AVX2_SETALLONES:
   5399     return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
   5400   case X86::TEST8ri_NOREX:
   5401     MI->setDesc(get(X86::TEST8ri));
   5402     return true;
   5403   case X86::KSET0B:
   5404   case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
   5405   case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr));
   5406   case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr));
   5407   case X86::KSET1B:
   5408   case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
   5409   case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr));
   5410   case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr));
   5411   case TargetOpcode::LOAD_STACK_GUARD:
   5412     expandLoadStackGuard(MIB, *this);
   5413     return true;
   5414   }
   5415   return false;
   5416 }
   5417 
   5418 static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
   5419                         int PtrOffset = 0) {
   5420   unsigned NumAddrOps = MOs.size();
   5421 
   5422   if (NumAddrOps < 4) {
   5423     // FrameIndex only - add an immediate offset (whether its zero or not).
   5424     for (unsigned i = 0; i != NumAddrOps; ++i)
   5425       MIB.addOperand(MOs[i]);
   5426     addOffset(MIB, PtrOffset);
   5427   } else {
   5428     // General Memory Addressing - we need to add any offset to an existing
   5429     // offset.
   5430     assert(MOs.size() == 5 && "Unexpected memory operand list length");
   5431     for (unsigned i = 0; i != NumAddrOps; ++i) {
   5432       const MachineOperand &MO = MOs[i];
   5433       if (i == 3 && PtrOffset != 0) {
   5434         MIB.addDisp(MO, PtrOffset);
   5435       } else {
   5436         MIB.addOperand(MO);
   5437       }
   5438     }
   5439   }
   5440 }
   5441 
   5442 static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
   5443                                      ArrayRef<MachineOperand> MOs,
   5444                                      MachineBasicBlock::iterator InsertPt,
   5445                                      MachineInstr *MI,
   5446                                      const TargetInstrInfo &TII) {
   5447   // Create the base instruction with the memory operand as the first part.
   5448   // Omit the implicit operands, something BuildMI can't do.
   5449   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
   5450                                               MI->getDebugLoc(), true);
   5451   MachineInstrBuilder MIB(MF, NewMI);
   5452   addOperands(MIB, MOs);
   5453 
   5454   // Loop over the rest of the ri operands, converting them over.
   5455   unsigned NumOps = MI->getDesc().getNumOperands()-2;
   5456   for (unsigned i = 0; i != NumOps; ++i) {
   5457     MachineOperand &MO = MI->getOperand(i+2);
   5458     MIB.addOperand(MO);
   5459   }
   5460   for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
   5461     MachineOperand &MO = MI->getOperand(i);
   5462     MIB.addOperand(MO);
   5463   }
   5464 
   5465   MachineBasicBlock *MBB = InsertPt->getParent();
   5466   MBB->insert(InsertPt, NewMI);
   5467 
   5468   return MIB;
   5469 }
   5470 
   5471 static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
   5472                               unsigned OpNo, ArrayRef<MachineOperand> MOs,
   5473                               MachineBasicBlock::iterator InsertPt,
   5474                               MachineInstr *MI, const TargetInstrInfo &TII,
   5475                               int PtrOffset = 0) {
   5476   // Omit the implicit operands, something BuildMI can't do.
   5477   MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
   5478                                               MI->getDebugLoc(), true);
   5479   MachineInstrBuilder MIB(MF, NewMI);
   5480 
   5481   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
   5482     MachineOperand &MO = MI->getOperand(i);
   5483     if (i == OpNo) {
   5484       assert(MO.isReg() && "Expected to fold into reg operand!");
   5485       addOperands(MIB, MOs, PtrOffset);
   5486     } else {
   5487       MIB.addOperand(MO);
   5488     }
   5489   }
   5490 
   5491   MachineBasicBlock *MBB = InsertPt->getParent();
   5492   MBB->insert(InsertPt, NewMI);
   5493 
   5494   return MIB;
   5495 }
   5496 
   5497 static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
   5498                                 ArrayRef<MachineOperand> MOs,
   5499                                 MachineBasicBlock::iterator InsertPt,
   5500                                 MachineInstr *MI) {
   5501   MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
   5502                                     MI->getDebugLoc(), TII.get(Opcode));
   5503   addOperands(MIB, MOs);
   5504   return MIB.addImm(0);
   5505 }
   5506 
   5507 MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
   5508     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
   5509     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
   5510     unsigned Size, unsigned Align) const {
   5511   switch (MI->getOpcode()) {
   5512   case X86::INSERTPSrr:
   5513   case X86::VINSERTPSrr:
   5514     // Attempt to convert the load of inserted vector into a fold load
   5515     // of a single float.
   5516     if (OpNum == 2) {
   5517       unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
   5518       unsigned ZMask = Imm & 15;
   5519       unsigned DstIdx = (Imm >> 4) & 3;
   5520       unsigned SrcIdx = (Imm >> 6) & 3;
   5521 
   5522       unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
   5523       if (Size <= RCSize && 4 <= Align) {
   5524         int PtrOffset = SrcIdx * 4;
   5525         unsigned NewImm = (DstIdx << 4) | ZMask;
   5526         unsigned NewOpCode =
   5527             (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
   5528                                                  : X86::INSERTPSrm);
   5529         MachineInstr *NewMI =
   5530             FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
   5531         NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
   5532         return NewMI;
   5533       }
   5534     }
   5535     break;
   5536   };
   5537 
   5538   return nullptr;
   5539 }
   5540 
   5541 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
   5542     MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
   5543     ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
   5544     unsigned Size, unsigned Align, bool AllowCommute) const {
   5545   const DenseMap<unsigned,
   5546                  std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
   5547   bool isCallRegIndirect = Subtarget.callRegIndirect();
   5548   bool isTwoAddrFold = false;
   5549 
   5550   // For CPUs that favor the register form of a call or push,
   5551   // do not fold loads into calls or pushes, unless optimizing for size
   5552   // aggressively.
   5553   if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
   5554       (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
   5555        MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
   5556        MI->getOpcode() == X86::PUSH64r))
   5557     return nullptr;
   5558 
   5559   unsigned NumOps = MI->getDesc().getNumOperands();
   5560   bool isTwoAddr = NumOps > 1 &&
   5561     MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
   5562 
   5563   // FIXME: AsmPrinter doesn't know how to handle
   5564   // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
   5565   if (MI->getOpcode() == X86::ADD32ri &&
   5566       MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
   5567     return nullptr;
   5568 
   5569   MachineInstr *NewMI = nullptr;
   5570 
   5571   // Attempt to fold any custom cases we have.
   5572   if (MachineInstr *CustomMI =
   5573           foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
   5574     return CustomMI;
   5575 
   5576   // Folding a memory location into the two-address part of a two-address
   5577   // instruction is different than folding it other places.  It requires
   5578   // replacing the *two* registers with the memory location.
   5579   if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
   5580       MI->getOperand(0).isReg() &&
   5581       MI->getOperand(1).isReg() &&
   5582       MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
   5583     OpcodeTablePtr = &RegOp2MemOpTable2Addr;
   5584     isTwoAddrFold = true;
   5585   } else if (OpNum == 0) {
   5586     if (MI->getOpcode() == X86::MOV32r0) {
   5587       NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
   5588       if (NewMI)
   5589         return NewMI;
   5590     }
   5591 
   5592     OpcodeTablePtr = &RegOp2MemOpTable0;
   5593   } else if (OpNum == 1) {
   5594     OpcodeTablePtr = &RegOp2MemOpTable1;
   5595   } else if (OpNum == 2) {
   5596     OpcodeTablePtr = &RegOp2MemOpTable2;
   5597   } else if (OpNum == 3) {
   5598     OpcodeTablePtr = &RegOp2MemOpTable3;
   5599   } else if (OpNum == 4) {
   5600     OpcodeTablePtr = &RegOp2MemOpTable4;
   5601   }
   5602 
   5603   // If table selected...
   5604   if (OpcodeTablePtr) {
   5605     // Find the Opcode to fuse
   5606     DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
   5607       OpcodeTablePtr->find(MI->getOpcode());
   5608     if (I != OpcodeTablePtr->end()) {
   5609       unsigned Opcode = I->second.first;
   5610       unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
   5611       if (Align < MinAlign)
   5612         return nullptr;
   5613       bool NarrowToMOV32rm = false;
   5614       if (Size) {
   5615         unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
   5616         if (Size < RCSize) {
   5617           // Check if it's safe to fold the load. If the size of the object is
   5618           // narrower than the load width, then it's not.
   5619           if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
   5620             return nullptr;
   5621           // If this is a 64-bit load, but the spill slot is 32, then we can do
   5622           // a 32-bit load which is implicitly zero-extended. This likely is
   5623           // due to live interval analysis remat'ing a load from stack slot.
   5624           if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
   5625             return nullptr;
   5626           Opcode = X86::MOV32rm;
   5627           NarrowToMOV32rm = true;
   5628         }
   5629       }
   5630 
   5631       if (isTwoAddrFold)
   5632         NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
   5633       else
   5634         NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
   5635 
   5636       if (NarrowToMOV32rm) {
   5637         // If this is the special case where we use a MOV32rm to load a 32-bit
   5638         // value and zero-extend the top bits. Change the destination register
   5639         // to a 32-bit one.
   5640         unsigned DstReg = NewMI->getOperand(0).getReg();
   5641         if (TargetRegisterInfo::isPhysicalRegister(DstReg))
   5642           NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
   5643         else
   5644           NewMI->getOperand(0).setSubReg(X86::sub_32bit);
   5645       }
   5646       return NewMI;
   5647     }
   5648   }
   5649 
   5650   // If the instruction and target operand are commutable, commute the
   5651   // instruction and try again.
   5652   if (AllowCommute) {
   5653     unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
   5654     if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
   5655       bool HasDef = MI->getDesc().getNumDefs();
   5656       unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
   5657       unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
   5658       unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
   5659       bool Tied1 =
   5660           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
   5661       bool Tied2 =
   5662           0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
   5663 
   5664       // If either of the commutable operands are tied to the destination
   5665       // then we can not commute + fold.
   5666       if ((HasDef && Reg0 == Reg1 && Tied1) ||
   5667           (HasDef && Reg0 == Reg2 && Tied2))
   5668         return nullptr;
   5669 
   5670       MachineInstr *CommutedMI =
   5671           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
   5672       if (!CommutedMI) {
   5673         // Unable to commute.
   5674         return nullptr;
   5675       }
   5676       if (CommutedMI != MI) {
   5677         // New instruction. We can't fold from this.
   5678         CommutedMI->eraseFromParent();
   5679         return nullptr;
   5680       }
   5681 
   5682       // Attempt to fold with the commuted version of the instruction.
   5683       NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
   5684                                     Size, Align, /*AllowCommute=*/false);
   5685       if (NewMI)
   5686         return NewMI;
   5687 
   5688       // Folding failed again - undo the commute before returning.
   5689       MachineInstr *UncommutedMI =
   5690           commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
   5691       if (!UncommutedMI) {
   5692         // Unable to commute.
   5693         return nullptr;
   5694       }
   5695       if (UncommutedMI != MI) {
   5696         // New instruction. It doesn't need to be kept.
   5697         UncommutedMI->eraseFromParent();
   5698         return nullptr;
   5699       }
   5700 
   5701       // Return here to prevent duplicate fuse failure report.
   5702       return nullptr;
   5703     }
   5704   }
   5705 
   5706   // No fusion
   5707   if (PrintFailedFusing && !MI->isCopy())
   5708     dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
   5709   return nullptr;
   5710 }
   5711 
   5712 /// Return true for all instructions that only update
   5713 /// the first 32 or 64-bits of the destination register and leave the rest
   5714 /// unmodified. This can be used to avoid folding loads if the instructions
   5715 /// only update part of the destination register, and the non-updated part is
   5716 /// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
   5717 /// instructions breaks the partial register dependency and it can improve
   5718 /// performance. e.g.:
   5719 ///
   5720 ///   movss (%rdi), %xmm0
   5721 ///   cvtss2sd %xmm0, %xmm0
   5722 ///
   5723 /// Instead of
   5724 ///   cvtss2sd (%rdi), %xmm0
   5725 ///
   5726 /// FIXME: This should be turned into a TSFlags.
   5727 ///
   5728 static bool hasPartialRegUpdate(unsigned Opcode) {
   5729   switch (Opcode) {
   5730   case X86::CVTSI2SSrr:
   5731   case X86::CVTSI2SSrm:
   5732   case X86::CVTSI2SS64rr:
   5733   case X86::CVTSI2SS64rm:
   5734   case X86::CVTSI2SDrr:
   5735   case X86::CVTSI2SDrm:
   5736   case X86::CVTSI2SD64rr:
   5737   case X86::CVTSI2SD64rm:
   5738   case X86::CVTSD2SSrr:
   5739   case X86::CVTSD2SSrm:
   5740   case X86::Int_CVTSD2SSrr:
   5741   case X86::Int_CVTSD2SSrm:
   5742   case X86::CVTSS2SDrr:
   5743   case X86::CVTSS2SDrm:
   5744   case X86::Int_CVTSS2SDrr:
   5745   case X86::Int_CVTSS2SDrm:
   5746   case X86::RCPSSr:
   5747   case X86::RCPSSm:
   5748   case X86::RCPSSr_Int:
   5749   case X86::RCPSSm_Int:
   5750   case X86::ROUNDSDr:
   5751   case X86::ROUNDSDm:
   5752   case X86::ROUNDSDr_Int:
   5753   case X86::ROUNDSSr:
   5754   case X86::ROUNDSSm:
   5755   case X86::ROUNDSSr_Int:
   5756   case X86::RSQRTSSr:
   5757   case X86::RSQRTSSm:
   5758   case X86::RSQRTSSr_Int:
   5759   case X86::RSQRTSSm_Int:
   5760   case X86::SQRTSSr:
   5761   case X86::SQRTSSm:
   5762   case X86::SQRTSSr_Int:
   5763   case X86::SQRTSSm_Int:
   5764   case X86::SQRTSDr:
   5765   case X86::SQRTSDm:
   5766   case X86::SQRTSDr_Int:
   5767   case X86::SQRTSDm_Int:
   5768     return true;
   5769   }
   5770 
   5771   return false;
   5772 }
   5773 
   5774 /// Inform the ExeDepsFix pass how many idle
   5775 /// instructions we would like before a partial register update.
   5776 unsigned X86InstrInfo::
   5777 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
   5778                              const TargetRegisterInfo *TRI) const {
   5779   if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
   5780     return 0;
   5781 
   5782   // If MI is marked as reading Reg, the partial register update is wanted.
   5783   const MachineOperand &MO = MI->getOperand(0);
   5784   unsigned Reg = MO.getReg();
   5785   if (TargetRegisterInfo::isVirtualRegister(Reg)) {
   5786     if (MO.readsReg() || MI->readsVirtualRegister(Reg))
   5787       return 0;
   5788   } else {
   5789     if (MI->readsRegister(Reg, TRI))
   5790       return 0;
   5791   }
   5792 
   5793   // If any of the preceding 16 instructions are reading Reg, insert a
   5794   // dependency breaking instruction.  The magic number is based on a few
   5795   // Nehalem experiments.
   5796   return 16;
   5797 }
   5798 
   5799 // Return true for any instruction the copies the high bits of the first source
   5800 // operand into the unused high bits of the destination operand.
   5801 static bool hasUndefRegUpdate(unsigned Opcode) {
   5802   switch (Opcode) {
   5803   case X86::VCVTSI2SSrr:
   5804   case X86::VCVTSI2SSrm:
   5805   case X86::Int_VCVTSI2SSrr:
   5806   case X86::Int_VCVTSI2SSrm:
   5807   case X86::VCVTSI2SS64rr:
   5808   case X86::VCVTSI2SS64rm:
   5809   case X86::Int_VCVTSI2SS64rr:
   5810   case X86::Int_VCVTSI2SS64rm:
   5811   case X86::VCVTSI2SDrr:
   5812   case X86::VCVTSI2SDrm:
   5813   case X86::Int_VCVTSI2SDrr:
   5814   case X86::Int_VCVTSI2SDrm:
   5815   case X86::VCVTSI2SD64rr:
   5816   case X86::VCVTSI2SD64rm:
   5817   case X86::Int_VCVTSI2SD64rr:
   5818   case X86::Int_VCVTSI2SD64rm:
   5819   case X86::VCVTSD2SSrr:
   5820   case X86::VCVTSD2SSrm:
   5821   case X86::Int_VCVTSD2SSrr:
   5822   case X86::Int_VCVTSD2SSrm:
   5823   case X86::VCVTSS2SDrr:
   5824   case X86::VCVTSS2SDrm:
   5825   case X86::Int_VCVTSS2SDrr:
   5826   case X86::Int_VCVTSS2SDrm:
   5827   case X86::VRCPSSr:
   5828   case X86::VRCPSSm:
   5829   case X86::VRCPSSm_Int:
   5830   case X86::VROUNDSDr:
   5831   case X86::VROUNDSDm:
   5832   case X86::VROUNDSDr_Int:
   5833   case X86::VROUNDSSr:
   5834   case X86::VROUNDSSm:
   5835   case X86::VROUNDSSr_Int:
   5836   case X86::VRSQRTSSr:
   5837   case X86::VRSQRTSSm:
   5838   case X86::VRSQRTSSm_Int:
   5839   case X86::VSQRTSSr:
   5840   case X86::VSQRTSSm:
   5841   case X86::VSQRTSSm_Int:
   5842   case X86::VSQRTSDr:
   5843   case X86::VSQRTSDm:
   5844   case X86::VSQRTSDm_Int:
   5845     // AVX-512
   5846   case X86::VCVTSD2SSZrr:
   5847   case X86::VCVTSD2SSZrm:
   5848   case X86::VCVTSS2SDZrr:
   5849   case X86::VCVTSS2SDZrm:
   5850     return true;
   5851   }
   5852 
   5853   return false;
   5854 }
   5855 
   5856 /// Inform the ExeDepsFix pass how many idle instructions we would like before
   5857 /// certain undef register reads.
   5858 ///
   5859 /// This catches the VCVTSI2SD family of instructions:
   5860 ///
   5861 /// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
   5862 ///
   5863 /// We should to be careful *not* to catch VXOR idioms which are presumably
   5864 /// handled specially in the pipeline:
   5865 ///
   5866 /// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
   5867 ///
   5868 /// Like getPartialRegUpdateClearance, this makes a strong assumption that the
   5869 /// high bits that are passed-through are not live.
   5870 unsigned X86InstrInfo::
   5871 getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
   5872                      const TargetRegisterInfo *TRI) const {
   5873   if (!hasUndefRegUpdate(MI->getOpcode()))
   5874     return 0;
   5875 
   5876   // Set the OpNum parameter to the first source operand.
   5877   OpNum = 1;
   5878 
   5879   const MachineOperand &MO = MI->getOperand(OpNum);
   5880   if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
   5881     // Use the same magic number as getPartialRegUpdateClearance.
   5882     return 16;
   5883   }
   5884   return 0;
   5885 }
   5886 
   5887 void X86InstrInfo::
   5888 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
   5889                           const TargetRegisterInfo *TRI) const {
   5890   unsigned Reg = MI->getOperand(OpNum).getReg();
   5891   // If MI kills this register, the false dependence is already broken.
   5892   if (MI->killsRegister(Reg, TRI))
   5893     return;
   5894   if (X86::VR128RegClass.contains(Reg)) {
   5895     // These instructions are all floating point domain, so xorps is the best
   5896     // choice.
   5897     bool HasAVX = Subtarget.hasAVX();
   5898     unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
   5899     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
   5900       .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
   5901   } else if (X86::VR256RegClass.contains(Reg)) {
   5902     // Use vxorps to clear the full ymm register.
   5903     // It wants to read and write the xmm sub-register.
   5904     unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
   5905     BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
   5906       .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
   5907       .addReg(Reg, RegState::ImplicitDefine);
   5908   } else
   5909     return;
   5910   MI->addRegisterKilled(Reg, TRI, true);
   5911 }
   5912 
   5913 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
   5914     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
   5915     MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
   5916   // Check switch flag
   5917   if (NoFusing) return nullptr;
   5918 
   5919   // Unless optimizing for size, don't fold to avoid partial
   5920   // register update stalls
   5921   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
   5922     return nullptr;
   5923 
   5924   const MachineFrameInfo *MFI = MF.getFrameInfo();
   5925   unsigned Size = MFI->getObjectSize(FrameIndex);
   5926   unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
   5927   // If the function stack isn't realigned we don't want to fold instructions
   5928   // that need increased alignment.
   5929   if (!RI.needsStackRealignment(MF))
   5930     Alignment =
   5931         std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
   5932   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
   5933     unsigned NewOpc = 0;
   5934     unsigned RCSize = 0;
   5935     switch (MI->getOpcode()) {
   5936     default: return nullptr;
   5937     case X86::TEST8rr:  NewOpc = X86::CMP8ri; RCSize = 1; break;
   5938     case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
   5939     case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
   5940     case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
   5941     }
   5942     // Check if it's safe to fold the load. If the size of the object is
   5943     // narrower than the load width, then it's not.
   5944     if (Size < RCSize)
   5945       return nullptr;
   5946     // Change to CMPXXri r, 0 first.
   5947     MI->setDesc(get(NewOpc));
   5948     MI->getOperand(1).ChangeToImmediate(0);
   5949   } else if (Ops.size() != 1)
   5950     return nullptr;
   5951 
   5952   return foldMemoryOperandImpl(MF, MI, Ops[0],
   5953                                MachineOperand::CreateFI(FrameIndex), InsertPt,
   5954                                Size, Alignment, /*AllowCommute=*/true);
   5955 }
   5956 
   5957 /// Check if \p LoadMI is a partial register load that we can't fold into \p MI
   5958 /// because the latter uses contents that wouldn't be defined in the folded
   5959 /// version.  For instance, this transformation isn't legal:
   5960 ///   movss (%rdi), %xmm0
   5961 ///   addps %xmm0, %xmm0
   5962 /// ->
   5963 ///   addps (%rdi), %xmm0
   5964 ///
   5965 /// But this one is:
   5966 ///   movss (%rdi), %xmm0
   5967 ///   addss %xmm0, %xmm0
   5968 /// ->
   5969 ///   addss (%rdi), %xmm0
   5970 ///
   5971 static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
   5972                                              const MachineInstr &UserMI,
   5973                                              const MachineFunction &MF) {
   5974   unsigned Opc = LoadMI.getOpcode();
   5975   unsigned UserOpc = UserMI.getOpcode();
   5976   unsigned RegSize =
   5977       MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
   5978 
   5979   if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
   5980     // These instructions only load 32 bits, we can't fold them if the
   5981     // destination register is wider than 32 bits (4 bytes), and its user
   5982     // instruction isn't scalar (SS).
   5983     switch (UserOpc) {
   5984     case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
   5985     case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
   5986     case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
   5987     case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
   5988     case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
   5989     case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
   5990     case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
   5991     case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
   5992     case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
   5993     case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
   5994       return false;
   5995     default:
   5996       return true;
   5997     }
   5998   }
   5999 
   6000   if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
   6001     // These instructions only load 64 bits, we can't fold them if the
   6002     // destination register is wider than 64 bits (8 bytes), and its user
   6003     // instruction isn't scalar (SD).
   6004     switch (UserOpc) {
   6005     case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
   6006     case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
   6007     case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
   6008     case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
   6009     case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
   6010     case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
   6011     case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
   6012     case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
   6013     case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
   6014     case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
   6015       return false;
   6016     default:
   6017       return true;
   6018     }
   6019   }
   6020 
   6021   return false;
   6022 }
   6023 
   6024 MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
   6025     MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
   6026     MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
   6027   // If loading from a FrameIndex, fold directly from the FrameIndex.
   6028   unsigned NumOps = LoadMI->getDesc().getNumOperands();
   6029   int FrameIndex;
   6030   if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
   6031     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
   6032       return nullptr;
   6033     return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
   6034   }
   6035 
   6036   // Check switch flag
   6037   if (NoFusing) return nullptr;
   6038 
   6039   // Avoid partial register update stalls unless optimizing for size.
   6040   if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
   6041     return nullptr;
   6042 
   6043   // Determine the alignment of the load.
   6044   unsigned Alignment = 0;
   6045   if (LoadMI->hasOneMemOperand())
   6046     Alignment = (*LoadMI->memoperands_begin())->getAlignment();
   6047   else
   6048     switch (LoadMI->getOpcode()) {
   6049     case X86::AVX2_SETALLONES:
   6050     case X86::AVX_SET0:
   6051       Alignment = 32;
   6052       break;
   6053     case X86::V_SET0:
   6054     case X86::V_SETALLONES:
   6055       Alignment = 16;
   6056       break;
   6057     case X86::FsFLD0SD:
   6058       Alignment = 8;
   6059       break;
   6060     case X86::FsFLD0SS:
   6061       Alignment = 4;
   6062       break;
   6063     default:
   6064       return nullptr;
   6065     }
   6066   if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
   6067     unsigned NewOpc = 0;
   6068     switch (MI->getOpcode()) {
   6069     default: return nullptr;
   6070     case X86::TEST8rr:  NewOpc = X86::CMP8ri; break;
   6071     case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
   6072     case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
   6073     case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
   6074     }
   6075     // Change to CMPXXri r, 0 first.
   6076     MI->setDesc(get(NewOpc));
   6077     MI->getOperand(1).ChangeToImmediate(0);
   6078   } else if (Ops.size() != 1)
   6079     return nullptr;
   6080 
   6081   // Make sure the subregisters match.
   6082   // Otherwise we risk changing the size of the load.
   6083   if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
   6084     return nullptr;
   6085 
   6086   SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
   6087   switch (LoadMI->getOpcode()) {
   6088   case X86::V_SET0:
   6089   case X86::V_SETALLONES:
   6090   case X86::AVX2_SETALLONES:
   6091   case X86::AVX_SET0:
   6092   case X86::FsFLD0SD:
   6093   case X86::FsFLD0SS: {
   6094     // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
   6095     // Create a constant-pool entry and operands to load from it.
   6096 
   6097     // Medium and large mode can't fold loads this way.
   6098     if (MF.getTarget().getCodeModel() != CodeModel::Small &&
   6099         MF.getTarget().getCodeModel() != CodeModel::Kernel)
   6100       return nullptr;
   6101 
   6102     // x86-32 PIC requires a PIC base register for constant pools.
   6103     unsigned PICBase = 0;
   6104     if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
   6105       if (Subtarget.is64Bit())
   6106         PICBase = X86::RIP;
   6107       else
   6108         // FIXME: PICBase = getGlobalBaseReg(&MF);
   6109         // This doesn't work for several reasons.
   6110         // 1. GlobalBaseReg may have been spilled.
   6111         // 2. It may not be live at MI.
   6112         return nullptr;
   6113     }
   6114 
   6115     // Create a constant-pool entry.
   6116     MachineConstantPool &MCP = *MF.getConstantPool();
   6117     Type *Ty;
   6118     unsigned Opc = LoadMI->getOpcode();
   6119     if (Opc == X86::FsFLD0SS)
   6120       Ty = Type::getFloatTy(MF.getFunction()->getContext());
   6121     else if (Opc == X86::FsFLD0SD)
   6122       Ty = Type::getDoubleTy(MF.getFunction()->getContext());
   6123     else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
   6124       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
   6125     else
   6126       Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
   6127 
   6128     bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
   6129     const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
   6130                                     Constant::getNullValue(Ty);
   6131     unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
   6132 
   6133     // Create operands to load from the constant pool entry.
   6134     MOs.push_back(MachineOperand::CreateReg(PICBase, false));
   6135     MOs.push_back(MachineOperand::CreateImm(1));
   6136     MOs.push_back(MachineOperand::CreateReg(0, false));
   6137     MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
   6138     MOs.push_back(MachineOperand::CreateReg(0, false));
   6139     break;
   6140   }
   6141   default: {
   6142     if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
   6143       return nullptr;
   6144 
   6145     // Folding a normal load. Just copy the load's address operands.
   6146     MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
   6147                LoadMI->operands_begin() + NumOps);
   6148     break;
   6149   }
   6150   }
   6151   return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
   6152                                /*Size=*/0, Alignment, /*AllowCommute=*/true);
   6153 }
   6154 
   6155 bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
   6156                                 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
   6157                                 SmallVectorImpl<MachineInstr*> &NewMIs) const {
   6158   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
   6159     MemOp2RegOpTable.find(MI->getOpcode());
   6160   if (I == MemOp2RegOpTable.end())
   6161     return false;
   6162   unsigned Opc = I->second.first;
   6163   unsigned Index = I->second.second & TB_INDEX_MASK;
   6164   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
   6165   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   6166   if (UnfoldLoad && !FoldedLoad)
   6167     return false;
   6168   UnfoldLoad &= FoldedLoad;
   6169   if (UnfoldStore && !FoldedStore)
   6170     return false;
   6171   UnfoldStore &= FoldedStore;
   6172 
   6173   const MCInstrDesc &MCID = get(Opc);
   6174   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
   6175   // TODO: Check if 32-byte or greater accesses are slow too?
   6176   if (!MI->hasOneMemOperand() &&
   6177       RC == &X86::VR128RegClass &&
   6178       Subtarget.isUnalignedMem16Slow())
   6179     // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
   6180     // conservatively assume the address is unaligned. That's bad for
   6181     // performance.
   6182     return false;
   6183   SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
   6184   SmallVector<MachineOperand,2> BeforeOps;
   6185   SmallVector<MachineOperand,2> AfterOps;
   6186   SmallVector<MachineOperand,4> ImpOps;
   6187   for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
   6188     MachineOperand &Op = MI->getOperand(i);
   6189     if (i >= Index && i < Index + X86::AddrNumOperands)
   6190       AddrOps.push_back(Op);
   6191     else if (Op.isReg() && Op.isImplicit())
   6192       ImpOps.push_back(Op);
   6193     else if (i < Index)
   6194       BeforeOps.push_back(Op);
   6195     else if (i > Index)
   6196       AfterOps.push_back(Op);
   6197   }
   6198 
   6199   // Emit the load instruction.
   6200   if (UnfoldLoad) {
   6201     std::pair<MachineInstr::mmo_iterator,
   6202               MachineInstr::mmo_iterator> MMOs =
   6203       MF.extractLoadMemRefs(MI->memoperands_begin(),
   6204                             MI->memoperands_end());
   6205     loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
   6206     if (UnfoldStore) {
   6207       // Address operands cannot be marked isKill.
   6208       for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
   6209         MachineOperand &MO = NewMIs[0]->getOperand(i);
   6210         if (MO.isReg())
   6211           MO.setIsKill(false);
   6212       }
   6213     }
   6214   }
   6215 
   6216   // Emit the data processing instruction.
   6217   MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
   6218   MachineInstrBuilder MIB(MF, DataMI);
   6219 
   6220   if (FoldedStore)
   6221     MIB.addReg(Reg, RegState::Define);
   6222   for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
   6223     MIB.addOperand(BeforeOps[i]);
   6224   if (FoldedLoad)
   6225     MIB.addReg(Reg);
   6226   for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
   6227     MIB.addOperand(AfterOps[i]);
   6228   for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
   6229     MachineOperand &MO = ImpOps[i];
   6230     MIB.addReg(MO.getReg(),
   6231                getDefRegState(MO.isDef()) |
   6232                RegState::Implicit |
   6233                getKillRegState(MO.isKill()) |
   6234                getDeadRegState(MO.isDead()) |
   6235                getUndefRegState(MO.isUndef()));
   6236   }
   6237   // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
   6238   switch (DataMI->getOpcode()) {
   6239   default: break;
   6240   case X86::CMP64ri32:
   6241   case X86::CMP64ri8:
   6242   case X86::CMP32ri:
   6243   case X86::CMP32ri8:
   6244   case X86::CMP16ri:
   6245   case X86::CMP16ri8:
   6246   case X86::CMP8ri: {
   6247     MachineOperand &MO0 = DataMI->getOperand(0);
   6248     MachineOperand &MO1 = DataMI->getOperand(1);
   6249     if (MO1.getImm() == 0) {
   6250       unsigned NewOpc;
   6251       switch (DataMI->getOpcode()) {
   6252       default: llvm_unreachable("Unreachable!");
   6253       case X86::CMP64ri8:
   6254       case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
   6255       case X86::CMP32ri8:
   6256       case X86::CMP32ri:   NewOpc = X86::TEST32rr; break;
   6257       case X86::CMP16ri8:
   6258       case X86::CMP16ri:   NewOpc = X86::TEST16rr; break;
   6259       case X86::CMP8ri:    NewOpc = X86::TEST8rr; break;
   6260       }
   6261       DataMI->setDesc(get(NewOpc));
   6262       MO1.ChangeToRegister(MO0.getReg(), false);
   6263     }
   6264   }
   6265   }
   6266   NewMIs.push_back(DataMI);
   6267 
   6268   // Emit the store instruction.
   6269   if (UnfoldStore) {
   6270     const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
   6271     std::pair<MachineInstr::mmo_iterator,
   6272               MachineInstr::mmo_iterator> MMOs =
   6273       MF.extractStoreMemRefs(MI->memoperands_begin(),
   6274                              MI->memoperands_end());
   6275     storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
   6276   }
   6277 
   6278   return true;
   6279 }
   6280 
   6281 bool
   6282 X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
   6283                                   SmallVectorImpl<SDNode*> &NewNodes) const {
   6284   if (!N->isMachineOpcode())
   6285     return false;
   6286 
   6287   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
   6288     MemOp2RegOpTable.find(N->getMachineOpcode());
   6289   if (I == MemOp2RegOpTable.end())
   6290     return false;
   6291   unsigned Opc = I->second.first;
   6292   unsigned Index = I->second.second & TB_INDEX_MASK;
   6293   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
   6294   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   6295   const MCInstrDesc &MCID = get(Opc);
   6296   MachineFunction &MF = DAG.getMachineFunction();
   6297   const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
   6298   unsigned NumDefs = MCID.NumDefs;
   6299   std::vector<SDValue> AddrOps;
   6300   std::vector<SDValue> BeforeOps;
   6301   std::vector<SDValue> AfterOps;
   6302   SDLoc dl(N);
   6303   unsigned NumOps = N->getNumOperands();
   6304   for (unsigned i = 0; i != NumOps-1; ++i) {
   6305     SDValue Op = N->getOperand(i);
   6306     if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
   6307       AddrOps.push_back(Op);
   6308     else if (i < Index-NumDefs)
   6309       BeforeOps.push_back(Op);
   6310     else if (i > Index-NumDefs)
   6311       AfterOps.push_back(Op);
   6312   }
   6313   SDValue Chain = N->getOperand(NumOps-1);
   6314   AddrOps.push_back(Chain);
   6315 
   6316   // Emit the load instruction.
   6317   SDNode *Load = nullptr;
   6318   if (FoldedLoad) {
   6319     EVT VT = *RC->vt_begin();
   6320     std::pair<MachineInstr::mmo_iterator,
   6321               MachineInstr::mmo_iterator> MMOs =
   6322       MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
   6323                             cast<MachineSDNode>(N)->memoperands_end());
   6324     if (!(*MMOs.first) &&
   6325         RC == &X86::VR128RegClass &&
   6326         Subtarget.isUnalignedMem16Slow())
   6327       // Do not introduce a slow unaligned load.
   6328       return false;
   6329     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
   6330     // memory access is slow above.
   6331     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
   6332     bool isAligned = (*MMOs.first) &&
   6333                      (*MMOs.first)->getAlignment() >= Alignment;
   6334     Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
   6335                               VT, MVT::Other, AddrOps);
   6336     NewNodes.push_back(Load);
   6337 
   6338     // Preserve memory reference information.
   6339     cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
   6340   }
   6341 
   6342   // Emit the data processing instruction.
   6343   std::vector<EVT> VTs;
   6344   const TargetRegisterClass *DstRC = nullptr;
   6345   if (MCID.getNumDefs() > 0) {
   6346     DstRC = getRegClass(MCID, 0, &RI, MF);
   6347     VTs.push_back(*DstRC->vt_begin());
   6348   }
   6349   for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
   6350     EVT VT = N->getValueType(i);
   6351     if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
   6352       VTs.push_back(VT);
   6353   }
   6354   if (Load)
   6355     BeforeOps.push_back(SDValue(Load, 0));
   6356   BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
   6357   SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
   6358   NewNodes.push_back(NewNode);
   6359 
   6360   // Emit the store instruction.
   6361   if (FoldedStore) {
   6362     AddrOps.pop_back();
   6363     AddrOps.push_back(SDValue(NewNode, 0));
   6364     AddrOps.push_back(Chain);
   6365     std::pair<MachineInstr::mmo_iterator,
   6366               MachineInstr::mmo_iterator> MMOs =
   6367       MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
   6368                              cast<MachineSDNode>(N)->memoperands_end());
   6369     if (!(*MMOs.first) &&
   6370         RC == &X86::VR128RegClass &&
   6371         Subtarget.isUnalignedMem16Slow())
   6372       // Do not introduce a slow unaligned store.
   6373       return false;
   6374     // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
   6375     // memory access is slow above.
   6376     unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
   6377     bool isAligned = (*MMOs.first) &&
   6378                      (*MMOs.first)->getAlignment() >= Alignment;
   6379     SDNode *Store =
   6380         DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
   6381                            dl, MVT::Other, AddrOps);
   6382     NewNodes.push_back(Store);
   6383 
   6384     // Preserve memory reference information.
   6385     cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
   6386   }
   6387 
   6388   return true;
   6389 }
   6390 
   6391 unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
   6392                                       bool UnfoldLoad, bool UnfoldStore,
   6393                                       unsigned *LoadRegIndex) const {
   6394   DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
   6395     MemOp2RegOpTable.find(Opc);
   6396   if (I == MemOp2RegOpTable.end())
   6397     return 0;
   6398   bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
   6399   bool FoldedStore = I->second.second & TB_FOLDED_STORE;
   6400   if (UnfoldLoad && !FoldedLoad)
   6401     return 0;
   6402   if (UnfoldStore && !FoldedStore)
   6403     return 0;
   6404   if (LoadRegIndex)
   6405     *LoadRegIndex = I->second.second & TB_INDEX_MASK;
   6406   return I->second.first;
   6407 }
   6408 
   6409 bool
   6410 X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
   6411                                      int64_t &Offset1, int64_t &Offset2) const {
   6412   if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
   6413     return false;
   6414   unsigned Opc1 = Load1->getMachineOpcode();
   6415   unsigned Opc2 = Load2->getMachineOpcode();
   6416   switch (Opc1) {
   6417   default: return false;
   6418   case X86::MOV8rm:
   6419   case X86::MOV16rm:
   6420   case X86::MOV32rm:
   6421   case X86::MOV64rm:
   6422   case X86::LD_Fp32m:
   6423   case X86::LD_Fp64m:
   6424   case X86::LD_Fp80m:
   6425   case X86::MOVSSrm:
   6426   case X86::MOVSDrm:
   6427   case X86::MMX_MOVD64rm:
   6428   case X86::MMX_MOVQ64rm:
   6429   case X86::FsMOVAPSrm:
   6430   case X86::FsMOVAPDrm:
   6431   case X86::MOVAPSrm:
   6432   case X86::MOVUPSrm:
   6433   case X86::MOVAPDrm:
   6434   case X86::MOVDQArm:
   6435   case X86::MOVDQUrm:
   6436   // AVX load instructions
   6437   case X86::VMOVSSrm:
   6438   case X86::VMOVSDrm:
   6439   case X86::FsVMOVAPSrm:
   6440   case X86::FsVMOVAPDrm:
   6441   case X86::VMOVAPSrm:
   6442   case X86::VMOVUPSrm:
   6443   case X86::VMOVAPDrm:
   6444   case X86::VMOVDQArm:
   6445   case X86::VMOVDQUrm:
   6446   case X86::VMOVAPSYrm:
   6447   case X86::VMOVUPSYrm:
   6448   case X86::VMOVAPDYrm:
   6449   case X86::VMOVDQAYrm:
   6450   case X86::VMOVDQUYrm:
   6451     break;
   6452   }
   6453   switch (Opc2) {
   6454   default: return false;
   6455   case X86::MOV8rm:
   6456   case X86::MOV16rm:
   6457   case X86::MOV32rm:
   6458   case X86::MOV64rm:
   6459   case X86::LD_Fp32m:
   6460   case X86::LD_Fp64m:
   6461   case X86::LD_Fp80m:
   6462   case X86::MOVSSrm:
   6463   case X86::MOVSDrm:
   6464   case X86::MMX_MOVD64rm:
   6465   case X86::MMX_MOVQ64rm:
   6466   case X86::FsMOVAPSrm:
   6467   case X86::FsMOVAPDrm:
   6468   case X86::MOVAPSrm:
   6469   case X86::MOVUPSrm:
   6470   case X86::MOVAPDrm:
   6471   case X86::MOVDQArm:
   6472   case X86::MOVDQUrm:
   6473   // AVX load instructions
   6474   case X86::VMOVSSrm:
   6475   case X86::VMOVSDrm:
   6476   case X86::FsVMOVAPSrm:
   6477   case X86::FsVMOVAPDrm:
   6478   case X86::VMOVAPSrm:
   6479   case X86::VMOVUPSrm:
   6480   case X86::VMOVAPDrm:
   6481   case X86::VMOVDQArm:
   6482   case X86::VMOVDQUrm:
   6483   case X86::VMOVAPSYrm:
   6484   case X86::VMOVUPSYrm:
   6485   case X86::VMOVAPDYrm:
   6486   case X86::VMOVDQAYrm:
   6487   case X86::VMOVDQUYrm:
   6488     break;
   6489   }
   6490 
   6491   // Check if chain operands and base addresses match.
   6492   if (Load1->getOperand(0) != Load2->getOperand(0) ||
   6493       Load1->getOperand(5) != Load2->getOperand(5))
   6494     return false;
   6495   // Segment operands should match as well.
   6496   if (Load1->getOperand(4) != Load2->getOperand(4))
   6497     return false;
   6498   // Scale should be 1, Index should be Reg0.
   6499   if (Load1->getOperand(1) == Load2->getOperand(1) &&
   6500       Load1->getOperand(2) == Load2->getOperand(2)) {
   6501     if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
   6502       return false;
   6503 
   6504     // Now let's examine the displacements.
   6505     if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
   6506         isa<ConstantSDNode>(Load2->getOperand(3))) {
   6507       Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
   6508       Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
   6509       return true;
   6510     }
   6511   }
   6512   return false;
   6513 }
   6514 
   6515 bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
   6516                                            int64_t Offset1, int64_t Offset2,
   6517                                            unsigned NumLoads) const {
   6518   assert(Offset2 > Offset1);
   6519   if ((Offset2 - Offset1) / 8 > 64)
   6520     return false;
   6521 
   6522   unsigned Opc1 = Load1->getMachineOpcode();
   6523   unsigned Opc2 = Load2->getMachineOpcode();
   6524   if (Opc1 != Opc2)
   6525     return false;  // FIXME: overly conservative?
   6526 
   6527   switch (Opc1) {
   6528   default: break;
   6529   case X86::LD_Fp32m:
   6530   case X86::LD_Fp64m:
   6531   case X86::LD_Fp80m:
   6532   case X86::MMX_MOVD64rm:
   6533   case X86::MMX_MOVQ64rm:
   6534     return false;
   6535   }
   6536 
   6537   EVT VT = Load1->getValueType(0);
   6538   switch (VT.getSimpleVT().SimpleTy) {
   6539   default:
   6540     // XMM registers. In 64-bit mode we can be a bit more aggressive since we
   6541     // have 16 of them to play with.
   6542     if (Subtarget.is64Bit()) {
   6543       if (NumLoads >= 3)
   6544         return false;
   6545     } else if (NumLoads) {
   6546       return false;
   6547     }
   6548     break;
   6549   case MVT::i8:
   6550   case MVT::i16:
   6551   case MVT::i32:
   6552   case MVT::i64:
   6553   case MVT::f32:
   6554   case MVT::f64:
   6555     if (NumLoads)
   6556       return false;
   6557     break;
   6558   }
   6559 
   6560   return true;
   6561 }
   6562 
   6563 bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
   6564                                           MachineInstr *Second) const {
   6565   // Check if this processor supports macro-fusion. Since this is a minor
   6566   // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
   6567   // proxy for SandyBridge+.
   6568   if (!Subtarget.hasAVX())
   6569     return false;
   6570 
   6571   enum {
   6572     FuseTest,
   6573     FuseCmp,
   6574     FuseInc
   6575   } FuseKind;
   6576 
   6577   switch(Second->getOpcode()) {
   6578   default:
   6579     return false;
   6580   case X86::JE_1:
   6581   case X86::JNE_1:
   6582   case X86::JL_1:
   6583   case X86::JLE_1:
   6584   case X86::JG_1:
   6585   case X86::JGE_1:
   6586     FuseKind = FuseInc;
   6587     break;
   6588   case X86::JB_1:
   6589   case X86::JBE_1:
   6590   case X86::JA_1:
   6591   case X86::JAE_1:
   6592     FuseKind = FuseCmp;
   6593     break;
   6594   case X86::JS_1:
   6595   case X86::JNS_1:
   6596   case X86::JP_1:
   6597   case X86::JNP_1:
   6598   case X86::JO_1:
   6599   case X86::JNO_1:
   6600     FuseKind = FuseTest;
   6601     break;
   6602   }
   6603   switch (First->getOpcode()) {
   6604   default:
   6605     return false;
   6606   case X86::TEST8rr:
   6607   case X86::TEST16rr:
   6608   case X86::TEST32rr:
   6609   case X86::TEST64rr:
   6610   case X86::TEST8ri:
   6611   case X86::TEST16ri:
   6612   case X86::TEST32ri:
   6613   case X86::TEST32i32:
   6614   case X86::TEST64i32:
   6615   case X86::TEST64ri32:
   6616   case X86::TEST8rm:
   6617   case X86::TEST16rm:
   6618   case X86::TEST32rm:
   6619   case X86::TEST64rm:
   6620   case X86::TEST8ri_NOREX:
   6621   case X86::AND16i16:
   6622   case X86::AND16ri:
   6623   case X86::AND16ri8:
   6624   case X86::AND16rm:
   6625   case X86::AND16rr:
   6626   case X86::AND32i32:
   6627   case X86::AND32ri:
   6628   case X86::AND32ri8:
   6629   case X86::AND32rm:
   6630   case X86::AND32rr:
   6631   case X86::AND64i32:
   6632   case X86::AND64ri32:
   6633   case X86::AND64ri8:
   6634   case X86::AND64rm:
   6635   case X86::AND64rr:
   6636   case X86::AND8i8:
   6637   case X86::AND8ri:
   6638   case X86::AND8rm:
   6639   case X86::AND8rr:
   6640     return true;
   6641   case X86::CMP16i16:
   6642   case X86::CMP16ri:
   6643   case X86::CMP16ri8:
   6644   case X86::CMP16rm:
   6645   case X86::CMP16rr:
   6646   case X86::CMP32i32:
   6647   case X86::CMP32ri:
   6648   case X86::CMP32ri8:
   6649   case X86::CMP32rm:
   6650   case X86::CMP32rr:
   6651   case X86::CMP64i32:
   6652   case X86::CMP64ri32:
   6653   case X86::CMP64ri8:
   6654   case X86::CMP64rm:
   6655   case X86::CMP64rr:
   6656   case X86::CMP8i8:
   6657   case X86::CMP8ri:
   6658   case X86::CMP8rm:
   6659   case X86::CMP8rr:
   6660   case X86::ADD16i16:
   6661   case X86::ADD16ri:
   6662   case X86::ADD16ri8:
   6663   case X86::ADD16ri8_DB:
   6664   case X86::ADD16ri_DB:
   6665   case X86::ADD16rm:
   6666   case X86::ADD16rr:
   6667   case X86::ADD16rr_DB:
   6668   case X86::ADD32i32:
   6669   case X86::ADD32ri:
   6670   case X86::ADD32ri8:
   6671   case X86::ADD32ri8_DB:
   6672   case X86::ADD32ri_DB:
   6673   case X86::ADD32rm:
   6674   case X86::ADD32rr:
   6675   case X86::ADD32rr_DB:
   6676   case X86::ADD64i32:
   6677   case X86::ADD64ri32:
   6678   case X86::ADD64ri32_DB:
   6679   case X86::ADD64ri8:
   6680   case X86::ADD64ri8_DB:
   6681   case X86::ADD64rm:
   6682   case X86::ADD64rr:
   6683   case X86::ADD64rr_DB:
   6684   case X86::ADD8i8:
   6685   case X86::ADD8mi:
   6686   case X86::ADD8mr:
   6687   case X86::ADD8ri:
   6688   case X86::ADD8rm:
   6689   case X86::ADD8rr:
   6690   case X86::SUB16i16:
   6691   case X86::SUB16ri:
   6692   case X86::SUB16ri8:
   6693   case X86::SUB16rm:
   6694   case X86::SUB16rr:
   6695   case X86::SUB32i32:
   6696   case X86::SUB32ri:
   6697   case X86::SUB32ri8:
   6698   case X86::SUB32rm:
   6699   case X86::SUB32rr:
   6700   case X86::SUB64i32:
   6701   case X86::SUB64ri32:
   6702   case X86::SUB64ri8:
   6703   case X86::SUB64rm:
   6704   case X86::SUB64rr:
   6705   case X86::SUB8i8:
   6706   case X86::SUB8ri:
   6707   case X86::SUB8rm:
   6708   case X86::SUB8rr:
   6709     return FuseKind == FuseCmp || FuseKind == FuseInc;
   6710   case X86::INC16r:
   6711   case X86::INC32r:
   6712   case X86::INC64r:
   6713   case X86::INC8r:
   6714   case X86::DEC16r:
   6715   case X86::DEC32r:
   6716   case X86::DEC64r:
   6717   case X86::DEC8r:
   6718     return FuseKind == FuseInc;
   6719   }
   6720 }
   6721 
   6722 bool X86InstrInfo::
   6723 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
   6724   assert(Cond.size() == 1 && "Invalid X86 branch condition!");
   6725   X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
   6726   if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
   6727     return true;
   6728   Cond[0].setImm(GetOppositeBranchCondition(CC));
   6729   return false;
   6730 }
   6731 
   6732 bool X86InstrInfo::
   6733 isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
   6734   // FIXME: Return false for x87 stack register classes for now. We can't
   6735   // allow any loads of these registers before FpGet_ST0_80.
   6736   return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
   6737            RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
   6738 }
   6739 
   6740 /// Return a virtual register initialized with the
   6741 /// the global base register value. Output instructions required to
   6742 /// initialize the register in the function entry block, if necessary.
   6743 ///
   6744 /// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
   6745 ///
   6746 unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
   6747   assert(!Subtarget.is64Bit() &&
   6748          "X86-64 PIC uses RIP relative addressing");
   6749 
   6750   X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
   6751   unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
   6752   if (GlobalBaseReg != 0)
   6753     return GlobalBaseReg;
   6754 
   6755   // Create the register. The code to initialize it is inserted
   6756   // later, by the CGBR pass (below).
   6757   MachineRegisterInfo &RegInfo = MF->getRegInfo();
   6758   GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
   6759   X86FI->setGlobalBaseReg(GlobalBaseReg);
   6760   return GlobalBaseReg;
   6761 }
   6762 
   6763 // These are the replaceable SSE instructions. Some of these have Int variants
   6764 // that we don't include here. We don't want to replace instructions selected
   6765 // by intrinsics.
   6766 static const uint16_t ReplaceableInstrs[][3] = {
   6767   //PackedSingle     PackedDouble    PackedInt
   6768   { X86::MOVAPSmr,   X86::MOVAPDmr,  X86::MOVDQAmr  },
   6769   { X86::MOVAPSrm,   X86::MOVAPDrm,  X86::MOVDQArm  },
   6770   { X86::MOVAPSrr,   X86::MOVAPDrr,  X86::MOVDQArr  },
   6771   { X86::MOVUPSmr,   X86::MOVUPDmr,  X86::MOVDQUmr  },
   6772   { X86::MOVUPSrm,   X86::MOVUPDrm,  X86::MOVDQUrm  },
   6773   { X86::MOVLPSmr,   X86::MOVLPDmr,  X86::MOVPQI2QImr  },
   6774   { X86::MOVNTPSmr,  X86::MOVNTPDmr, X86::MOVNTDQmr },
   6775   { X86::ANDNPSrm,   X86::ANDNPDrm,  X86::PANDNrm   },
   6776   { X86::ANDNPSrr,   X86::ANDNPDrr,  X86::PANDNrr   },
   6777   { X86::ANDPSrm,    X86::ANDPDrm,   X86::PANDrm    },
   6778   { X86::ANDPSrr,    X86::ANDPDrr,   X86::PANDrr    },
   6779   { X86::ORPSrm,     X86::ORPDrm,    X86::PORrm     },
   6780   { X86::ORPSrr,     X86::ORPDrr,    X86::PORrr     },
   6781   { X86::XORPSrm,    X86::XORPDrm,   X86::PXORrm    },
   6782   { X86::XORPSrr,    X86::XORPDrr,   X86::PXORrr    },
   6783   // AVX 128-bit support
   6784   { X86::VMOVAPSmr,  X86::VMOVAPDmr,  X86::VMOVDQAmr  },
   6785   { X86::VMOVAPSrm,  X86::VMOVAPDrm,  X86::VMOVDQArm  },
   6786   { X86::VMOVAPSrr,  X86::VMOVAPDrr,  X86::VMOVDQArr  },
   6787   { X86::VMOVUPSmr,  X86::VMOVUPDmr,  X86::VMOVDQUmr  },
   6788   { X86::VMOVUPSrm,  X86::VMOVUPDrm,  X86::VMOVDQUrm  },
   6789   { X86::VMOVLPSmr,  X86::VMOVLPDmr,  X86::VMOVPQI2QImr  },
   6790   { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
   6791   { X86::VANDNPSrm,  X86::VANDNPDrm,  X86::VPANDNrm   },
   6792   { X86::VANDNPSrr,  X86::VANDNPDrr,  X86::VPANDNrr   },
   6793   { X86::VANDPSrm,   X86::VANDPDrm,   X86::VPANDrm    },
   6794   { X86::VANDPSrr,   X86::VANDPDrr,   X86::VPANDrr    },
   6795   { X86::VORPSrm,    X86::VORPDrm,    X86::VPORrm     },
   6796   { X86::VORPSrr,    X86::VORPDrr,    X86::VPORrr     },
   6797   { X86::VXORPSrm,   X86::VXORPDrm,   X86::VPXORrm    },
   6798   { X86::VXORPSrr,   X86::VXORPDrr,   X86::VPXORrr    },
   6799   // AVX 256-bit support
   6800   { X86::VMOVAPSYmr,   X86::VMOVAPDYmr,   X86::VMOVDQAYmr  },
   6801   { X86::VMOVAPSYrm,   X86::VMOVAPDYrm,   X86::VMOVDQAYrm  },
   6802   { X86::VMOVAPSYrr,   X86::VMOVAPDYrr,   X86::VMOVDQAYrr  },
   6803   { X86::VMOVUPSYmr,   X86::VMOVUPDYmr,   X86::VMOVDQUYmr  },
   6804   { X86::VMOVUPSYrm,   X86::VMOVUPDYrm,   X86::VMOVDQUYrm  },
   6805   { X86::VMOVNTPSYmr,  X86::VMOVNTPDYmr,  X86::VMOVNTDQYmr }
   6806 };
   6807 
   6808 static const uint16_t ReplaceableInstrsAVX2[][3] = {
   6809   //PackedSingle       PackedDouble       PackedInt
   6810   { X86::VANDNPSYrm,   X86::VANDNPDYrm,   X86::VPANDNYrm   },
   6811   { X86::VANDNPSYrr,   X86::VANDNPDYrr,   X86::VPANDNYrr   },
   6812   { X86::VANDPSYrm,    X86::VANDPDYrm,    X86::VPANDYrm    },
   6813   { X86::VANDPSYrr,    X86::VANDPDYrr,    X86::VPANDYrr    },
   6814   { X86::VORPSYrm,     X86::VORPDYrm,     X86::VPORYrm     },
   6815   { X86::VORPSYrr,     X86::VORPDYrr,     X86::VPORYrr     },
   6816   { X86::VXORPSYrm,    X86::VXORPDYrm,    X86::VPXORYrm    },
   6817   { X86::VXORPSYrr,    X86::VXORPDYrr,    X86::VPXORYrr    },
   6818   { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
   6819   { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
   6820   { X86::VINSERTF128rm,  X86::VINSERTF128rm,  X86::VINSERTI128rm },
   6821   { X86::VINSERTF128rr,  X86::VINSERTF128rr,  X86::VINSERTI128rr },
   6822   { X86::VPERM2F128rm,   X86::VPERM2F128rm,   X86::VPERM2I128rm },
   6823   { X86::VPERM2F128rr,   X86::VPERM2F128rr,   X86::VPERM2I128rr },
   6824   { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
   6825   { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
   6826   { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
   6827   { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
   6828   { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
   6829   { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
   6830 };
   6831 
   6832 // FIXME: Some shuffle and unpack instructions have equivalents in different
   6833 // domains, but they require a bit more work than just switching opcodes.
   6834 
   6835 static const uint16_t *lookup(unsigned opcode, unsigned domain) {
   6836   for (const uint16_t (&Row)[3] : ReplaceableInstrs)
   6837     if (Row[domain-1] == opcode)
   6838       return Row;
   6839   return nullptr;
   6840 }
   6841 
   6842 static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
   6843   for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
   6844     if (Row[domain-1] == opcode)
   6845       return Row;
   6846   return nullptr;
   6847 }
   6848 
   6849 std::pair<uint16_t, uint16_t>
   6850 X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
   6851   uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
   6852   bool hasAVX2 = Subtarget.hasAVX2();
   6853   uint16_t validDomains = 0;
   6854   if (domain && lookup(MI->getOpcode(), domain))
   6855     validDomains = 0xe;
   6856   else if (domain && lookupAVX2(MI->getOpcode(), domain))
   6857     validDomains = hasAVX2 ? 0xe : 0x6;
   6858   return std::make_pair(domain, validDomains);
   6859 }
   6860 
   6861 void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
   6862   assert(Domain>0 && Domain<4 && "Invalid execution domain");
   6863   uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
   6864   assert(dom && "Not an SSE instruction");
   6865   const uint16_t *table = lookup(MI->getOpcode(), dom);
   6866   if (!table) { // try the other table
   6867     assert((Subtarget.hasAVX2() || Domain < 3) &&
   6868            "256-bit vector operations only available in AVX2");
   6869     table = lookupAVX2(MI->getOpcode(), dom);
   6870   }
   6871   assert(table && "Cannot change domain");
   6872   MI->setDesc(get(table[Domain-1]));
   6873 }
   6874 
   6875 /// Return the noop instruction to use for a noop.
   6876 void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
   6877   NopInst.setOpcode(X86::NOOP);
   6878 }
   6879 
   6880 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
   6881 // In particular, getJumpInstrTableEntryBound must always return an upper bound
   6882 // on the encoding lengths of the instructions generated by
   6883 // getUnconditionalBranch and getTrap.
   6884 void X86InstrInfo::getUnconditionalBranch(
   6885     MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
   6886   Branch.setOpcode(X86::JMP_1);
   6887   Branch.addOperand(MCOperand::createExpr(BranchTarget));
   6888 }
   6889 
   6890 // This code must remain in sync with getJumpInstrTableEntryBound in this class!
   6891 // In particular, getJumpInstrTableEntryBound must always return an upper bound
   6892 // on the encoding lengths of the instructions generated by
   6893 // getUnconditionalBranch and getTrap.
   6894 void X86InstrInfo::getTrap(MCInst &MI) const {
   6895   MI.setOpcode(X86::TRAP);
   6896 }
   6897 
   6898 // See getTrap and getUnconditionalBranch for conditions on the value returned
   6899 // by this function.
   6900 unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
   6901   // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
   6902   // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
   6903   return 5;
   6904 }
   6905 
   6906 bool X86InstrInfo::isHighLatencyDef(int opc) const {
   6907   switch (opc) {
   6908   default: return false;
   6909   case X86::DIVSDrm:
   6910   case X86::DIVSDrm_Int:
   6911   case X86::DIVSDrr:
   6912   case X86::DIVSDrr_Int:
   6913   case X86::DIVSSrm:
   6914   case X86::DIVSSrm_Int:
   6915   case X86::DIVSSrr:
   6916   case X86::DIVSSrr_Int:
   6917   case X86::SQRTPDm:
   6918   case X86::SQRTPDr:
   6919   case X86::SQRTPSm:
   6920   case X86::SQRTPSr:
   6921   case X86::SQRTSDm:
   6922   case X86::SQRTSDm_Int:
   6923   case X86::SQRTSDr:
   6924   case X86::SQRTSDr_Int:
   6925   case X86::SQRTSSm:
   6926   case X86::SQRTSSm_Int:
   6927   case X86::SQRTSSr:
   6928   case X86::SQRTSSr_Int:
   6929   // AVX instructions with high latency
   6930   case X86::VDIVSDrm:
   6931   case X86::VDIVSDrm_Int:
   6932   case X86::VDIVSDrr:
   6933   case X86::VDIVSDrr_Int:
   6934   case X86::VDIVSSrm:
   6935   case X86::VDIVSSrm_Int:
   6936   case X86::VDIVSSrr:
   6937   case X86::VDIVSSrr_Int:
   6938   case X86::VSQRTPDm:
   6939   case X86::VSQRTPDr:
   6940   case X86::VSQRTPSm:
   6941   case X86::VSQRTPSr:
   6942   case X86::VSQRTSDm:
   6943   case X86::VSQRTSDm_Int:
   6944   case X86::VSQRTSDr:
   6945   case X86::VSQRTSSm:
   6946   case X86::VSQRTSSm_Int:
   6947   case X86::VSQRTSSr:
   6948   case X86::VSQRTPDZm:
   6949   case X86::VSQRTPDZr:
   6950   case X86::VSQRTPSZm:
   6951   case X86::VSQRTPSZr:
   6952   case X86::VSQRTSDZm:
   6953   case X86::VSQRTSDZm_Int:
   6954   case X86::VSQRTSDZr:
   6955   case X86::VSQRTSSZm_Int:
   6956   case X86::VSQRTSSZr:
   6957   case X86::VSQRTSSZm:
   6958   case X86::VDIVSDZrm:
   6959   case X86::VDIVSDZrr:
   6960   case X86::VDIVSSZrm:
   6961   case X86::VDIVSSZrr:
   6962 
   6963   case X86::VGATHERQPSZrm:
   6964   case X86::VGATHERQPDZrm:
   6965   case X86::VGATHERDPDZrm:
   6966   case X86::VGATHERDPSZrm:
   6967   case X86::VPGATHERQDZrm:
   6968   case X86::VPGATHERQQZrm:
   6969   case X86::VPGATHERDDZrm:
   6970   case X86::VPGATHERDQZrm:
   6971   case X86::VSCATTERQPDZmr:
   6972   case X86::VSCATTERQPSZmr:
   6973   case X86::VSCATTERDPDZmr:
   6974   case X86::VSCATTERDPSZmr:
   6975   case X86::VPSCATTERQDZmr:
   6976   case X86::VPSCATTERQQZmr:
   6977   case X86::VPSCATTERDDZmr:
   6978   case X86::VPSCATTERDQZmr:
   6979     return true;
   6980   }
   6981 }
   6982 
   6983 bool X86InstrInfo::
   6984 hasHighOperandLatency(const TargetSchedModel &SchedModel,
   6985                       const MachineRegisterInfo *MRI,
   6986                       const MachineInstr *DefMI, unsigned DefIdx,
   6987                       const MachineInstr *UseMI, unsigned UseIdx) const {
   6988   return isHighLatencyDef(DefMI->getOpcode());
   6989 }
   6990 
   6991 bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
   6992                                            const MachineBasicBlock *MBB) const {
   6993   assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
   6994          "Reassociation needs binary operators");
   6995 
   6996   // Integer binary math/logic instructions have a third source operand:
   6997   // the EFLAGS register. That operand must be both defined here and never
   6998   // used; ie, it must be dead. If the EFLAGS operand is live, then we can
   6999   // not change anything because rearranging the operands could affect other
   7000   // instructions that depend on the exact status flags (zero, sign, etc.)
   7001   // that are set by using these particular operands with this operation.
   7002   if (Inst.getNumOperands() == 4) {
   7003     assert(Inst.getOperand(3).isReg() &&
   7004            Inst.getOperand(3).getReg() == X86::EFLAGS &&
   7005            "Unexpected operand in reassociable instruction");
   7006     if (!Inst.getOperand(3).isDead())
   7007       return false;
   7008   }
   7009 
   7010   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
   7011 }
   7012 
   7013 // TODO: There are many more machine instruction opcodes to match:
   7014 //       1. Other data types (integer, vectors)
   7015 //       2. Other math / logic operations (xor, or)
   7016 //       3. Other forms of the same operation (intrinsics and other variants)
   7017 bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
   7018   switch (Inst.getOpcode()) {
   7019   case X86::AND8rr:
   7020   case X86::AND16rr:
   7021   case X86::AND32rr:
   7022   case X86::AND64rr:
   7023   case X86::OR8rr:
   7024   case X86::OR16rr:
   7025   case X86::OR32rr:
   7026   case X86::OR64rr:
   7027   case X86::XOR8rr:
   7028   case X86::XOR16rr:
   7029   case X86::XOR32rr:
   7030   case X86::XOR64rr:
   7031   case X86::IMUL16rr:
   7032   case X86::IMUL32rr:
   7033   case X86::IMUL64rr:
   7034   case X86::PANDrr:
   7035   case X86::PORrr:
   7036   case X86::PXORrr:
   7037   case X86::VPANDrr:
   7038   case X86::VPANDYrr:
   7039   case X86::VPORrr:
   7040   case X86::VPORYrr:
   7041   case X86::VPXORrr:
   7042   case X86::VPXORYrr:
   7043   // Normal min/max instructions are not commutative because of NaN and signed
   7044   // zero semantics, but these are. Thus, there's no need to check for global
   7045   // relaxed math; the instructions themselves have the properties we need.
   7046   case X86::MAXCPDrr:
   7047   case X86::MAXCPSrr:
   7048   case X86::MAXCSDrr:
   7049   case X86::MAXCSSrr:
   7050   case X86::MINCPDrr:
   7051   case X86::MINCPSrr:
   7052   case X86::MINCSDrr:
   7053   case X86::MINCSSrr:
   7054   case X86::VMAXCPDrr:
   7055   case X86::VMAXCPSrr:
   7056   case X86::VMAXCPDYrr:
   7057   case X86::VMAXCPSYrr:
   7058   case X86::VMAXCSDrr:
   7059   case X86::VMAXCSSrr:
   7060   case X86::VMINCPDrr:
   7061   case X86::VMINCPSrr:
   7062   case X86::VMINCPDYrr:
   7063   case X86::VMINCPSYrr:
   7064   case X86::VMINCSDrr:
   7065   case X86::VMINCSSrr:
   7066     return true;
   7067   case X86::ADDPDrr:
   7068   case X86::ADDPSrr:
   7069   case X86::ADDSDrr:
   7070   case X86::ADDSSrr:
   7071   case X86::MULPDrr:
   7072   case X86::MULPSrr:
   7073   case X86::MULSDrr:
   7074   case X86::MULSSrr:
   7075   case X86::VADDPDrr:
   7076   case X86::VADDPSrr:
   7077   case X86::VADDPDYrr:
   7078   case X86::VADDPSYrr:
   7079   case X86::VADDSDrr:
   7080   case X86::VADDSSrr:
   7081   case X86::VMULPDrr:
   7082   case X86::VMULPSrr:
   7083   case X86::VMULPDYrr:
   7084   case X86::VMULPSYrr:
   7085   case X86::VMULSDrr:
   7086   case X86::VMULSSrr:
   7087     return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
   7088   default:
   7089     return false;
   7090   }
   7091 }
   7092 
   7093 /// This is an architecture-specific helper function of reassociateOps.
   7094 /// Set special operand attributes for new instructions after reassociation.
   7095 void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
   7096                                          MachineInstr &OldMI2,
   7097                                          MachineInstr &NewMI1,
   7098                                          MachineInstr &NewMI2) const {
   7099   // Integer instructions define an implicit EFLAGS source register operand as
   7100   // the third source (fourth total) operand.
   7101   if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
   7102     return;
   7103 
   7104   assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
   7105          "Unexpected instruction type for reassociation");
   7106 
   7107   MachineOperand &OldOp1 = OldMI1.getOperand(3);
   7108   MachineOperand &OldOp2 = OldMI2.getOperand(3);
   7109   MachineOperand &NewOp1 = NewMI1.getOperand(3);
   7110   MachineOperand &NewOp2 = NewMI2.getOperand(3);
   7111 
   7112   assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
   7113          "Must have dead EFLAGS operand in reassociable instruction");
   7114   assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
   7115          "Must have dead EFLAGS operand in reassociable instruction");
   7116 
   7117   (void)OldOp1;
   7118   (void)OldOp2;
   7119 
   7120   assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
   7121          "Unexpected operand in reassociable instruction");
   7122   assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
   7123          "Unexpected operand in reassociable instruction");
   7124 
   7125   // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
   7126   // of this pass or other passes. The EFLAGS operands must be dead in these new
   7127   // instructions because the EFLAGS operands in the original instructions must
   7128   // be dead in order for reassociation to occur.
   7129   NewOp1.setIsDead();
   7130   NewOp2.setIsDead();
   7131 }
   7132 
   7133 std::pair<unsigned, unsigned>
   7134 X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
   7135   return std::make_pair(TF, 0u);
   7136 }
   7137 
   7138 ArrayRef<std::pair<unsigned, const char *>>
   7139 X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
   7140   using namespace X86II;
   7141   static const std::pair<unsigned, const char *> TargetFlags[] = {
   7142       {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
   7143       {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
   7144       {MO_GOT, "x86-got"},
   7145       {MO_GOTOFF, "x86-gotoff"},
   7146       {MO_GOTPCREL, "x86-gotpcrel"},
   7147       {MO_PLT, "x86-plt"},
   7148       {MO_TLSGD, "x86-tlsgd"},
   7149       {MO_TLSLD, "x86-tlsld"},
   7150       {MO_TLSLDM, "x86-tlsldm"},
   7151       {MO_GOTTPOFF, "x86-gottpoff"},
   7152       {MO_INDNTPOFF, "x86-indntpoff"},
   7153       {MO_TPOFF, "x86-tpoff"},
   7154       {MO_DTPOFF, "x86-dtpoff"},
   7155       {MO_NTPOFF, "x86-ntpoff"},
   7156       {MO_GOTNTPOFF, "x86-gotntpoff"},
   7157       {MO_DLLIMPORT, "x86-dllimport"},
   7158       {MO_DARWIN_STUB, "x86-darwin-stub"},
   7159       {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
   7160       {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
   7161       {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
   7162       {MO_TLVP, "x86-tlvp"},
   7163       {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
   7164       {MO_SECREL, "x86-secrel"}};
   7165   return makeArrayRef(TargetFlags);
   7166 }
   7167 
   7168 namespace {
   7169   /// Create Global Base Reg pass. This initializes the PIC
   7170   /// global base register for x86-32.
   7171   struct CGBR : public MachineFunctionPass {
   7172     static char ID;
   7173     CGBR() : MachineFunctionPass(ID) {}
   7174 
   7175     bool runOnMachineFunction(MachineFunction &MF) override {
   7176       const X86TargetMachine *TM =
   7177         static_cast<const X86TargetMachine *>(&MF.getTarget());
   7178       const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
   7179 
   7180       // Don't do anything if this is 64-bit as 64-bit PIC
   7181       // uses RIP relative addressing.
   7182       if (STI.is64Bit())
   7183         return false;
   7184 
   7185       // Only emit a global base reg in PIC mode.
   7186       if (TM->getRelocationModel() != Reloc::PIC_)
   7187         return false;
   7188 
   7189       X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
   7190       unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
   7191 
   7192       // If we didn't need a GlobalBaseReg, don't insert code.
   7193       if (GlobalBaseReg == 0)
   7194         return false;
   7195 
   7196       // Insert the set of GlobalBaseReg into the first MBB of the function
   7197       MachineBasicBlock &FirstMBB = MF.front();
   7198       MachineBasicBlock::iterator MBBI = FirstMBB.begin();
   7199       DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
   7200       MachineRegisterInfo &RegInfo = MF.getRegInfo();
   7201       const X86InstrInfo *TII = STI.getInstrInfo();
   7202 
   7203       unsigned PC;
   7204       if (STI.isPICStyleGOT())
   7205         PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
   7206       else
   7207         PC = GlobalBaseReg;
   7208 
   7209       // Operand of MovePCtoStack is completely ignored by asm printer. It's
   7210       // only used in JIT code emission as displacement to pc.
   7211       BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
   7212 
   7213       // If we're using vanilla 'GOT' PIC style, we should use relative addressing
   7214       // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
   7215       if (STI.isPICStyleGOT()) {
   7216         // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
   7217         BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
   7218           .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
   7219                                         X86II::MO_GOT_ABSOLUTE_ADDRESS);
   7220       }
   7221 
   7222       return true;
   7223     }
   7224 
   7225     const char *getPassName() const override {
   7226       return "X86 PIC Global Base Reg Initialization";
   7227     }
   7228 
   7229     void getAnalysisUsage(AnalysisUsage &AU) const override {
   7230       AU.setPreservesCFG();
   7231       MachineFunctionPass::getAnalysisUsage(AU);
   7232     }
   7233   };
   7234 }
   7235 
   7236 char CGBR::ID = 0;
   7237 FunctionPass*
   7238 llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
   7239 
   7240 namespace {
   7241   struct LDTLSCleanup : public MachineFunctionPass {
   7242     static char ID;
   7243     LDTLSCleanup() : MachineFunctionPass(ID) {}
   7244 
   7245     bool runOnMachineFunction(MachineFunction &MF) override {
   7246       X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
   7247       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
   7248         // No point folding accesses if there isn't at least two.
   7249         return false;
   7250       }
   7251 
   7252       MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
   7253       return VisitNode(DT->getRootNode(), 0);
   7254     }
   7255 
   7256     // Visit the dominator subtree rooted at Node in pre-order.
   7257     // If TLSBaseAddrReg is non-null, then use that to replace any
   7258     // TLS_base_addr instructions. Otherwise, create the register
   7259     // when the first such instruction is seen, and then use it
   7260     // as we encounter more instructions.
   7261     bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
   7262       MachineBasicBlock *BB = Node->getBlock();
   7263       bool Changed = false;
   7264 
   7265       // Traverse the current block.
   7266       for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
   7267            ++I) {
   7268         switch (I->getOpcode()) {
   7269           case X86::TLS_base_addr32:
   7270           case X86::TLS_base_addr64:
   7271             if (TLSBaseAddrReg)
   7272               I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
   7273             else
   7274               I = SetRegister(I, &TLSBaseAddrReg);
   7275             Changed = true;
   7276             break;
   7277           default:
   7278             break;
   7279         }
   7280       }
   7281 
   7282       // Visit the children of this block in the dominator tree.
   7283       for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
   7284            I != E; ++I) {
   7285         Changed |= VisitNode(*I, TLSBaseAddrReg);
   7286       }
   7287 
   7288       return Changed;
   7289     }
   7290 
   7291     // Replace the TLS_base_addr instruction I with a copy from
   7292     // TLSBaseAddrReg, returning the new instruction.
   7293     MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
   7294                                          unsigned TLSBaseAddrReg) {
   7295       MachineFunction *MF = I->getParent()->getParent();
   7296       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
   7297       const bool is64Bit = STI.is64Bit();
   7298       const X86InstrInfo *TII = STI.getInstrInfo();
   7299 
   7300       // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
   7301       MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
   7302                                    TII->get(TargetOpcode::COPY),
   7303                                    is64Bit ? X86::RAX : X86::EAX)
   7304                                    .addReg(TLSBaseAddrReg);
   7305 
   7306       // Erase the TLS_base_addr instruction.
   7307       I->eraseFromParent();
   7308 
   7309       return Copy;
   7310     }
   7311 
   7312     // Create a virtal register in *TLSBaseAddrReg, and populate it by
   7313     // inserting a copy instruction after I. Returns the new instruction.
   7314     MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
   7315       MachineFunction *MF = I->getParent()->getParent();
   7316       const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
   7317       const bool is64Bit = STI.is64Bit();
   7318       const X86InstrInfo *TII = STI.getInstrInfo();
   7319 
   7320       // Create a virtual register for the TLS base address.
   7321       MachineRegisterInfo &RegInfo = MF->getRegInfo();
   7322       *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
   7323                                                       ? &X86::GR64RegClass
   7324                                                       : &X86::GR32RegClass);
   7325 
   7326       // Insert a copy from RAX/EAX to TLSBaseAddrReg.
   7327       MachineInstr *Next = I->getNextNode();
   7328       MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
   7329                                    TII->get(TargetOpcode::COPY),
   7330                                    *TLSBaseAddrReg)
   7331                                    .addReg(is64Bit ? X86::RAX : X86::EAX);
   7332 
   7333       return Copy;
   7334     }
   7335 
   7336     const char *getPassName() const override {
   7337       return "Local Dynamic TLS Access Clean-up";
   7338     }
   7339 
   7340     void getAnalysisUsage(AnalysisUsage &AU) const override {
   7341       AU.setPreservesCFG();
   7342       AU.addRequired<MachineDominatorTree>();
   7343       MachineFunctionPass::getAnalysisUsage(AU);
   7344     }
   7345   };
   7346 }
   7347 
   7348 char LDTLSCleanup::ID = 0;
   7349 FunctionPass*
   7350 llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }
   7351